drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/kthread.h>
  27 #include <linux/pci.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_pm.h"
  33 #include "amdgpu_dm_debugfs.h"
  34 #include "amdgpu_ras.h"
  35 #include "amdgpu_rap.h"
  36 #include "amdgpu_securedisplay.h"
  37 #include "amdgpu_fw_attestation.h"
  38 #include "amdgpu_umr.h"
  39
  40 #include "amdgpu_reset.h"
  41 #include "amdgpu_psp_ta.h"
  42
  43 #if defined(CONFIG_DEBUG_FS)
  44
  45 /**
  46  * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
  47  *
  48  * @read: True if reading
  49  * @f: open file handle
  50  * @buf: User buffer to write/read to
  51  * @size: Number of bytes to write/read
  52  * @pos:  Offset to seek to
  53  *
  54  * This debugfs entry has special meaning on the offset being sought.
  55  * Various bits have different meanings:
  56  *
  57  * Bit 62:  Indicates a GRBM bank switch is needed
  58  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  59  *          zero)
  60  * Bits 24..33: The SE or ME selector if needed
  61  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  62  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  63  *
  64  * Bit 23:  Indicates that the PM power gating lock should be held
  65  *          This is necessary to read registers that might be
  66  *          unreliable during a power gating transistion.
  67  *
  68  * The lower bits are the BYTE offset of the register to read.  This
  69  * allows reading multiple registers in a single call and having
  70  * the returned size reflect that.
  71  */
  72 static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
  73                 char __user *buf, size_t size, loff_t *pos)
  74 {
  75         struct amdgpu_device *adev = file_inode(f)->i_private;
  76         ssize_t result = 0;
  77         int r;
  78         bool pm_pg_lock, use_bank, use_ring;
  79         unsigned int instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
  80
  81         pm_pg_lock = use_bank = use_ring = false;
  82         instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
  83
  84         if (size & 0x3 || *pos & 0x3 ||
  85                         ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
  86                 return -EINVAL;
  87
  88         /* are we reading registers for which a PG lock is necessary? */
  89         pm_pg_lock = (*pos >> 23) & 1;
  90
  91         if (*pos & (1ULL << 62)) {
  92                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
  93                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
  94                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
  95
  96                 if (se_bank == 0x3FF)
  97                         se_bank = 0xFFFFFFFF;
  98                 if (sh_bank == 0x3FF)
  99                         sh_bank = 0xFFFFFFFF;
 100                 if (instance_bank == 0x3FF)
 101                         instance_bank = 0xFFFFFFFF;
 102                 use_bank = true;
 103         } else if (*pos & (1ULL << 61)) {
 104
 105                 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
 106                 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
 107                 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
 108                 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
 109
 110                 use_ring = true;
 111         } else {
 112                 use_bank = use_ring = false;
 113         }
 114
 115         *pos &= (1UL << 22) - 1;
 116
 117         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 118         if (r < 0) {
 119                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 120                 return r;
 121         }
 122
 123         r = amdgpu_virt_enable_access_debugfs(adev);
 124         if (r < 0) {
 125                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 126                 return r;
 127         }
 128
 129         if (use_bank) {
 130                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
 131                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
 132                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 133                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 134                         amdgpu_virt_disable_access_debugfs(adev);
 135                         return -EINVAL;
 136                 }
 137                 mutex_lock(&adev->grbm_idx_mutex);
 138                 amdgpu_gfx_select_se_sh(adev, se_bank,
 139                                         sh_bank, instance_bank, 0);
 140         } else if (use_ring) {
 141                 mutex_lock(&adev->srbm_mutex);
 142                 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
 143         }
 144
 145         if (pm_pg_lock)
 146                 mutex_lock(&adev->pm.mutex);
 147
 148         while (size) {
 149                 uint32_t value;
 150
 151                 if (read) {
 152                         value = RREG32(*pos >> 2);
 153                         r = put_user(value, (uint32_t *)buf);
 154                 } else {
 155                         r = get_user(value, (uint32_t *)buf);
 156                         if (!r)
 157                                 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value);
 158                 }
 159                 if (r) {
 160                         result = r;
 161                         goto end;
 162                 }
 163
 164                 result += 4;
 165                 buf += 4;
 166                 *pos += 4;
 167                 size -= 4;
 168         }
 169
 170 end:
 171         if (use_bank) {
 172                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 173                 mutex_unlock(&adev->grbm_idx_mutex);
 174         } else if (use_ring) {
 175                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
 176                 mutex_unlock(&adev->srbm_mutex);
 177         }
 178
 179         if (pm_pg_lock)
 180                 mutex_unlock(&adev->pm.mutex);
 181
 182         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 183         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 184
 185         amdgpu_virt_disable_access_debugfs(adev);
 186         return result;
 187 }
 188
 189 /*
 190  * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
 191  */
 192 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 193                                         size_t size, loff_t *pos)
 194 {
 195         return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
 196 }
 197
 198 /*
 199  * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
 200  */
 201 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 202                                          size_t size, loff_t *pos)
 203 {
 204         return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
 205 }
 206
 207 static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file)
 208 {
 209         struct amdgpu_debugfs_regs2_data *rd;
 210
 211         rd = kzalloc(sizeof(*rd), GFP_KERNEL);
 212         if (!rd)
 213                 return -ENOMEM;
 214         rd->adev = file_inode(file)->i_private;
 215         file->private_data = rd;
 216         mutex_init(&rd->lock);
 217
 218         return 0;
 219 }
 220
 221 static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file)
 222 {
 223         struct amdgpu_debugfs_regs2_data *rd = file->private_data;
 224
 225         mutex_destroy(&rd->lock);
 226         kfree(file->private_data);
 227         return 0;
 228 }
 229
 230 static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en)
 231 {
 232         struct amdgpu_debugfs_regs2_data *rd = f->private_data;
 233         struct amdgpu_device *adev = rd->adev;
 234         ssize_t result = 0;
 235         int r;
 236         uint32_t value;
 237
 238         if (size & 0x3 || offset & 0x3)
 239                 return -EINVAL;
 240
 241         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 242         if (r < 0) {
 243                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 244                 return r;
 245         }
 246
 247         r = amdgpu_virt_enable_access_debugfs(adev);
 248         if (r < 0) {
 249                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 250                 return r;
 251         }
 252
 253         mutex_lock(&rd->lock);
 254
 255         if (rd->id.use_grbm) {
 256                 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||
 257                     (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {
 258                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 259                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 260                         amdgpu_virt_disable_access_debugfs(adev);
 261                         mutex_unlock(&rd->lock);
 262                         return -EINVAL;
 263                 }
 264                 mutex_lock(&adev->grbm_idx_mutex);
 265                 amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
 266                                                                 rd->id.grbm.sh,
 267                                                                 rd->id.grbm.instance, 0);
 268         }
 269
 270         if (rd->id.use_srbm) {
 271                 mutex_lock(&adev->srbm_mutex);
 272                 amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,
 273                                                                         rd->id.srbm.queue, rd->id.srbm.vmid);
 274         }
 275
 276         if (rd->id.pg_lock)
 277                 mutex_lock(&adev->pm.mutex);
 278
 279         while (size) {
 280                 if (!write_en) {
 281                         value = RREG32(offset >> 2);
 282                         r = put_user(value, (uint32_t *)buf);
 283                 } else {
 284                         r = get_user(value, (uint32_t *)buf);
 285                         if (!r)
 286                                 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value);
 287                 }
 288                 if (r) {
 289                         result = r;
 290                         goto end;
 291                 }
 292                 offset += 4;
 293                 size -= 4;
 294                 result += 4;
 295                 buf += 4;
 296         }
 297 end:
 298         if (rd->id.use_grbm) {
 299                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 300                 mutex_unlock(&adev->grbm_idx_mutex);
 301         }
 302
 303         if (rd->id.use_srbm) {
 304                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
 305                 mutex_unlock(&adev->srbm_mutex);
 306         }
 307
 308         if (rd->id.pg_lock)
 309                 mutex_unlock(&adev->pm.mutex);
 310
 311         mutex_unlock(&rd->lock);
 312
 313         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 314         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 315
 316         amdgpu_virt_disable_access_debugfs(adev);
 317         return result;
 318 }
 319
 320 static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data)
 321 {
 322         struct amdgpu_debugfs_regs2_data *rd = f->private_data;
 323         int r;
 324
 325         switch (cmd) {
 326         case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:
 327                 mutex_lock(&rd->lock);
 328                 r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata *)data,
 329                                    sizeof(rd->id));
 330                 mutex_unlock(&rd->lock);
 331                 return r ? -EINVAL : 0;
 332         default:
 333                 return -EINVAL;
 334         }
 335         return 0;
 336 }
 337
 338 static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
 339 {
 340         return amdgpu_debugfs_regs2_op(f, buf, *pos, size, 0);
 341 }
 342
 343 static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf, size_t size, loff_t *pos)
 344 {
 345         return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);
 346 }
 347
 348
 349 /**
 350  * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
 351  *
 352  * @f: open file handle
 353  * @buf: User buffer to store read data in
 354  * @size: Number of bytes to read
 355  * @pos:  Offset to seek to
 356  *
 357  * The lower bits are the BYTE offset of the register to read.  This
 358  * allows reading multiple registers in a single call and having
 359  * the returned size reflect that.
 360  */
 361 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
 362                                         size_t size, loff_t *pos)
 363 {
 364         struct amdgpu_device *adev = file_inode(f)->i_private;
 365         ssize_t result = 0;
 366         int r;
 367
 368         if (size & 0x3 || *pos & 0x3)
 369                 return -EINVAL;
 370
 371         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 372         if (r < 0) {
 373                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 374                 return r;
 375         }
 376
 377         r = amdgpu_virt_enable_access_debugfs(adev);
 378         if (r < 0) {
 379                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 380                 return r;
 381         }
 382
 383         while (size) {
 384                 uint32_t value;
 385
 386                 value = RREG32_PCIE(*pos);
 387                 r = put_user(value, (uint32_t *)buf);
 388                 if (r)
 389                         goto out;
 390
 391                 result += 4;
 392                 buf += 4;
 393                 *pos += 4;
 394                 size -= 4;
 395         }
 396
 397         r = result;
 398 out:
 399         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 400         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 401         amdgpu_virt_disable_access_debugfs(adev);
 402         return r;
 403 }
 404
 405 /**
 406  * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
 407  *
 408  * @f: open file handle
 409  * @buf: User buffer to write data from
 410  * @size: Number of bytes to write
 411  * @pos:  Offset to seek to
 412  *
 413  * The lower bits are the BYTE offset of the register to write.  This
 414  * allows writing multiple registers in a single call and having
 415  * the returned size reflect that.
 416  */
 417 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
 418                                          size_t size, loff_t *pos)
 419 {
 420         struct amdgpu_device *adev = file_inode(f)->i_private;
 421         ssize_t result = 0;
 422         int r;
 423
 424         if (size & 0x3 || *pos & 0x3)
 425                 return -EINVAL;
 426
 427         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 428         if (r < 0) {
 429                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 430                 return r;
 431         }
 432
 433         r = amdgpu_virt_enable_access_debugfs(adev);
 434         if (r < 0) {
 435                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 436                 return r;
 437         }
 438
 439         while (size) {
 440                 uint32_t value;
 441
 442                 r = get_user(value, (uint32_t *)buf);
 443                 if (r)
 444                         goto out;
 445
 446                 WREG32_PCIE(*pos, value);
 447
 448                 result += 4;
 449                 buf += 4;
 450                 *pos += 4;
 451                 size -= 4;
 452         }
 453
 454         r = result;
 455 out:
 456         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 457         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 458         amdgpu_virt_disable_access_debugfs(adev);
 459         return r;
 460 }
 461
 462 /**
 463  * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
 464  *
 465  * @f: open file handle
 466  * @buf: User buffer to store read data in
 467  * @size: Number of bytes to read
 468  * @pos:  Offset to seek to
 469  *
 470  * The lower bits are the BYTE offset of the register to read.  This
 471  * allows reading multiple registers in a single call and having
 472  * the returned size reflect that.
 473  */
 474 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
 475                                         size_t size, loff_t *pos)
 476 {
 477         struct amdgpu_device *adev = file_inode(f)->i_private;
 478         ssize_t result = 0;
 479         int r;
 480
 481         if (size & 0x3 || *pos & 0x3)
 482                 return -EINVAL;
 483
 484         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 485         if (r < 0) {
 486                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 487                 return r;
 488         }
 489
 490         r = amdgpu_virt_enable_access_debugfs(adev);
 491         if (r < 0) {
 492                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 493                 return r;
 494         }
 495
 496         while (size) {
 497                 uint32_t value;
 498
 499                 value = RREG32_DIDT(*pos >> 2);
 500                 r = put_user(value, (uint32_t *)buf);
 501                 if (r)
 502                         goto out;
 503
 504                 result += 4;
 505                 buf += 4;
 506                 *pos += 4;
 507                 size -= 4;
 508         }
 509
 510         r = result;
 511 out:
 512         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 513         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 514         amdgpu_virt_disable_access_debugfs(adev);
 515         return r;
 516 }
 517
 518 /**
 519  * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
 520  *
 521  * @f: open file handle
 522  * @buf: User buffer to write data from
 523  * @size: Number of bytes to write
 524  * @pos:  Offset to seek to
 525  *
 526  * The lower bits are the BYTE offset of the register to write.  This
 527  * allows writing multiple registers in a single call and having
 528  * the returned size reflect that.
 529  */
 530 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
 531                                          size_t size, loff_t *pos)
 532 {
 533         struct amdgpu_device *adev = file_inode(f)->i_private;
 534         ssize_t result = 0;
 535         int r;
 536
 537         if (size & 0x3 || *pos & 0x3)
 538                 return -EINVAL;
 539
 540         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 541         if (r < 0) {
 542                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 543                 return r;
 544         }
 545
 546         r = amdgpu_virt_enable_access_debugfs(adev);
 547         if (r < 0) {
 548                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 549                 return r;
 550         }
 551
 552         while (size) {
 553                 uint32_t value;
 554
 555                 r = get_user(value, (uint32_t *)buf);
 556                 if (r)
 557                         goto out;
 558
 559                 WREG32_DIDT(*pos >> 2, value);
 560
 561                 result += 4;
 562                 buf += 4;
 563                 *pos += 4;
 564                 size -= 4;
 565         }
 566
 567         r = result;
 568 out:
 569         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 570         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 571         amdgpu_virt_disable_access_debugfs(adev);
 572         return r;
 573 }
 574
 575 /**
 576  * amdgpu_debugfs_regs_smc_read - Read from a SMC register
 577  *
 578  * @f: open file handle
 579  * @buf: User buffer to store read data in
 580  * @size: Number of bytes to read
 581  * @pos:  Offset to seek to
 582  *
 583  * The lower bits are the BYTE offset of the register to read.  This
 584  * allows reading multiple registers in a single call and having
 585  * the returned size reflect that.
 586  */
 587 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
 588                                         size_t size, loff_t *pos)
 589 {
 590         struct amdgpu_device *adev = file_inode(f)->i_private;
 591         ssize_t result = 0;
 592         int r;
 593
 594         if (size & 0x3 || *pos & 0x3)
 595                 return -EINVAL;
 596
 597         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 598         if (r < 0) {
 599                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 600                 return r;
 601         }
 602
 603         r = amdgpu_virt_enable_access_debugfs(adev);
 604         if (r < 0) {
 605                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 606                 return r;
 607         }
 608
 609         while (size) {
 610                 uint32_t value;
 611
 612                 value = RREG32_SMC(*pos);
 613                 r = put_user(value, (uint32_t *)buf);
 614                 if (r)
 615                         goto out;
 616
 617                 result += 4;
 618                 buf += 4;
 619                 *pos += 4;
 620                 size -= 4;
 621         }
 622
 623         r = result;
 624 out:
 625         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 626         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 627         amdgpu_virt_disable_access_debugfs(adev);
 628         return r;
 629 }
 630
 631 /**
 632  * amdgpu_debugfs_regs_smc_write - Write to a SMC register
 633  *
 634  * @f: open file handle
 635  * @buf: User buffer to write data from
 636  * @size: Number of bytes to write
 637  * @pos:  Offset to seek to
 638  *
 639  * The lower bits are the BYTE offset of the register to write.  This
 640  * allows writing multiple registers in a single call and having
 641  * the returned size reflect that.
 642  */
 643 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
 644                                          size_t size, loff_t *pos)
 645 {
 646         struct amdgpu_device *adev = file_inode(f)->i_private;
 647         ssize_t result = 0;
 648         int r;
 649
 650         if (size & 0x3 || *pos & 0x3)
 651                 return -EINVAL;
 652
 653         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 654         if (r < 0) {
 655                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 656                 return r;
 657         }
 658
 659         r = amdgpu_virt_enable_access_debugfs(adev);
 660         if (r < 0) {
 661                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 662                 return r;
 663         }
 664
 665         while (size) {
 666                 uint32_t value;
 667
 668                 r = get_user(value, (uint32_t *)buf);
 669                 if (r)
 670                         goto out;
 671
 672                 WREG32_SMC(*pos, value);
 673
 674                 result += 4;
 675                 buf += 4;
 676                 *pos += 4;
 677                 size -= 4;
 678         }
 679
 680         r = result;
 681 out:
 682         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 683         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 684         amdgpu_virt_disable_access_debugfs(adev);
 685         return r;
 686 }
 687
 688 /**
 689  * amdgpu_debugfs_gca_config_read - Read from gfx config data
 690  *
 691  * @f: open file handle
 692  * @buf: User buffer to store read data in
 693  * @size: Number of bytes to read
 694  * @pos:  Offset to seek to
 695  *
 696  * This file is used to access configuration data in a somewhat
 697  * stable fashion.  The format is a series of DWORDs with the first
 698  * indicating which revision it is.  New content is appended to the
 699  * end so that older software can still read the data.
 700  */
 701
 702 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
 703                                         size_t size, loff_t *pos)
 704 {
 705         struct amdgpu_device *adev = file_inode(f)->i_private;
 706         ssize_t result = 0;
 707         int r;
 708         uint32_t *config, no_regs = 0;
 709
 710         if (size & 0x3 || *pos & 0x3)
 711                 return -EINVAL;
 712
 713         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
 714         if (!config)
 715                 return -ENOMEM;
 716
 717         /* version, increment each time something is added */
 718         config[no_regs++] = 5;
 719         config[no_regs++] = adev->gfx.config.max_shader_engines;
 720         config[no_regs++] = adev->gfx.config.max_tile_pipes;
 721         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
 722         config[no_regs++] = adev->gfx.config.max_sh_per_se;
 723         config[no_regs++] = adev->gfx.config.max_backends_per_se;
 724         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
 725         config[no_regs++] = adev->gfx.config.max_gprs;
 726         config[no_regs++] = adev->gfx.config.max_gs_threads;
 727         config[no_regs++] = adev->gfx.config.max_hw_contexts;
 728         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
 729         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
 730         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
 731         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
 732         config[no_regs++] = adev->gfx.config.num_tile_pipes;
 733         config[no_regs++] = adev->gfx.config.backend_enable_mask;
 734         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
 735         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
 736         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
 737         config[no_regs++] = adev->gfx.config.num_gpus;
 738         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
 739         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
 740         config[no_regs++] = adev->gfx.config.gb_addr_config;
 741         config[no_regs++] = adev->gfx.config.num_rbs;
 742
 743         /* rev==1 */
 744         config[no_regs++] = adev->rev_id;
 745         config[no_regs++] = lower_32_bits(adev->pg_flags);
 746         config[no_regs++] = lower_32_bits(adev->cg_flags);
 747
 748         /* rev==2 */
 749         config[no_regs++] = adev->family;
 750         config[no_regs++] = adev->external_rev_id;
 751
 752         /* rev==3 */
 753         config[no_regs++] = adev->pdev->device;
 754         config[no_regs++] = adev->pdev->revision;
 755         config[no_regs++] = adev->pdev->subsystem_device;
 756         config[no_regs++] = adev->pdev->subsystem_vendor;
 757
 758         /* rev==4 APU flag */
 759         config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
 760
 761         /* rev==5 PG/CG flag upper 32bit */
 762         config[no_regs++] = upper_32_bits(adev->pg_flags);
 763         config[no_regs++] = upper_32_bits(adev->cg_flags);
 764
 765         while (size && (*pos < no_regs * 4)) {
 766                 uint32_t value;
 767
 768                 value = config[*pos >> 2];
 769                 r = put_user(value, (uint32_t *)buf);
 770                 if (r) {
 771                         kfree(config);
 772                         return r;
 773                 }
 774
 775                 result += 4;
 776                 buf += 4;
 777                 *pos += 4;
 778                 size -= 4;
 779         }
 780
 781         kfree(config);
 782         return result;
 783 }
 784
 785 /**
 786  * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
 787  *
 788  * @f: open file handle
 789  * @buf: User buffer to store read data in
 790  * @size: Number of bytes to read
 791  * @pos:  Offset to seek to
 792  *
 793  * The offset is treated as the BYTE address of one of the sensors
 794  * enumerated in amd/include/kgd_pp_interface.h under the
 795  * 'amd_pp_sensors' enumeration.  For instance to read the UVD VCLK
 796  * you would use the offset 3 * 4 = 12.
 797  */
 798 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
 799                                         size_t size, loff_t *pos)
 800 {
 801         struct amdgpu_device *adev = file_inode(f)->i_private;
 802         int idx, x, outsize, r, valuesize;
 803         uint32_t values[16];
 804
 805         if (size & 3 || *pos & 0x3)
 806                 return -EINVAL;
 807
 808         if (!adev->pm.dpm_enabled)
 809                 return -EINVAL;
 810
 811         /* convert offset to sensor number */
 812         idx = *pos >> 2;
 813
 814         valuesize = sizeof(values);
 815
 816         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 817         if (r < 0) {
 818                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 819                 return r;
 820         }
 821
 822         r = amdgpu_virt_enable_access_debugfs(adev);
 823         if (r < 0) {
 824                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 825                 return r;
 826         }
 827
 828         r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
 829
 830         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 831         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 832
 833         if (r) {
 834                 amdgpu_virt_disable_access_debugfs(adev);
 835                 return r;
 836         }
 837
 838         if (size > valuesize) {
 839                 amdgpu_virt_disable_access_debugfs(adev);
 840                 return -EINVAL;
 841         }
 842
 843         outsize = 0;
 844         x = 0;
 845         if (!r) {
 846                 while (size) {
 847                         r = put_user(values[x++], (int32_t *)buf);
 848                         buf += 4;
 849                         size -= 4;
 850                         outsize += 4;
 851                 }
 852         }
 853
 854         amdgpu_virt_disable_access_debugfs(adev);
 855         return !r ? outsize : r;
 856 }
 857
 858 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
 859  *
 860  * @f: open file handle
 861  * @buf: User buffer to store read data in
 862  * @size: Number of bytes to read
 863  * @pos:  Offset to seek to
 864  *
 865  * The offset being sought changes which wave that the status data
 866  * will be returned for.  The bits are used as follows:
 867  *
 868  * Bits 0..6:   Byte offset into data
 869  * Bits 7..14:  SE selector
 870  * Bits 15..22: SH/SA selector
 871  * Bits 23..30: CU/{WGP+SIMD} selector
 872  * Bits 31..36: WAVE ID selector
 873  * Bits 37..44: SIMD ID selector
 874  *
 875  * The returned data begins with one DWORD of version information
 876  * Followed by WAVE STATUS registers relevant to the GFX IP version
 877  * being used.  See gfx_v8_0_read_wave_data() for an example output.
 878  */
 879 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 880                                         size_t size, loff_t *pos)
 881 {
 882         struct amdgpu_device *adev = f->f_inode->i_private;
 883         int r, x;
 884         ssize_t result = 0;
 885         uint32_t offset, se, sh, cu, wave, simd, data[32];
 886
 887         if (size & 3 || *pos & 3)
 888                 return -EINVAL;
 889
 890         /* decode offset */
 891         offset = (*pos & GENMASK_ULL(6, 0));
 892         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
 893         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
 894         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
 895         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
 896         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
 897
 898         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 899         if (r < 0) {
 900                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 901                 return r;
 902         }
 903
 904         r = amdgpu_virt_enable_access_debugfs(adev);
 905         if (r < 0) {
 906                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 907                 return r;
 908         }
 909
 910         /* switch to the specific se/sh/cu */
 911         mutex_lock(&adev->grbm_idx_mutex);
 912         amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0);
 913
 914         x = 0;
 915         if (adev->gfx.funcs->read_wave_data)
 916                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
 917
 918         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
 919         mutex_unlock(&adev->grbm_idx_mutex);
 920
 921         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 922         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 923
 924         if (!x) {
 925                 amdgpu_virt_disable_access_debugfs(adev);
 926                 return -EINVAL;
 927         }
 928
 929         while (size && (offset < x * 4)) {
 930                 uint32_t value;
 931
 932                 value = data[offset >> 2];
 933                 r = put_user(value, (uint32_t *)buf);
 934                 if (r) {
 935                         amdgpu_virt_disable_access_debugfs(adev);
 936                         return r;
 937                 }
 938
 939                 result += 4;
 940                 buf += 4;
 941                 offset += 4;
 942                 size -= 4;
 943         }
 944
 945         amdgpu_virt_disable_access_debugfs(adev);
 946         return result;
 947 }
 948
 949 /** amdgpu_debugfs_gpr_read - Read wave gprs
 950  *
 951  * @f: open file handle
 952  * @buf: User buffer to store read data in
 953  * @size: Number of bytes to read
 954  * @pos:  Offset to seek to
 955  *
 956  * The offset being sought changes which wave that the status data
 957  * will be returned for.  The bits are used as follows:
 958  *
 959  * Bits 0..11:  Byte offset into data
 960  * Bits 12..19: SE selector
 961  * Bits 20..27: SH/SA selector
 962  * Bits 28..35: CU/{WGP+SIMD} selector
 963  * Bits 36..43: WAVE ID selector
 964  * Bits 37..44: SIMD ID selector
 965  * Bits 52..59: Thread selector
 966  * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
 967  *
 968  * The return data comes from the SGPR or VGPR register bank for
 969  * the selected operational unit.
 970  */
 971 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
 972                                         size_t size, loff_t *pos)
 973 {
 974         struct amdgpu_device *adev = f->f_inode->i_private;
 975         int r;
 976         ssize_t result = 0;
 977         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
 978
 979         if (size > 4096 || size & 3 || *pos & 3)
 980                 return -EINVAL;
 981
 982         /* decode offset */
 983         offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
 984         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
 985         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
 986         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
 987         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
 988         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
 989         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
 990         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
 991
 992         data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
 993         if (!data)
 994                 return -ENOMEM;
 995
 996         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 997         if (r < 0)
 998                 goto err;
 999
1000         r = amdgpu_virt_enable_access_debugfs(adev);
1001         if (r < 0)
1002                 goto err;
1003
1004         /* switch to the specific se/sh/cu */
1005         mutex_lock(&adev->grbm_idx_mutex);
1006         amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0);
1007
1008         if (bank == 0) {
1009                 if (adev->gfx.funcs->read_wave_vgprs)
1010                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
1011         } else {
1012                 if (adev->gfx.funcs->read_wave_sgprs)
1013                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
1014         }
1015
1016         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
1017         mutex_unlock(&adev->grbm_idx_mutex);
1018
1019         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1020         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1021
1022         while (size) {
1023                 uint32_t value;
1024
1025                 value = data[result >> 2];
1026                 r = put_user(value, (uint32_t *)buf);
1027                 if (r) {
1028                         amdgpu_virt_disable_access_debugfs(adev);
1029                         goto err;
1030                 }
1031
1032                 result += 4;
1033                 buf += 4;
1034                 size -= 4;
1035         }
1036
1037         kfree(data);
1038         amdgpu_virt_disable_access_debugfs(adev);
1039         return result;
1040
1041 err:
1042         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1043         kfree(data);
1044         return r;
1045 }
1046
1047 /**
1048  * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
1049  *
1050  * @f: open file handle
1051  * @buf: User buffer to store read data in
1052  * @size: Number of bytes to read
1053  * @pos:  Offset to seek to
1054  *
1055  * Read the last residency value logged. It doesn't auto update, one needs to
1056  * stop logging before getting the current value.
1057  */
1058 static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char __user *buf,
1059                                                     size_t size, loff_t *pos)
1060 {
1061         struct amdgpu_device *adev = file_inode(f)->i_private;
1062         ssize_t result = 0;
1063         int r;
1064
1065         if (size & 0x3 || *pos & 0x3)
1066                 return -EINVAL;
1067
1068         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1069         if (r < 0) {
1070                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1071                 return r;
1072         }
1073
1074         while (size) {
1075                 uint32_t value;
1076
1077                 r = amdgpu_get_gfx_off_residency(adev, &value);
1078                 if (r)
1079                         goto out;
1080
1081                 r = put_user(value, (uint32_t *)buf);
1082                 if (r)
1083                         goto out;
1084
1085                 result += 4;
1086                 buf += 4;
1087                 *pos += 4;
1088                 size -= 4;
1089         }
1090
1091         r = result;
1092 out:
1093         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1094         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1095
1096         return r;
1097 }
1098
1099 /**
1100  * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
1101  *
1102  * @f: open file handle
1103  * @buf: User buffer to write data from
1104  * @size: Number of bytes to write
1105  * @pos:  Offset to seek to
1106  *
1107  * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
1108  */
1109 static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const char __user *buf,
1110                                                      size_t size, loff_t *pos)
1111 {
1112         struct amdgpu_device *adev = file_inode(f)->i_private;
1113         ssize_t result = 0;
1114         int r;
1115
1116         if (size & 0x3 || *pos & 0x3)
1117                 return -EINVAL;
1118
1119         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1120         if (r < 0) {
1121                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1122                 return r;
1123         }
1124
1125         while (size) {
1126                 u32 value;
1127
1128                 r = get_user(value, (uint32_t *)buf);
1129                 if (r)
1130                         goto out;
1131
1132                 amdgpu_set_gfx_off_residency(adev, value ? true : false);
1133
1134                 result += 4;
1135                 buf += 4;
1136                 *pos += 4;
1137                 size -= 4;
1138         }
1139
1140         r = result;
1141 out:
1142         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1143         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1144
1145         return r;
1146 }
1147
1148
1149 /**
1150  * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
1151  *
1152  * @f: open file handle
1153  * @buf: User buffer to store read data in
1154  * @size: Number of bytes to read
1155  * @pos:  Offset to seek to
1156  */
1157 static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user *buf,
1158                                                 size_t size, loff_t *pos)
1159 {
1160         struct amdgpu_device *adev = file_inode(f)->i_private;
1161         ssize_t result = 0;
1162         int r;
1163
1164         if (size & 0x3 || *pos & 0x3)
1165                 return -EINVAL;
1166
1167         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1168         if (r < 0) {
1169                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1170                 return r;
1171         }
1172
1173         while (size) {
1174                 u64 value = 0;
1175
1176                 r = amdgpu_get_gfx_off_entrycount(adev, &value);
1177                 if (r)
1178                         goto out;
1179
1180                 r = put_user(value, (u64 *)buf);
1181                 if (r)
1182                         goto out;
1183
1184                 result += 4;
1185                 buf += 4;
1186                 *pos += 4;
1187                 size -= 4;
1188         }
1189
1190         r = result;
1191 out:
1192         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1193         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1194
1195         return r;
1196 }
1197
1198 /**
1199  * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1200  *
1201  * @f: open file handle
1202  * @buf: User buffer to write data from
1203  * @size: Number of bytes to write
1204  * @pos:  Offset to seek to
1205  *
1206  * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1207  */
1208 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1209                                          size_t size, loff_t *pos)
1210 {
1211         struct amdgpu_device *adev = file_inode(f)->i_private;
1212         ssize_t result = 0;
1213         int r;
1214
1215         if (size & 0x3 || *pos & 0x3)
1216                 return -EINVAL;
1217
1218         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1219         if (r < 0) {
1220                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1221                 return r;
1222         }
1223
1224         while (size) {
1225                 uint32_t value;
1226
1227                 r = get_user(value, (uint32_t *)buf);
1228                 if (r)
1229                         goto out;
1230
1231                 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1232
1233                 result += 4;
1234                 buf += 4;
1235                 *pos += 4;
1236                 size -= 4;
1237         }
1238
1239         r = result;
1240 out:
1241         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1242         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1243
1244         return r;
1245 }
1246
1247
1248 /**
1249  * amdgpu_debugfs_gfxoff_read - read gfxoff status
1250  *
1251  * @f: open file handle
1252  * @buf: User buffer to store read data in
1253  * @size: Number of bytes to read
1254  * @pos:  Offset to seek to
1255  */
1256 static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1257                                          size_t size, loff_t *pos)
1258 {
1259         struct amdgpu_device *adev = file_inode(f)->i_private;
1260         ssize_t result = 0;
1261         int r;
1262
1263         if (size & 0x3 || *pos & 0x3)
1264                 return -EINVAL;
1265
1266         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1267         if (r < 0) {
1268                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1269                 return r;
1270         }
1271
1272         while (size) {
1273                 u32 value = adev->gfx.gfx_off_state;
1274
1275                 r = put_user(value, (u32 *)buf);
1276                 if (r)
1277                         goto out;
1278
1279                 result += 4;
1280                 buf += 4;
1281                 *pos += 4;
1282                 size -= 4;
1283         }
1284
1285         r = result;
1286 out:
1287         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1288         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1289
1290         return r;
1291 }
1292
1293 static ssize_t amdgpu_debugfs_gfxoff_status_read(struct file *f, char __user *buf,
1294                                                  size_t size, loff_t *pos)
1295 {
1296         struct amdgpu_device *adev = file_inode(f)->i_private;
1297         ssize_t result = 0;
1298         int r;
1299
1300         if (size & 0x3 || *pos & 0x3)
1301                 return -EINVAL;
1302
1303         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1304         if (r < 0) {
1305                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1306                 return r;
1307         }
1308
1309         while (size) {
1310                 u32 value;
1311
1312                 r = amdgpu_get_gfx_off_status(adev, &value);
1313                 if (r)
1314                         goto out;
1315
1316                 r = put_user(value, (u32 *)buf);
1317                 if (r)
1318                         goto out;
1319
1320                 result += 4;
1321                 buf += 4;
1322                 *pos += 4;
1323                 size -= 4;
1324         }
1325
1326         r = result;
1327 out:
1328         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1329         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1330
1331         return r;
1332 }
1333
1334 static const struct file_operations amdgpu_debugfs_regs2_fops = {
1335         .owner = THIS_MODULE,
1336         .unlocked_ioctl = amdgpu_debugfs_regs2_ioctl,
1337         .read = amdgpu_debugfs_regs2_read,
1338         .write = amdgpu_debugfs_regs2_write,
1339         .open = amdgpu_debugfs_regs2_open,
1340         .release = amdgpu_debugfs_regs2_release,
1341         .llseek = default_llseek
1342 };
1343
1344 static const struct file_operations amdgpu_debugfs_regs_fops = {
1345         .owner = THIS_MODULE,
1346         .read = amdgpu_debugfs_regs_read,
1347         .write = amdgpu_debugfs_regs_write,
1348         .llseek = default_llseek
1349 };
1350 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1351         .owner = THIS_MODULE,
1352         .read = amdgpu_debugfs_regs_didt_read,
1353         .write = amdgpu_debugfs_regs_didt_write,
1354         .llseek = default_llseek
1355 };
1356 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1357         .owner = THIS_MODULE,
1358         .read = amdgpu_debugfs_regs_pcie_read,
1359         .write = amdgpu_debugfs_regs_pcie_write,
1360         .llseek = default_llseek
1361 };
1362 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1363         .owner = THIS_MODULE,
1364         .read = amdgpu_debugfs_regs_smc_read,
1365         .write = amdgpu_debugfs_regs_smc_write,
1366         .llseek = default_llseek
1367 };
1368
1369 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1370         .owner = THIS_MODULE,
1371         .read = amdgpu_debugfs_gca_config_read,
1372         .llseek = default_llseek
1373 };
1374
1375 static const struct file_operations amdgpu_debugfs_sensors_fops = {
1376         .owner = THIS_MODULE,
1377         .read = amdgpu_debugfs_sensor_read,
1378         .llseek = default_llseek
1379 };
1380
1381 static const struct file_operations amdgpu_debugfs_wave_fops = {
1382         .owner = THIS_MODULE,
1383         .read = amdgpu_debugfs_wave_read,
1384         .llseek = default_llseek
1385 };
1386 static const struct file_operations amdgpu_debugfs_gpr_fops = {
1387         .owner = THIS_MODULE,
1388         .read = amdgpu_debugfs_gpr_read,
1389         .llseek = default_llseek
1390 };
1391
1392 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1393         .owner = THIS_MODULE,
1394         .read = amdgpu_debugfs_gfxoff_read,
1395         .write = amdgpu_debugfs_gfxoff_write,
1396         .llseek = default_llseek
1397 };
1398
1399 static const struct file_operations amdgpu_debugfs_gfxoff_status_fops = {
1400         .owner = THIS_MODULE,
1401         .read = amdgpu_debugfs_gfxoff_status_read,
1402         .llseek = default_llseek
1403 };
1404
1405 static const struct file_operations amdgpu_debugfs_gfxoff_count_fops = {
1406         .owner = THIS_MODULE,
1407         .read = amdgpu_debugfs_gfxoff_count_read,
1408         .llseek = default_llseek
1409 };
1410
1411 static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = {
1412         .owner = THIS_MODULE,
1413         .read = amdgpu_debugfs_gfxoff_residency_read,
1414         .write = amdgpu_debugfs_gfxoff_residency_write,
1415         .llseek = default_llseek
1416 };
1417
1418 static const struct file_operations *debugfs_regs[] = {
1419         &amdgpu_debugfs_regs_fops,
1420         &amdgpu_debugfs_regs2_fops,
1421         &amdgpu_debugfs_regs_didt_fops,
1422         &amdgpu_debugfs_regs_pcie_fops,
1423         &amdgpu_debugfs_regs_smc_fops,
1424         &amdgpu_debugfs_gca_config_fops,
1425         &amdgpu_debugfs_sensors_fops,
1426         &amdgpu_debugfs_wave_fops,
1427         &amdgpu_debugfs_gpr_fops,
1428         &amdgpu_debugfs_gfxoff_fops,
1429         &amdgpu_debugfs_gfxoff_status_fops,
1430         &amdgpu_debugfs_gfxoff_count_fops,
1431         &amdgpu_debugfs_gfxoff_residency_fops,
1432 };
1433
1434 static const char * const debugfs_regs_names[] = {
1435         "amdgpu_regs",
1436         "amdgpu_regs2",
1437         "amdgpu_regs_didt",
1438         "amdgpu_regs_pcie",
1439         "amdgpu_regs_smc",
1440         "amdgpu_gca_config",
1441         "amdgpu_sensors",
1442         "amdgpu_wave",
1443         "amdgpu_gpr",
1444         "amdgpu_gfxoff",
1445         "amdgpu_gfxoff_status",
1446         "amdgpu_gfxoff_count",
1447         "amdgpu_gfxoff_residency",
1448 };
1449
1450 /**
1451  * amdgpu_debugfs_regs_init -   Initialize debugfs entries that provide
1452  *                              register access.
1453  *
1454  * @adev: The device to attach the debugfs entries to
1455  */
1456 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1457 {
1458         struct drm_minor *minor = adev_to_drm(adev)->primary;
1459         struct dentry *ent, *root = minor->debugfs_root;
1460         unsigned int i;
1461
1462         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1463                 ent = debugfs_create_file(debugfs_regs_names[i],
1464                                           S_IFREG | 0444, root,
1465                                           adev, debugfs_regs[i]);
1466                 if (!i && !IS_ERR_OR_NULL(ent))
1467                         i_size_write(ent->d_inode, adev->rmmio_size);
1468         }
1469
1470         return 0;
1471 }
1472
1473 static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)
1474 {
1475         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1476         struct drm_device *dev = adev_to_drm(adev);
1477         int r = 0, i;
1478
1479         r = pm_runtime_get_sync(dev->dev);
1480         if (r < 0) {
1481                 pm_runtime_put_autosuspend(dev->dev);
1482                 return r;
1483         }
1484
1485         /* Avoid accidently unparking the sched thread during GPU reset */
1486         r = down_write_killable(&adev->reset_domain->sem);
1487         if (r)
1488                 return r;
1489
1490         /* hold on the scheduler */
1491         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1492                 struct amdgpu_ring *ring = adev->rings[i];
1493
1494                 if (!ring || !ring->sched.thread)
1495                         continue;
1496                 kthread_park(ring->sched.thread);
1497         }
1498
1499         seq_puts(m, "run ib test:\n");
1500         r = amdgpu_ib_ring_tests(adev);
1501         if (r)
1502                 seq_printf(m, "ib ring tests failed (%d).\n", r);
1503         else
1504                 seq_puts(m, "ib ring tests passed.\n");
1505
1506         /* go on the scheduler */
1507         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1508                 struct amdgpu_ring *ring = adev->rings[i];
1509
1510                 if (!ring || !ring->sched.thread)
1511                         continue;
1512                 kthread_unpark(ring->sched.thread);
1513         }
1514
1515         up_write(&adev->reset_domain->sem);
1516
1517         pm_runtime_mark_last_busy(dev->dev);
1518         pm_runtime_put_autosuspend(dev->dev);
1519
1520         return 0;
1521 }
1522
1523 static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
1524 {
1525         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1526         struct drm_device *dev = adev_to_drm(adev);
1527         int r;
1528
1529         r = pm_runtime_get_sync(dev->dev);
1530         if (r < 0) {
1531                 pm_runtime_put_autosuspend(dev->dev);
1532                 return r;
1533         }
1534
1535         *val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
1536
1537         pm_runtime_mark_last_busy(dev->dev);
1538         pm_runtime_put_autosuspend(dev->dev);
1539
1540         return 0;
1541 }
1542
1543
1544 static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
1545 {
1546         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1547         struct drm_device *dev = adev_to_drm(adev);
1548         int r;
1549
1550         r = pm_runtime_get_sync(dev->dev);
1551         if (r < 0) {
1552                 pm_runtime_put_autosuspend(dev->dev);
1553                 return r;
1554         }
1555
1556         *val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);
1557
1558         pm_runtime_mark_last_busy(dev->dev);
1559         pm_runtime_put_autosuspend(dev->dev);
1560
1561         return 0;
1562 }
1563
1564 static int amdgpu_debugfs_benchmark(void *data, u64 val)
1565 {
1566         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1567         struct drm_device *dev = adev_to_drm(adev);
1568         int r;
1569
1570         r = pm_runtime_get_sync(dev->dev);
1571         if (r < 0) {
1572                 pm_runtime_put_autosuspend(dev->dev);
1573                 return r;
1574         }
1575
1576         r = amdgpu_benchmark(adev, val);
1577
1578         pm_runtime_mark_last_busy(dev->dev);
1579         pm_runtime_put_autosuspend(dev->dev);
1580
1581         return r;
1582 }
1583
1584 static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
1585 {
1586         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1587         struct drm_device *dev = adev_to_drm(adev);
1588         struct drm_file *file;
1589         int r;
1590
1591         r = mutex_lock_interruptible(&dev->filelist_mutex);
1592         if (r)
1593                 return r;
1594
1595         list_for_each_entry(file, &dev->filelist, lhead) {
1596                 struct amdgpu_fpriv *fpriv = file->driver_priv;
1597                 struct amdgpu_vm *vm = &fpriv->vm;
1598
1599                 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1600                                 vm->task_info.pid, vm->task_info.process_name);
1601                 r = amdgpu_bo_reserve(vm->root.bo, true);
1602                 if (r)
1603                         break;
1604                 amdgpu_debugfs_vm_bo_info(vm, m);
1605                 amdgpu_bo_unreserve(vm->root.bo);
1606         }
1607
1608         mutex_unlock(&dev->filelist_mutex);
1609
1610         return r;
1611 }
1612
1613 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib);
1614 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info);
1615 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
1616                          NULL, "%lld\n");
1617 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
1618                          NULL, "%lld\n");
1619 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark,
1620                          "%lld\n");
1621
1622 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1623                                           struct dma_fence **fences)
1624 {
1625         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1626         uint32_t sync_seq, last_seq;
1627
1628         last_seq = atomic_read(&ring->fence_drv.last_seq);
1629         sync_seq = ring->fence_drv.sync_seq;
1630
1631         last_seq &= drv->num_fences_mask;
1632         sync_seq &= drv->num_fences_mask;
1633
1634         do {
1635                 struct dma_fence *fence, **ptr;
1636
1637                 ++last_seq;
1638                 last_seq &= drv->num_fences_mask;
1639                 ptr = &drv->fences[last_seq];
1640
1641                 fence = rcu_dereference_protected(*ptr, 1);
1642                 RCU_INIT_POINTER(*ptr, NULL);
1643
1644                 if (!fence)
1645                         continue;
1646
1647                 fences[last_seq] = fence;
1648
1649         } while (last_seq != sync_seq);
1650 }
1651
1652 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1653                                             int length)
1654 {
1655         int i;
1656         struct dma_fence *fence;
1657
1658         for (i = 0; i < length; i++) {
1659                 fence = fences[i];
1660                 if (!fence)
1661                         continue;
1662                 dma_fence_signal(fence);
1663                 dma_fence_put(fence);
1664         }
1665 }
1666
1667 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1668 {
1669         struct drm_sched_job *s_job;
1670         struct dma_fence *fence;
1671
1672         spin_lock(&sched->job_list_lock);
1673         list_for_each_entry(s_job, &sched->pending_list, list) {
1674                 fence = sched->ops->run_job(s_job);
1675                 dma_fence_put(fence);
1676         }
1677         spin_unlock(&sched->job_list_lock);
1678 }
1679
1680 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1681 {
1682         struct amdgpu_job *job;
1683         struct drm_sched_job *s_job, *tmp;
1684         uint32_t preempt_seq;
1685         struct dma_fence *fence, **ptr;
1686         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1687         struct drm_gpu_scheduler *sched = &ring->sched;
1688         bool preempted = true;
1689
1690         if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1691                 return;
1692
1693         preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1694         if (preempt_seq <= atomic_read(&drv->last_seq)) {
1695                 preempted = false;
1696                 goto no_preempt;
1697         }
1698
1699         preempt_seq &= drv->num_fences_mask;
1700         ptr = &drv->fences[preempt_seq];
1701         fence = rcu_dereference_protected(*ptr, 1);
1702
1703 no_preempt:
1704         spin_lock(&sched->job_list_lock);
1705         list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
1706                 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1707                         /* remove job from ring_mirror_list */
1708                         list_del_init(&s_job->list);
1709                         sched->ops->free_job(s_job);
1710                         continue;
1711                 }
1712                 job = to_amdgpu_job(s_job);
1713                 if (preempted && (&job->hw_fence) == fence)
1714                         /* mark the job as preempted */
1715                         job->preemption_status |= AMDGPU_IB_PREEMPTED;
1716         }
1717         spin_unlock(&sched->job_list_lock);
1718 }
1719
1720 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1721 {
1722         int r, length;
1723         struct amdgpu_ring *ring;
1724         struct dma_fence **fences = NULL;
1725         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1726
1727         if (val >= AMDGPU_MAX_RINGS)
1728                 return -EINVAL;
1729
1730         ring = adev->rings[val];
1731
1732         if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1733                 return -EINVAL;
1734
1735         /* the last preemption failed */
1736         if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1737                 return -EBUSY;
1738
1739         length = ring->fence_drv.num_fences_mask + 1;
1740         fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1741         if (!fences)
1742                 return -ENOMEM;
1743
1744         /* Avoid accidently unparking the sched thread during GPU reset */
1745         r = down_read_killable(&adev->reset_domain->sem);
1746         if (r)
1747                 goto pro_end;
1748
1749         /* stop the scheduler */
1750         kthread_park(ring->sched.thread);
1751
1752         /* preempt the IB */
1753         r = amdgpu_ring_preempt_ib(ring);
1754         if (r) {
1755                 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1756                 goto failure;
1757         }
1758
1759         amdgpu_fence_process(ring);
1760
1761         if (atomic_read(&ring->fence_drv.last_seq) !=
1762             ring->fence_drv.sync_seq) {
1763                 DRM_INFO("ring %d was preempted\n", ring->idx);
1764
1765                 amdgpu_ib_preempt_mark_partial_job(ring);
1766
1767                 /* swap out the old fences */
1768                 amdgpu_ib_preempt_fences_swap(ring, fences);
1769
1770                 amdgpu_fence_driver_force_completion(ring);
1771
1772                 /* resubmit unfinished jobs */
1773                 amdgpu_ib_preempt_job_recovery(&ring->sched);
1774
1775                 /* wait for jobs finished */
1776                 amdgpu_fence_wait_empty(ring);
1777
1778                 /* signal the old fences */
1779                 amdgpu_ib_preempt_signal_fences(fences, length);
1780         }
1781
1782 failure:
1783         /* restart the scheduler */
1784         kthread_unpark(ring->sched.thread);
1785
1786         up_read(&adev->reset_domain->sem);
1787
1788 pro_end:
1789         kfree(fences);
1790
1791         return r;
1792 }
1793
1794 static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1795 {
1796         int ret = 0;
1797         uint32_t max_freq, min_freq;
1798         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1799
1800         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1801                 return -EINVAL;
1802
1803         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1804         if (ret < 0) {
1805                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1806                 return ret;
1807         }
1808
1809         ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
1810         if (ret == -EOPNOTSUPP) {
1811                 ret = 0;
1812                 goto out;
1813         }
1814         if (ret || val > max_freq || val < min_freq) {
1815                 ret = -EINVAL;
1816                 goto out;
1817         }
1818
1819         ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
1820         if (ret)
1821                 ret = -EINVAL;
1822
1823 out:
1824         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1825         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1826
1827         return ret;
1828 }
1829
1830 DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
1831                         amdgpu_debugfs_ib_preempt, "%llu\n");
1832
1833 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
1834                         amdgpu_debugfs_sclk_set, "%llu\n");
1835
1836 static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
1837                                 char __user *buf, size_t size, loff_t *pos)
1838 {
1839         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1840         char reg_offset[12];
1841         int i, ret, len = 0;
1842
1843         if (*pos)
1844                 return 0;
1845
1846         memset(reg_offset, 0, 12);
1847         ret = down_read_killable(&adev->reset_domain->sem);
1848         if (ret)
1849                 return ret;
1850
1851         for (i = 0; i < adev->num_regs; i++) {
1852                 sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
1853                 up_read(&adev->reset_domain->sem);
1854                 if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
1855                         return -EFAULT;
1856
1857                 len += strlen(reg_offset);
1858                 ret = down_read_killable(&adev->reset_domain->sem);
1859                 if (ret)
1860                         return ret;
1861         }
1862
1863         up_read(&adev->reset_domain->sem);
1864         *pos += len;
1865
1866         return len;
1867 }
1868
1869 static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
1870                         const char __user *buf, size_t size, loff_t *pos)
1871 {
1872         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
1873         char reg_offset[11];
1874         uint32_t *new = NULL, *tmp = NULL;
1875         int ret, i = 0, len = 0;
1876
1877         do {
1878                 memset(reg_offset, 0, 11);
1879                 if (copy_from_user(reg_offset, buf + len,
1880                                         min(10, ((int)size-len)))) {
1881                         ret = -EFAULT;
1882                         goto error_free;
1883                 }
1884
1885                 new = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
1886                 if (!new) {
1887                         ret = -ENOMEM;
1888                         goto error_free;
1889                 }
1890                 tmp = new;
1891                 if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
1892                         ret = -EINVAL;
1893                         goto error_free;
1894                 }
1895
1896                 len += ret;
1897                 i++;
1898         } while (len < size);
1899
1900         new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
1901         if (!new) {
1902                 ret = -ENOMEM;
1903                 goto error_free;
1904         }
1905         ret = down_write_killable(&adev->reset_domain->sem);
1906         if (ret)
1907                 goto error_free;
1908
1909         swap(adev->reset_dump_reg_list, tmp);
1910         swap(adev->reset_dump_reg_value, new);
1911         adev->num_regs = i;
1912         up_write(&adev->reset_domain->sem);
1913         ret = size;
1914
1915 error_free:
1916         if (tmp != new)
1917                 kfree(tmp);
1918         kfree(new);
1919         return ret;
1920 }
1921
1922 static const struct file_operations amdgpu_reset_dump_register_list = {
1923         .owner = THIS_MODULE,
1924         .read = amdgpu_reset_dump_register_list_read,
1925         .write = amdgpu_reset_dump_register_list_write,
1926         .llseek = default_llseek
1927 };
1928
1929 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1930 {
1931         struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
1932         struct dentry *ent;
1933         int r, i;
1934
1935         if (!debugfs_initialized())
1936                 return 0;
1937
1938         debugfs_create_x32("amdgpu_smu_debug", 0600, root,
1939                            &adev->pm.smu_debug_mask);
1940
1941         ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
1942                                   &fops_ib_preempt);
1943         if (IS_ERR(ent)) {
1944                 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1945                 return PTR_ERR(ent);
1946         }
1947
1948         ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
1949                                   &fops_sclk_set);
1950         if (IS_ERR(ent)) {
1951                 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1952                 return PTR_ERR(ent);
1953         }
1954
1955         /* Register debugfs entries for amdgpu_ttm */
1956         amdgpu_ttm_debugfs_init(adev);
1957         amdgpu_debugfs_pm_init(adev);
1958         amdgpu_debugfs_sa_init(adev);
1959         amdgpu_debugfs_fence_init(adev);
1960         amdgpu_debugfs_gem_init(adev);
1961
1962         r = amdgpu_debugfs_regs_init(adev);
1963         if (r)
1964                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1965
1966         amdgpu_debugfs_firmware_init(adev);
1967         amdgpu_ta_if_debugfs_init(adev);
1968
1969 #if defined(CONFIG_DRM_AMD_DC)
1970         if (adev->dc_enabled)
1971                 dtn_debugfs_init(adev);
1972 #endif
1973
1974         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1975                 struct amdgpu_ring *ring = adev->rings[i];
1976
1977                 if (!ring)
1978                         continue;
1979
1980                 amdgpu_debugfs_ring_init(adev, ring);
1981         }
1982
1983         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1984                 if (!amdgpu_vcnfw_log)
1985                         break;
1986
1987                 if (adev->vcn.harvest_config & (1 << i))
1988                         continue;
1989
1990                 amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
1991         }
1992
1993         amdgpu_ras_debugfs_create_all(adev);
1994         amdgpu_rap_debugfs_init(adev);
1995         amdgpu_securedisplay_debugfs_init(adev);
1996         amdgpu_fw_attestation_debugfs_init(adev);
1997
1998         debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
1999                             &amdgpu_evict_vram_fops);
2000         debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
2001                             &amdgpu_evict_gtt_fops);
2002         debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
2003                             &amdgpu_debugfs_test_ib_fops);
2004         debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
2005                             &amdgpu_debugfs_vm_info_fops);
2006         debugfs_create_file("amdgpu_benchmark", 0200, root, adev,
2007                             &amdgpu_benchmark_fops);
2008         debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
2009                             &amdgpu_reset_dump_register_list);
2010
2011         adev->debugfs_vbios_blob.data = adev->bios;
2012         adev->debugfs_vbios_blob.size = adev->bios_size;
2013         debugfs_create_blob("amdgpu_vbios", 0444, root,
2014                             &adev->debugfs_vbios_blob);
2015
2016         adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
2017         adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
2018         debugfs_create_blob("amdgpu_discovery", 0444, root,
2019                             &adev->debugfs_discovery_blob);
2020
2021         return 0;
2022 }
2023
2024 #else
2025 int amdgpu_debugfs_init(struct amdgpu_device *adev)
2026 {
2027         return 0;
2028 }
2029 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2030 {
2031         return 0;
2032 }
2033 #endif