drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "amdgpu_smu.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40
  41 #include "gc/gc_10_1_0_offset.h"
  42 #include "gc/gc_10_1_0_sh_mask.h"
  43 #include "mp/mp_11_0_offset.h"
  44
  45 #include "soc15.h"
  46 #include "soc15_common.h"
  47 #include "gmc_v10_0.h"
  48 #include "gfxhub_v2_0.h"
  49 #include "mmhub_v2_0.h"
  50 #include "nbio_v2_3.h"
  51 #include "nbio_v7_2.h"
  52 #include "hdp_v5_0.h"
  53 #include "nv.h"
  54 #include "navi10_ih.h"
  55 #include "gfx_v10_0.h"
  56 #include "sdma_v5_0.h"
  57 #include "sdma_v5_2.h"
  58 #include "vcn_v2_0.h"
  59 #include "jpeg_v2_0.h"
  60 #include "vcn_v3_0.h"
  61 #include "jpeg_v3_0.h"
  62 #include "dce_virtual.h"
  63 #include "mes_v10_1.h"
  64 #include "mxgpu_nv.h"
  65 #include "smuio_v11_0.h"
  66 #include "smuio_v11_0_6.h"
  67
  68 static const struct amd_ip_funcs nv_common_ip_funcs;
  69
  70 /* Navi */
  71 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  72 {
  73         {
  74                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
  75                 .max_width = 4096,
  76                 .max_height = 2304,
  77                 .max_pixels_per_frame = 4096 * 2304,
  78                 .max_level = 0,
  79         },
  80         {
  81                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
  82                 .max_width = 4096,
  83                 .max_height = 2304,
  84                 .max_pixels_per_frame = 4096 * 2304,
  85                 .max_level = 0,
  86         },
  87 };
  88
  89 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  90 {
  91         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  92         .codec_array = nv_video_codecs_encode_array,
  93 };
  94
  95 /* Navi1x */
  96 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  97 {
  98         {
  99                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 100                 .max_width = 4096,
 101                 .max_height = 4096,
 102                 .max_pixels_per_frame = 4096 * 4096,
 103                 .max_level = 3,
 104         },
 105         {
 106                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 107                 .max_width = 4096,
 108                 .max_height = 4096,
 109                 .max_pixels_per_frame = 4096 * 4096,
 110                 .max_level = 5,
 111         },
 112         {
 113                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 114                 .max_width = 4096,
 115                 .max_height = 4096,
 116                 .max_pixels_per_frame = 4096 * 4096,
 117                 .max_level = 52,
 118         },
 119         {
 120                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 121                 .max_width = 4096,
 122                 .max_height = 4096,
 123                 .max_pixels_per_frame = 4096 * 4096,
 124                 .max_level = 4,
 125         },
 126         {
 127                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 128                 .max_width = 8192,
 129                 .max_height = 4352,
 130                 .max_pixels_per_frame = 8192 * 4352,
 131                 .max_level = 186,
 132         },
 133         {
 134                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 135                 .max_width = 4096,
 136                 .max_height = 4096,
 137                 .max_pixels_per_frame = 4096 * 4096,
 138                 .max_level = 0,
 139         },
 140         {
 141                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 142                 .max_width = 8192,
 143                 .max_height = 4352,
 144                 .max_pixels_per_frame = 8192 * 4352,
 145                 .max_level = 0,
 146         },
 147 };
 148
 149 static const struct amdgpu_video_codecs nv_video_codecs_decode =
 150 {
 151         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
 152         .codec_array = nv_video_codecs_decode_array,
 153 };
 154
 155 /* Sienna Cichlid */
 156 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 157 {
 158         {
 159                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 160                 .max_width = 4096,
 161                 .max_height = 4096,
 162                 .max_pixels_per_frame = 4096 * 4096,
 163                 .max_level = 3,
 164         },
 165         {
 166                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 167                 .max_width = 4096,
 168                 .max_height = 4096,
 169                 .max_pixels_per_frame = 4096 * 4096,
 170                 .max_level = 5,
 171         },
 172         {
 173                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 174                 .max_width = 4096,
 175                 .max_height = 4096,
 176                 .max_pixels_per_frame = 4096 * 4096,
 177                 .max_level = 52,
 178         },
 179         {
 180                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 181                 .max_width = 4096,
 182                 .max_height = 4096,
 183                 .max_pixels_per_frame = 4096 * 4096,
 184                 .max_level = 4,
 185         },
 186         {
 187                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 188                 .max_width = 8192,
 189                 .max_height = 4352,
 190                 .max_pixels_per_frame = 8192 * 4352,
 191                 .max_level = 186,
 192         },
 193         {
 194                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 195                 .max_width = 4096,
 196                 .max_height = 4096,
 197                 .max_pixels_per_frame = 4096 * 4096,
 198                 .max_level = 0,
 199         },
 200         {
 201                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 202                 .max_width = 8192,
 203                 .max_height = 4352,
 204                 .max_pixels_per_frame = 8192 * 4352,
 205                 .max_level = 0,
 206         },
 207         {
 208                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
 209                 .max_width = 8192,
 210                 .max_height = 4352,
 211                 .max_pixels_per_frame = 8192 * 4352,
 212                 .max_level = 0,
 213         },
 214 };
 215
 216 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 217 {
 218         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 219         .codec_array = sc_video_codecs_decode_array,
 220 };
 221
 222 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 223                                  const struct amdgpu_video_codecs **codecs)
 224 {
 225         switch (adev->asic_type) {
 226         case CHIP_SIENNA_CICHLID:
 227         case CHIP_NAVY_FLOUNDER:
 228         case CHIP_DIMGREY_CAVEFISH:
 229         case CHIP_VANGOGH:
 230                 if (encode)
 231                         *codecs = &nv_video_codecs_encode;
 232                 else
 233                         *codecs = &sc_video_codecs_decode;
 234                 return 0;
 235         case CHIP_NAVI10:
 236         case CHIP_NAVI14:
 237         case CHIP_NAVI12:
 238                 if (encode)
 239                         *codecs = &nv_video_codecs_encode;
 240                 else
 241                         *codecs = &nv_video_codecs_decode;
 242                 return 0;
 243         default:
 244                 return -EINVAL;
 245         }
 246 }
 247
 248 /*
 249  * Indirect registers accessor
 250  */
 251 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 252 {
 253         unsigned long address, data;
 254         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 255         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 256
 257         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 258 }
 259
 260 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 261 {
 262         unsigned long address, data;
 263
 264         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 265         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 266
 267         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 268 }
 269
 270 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 271 {
 272         unsigned long address, data;
 273         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 274         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 275
 276         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 277 }
 278
 279 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 280 {
 281         unsigned long flags, address, data;
 282         u32 r;
 283         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 284         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 285
 286         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 287         WREG32(address, reg * 4);
 288         (void)RREG32(address);
 289         r = RREG32(data);
 290         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 291         return r;
 292 }
 293
 294 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 295 {
 296         unsigned long address, data;
 297
 298         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 299         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 300
 301         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 302 }
 303
 304 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 305 {
 306         unsigned long flags, address, data;
 307
 308         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 309         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 310
 311         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 312         WREG32(address, reg * 4);
 313         (void)RREG32(address);
 314         WREG32(data, v);
 315         (void)RREG32(data);
 316         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 317 }
 318
 319 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 320 {
 321         unsigned long flags, address, data;
 322         u32 r;
 323
 324         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 325         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 326
 327         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 328         WREG32(address, (reg));
 329         r = RREG32(data);
 330         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 331         return r;
 332 }
 333
 334 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 335 {
 336         unsigned long flags, address, data;
 337
 338         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 339         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 340
 341         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 342         WREG32(address, (reg));
 343         WREG32(data, (v));
 344         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 345 }
 346
 347 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 348 {
 349         return adev->nbio.funcs->get_memsize(adev);
 350 }
 351
 352 static u32 nv_get_xclk(struct amdgpu_device *adev)
 353 {
 354         return adev->clock.spll.reference_freq;
 355 }
 356
 357
 358 void nv_grbm_select(struct amdgpu_device *adev,
 359                      u32 me, u32 pipe, u32 queue, u32 vmid)
 360 {
 361         u32 grbm_gfx_cntl = 0;
 362         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 363         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 364         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 365         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 366
 367         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 368 }
 369
 370 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 371 {
 372         /* todo */
 373 }
 374
 375 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 376 {
 377         /* todo */
 378         return false;
 379 }
 380
 381 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 382                                   u8 *bios, u32 length_bytes)
 383 {
 384         u32 *dw_ptr;
 385         u32 i, length_dw;
 386         u32 rom_index_offset, rom_data_offset;
 387
 388         if (bios == NULL)
 389                 return false;
 390         if (length_bytes == 0)
 391                 return false;
 392         /* APU vbios image is part of sbios image */
 393         if (adev->flags & AMD_IS_APU)
 394                 return false;
 395
 396         dw_ptr = (u32 *)bios;
 397         length_dw = ALIGN(length_bytes, 4) / 4;
 398
 399         rom_index_offset =
 400                 adev->smuio.funcs->get_rom_index_offset(adev);
 401         rom_data_offset =
 402                 adev->smuio.funcs->get_rom_data_offset(adev);
 403
 404         /* set rom index to 0 */
 405         WREG32(rom_index_offset, 0);
 406         /* read out the rom data */
 407         for (i = 0; i < length_dw; i++)
 408                 dw_ptr[i] = RREG32(rom_data_offset);
 409
 410         return true;
 411 }
 412
 413 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 414         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 415         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 416         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 417         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 418         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 419         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 420         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 421         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 422         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 423         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 424         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 425         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 426         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 427         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 428         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 429         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 430         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 431         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 432         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 433 };
 434
 435 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 436                                          u32 sh_num, u32 reg_offset)
 437 {
 438         uint32_t val;
 439
 440         mutex_lock(&adev->grbm_idx_mutex);
 441         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 442                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 443
 444         val = RREG32(reg_offset);
 445
 446         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 447                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 448         mutex_unlock(&adev->grbm_idx_mutex);
 449         return val;
 450 }
 451
 452 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 453                                       bool indexed, u32 se_num,
 454                                       u32 sh_num, u32 reg_offset)
 455 {
 456         if (indexed) {
 457                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 458         } else {
 459                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 460                         return adev->gfx.config.gb_addr_config;
 461                 return RREG32(reg_offset);
 462         }
 463 }
 464
 465 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 466                             u32 sh_num, u32 reg_offset, u32 *value)
 467 {
 468         uint32_t i;
 469         struct soc15_allowed_register_entry  *en;
 470
 471         *value = 0;
 472         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 473                 en = &nv_allowed_read_registers[i];
 474                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 475                     reg_offset !=
 476                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 477                         continue;
 478
 479                 *value = nv_get_register_value(adev,
 480                                                nv_allowed_read_registers[i].grbm_indexed,
 481                                                se_num, sh_num, reg_offset);
 482                 return 0;
 483         }
 484         return -EINVAL;
 485 }
 486
 487 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 488 {
 489         u32 i;
 490         int ret = 0;
 491
 492         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 493
 494         /* disable BM */
 495         pci_clear_master(adev->pdev);
 496
 497         amdgpu_device_cache_pci_state(adev->pdev);
 498
 499         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 500                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 501                 ret = amdgpu_dpm_mode1_reset(adev);
 502         } else {
 503                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 504                 ret = psp_gpu_reset(adev);
 505         }
 506
 507         if (ret)
 508                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 509         amdgpu_device_load_pci_state(adev->pdev);
 510
 511         /* wait for asic to come out of reset */
 512         for (i = 0; i < adev->usec_timeout; i++) {
 513                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 514
 515                 if (memsize != 0xffffffff)
 516                         break;
 517                 udelay(1);
 518         }
 519
 520         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 521
 522         return ret;
 523 }
 524
 525 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 526 {
 527         u32 i;
 528         int ret = 0;
 529
 530         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 531
 532         /* disable BM */
 533         pci_clear_master(adev->pdev);
 534
 535         amdgpu_device_cache_pci_state(adev->pdev);
 536
 537         ret = amdgpu_dpm_mode2_reset(adev);
 538         if (ret)
 539                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 540
 541         amdgpu_device_load_pci_state(adev->pdev);
 542
 543         /* wait for asic to come out of reset */
 544         for (i = 0; i < adev->usec_timeout; i++) {
 545                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 546
 547                 if (memsize != 0xffffffff)
 548                         break;
 549                 udelay(1);
 550         }
 551
 552         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 553
 554         return ret;
 555 }
 556
 557 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 558 {
 559         struct smu_context *smu = &adev->smu;
 560
 561         if (smu_baco_is_support(smu))
 562                 return true;
 563         else
 564                 return false;
 565 }
 566
 567 static enum amd_reset_method
 568 nv_asic_reset_method(struct amdgpu_device *adev)
 569 {
 570         struct smu_context *smu = &adev->smu;
 571
 572         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 573             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 574             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 575             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 576                 return amdgpu_reset_method;
 577
 578         if (amdgpu_reset_method != -1)
 579                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 580                                   amdgpu_reset_method);
 581
 582         switch (adev->asic_type) {
 583         case CHIP_VANGOGH:
 584                 return AMD_RESET_METHOD_MODE2;
 585         case CHIP_SIENNA_CICHLID:
 586         case CHIP_NAVY_FLOUNDER:
 587         case CHIP_DIMGREY_CAVEFISH:
 588                 return AMD_RESET_METHOD_MODE1;
 589         default:
 590                 if (smu_baco_is_support(smu))
 591                         return AMD_RESET_METHOD_BACO;
 592                 else
 593                         return AMD_RESET_METHOD_MODE1;
 594         }
 595 }
 596
 597 static int nv_asic_reset(struct amdgpu_device *adev)
 598 {
 599         int ret = 0;
 600         struct smu_context *smu = &adev->smu;
 601
 602         /* skip reset on vangogh for now */
 603         if (adev->asic_type == CHIP_VANGOGH)
 604                 return 0;
 605
 606         switch (nv_asic_reset_method(adev)) {
 607         case AMD_RESET_METHOD_PCI:
 608                 dev_info(adev->dev, "PCI reset\n");
 609                 ret = amdgpu_device_pci_reset(adev);
 610                 break;
 611         case AMD_RESET_METHOD_BACO:
 612                 dev_info(adev->dev, "BACO reset\n");
 613
 614                 ret = smu_baco_enter(smu);
 615                 if (ret)
 616                         return ret;
 617                 ret = smu_baco_exit(smu);
 618                 if (ret)
 619                         return ret;
 620                 break;
 621         case AMD_RESET_METHOD_MODE2:
 622                 dev_info(adev->dev, "MODE2 reset\n");
 623                 ret = nv_asic_mode2_reset(adev);
 624                 break;
 625         default:
 626                 dev_info(adev->dev, "MODE1 reset\n");
 627                 ret = nv_asic_mode1_reset(adev);
 628                 break;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 635 {
 636         /* todo */
 637         return 0;
 638 }
 639
 640 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 641 {
 642         /* todo */
 643         return 0;
 644 }
 645
 646 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 647 {
 648         if (pci_is_root_bus(adev->pdev->bus))
 649                 return;
 650
 651         if (amdgpu_pcie_gen2 == 0)
 652                 return;
 653
 654         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 655                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 656                 return;
 657
 658         /* todo */
 659 }
 660
 661 static void nv_program_aspm(struct amdgpu_device *adev)
 662 {
 663         if (amdgpu_aspm != 1)
 664                 return;
 665
 666         if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
 667             !(adev->flags & AMD_IS_APU) &&
 668             (adev->nbio.funcs->program_aspm))
 669                 adev->nbio.funcs->program_aspm(adev);
 670
 671 }
 672
 673 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 674                                         bool enable)
 675 {
 676         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 677         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 678 }
 679
 680 static const struct amdgpu_ip_block_version nv_common_ip_block =
 681 {
 682         .type = AMD_IP_BLOCK_TYPE_COMMON,
 683         .major = 1,
 684         .minor = 0,
 685         .rev = 0,
 686         .funcs = &nv_common_ip_funcs,
 687 };
 688
 689 static int nv_reg_base_init(struct amdgpu_device *adev)
 690 {
 691         int r;
 692
 693         if (amdgpu_discovery) {
 694                 r = amdgpu_discovery_reg_base_init(adev);
 695                 if (r) {
 696                         DRM_WARN("failed to init reg base from ip discovery table, "
 697                                         "fallback to legacy init method\n");
 698                         goto legacy_init;
 699                 }
 700
 701                 return 0;
 702         }
 703
 704 legacy_init:
 705         switch (adev->asic_type) {
 706         case CHIP_NAVI10:
 707                 navi10_reg_base_init(adev);
 708                 break;
 709         case CHIP_NAVI14:
 710                 navi14_reg_base_init(adev);
 711                 break;
 712         case CHIP_NAVI12:
 713                 navi12_reg_base_init(adev);
 714                 break;
 715         case CHIP_SIENNA_CICHLID:
 716         case CHIP_NAVY_FLOUNDER:
 717                 sienna_cichlid_reg_base_init(adev);
 718                 break;
 719         case CHIP_VANGOGH:
 720                 vangogh_reg_base_init(adev);
 721                 break;
 722         case CHIP_DIMGREY_CAVEFISH:
 723                 dimgrey_cavefish_reg_base_init(adev);
 724                 break;
 725         default:
 726                 return -EINVAL;
 727         }
 728
 729         return 0;
 730 }
 731
 732 void nv_set_virt_ops(struct amdgpu_device *adev)
 733 {
 734         adev->virt.ops = &xgpu_nv_virt_ops;
 735 }
 736
 737 static bool nv_is_headless_sku(struct pci_dev *pdev)
 738 {
 739         if ((pdev->device == 0x731E &&
 740             (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
 741             (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||
 742             (pdev->device == 0x7360 && pdev->revision == 0xC7))
 743                 return true;
 744         return false;
 745 }
 746
 747 int nv_set_ip_blocks(struct amdgpu_device *adev)
 748 {
 749         int r;
 750
 751         if (adev->flags & AMD_IS_APU) {
 752                 adev->nbio.funcs = &nbio_v7_2_funcs;
 753                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
 754         } else {
 755                 adev->nbio.funcs = &nbio_v2_3_funcs;
 756                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 757         }
 758         adev->hdp.funcs = &hdp_v5_0_funcs;
 759
 760         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 761                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
 762         else
 763                 adev->smuio.funcs = &smuio_v11_0_funcs;
 764
 765         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 766                 adev->gmc.xgmi.supported = true;
 767
 768         /* Set IP register base before any HW register access */
 769         r = nv_reg_base_init(adev);
 770         if (r)
 771                 return r;
 772
 773         switch (adev->asic_type) {
 774         case CHIP_NAVI10:
 775         case CHIP_NAVI14:
 776                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 777                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 778                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 779                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 780                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 781                     !amdgpu_sriov_vf(adev))
 782                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 783                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 784                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 785 #if defined(CONFIG_DRM_AMD_DC)
 786                 else if (amdgpu_device_has_dc_support(adev))
 787                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 788 #endif
 789                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 790                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 791                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 792                     !amdgpu_sriov_vf(adev))
 793                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 794                 if (!nv_is_headless_sku(adev->pdev))
 795                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 796                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 797                 if (adev->enable_mes)
 798                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 799                 break;
 800         case CHIP_NAVI12:
 801                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 802                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 803                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 804                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 805                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 806                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 807                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 808                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 809 #if defined(CONFIG_DRM_AMD_DC)
 810                 else if (amdgpu_device_has_dc_support(adev))
 811                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 812 #endif
 813                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 814                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 815                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 816                     !amdgpu_sriov_vf(adev))
 817                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 818                 if (!nv_is_headless_sku(adev->pdev))
 819                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 820                 if (!amdgpu_sriov_vf(adev))
 821                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 822                 break;
 823         case CHIP_SIENNA_CICHLID:
 824                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 825                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 826                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 827                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 828                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 829                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 830                     is_support_sw_smu(adev))
 831                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 832                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 833                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 834 #if defined(CONFIG_DRM_AMD_DC)
 835                 else if (amdgpu_device_has_dc_support(adev))
 836                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 837 #endif
 838                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 839                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 840                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 841                 if (!amdgpu_sriov_vf(adev))
 842                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 843
 844                 if (adev->enable_mes)
 845                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 846                 break;
 847         case CHIP_NAVY_FLOUNDER:
 848                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 849                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 850                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 851                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 852                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 853                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 854                     is_support_sw_smu(adev))
 855                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 856                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 857                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 858 #if defined(CONFIG_DRM_AMD_DC)
 859                 else if (amdgpu_device_has_dc_support(adev))
 860                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 861 #endif
 862                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 863                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 864                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 865                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 866                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 867                     is_support_sw_smu(adev))
 868                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 869                 break;
 870         case CHIP_VANGOGH:
 871                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 872                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 873                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 874                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 875                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 876                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 877                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 878                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 879 #if defined(CONFIG_DRM_AMD_DC)
 880                 else if (amdgpu_device_has_dc_support(adev))
 881                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 882 #endif
 883                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 884                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 885                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 886                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 887                 break;
 888         case CHIP_DIMGREY_CAVEFISH:
 889                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 890                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 891                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 892                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 893                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 894                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 895                     is_support_sw_smu(adev))
 896                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 897                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 898                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 899 #if defined(CONFIG_DRM_AMD_DC)
 900                 else if (amdgpu_device_has_dc_support(adev))
 901                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 902 #endif
 903                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 904                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 905                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 906                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 907                 break;
 908         default:
 909                 return -EINVAL;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 916 {
 917         return adev->nbio.funcs->get_rev_id(adev);
 918 }
 919
 920 static bool nv_need_full_reset(struct amdgpu_device *adev)
 921 {
 922         return true;
 923 }
 924
 925 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 926 {
 927         u32 sol_reg;
 928
 929         if (adev->flags & AMD_IS_APU)
 930                 return false;
 931
 932         /* Check sOS sign of life register to confirm sys driver and sOS
 933          * are already been loaded.
 934          */
 935         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 936         if (sol_reg)
 937                 return true;
 938
 939         return false;
 940 }
 941
 942 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 943 {
 944
 945         /* TODO
 946          * dummy implement for pcie_replay_count sysfs interface
 947          * */
 948
 949         return 0;
 950 }
 951
 952 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 953 {
 954         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 955         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 956         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 957         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 958         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 959         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 960         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 961         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 962         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 963         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 964         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 965         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 966         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 967         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 968         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 969         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 970         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 971         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 972         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 973         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 974         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 975         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 976         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 977         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 978         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 979
 980         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 981         adev->doorbell_index.sdma_doorbell_range = 20;
 982 }
 983
 984 static void nv_pre_asic_init(struct amdgpu_device *adev)
 985 {
 986 }
 987
 988 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 989                                        bool enter)
 990 {
 991         if (enter)
 992                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 993         else
 994                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 995
 996         if (adev->gfx.funcs->update_perfmon_mgcg)
 997                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 998
 999         /*
1000          * The ASPM function is not fully enabled and verified on
1001          * Navi yet. Temporarily skip this until ASPM enabled.
1002          */
1003         if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
1004             !(adev->flags & AMD_IS_APU) &&
1005             (adev->nbio.funcs->enable_aspm))
1006                 adev->nbio.funcs->enable_aspm(adev, !enter);
1007
1008         return 0;
1009 }
1010
1011 static const struct amdgpu_asic_funcs nv_asic_funcs =
1012 {
1013         .read_disabled_bios = &nv_read_disabled_bios,
1014         .read_bios_from_rom = &nv_read_bios_from_rom,
1015         .read_register = &nv_read_register,
1016         .reset = &nv_asic_reset,
1017         .reset_method = &nv_asic_reset_method,
1018         .set_vga_state = &nv_vga_set_state,
1019         .get_xclk = &nv_get_xclk,
1020         .set_uvd_clocks = &nv_set_uvd_clocks,
1021         .set_vce_clocks = &nv_set_vce_clocks,
1022         .get_config_memsize = &nv_get_config_memsize,
1023         .init_doorbell_index = &nv_init_doorbell_index,
1024         .need_full_reset = &nv_need_full_reset,
1025         .need_reset_on_init = &nv_need_reset_on_init,
1026         .get_pcie_replay_count = &nv_get_pcie_replay_count,
1027         .supports_baco = &nv_asic_supports_baco,
1028         .pre_asic_init = &nv_pre_asic_init,
1029         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
1030         .query_video_codecs = &nv_query_video_codecs,
1031 };
1032
1033 static int nv_common_early_init(void *handle)
1034 {
1035 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
1036         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1037
1038         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1039         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1040         adev->smc_rreg = NULL;
1041         adev->smc_wreg = NULL;
1042         adev->pcie_rreg = &nv_pcie_rreg;
1043         adev->pcie_wreg = &nv_pcie_wreg;
1044         adev->pcie_rreg64 = &nv_pcie_rreg64;
1045         adev->pcie_wreg64 = &nv_pcie_wreg64;
1046         adev->pciep_rreg = &nv_pcie_port_rreg;
1047         adev->pciep_wreg = &nv_pcie_port_wreg;
1048
1049         /* TODO: will add them during VCN v2 implementation */
1050         adev->uvd_ctx_rreg = NULL;
1051         adev->uvd_ctx_wreg = NULL;
1052
1053         adev->didt_rreg = &nv_didt_rreg;
1054         adev->didt_wreg = &nv_didt_wreg;
1055
1056         adev->asic_funcs = &nv_asic_funcs;
1057
1058         adev->rev_id = nv_get_rev_id(adev);
1059         adev->external_rev_id = 0xff;
1060         switch (adev->asic_type) {
1061         case CHIP_NAVI10:
1062                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1063                         AMD_CG_SUPPORT_GFX_CGCG |
1064                         AMD_CG_SUPPORT_IH_CG |
1065                         AMD_CG_SUPPORT_HDP_MGCG |
1066                         AMD_CG_SUPPORT_HDP_LS |
1067                         AMD_CG_SUPPORT_SDMA_MGCG |
1068                         AMD_CG_SUPPORT_SDMA_LS |
1069                         AMD_CG_SUPPORT_MC_MGCG |
1070                         AMD_CG_SUPPORT_MC_LS |
1071                         AMD_CG_SUPPORT_ATHUB_MGCG |
1072                         AMD_CG_SUPPORT_ATHUB_LS |
1073                         AMD_CG_SUPPORT_VCN_MGCG |
1074                         AMD_CG_SUPPORT_JPEG_MGCG |
1075                         AMD_CG_SUPPORT_BIF_MGCG |
1076                         AMD_CG_SUPPORT_BIF_LS;
1077                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1078                         AMD_PG_SUPPORT_VCN_DPG |
1079                         AMD_PG_SUPPORT_JPEG |
1080                         AMD_PG_SUPPORT_ATHUB;
1081                 adev->external_rev_id = adev->rev_id + 0x1;
1082                 break;
1083         case CHIP_NAVI14:
1084                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1085                         AMD_CG_SUPPORT_GFX_CGCG |
1086                         AMD_CG_SUPPORT_IH_CG |
1087                         AMD_CG_SUPPORT_HDP_MGCG |
1088                         AMD_CG_SUPPORT_HDP_LS |
1089                         AMD_CG_SUPPORT_SDMA_MGCG |
1090                         AMD_CG_SUPPORT_SDMA_LS |
1091                         AMD_CG_SUPPORT_MC_MGCG |
1092                         AMD_CG_SUPPORT_MC_LS |
1093                         AMD_CG_SUPPORT_ATHUB_MGCG |
1094                         AMD_CG_SUPPORT_ATHUB_LS |
1095                         AMD_CG_SUPPORT_VCN_MGCG |
1096                         AMD_CG_SUPPORT_JPEG_MGCG |
1097                         AMD_CG_SUPPORT_BIF_MGCG |
1098                         AMD_CG_SUPPORT_BIF_LS;
1099                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1100                         AMD_PG_SUPPORT_JPEG |
1101                         AMD_PG_SUPPORT_VCN_DPG;
1102                 adev->external_rev_id = adev->rev_id + 20;
1103                 break;
1104         case CHIP_NAVI12:
1105                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1106                         AMD_CG_SUPPORT_GFX_MGLS |
1107                         AMD_CG_SUPPORT_GFX_CGCG |
1108                         AMD_CG_SUPPORT_GFX_CP_LS |
1109                         AMD_CG_SUPPORT_GFX_RLC_LS |
1110                         AMD_CG_SUPPORT_IH_CG |
1111                         AMD_CG_SUPPORT_HDP_MGCG |
1112                         AMD_CG_SUPPORT_HDP_LS |
1113                         AMD_CG_SUPPORT_SDMA_MGCG |
1114                         AMD_CG_SUPPORT_SDMA_LS |
1115                         AMD_CG_SUPPORT_MC_MGCG |
1116                         AMD_CG_SUPPORT_MC_LS |
1117                         AMD_CG_SUPPORT_ATHUB_MGCG |
1118                         AMD_CG_SUPPORT_ATHUB_LS |
1119                         AMD_CG_SUPPORT_VCN_MGCG |
1120                         AMD_CG_SUPPORT_JPEG_MGCG;
1121                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1122                         AMD_PG_SUPPORT_VCN_DPG |
1123                         AMD_PG_SUPPORT_JPEG |
1124                         AMD_PG_SUPPORT_ATHUB;
1125                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1126                  * as a consequence, the rev_id and external_rev_id are wrong.
1127                  * workaround it by hardcoding rev_id to 0 (default value).
1128                  */
1129                 if (amdgpu_sriov_vf(adev))
1130                         adev->rev_id = 0;
1131                 adev->external_rev_id = adev->rev_id + 0xa;
1132                 break;
1133         case CHIP_SIENNA_CICHLID:
1134                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1135                         AMD_CG_SUPPORT_GFX_CGCG |
1136                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1137                         AMD_CG_SUPPORT_MC_MGCG |
1138                         AMD_CG_SUPPORT_VCN_MGCG |
1139                         AMD_CG_SUPPORT_JPEG_MGCG |
1140                         AMD_CG_SUPPORT_HDP_MGCG |
1141                         AMD_CG_SUPPORT_HDP_LS |
1142                         AMD_CG_SUPPORT_IH_CG |
1143                         AMD_CG_SUPPORT_MC_LS;
1144                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1145                         AMD_PG_SUPPORT_VCN_DPG |
1146                         AMD_PG_SUPPORT_JPEG |
1147                         AMD_PG_SUPPORT_ATHUB |
1148                         AMD_PG_SUPPORT_MMHUB;
1149                 if (amdgpu_sriov_vf(adev)) {
1150                         /* hypervisor control CG and PG enablement */
1151                         adev->cg_flags = 0;
1152                         adev->pg_flags = 0;
1153                 }
1154                 adev->external_rev_id = adev->rev_id + 0x28;
1155                 break;
1156         case CHIP_NAVY_FLOUNDER:
1157                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1158                         AMD_CG_SUPPORT_GFX_CGCG |
1159                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1160                         AMD_CG_SUPPORT_VCN_MGCG |
1161                         AMD_CG_SUPPORT_JPEG_MGCG |
1162                         AMD_CG_SUPPORT_MC_MGCG |
1163                         AMD_CG_SUPPORT_MC_LS |
1164                         AMD_CG_SUPPORT_HDP_MGCG |
1165                         AMD_CG_SUPPORT_HDP_LS |
1166                         AMD_CG_SUPPORT_IH_CG;
1167                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1168                         AMD_PG_SUPPORT_VCN_DPG |
1169                         AMD_PG_SUPPORT_JPEG |
1170                         AMD_PG_SUPPORT_ATHUB |
1171                         AMD_PG_SUPPORT_MMHUB;
1172                 adev->external_rev_id = adev->rev_id + 0x32;
1173                 break;
1174
1175         case CHIP_VANGOGH:
1176                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1177                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1178                         AMD_CG_SUPPORT_GFX_MGLS |
1179                         AMD_CG_SUPPORT_GFX_CP_LS |
1180                         AMD_CG_SUPPORT_GFX_RLC_LS |
1181                         AMD_CG_SUPPORT_GFX_CGCG |
1182                         AMD_CG_SUPPORT_GFX_CGLS |
1183                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1184                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1185                         AMD_CG_SUPPORT_MC_MGCG |
1186                         AMD_CG_SUPPORT_MC_LS |
1187                         AMD_CG_SUPPORT_GFX_FGCG |
1188                         AMD_CG_SUPPORT_VCN_MGCG |
1189                         AMD_CG_SUPPORT_JPEG_MGCG;
1190                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1191                         AMD_PG_SUPPORT_VCN |
1192                         AMD_PG_SUPPORT_VCN_DPG |
1193                         AMD_PG_SUPPORT_JPEG;
1194                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1195                         adev->external_rev_id = adev->rev_id + 0x01;
1196                 break;
1197         case CHIP_DIMGREY_CAVEFISH:
1198                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1199                         AMD_CG_SUPPORT_GFX_CGCG |
1200                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1201                         AMD_CG_SUPPORT_VCN_MGCG |
1202                         AMD_CG_SUPPORT_JPEG_MGCG |
1203                         AMD_CG_SUPPORT_MC_MGCG |
1204                         AMD_CG_SUPPORT_MC_LS |
1205                         AMD_CG_SUPPORT_HDP_MGCG |
1206                         AMD_CG_SUPPORT_HDP_LS |
1207                         AMD_CG_SUPPORT_IH_CG;
1208                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1209                         AMD_PG_SUPPORT_VCN_DPG |
1210                         AMD_PG_SUPPORT_JPEG |
1211                         AMD_PG_SUPPORT_ATHUB |
1212                         AMD_PG_SUPPORT_MMHUB;
1213                 adev->external_rev_id = adev->rev_id + 0x3c;
1214                 break;
1215         default:
1216                 /* FIXME: not supported yet */
1217                 return -EINVAL;
1218         }
1219
1220         if (amdgpu_sriov_vf(adev)) {
1221                 amdgpu_virt_init_setting(adev);
1222                 xgpu_nv_mailbox_set_irq_funcs(adev);
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int nv_common_late_init(void *handle)
1229 {
1230         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1231
1232         if (amdgpu_sriov_vf(adev))
1233                 xgpu_nv_mailbox_get_irq(adev);
1234
1235         return 0;
1236 }
1237
1238 static int nv_common_sw_init(void *handle)
1239 {
1240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1241
1242         if (amdgpu_sriov_vf(adev))
1243                 xgpu_nv_mailbox_add_irq_id(adev);
1244
1245         return 0;
1246 }
1247
1248 static int nv_common_sw_fini(void *handle)
1249 {
1250         return 0;
1251 }
1252
1253 static int nv_common_hw_init(void *handle)
1254 {
1255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1256
1257         /* enable pcie gen2/3 link */
1258         nv_pcie_gen3_enable(adev);
1259         /* enable aspm */
1260         nv_program_aspm(adev);
1261         /* setup nbio registers */
1262         adev->nbio.funcs->init_registers(adev);
1263         /* remap HDP registers to a hole in mmio space,
1264          * for the purpose of expose those registers
1265          * to process space
1266          */
1267         if (adev->nbio.funcs->remap_hdp_registers)
1268                 adev->nbio.funcs->remap_hdp_registers(adev);
1269         /* enable the doorbell aperture */
1270         nv_enable_doorbell_aperture(adev, true);
1271
1272         return 0;
1273 }
1274
1275 static int nv_common_hw_fini(void *handle)
1276 {
1277         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1278
1279         /* disable the doorbell aperture */
1280         nv_enable_doorbell_aperture(adev, false);
1281
1282         return 0;
1283 }
1284
1285 static int nv_common_suspend(void *handle)
1286 {
1287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1288
1289         return nv_common_hw_fini(adev);
1290 }
1291
1292 static int nv_common_resume(void *handle)
1293 {
1294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295
1296         return nv_common_hw_init(adev);
1297 }
1298
1299 static bool nv_common_is_idle(void *handle)
1300 {
1301         return true;
1302 }
1303
1304 static int nv_common_wait_for_idle(void *handle)
1305 {
1306         return 0;
1307 }
1308
1309 static int nv_common_soft_reset(void *handle)
1310 {
1311         return 0;
1312 }
1313
1314 static int nv_common_set_clockgating_state(void *handle,
1315                                            enum amd_clockgating_state state)
1316 {
1317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318
1319         if (amdgpu_sriov_vf(adev))
1320                 return 0;
1321
1322         switch (adev->asic_type) {
1323         case CHIP_NAVI10:
1324         case CHIP_NAVI14:
1325         case CHIP_NAVI12:
1326         case CHIP_SIENNA_CICHLID:
1327         case CHIP_NAVY_FLOUNDER:
1328         case CHIP_DIMGREY_CAVEFISH:
1329                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1330                                 state == AMD_CG_STATE_GATE);
1331                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1332                                 state == AMD_CG_STATE_GATE);
1333                 adev->hdp.funcs->update_clock_gating(adev,
1334                                 state == AMD_CG_STATE_GATE);
1335                 adev->smuio.funcs->update_rom_clock_gating(adev,
1336                                 state == AMD_CG_STATE_GATE);
1337                 break;
1338         default:
1339                 break;
1340         }
1341         return 0;
1342 }
1343
1344 static int nv_common_set_powergating_state(void *handle,
1345                                            enum amd_powergating_state state)
1346 {
1347         /* TODO */
1348         return 0;
1349 }
1350
1351 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1352 {
1353         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1354
1355         if (amdgpu_sriov_vf(adev))
1356                 *flags = 0;
1357
1358         adev->nbio.funcs->get_clockgating_state(adev, flags);
1359
1360         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1361
1362         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1363
1364         return;
1365 }
1366
1367 static const struct amd_ip_funcs nv_common_ip_funcs = {
1368         .name = "nv_common",
1369         .early_init = nv_common_early_init,
1370         .late_init = nv_common_late_init,
1371         .sw_init = nv_common_sw_init,
1372         .sw_fini = nv_common_sw_fini,
1373         .hw_init = nv_common_hw_init,
1374         .hw_fini = nv_common_hw_fini,
1375         .suspend = nv_common_suspend,
1376         .resume = nv_common_resume,
1377         .is_idle = nv_common_is_idle,
1378         .wait_for_idle = nv_common_wait_for_idle,
1379         .soft_reset = nv_common_soft_reset,
1380         .set_clockgating_state = nv_common_set_clockgating_state,
1381         .set_powergating_state = nv_common_set_powergating_state,
1382         .get_clockgating_state = nv_common_get_clockgating_state,
1383 };