drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 103                                         size_t size, loff_t *pos)
 104 {
 105         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 106         struct ras_query_if info = {
 107                 .head = obj->head,
 108         };
 109         ssize_t s;
 110         char val[128];
 111
 112         if (amdgpu_ras_error_query(obj->adev, &info))
 113                 return -EINVAL;
 114
 115         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 116                         "ue", info.ue_count,
 117                         "ce", info.ce_count);
 118         if (*pos >= s)
 119                 return 0;
 120
 121         s -= *pos;
 122         s = min_t(u64, s, size);
 123
 124
 125         if (copy_to_user(buf, &val[*pos], s))
 126                 return -EINVAL;
 127
 128         *pos += s;
 129
 130         return s;
 131 }
 132
 133 static const struct file_operations amdgpu_ras_debugfs_ops = {
 134         .owner = THIS_MODULE,
 135         .read = amdgpu_ras_debugfs_read,
 136         .write = NULL,
 137         .llseek = default_llseek
 138 };
 139
 140 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 141 {
 142         int i;
 143
 144         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 145                 *block_id = i;
 146                 if (strcmp(name, ras_block_str(i)) == 0)
 147                         return 0;
 148         }
 149         return -EINVAL;
 150 }
 151
 152 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 153                 const char __user *buf, size_t size,
 154                 loff_t *pos, struct ras_debug_if *data)
 155 {
 156         ssize_t s = min_t(u64, 64, size);
 157         char str[65];
 158         char block_name[33];
 159         char err[9] = "ue";
 160         int op = -1;
 161         int block_id;
 162         uint32_t sub_block;
 163         u64 address, value;
 164
 165         if (*pos)
 166                 return -EINVAL;
 167         *pos = size;
 168
 169         memset(str, 0, sizeof(str));
 170         memset(data, 0, sizeof(*data));
 171
 172         if (copy_from_user(str, buf, s))
 173                 return -EINVAL;
 174
 175         if (sscanf(str, "disable %32s", block_name) == 1)
 176                 op = 0;
 177         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 178                 op = 1;
 179         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 180                 op = 2;
 181         else if (str[0] && str[1] && str[2] && str[3])
 182                 /* ascii string, but commands are not matched. */
 183                 return -EINVAL;
 184
 185         if (op != -1) {
 186                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 187                         return -EINVAL;
 188
 189                 data->head.block = block_id;
 190                 /* only ue and ce errors are supported */
 191                 if (!memcmp("ue", err, 2))
 192                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 193                 else if (!memcmp("ce", err, 2))
 194                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 195                 else
 196                         return -EINVAL;
 197
 198                 data->op = op;
 199
 200                 if (op == 2) {
 201                         if (sscanf(str, "%*s %*s %*s %u %llu %llu",
 202                                                 &sub_block, &address, &value) != 3)
 203                                 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 204                                                         &sub_block, &address, &value) != 3)
 205                                         return -EINVAL;
 206                         data->head.sub_block_index = sub_block;
 207                         data->inject.address = address;
 208                         data->inject.value = value;
 209                 }
 210         } else {
 211                 if (size < sizeof(*data))
 212                         return -EINVAL;
 213
 214                 if (copy_from_user(data, buf, sizeof(*data)))
 215                         return -EINVAL;
 216         }
 217
 218         return 0;
 219 }
 220
 221 /**
 222  * DOC: AMDGPU RAS debugfs control interface
 223  *
 224  * It accepts struct ras_debug_if who has two members.
 225  *
 226  * First member: ras_debug_if::head or ras_debug_if::inject.
 227  *
 228  * head is used to indicate which IP block will be under control.
 229  *
 230  * head has four members, they are block, type, sub_block_index, name.
 231  * block: which IP will be under control.
 232  * type: what kind of error will be enabled/disabled/injected.
 233  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 234  * name: the name of IP.
 235  *
 236  * inject has two more members than head, they are address, value.
 237  * As their names indicate, inject operation will write the
 238  * value to the address.
 239  *
 240  * The second member: struct ras_debug_if::op.
 241  * It has three kinds of operations.
 242  *
 243  * - 0: disable RAS on the block. Take ::head as its data.
 244  * - 1: enable RAS on the block. Take ::head as its data.
 245  * - 2: inject errors on the block. Take ::inject as its data.
 246  *
 247  * How to use the interface?
 248  *
 249  * Programs
 250  *
 251  * Copy the struct ras_debug_if in your codes and initialize it.
 252  * Write the struct to the control node.
 253  *
 254  * Shells
 255  *
 256  * .. code-block:: bash
 257  *
 258  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 259  *
 260  * Parameters:
 261  *
 262  * op: disable, enable, inject
 263  *      disable: only block is needed
 264  *      enable: block and error are needed
 265  *      inject: error, address, value are needed
 266  * block: umc, sdma, gfx, .........
 267  *      see ras_block_string[] for details
 268  * error: ue, ce
 269  *      ue: multi_uncorrectable
 270  *      ce: single_correctable
 271  * sub_block:
 272  *      sub block index, pass 0 if there is no sub block
 273  *
 274  * here are some examples for bash commands:
 275  *
 276  * .. code-block:: bash
 277  *
 278  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 279  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 280  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 281  *
 282  * How to check the result?
 283  *
 284  * For disable/enable, please check ras features at
 285  * /sys/class/drm/card[0/1/2...]/device/ras/features
 286  *
 287  * For inject, please check corresponding err count at
 288  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 289  *
 290  * .. note::
 291  *      Operations are only allowed on blocks which are supported.
 292  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 293  *      to see which blocks support RAS on a particular asic.
 294  *
 295  */
 296 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 297                 size_t size, loff_t *pos)
 298 {
 299         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 300         struct ras_debug_if data;
 301         int ret = 0;
 302
 303         if (!amdgpu_ras_get_error_query_ready(adev)) {
 304                 dev_warn(adev->dev, "RAS WARN: error injection "
 305                                 "currently inaccessible\n");
 306                 return size;
 307         }
 308
 309         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 310         if (ret)
 311                 return -EINVAL;
 312
 313         if (!amdgpu_ras_is_supported(adev, data.head.block))
 314                 return -EINVAL;
 315
 316         switch (data.op) {
 317         case 0:
 318                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 319                 break;
 320         case 1:
 321                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 322                 break;
 323         case 2:
 324                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 325                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 326                         dev_warn(adev->dev, "RAS WARN: input address "
 327                                         "0x%llx is invalid.",
 328                                         data.inject.address);
 329                         ret = -EINVAL;
 330                         break;
 331                 }
 332
 333                 /* umc ce/ue error injection for a bad page is not allowed */
 334                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 335                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 336                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 337                                         "as bad before error injection!\n",
 338                                         data.inject.address);
 339                         break;
 340                 }
 341
 342                 /* data.inject.address is offset instead of absolute gpu address */
 343                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 344                 break;
 345         default:
 346                 ret = -EINVAL;
 347                 break;
 348         }
 349
 350         if (ret)
 351                 return -EINVAL;
 352
 353         return size;
 354 }
 355
 356 /**
 357  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 358  *
 359  * Some boards contain an EEPROM which is used to persistently store a list of
 360  * bad pages which experiences ECC errors in vram.  This interface provides
 361  * a way to reset the EEPROM, e.g., after testing error injection.
 362  *
 363  * Usage:
 364  *
 365  * .. code-block:: bash
 366  *
 367  *      echo 1 > ../ras/ras_eeprom_reset
 368  *
 369  * will reset EEPROM table to 0 entries.
 370  *
 371  */
 372 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 373                 size_t size, loff_t *pos)
 374 {
 375         struct amdgpu_device *adev =
 376                 (struct amdgpu_device *)file_inode(f)->i_private;
 377         int ret;
 378
 379         ret = amdgpu_ras_eeprom_reset_table(
 380                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 381
 382         if (ret == 1) {
 383                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 384                 return size;
 385         } else {
 386                 return -EIO;
 387         }
 388 }
 389
 390 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 391         .owner = THIS_MODULE,
 392         .read = NULL,
 393         .write = amdgpu_ras_debugfs_ctrl_write,
 394         .llseek = default_llseek
 395 };
 396
 397 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 398         .owner = THIS_MODULE,
 399         .read = NULL,
 400         .write = amdgpu_ras_debugfs_eeprom_write,
 401         .llseek = default_llseek
 402 };
 403
 404 /**
 405  * DOC: AMDGPU RAS sysfs Error Count Interface
 406  *
 407  * It allows the user to read the error count for each IP block on the gpu through
 408  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 409  *
 410  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 411  * (ce) error counts.
 412  *
 413  * The format of one line is below,
 414  *
 415  * [ce|ue]: count
 416  *
 417  * Example:
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      ue: 0
 422  *      ce: 1
 423  *
 424  */
 425 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 426                 struct device_attribute *attr, char *buf)
 427 {
 428         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 429         struct ras_query_if info = {
 430                 .head = obj->head,
 431         };
 432
 433         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 434                 return snprintf(buf, PAGE_SIZE,
 435                                 "Query currently inaccessible\n");
 436
 437         if (amdgpu_ras_error_query(obj->adev, &info))
 438                 return -EINVAL;
 439
 440         return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n",
 441                         "ue", info.ue_count,
 442                         "ce", info.ce_count);
 443 }
 444
 445 /* obj begin */
 446
 447 #define get_obj(obj) do { (obj)->use++; } while (0)
 448 #define alive_obj(obj) ((obj)->use)
 449
 450 static inline void put_obj(struct ras_manager *obj)
 451 {
 452         if (obj && --obj->use == 0)
 453                 list_del(&obj->node);
 454         if (obj && obj->use < 0) {
 455                  DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 456         }
 457 }
 458
 459 /* make one obj and return it. */
 460 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 461                 struct ras_common_if *head)
 462 {
 463         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 464         struct ras_manager *obj;
 465
 466         if (!con)
 467                 return NULL;
 468
 469         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 470                 return NULL;
 471
 472         obj = &con->objs[head->block];
 473         /* already exist. return obj? */
 474         if (alive_obj(obj))
 475                 return NULL;
 476
 477         obj->head = *head;
 478         obj->adev = adev;
 479         list_add(&obj->node, &con->head);
 480         get_obj(obj);
 481
 482         return obj;
 483 }
 484
 485 /* return an obj equal to head, or the first when head is NULL */
 486 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 487                 struct ras_common_if *head)
 488 {
 489         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 490         struct ras_manager *obj;
 491         int i;
 492
 493         if (!con)
 494                 return NULL;
 495
 496         if (head) {
 497                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 498                         return NULL;
 499
 500                 obj = &con->objs[head->block];
 501
 502                 if (alive_obj(obj)) {
 503                         WARN_ON(head->block != obj->head.block);
 504                         return obj;
 505                 }
 506         } else {
 507                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 508                         obj = &con->objs[i];
 509                         if (alive_obj(obj)) {
 510                                 WARN_ON(i != obj->head.block);
 511                                 return obj;
 512                         }
 513                 }
 514         }
 515
 516         return NULL;
 517 }
 518 /* obj end */
 519
 520 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 521                                          const char* invoke_type,
 522                                          const char* block_name,
 523                                          enum ta_ras_status ret)
 524 {
 525         switch (ret) {
 526         case TA_RAS_STATUS__SUCCESS:
 527                 return;
 528         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 529                 dev_warn(adev->dev,
 530                         "RAS WARN: %s %s currently unavailable\n",
 531                         invoke_type,
 532                         block_name);
 533                 break;
 534         default:
 535                 dev_err(adev->dev,
 536                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 537                         invoke_type,
 538                         block_name,
 539                         ret);
 540         }
 541 }
 542
 543 /* feature ctl begin */
 544 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 545                 struct ras_common_if *head)
 546 {
 547         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 548
 549         return con->hw_supported & BIT(head->block);
 550 }
 551
 552 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 553                 struct ras_common_if *head)
 554 {
 555         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 556
 557         return con->features & BIT(head->block);
 558 }
 559
 560 /*
 561  * if obj is not created, then create one.
 562  * set feature enable flag.
 563  */
 564 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 565                 struct ras_common_if *head, int enable)
 566 {
 567         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 568         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 569
 570         /* If hardware does not support ras, then do not create obj.
 571          * But if hardware support ras, we can create the obj.
 572          * Ras framework checks con->hw_supported to see if it need do
 573          * corresponding initialization.
 574          * IP checks con->support to see if it need disable ras.
 575          */
 576         if (!amdgpu_ras_is_feature_allowed(adev, head))
 577                 return 0;
 578         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 579                 return 0;
 580
 581         if (enable) {
 582                 if (!obj) {
 583                         obj = amdgpu_ras_create_obj(adev, head);
 584                         if (!obj)
 585                                 return -EINVAL;
 586                 } else {
 587                         /* In case we create obj somewhere else */
 588                         get_obj(obj);
 589                 }
 590                 con->features |= BIT(head->block);
 591         } else {
 592                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 593                         con->features &= ~BIT(head->block);
 594                         put_obj(obj);
 595                 }
 596         }
 597
 598         return 0;
 599 }
 600
 601 /* wrapper of psp_ras_enable_features */
 602 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 603                 struct ras_common_if *head, bool enable)
 604 {
 605         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 606         union ta_ras_cmd_input *info;
 607         int ret;
 608
 609         if (!con)
 610                 return -EINVAL;
 611
 612         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 613         if (!info)
 614                 return -ENOMEM;
 615
 616         if (!enable) {
 617                 info->disable_features = (struct ta_ras_disable_features_input) {
 618                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 619                         .error_type = amdgpu_ras_error_to_ta(head->type),
 620                 };
 621         } else {
 622                 info->enable_features = (struct ta_ras_enable_features_input) {
 623                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 624                         .error_type = amdgpu_ras_error_to_ta(head->type),
 625                 };
 626         }
 627
 628         /* Do not enable if it is not allowed. */
 629         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 630         /* Are we alerady in that state we are going to set? */
 631         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 632                 ret = 0;
 633                 goto out;
 634         }
 635
 636         if (!amdgpu_ras_intr_triggered()) {
 637                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 638                 if (ret) {
 639                         amdgpu_ras_parse_status_code(adev,
 640                                                      enable ? "enable":"disable",
 641                                                      ras_block_str(head->block),
 642                                                     (enum ta_ras_status)ret);
 643                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 644                                 ret = -EAGAIN;
 645                         else
 646                                 ret = -EINVAL;
 647
 648                         goto out;
 649                 }
 650         }
 651
 652         /* setup the obj */
 653         __amdgpu_ras_feature_enable(adev, head, enable);
 654         ret = 0;
 655 out:
 656         kfree(info);
 657         return ret;
 658 }
 659
 660 /* Only used in device probe stage and called only once. */
 661 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 662                 struct ras_common_if *head, bool enable)
 663 {
 664         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 665         int ret;
 666
 667         if (!con)
 668                 return -EINVAL;
 669
 670         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 671                 if (enable) {
 672                         /* There is no harm to issue a ras TA cmd regardless of
 673                          * the currecnt ras state.
 674                          * If current state == target state, it will do nothing
 675                          * But sometimes it requests driver to reset and repost
 676                          * with error code -EAGAIN.
 677                          */
 678                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 679                         /* With old ras TA, we might fail to enable ras.
 680                          * Log it and just setup the object.
 681                          * TODO need remove this WA in the future.
 682                          */
 683                         if (ret == -EINVAL) {
 684                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 685                                 if (!ret)
 686                                         dev_info(adev->dev,
 687                                                 "RAS INFO: %s setup object\n",
 688                                                 ras_block_str(head->block));
 689                         }
 690                 } else {
 691                         /* setup the object then issue a ras TA disable cmd.*/
 692                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 693                         if (ret)
 694                                 return ret;
 695
 696                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 697                 }
 698         } else
 699                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 700
 701         return ret;
 702 }
 703
 704 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 705                 bool bypass)
 706 {
 707         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 708         struct ras_manager *obj, *tmp;
 709
 710         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 711                 /* bypass psp.
 712                  * aka just release the obj and corresponding flags
 713                  */
 714                 if (bypass) {
 715                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 716                                 break;
 717                 } else {
 718                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 719                                 break;
 720                 }
 721         }
 722
 723         return con->features;
 724 }
 725
 726 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 727                 bool bypass)
 728 {
 729         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 730         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 731         int i;
 732         const enum amdgpu_ras_error_type default_ras_type =
 733                 AMDGPU_RAS_ERROR__NONE;
 734
 735         for (i = 0; i < ras_block_count; i++) {
 736                 struct ras_common_if head = {
 737                         .block = i,
 738                         .type = default_ras_type,
 739                         .sub_block_index = 0,
 740                 };
 741                 strcpy(head.name, ras_block_str(i));
 742                 if (bypass) {
 743                         /*
 744                          * bypass psp. vbios enable ras for us.
 745                          * so just create the obj
 746                          */
 747                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 748                                 break;
 749                 } else {
 750                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 751                                 break;
 752                 }
 753         }
 754
 755         return con->features;
 756 }
 757 /* feature ctl end */
 758
 759 /* query/inject/cure begin */
 760 int amdgpu_ras_error_query(struct amdgpu_device *adev,
 761                 struct ras_query_if *info)
 762 {
 763         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 764         struct ras_err_data err_data = {0, 0, 0, NULL};
 765         int i;
 766
 767         if (!obj)
 768                 return -EINVAL;
 769
 770         switch (info->head.block) {
 771         case AMDGPU_RAS_BLOCK__UMC:
 772                 if (adev->umc.funcs->query_ras_error_count)
 773                         adev->umc.funcs->query_ras_error_count(adev, &err_data);
 774                 /* umc query_ras_error_address is also responsible for clearing
 775                  * error status
 776                  */
 777                 if (adev->umc.funcs->query_ras_error_address)
 778                         adev->umc.funcs->query_ras_error_address(adev, &err_data);
 779                 break;
 780         case AMDGPU_RAS_BLOCK__SDMA:
 781                 if (adev->sdma.funcs->query_ras_error_count) {
 782                         for (i = 0; i < adev->sdma.num_instances; i++)
 783                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 784                                                                         &err_data);
 785                 }
 786                 break;
 787         case AMDGPU_RAS_BLOCK__GFX:
 788                 if (adev->gfx.funcs->query_ras_error_count)
 789                         adev->gfx.funcs->query_ras_error_count(adev, &err_data);
 790                 break;
 791         case AMDGPU_RAS_BLOCK__MMHUB:
 792                 if (adev->mmhub.funcs->query_ras_error_count)
 793                         adev->mmhub.funcs->query_ras_error_count(adev, &err_data);
 794                 break;
 795         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 796                 if (adev->nbio.funcs->query_ras_error_count)
 797                         adev->nbio.funcs->query_ras_error_count(adev, &err_data);
 798                 break;
 799         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 800                 amdgpu_xgmi_query_ras_error_count(adev, &err_data);
 801                 break;
 802         default:
 803                 break;
 804         }
 805
 806         obj->err_data.ue_count += err_data.ue_count;
 807         obj->err_data.ce_count += err_data.ce_count;
 808
 809         info->ue_count = obj->err_data.ue_count;
 810         info->ce_count = obj->err_data.ce_count;
 811
 812         if (err_data.ce_count) {
 813                 dev_info(adev->dev, "%ld correctable hardware errors "
 814                                         "detected in %s block, no user "
 815                                         "action is needed.\n",
 816                                         obj->err_data.ce_count,
 817                                         ras_block_str(info->head.block));
 818         }
 819         if (err_data.ue_count) {
 820                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 821                                         "detected in %s block\n",
 822                                         obj->err_data.ue_count,
 823                                         ras_block_str(info->head.block));
 824         }
 825
 826         return 0;
 827 }
 828
 829 /* Trigger XGMI/WAFL error */
 830 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 831                                  struct ta_ras_trigger_error_input *block_info)
 832 {
 833         int ret;
 834
 835         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 836                 dev_warn(adev->dev, "Failed to disallow df cstate");
 837
 838         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 839                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 840
 841         ret = psp_ras_trigger_error(&adev->psp, block_info);
 842
 843         if (amdgpu_ras_intr_triggered())
 844                 return ret;
 845
 846         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 847                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 848
 849         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 850                 dev_warn(adev->dev, "Failed to allow df cstate");
 851
 852         return ret;
 853 }
 854
 855 /* wrapper of psp_ras_trigger_error */
 856 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 857                 struct ras_inject_if *info)
 858 {
 859         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 860         struct ta_ras_trigger_error_input block_info = {
 861                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 862                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 863                 .sub_block_index = info->head.sub_block_index,
 864                 .address = info->address,
 865                 .value = info->value,
 866         };
 867         int ret = 0;
 868
 869         if (!obj)
 870                 return -EINVAL;
 871
 872         /* Calculate XGMI relative offset */
 873         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 874                 block_info.address =
 875                         amdgpu_xgmi_get_relative_phy_addr(adev,
 876                                                           block_info.address);
 877         }
 878
 879         switch (info->head.block) {
 880         case AMDGPU_RAS_BLOCK__GFX:
 881                 if (adev->gfx.funcs->ras_error_inject)
 882                         ret = adev->gfx.funcs->ras_error_inject(adev, info);
 883                 else
 884                         ret = -EINVAL;
 885                 break;
 886         case AMDGPU_RAS_BLOCK__UMC:
 887         case AMDGPU_RAS_BLOCK__MMHUB:
 888         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 889                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
 890                 break;
 891         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 892                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
 893                 break;
 894         default:
 895                 dev_info(adev->dev, "%s error injection is not supported yet\n",
 896                          ras_block_str(info->head.block));
 897                 ret = -EINVAL;
 898         }
 899
 900         amdgpu_ras_parse_status_code(adev,
 901                                      "inject",
 902                                      ras_block_str(info->head.block),
 903                                      (enum ta_ras_status)ret);
 904
 905         return ret;
 906 }
 907
 908 /* get the total error counts on all IPs */
 909 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 910                 bool is_ce)
 911 {
 912         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 913         struct ras_manager *obj;
 914         struct ras_err_data data = {0, 0};
 915
 916         if (!con)
 917                 return 0;
 918
 919         list_for_each_entry(obj, &con->head, node) {
 920                 struct ras_query_if info = {
 921                         .head = obj->head,
 922                 };
 923
 924                 if (amdgpu_ras_error_query(adev, &info))
 925                         return 0;
 926
 927                 data.ce_count += info.ce_count;
 928                 data.ue_count += info.ue_count;
 929         }
 930
 931         return is_ce ? data.ce_count : data.ue_count;
 932 }
 933 /* query/inject/cure end */
 934
 935
 936 /* sysfs begin */
 937
 938 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
 939                 struct ras_badpage **bps, unsigned int *count);
 940
 941 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
 942 {
 943         switch (flags) {
 944         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
 945                 return "R";
 946         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
 947                 return "P";
 948         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
 949         default:
 950                 return "F";
 951         }
 952 }
 953
 954 /**
 955  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
 956  *
 957  * It allows user to read the bad pages of vram on the gpu through
 958  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
 959  *
 960  * It outputs multiple lines, and each line stands for one gpu page.
 961  *
 962  * The format of one line is below,
 963  * gpu pfn : gpu page size : flags
 964  *
 965  * gpu pfn and gpu page size are printed in hex format.
 966  * flags can be one of below character,
 967  *
 968  * R: reserved, this gpu page is reserved and not able to use.
 969  *
 970  * P: pending for reserve, this gpu page is marked as bad, will be reserved
 971  * in next window of page_reserve.
 972  *
 973  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
 974  *
 975  * Examples:
 976  *
 977  * .. code-block:: bash
 978  *
 979  *      0x00000001 : 0x00001000 : R
 980  *      0x00000002 : 0x00001000 : P
 981  *
 982  */
 983
 984 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
 985                 struct kobject *kobj, struct bin_attribute *attr,
 986                 char *buf, loff_t ppos, size_t count)
 987 {
 988         struct amdgpu_ras *con =
 989                 container_of(attr, struct amdgpu_ras, badpages_attr);
 990         struct amdgpu_device *adev = con->adev;
 991         const unsigned int element_size =
 992                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
 993         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
 994         unsigned int end = div64_ul(ppos + count - 1, element_size);
 995         ssize_t s = 0;
 996         struct ras_badpage *bps = NULL;
 997         unsigned int bps_count = 0;
 998
 999         memset(buf, 0, count);
1000
1001         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1002                 return 0;
1003
1004         for (; start < end && start < bps_count; start++)
1005                 s += scnprintf(&buf[s], element_size + 1,
1006                                 "0x%08x : 0x%08x : %1s\n",
1007                                 bps[start].bp,
1008                                 bps[start].size,
1009                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1010
1011         kfree(bps);
1012
1013         return s;
1014 }
1015
1016 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1017                 struct device_attribute *attr, char *buf)
1018 {
1019         struct amdgpu_ras *con =
1020                 container_of(attr, struct amdgpu_ras, features_attr);
1021
1022         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1023 }
1024
1025 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1026 {
1027         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1028
1029         sysfs_remove_file_from_group(&adev->dev->kobj,
1030                                 &con->badpages_attr.attr,
1031                                 RAS_FS_NAME);
1032 }
1033
1034 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1035 {
1036         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1037         struct attribute *attrs[] = {
1038                 &con->features_attr.attr,
1039                 NULL
1040         };
1041         struct attribute_group group = {
1042                 .name = RAS_FS_NAME,
1043                 .attrs = attrs,
1044         };
1045
1046         sysfs_remove_group(&adev->dev->kobj, &group);
1047
1048         return 0;
1049 }
1050
1051 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1052                 struct ras_fs_if *head)
1053 {
1054         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1055
1056         if (!obj || obj->attr_inuse)
1057                 return -EINVAL;
1058
1059         get_obj(obj);
1060
1061         memcpy(obj->fs_data.sysfs_name,
1062                         head->sysfs_name,
1063                         sizeof(obj->fs_data.sysfs_name));
1064
1065         obj->sysfs_attr = (struct device_attribute){
1066                 .attr = {
1067                         .name = obj->fs_data.sysfs_name,
1068                         .mode = S_IRUGO,
1069                 },
1070                         .show = amdgpu_ras_sysfs_read,
1071         };
1072         sysfs_attr_init(&obj->sysfs_attr.attr);
1073
1074         if (sysfs_add_file_to_group(&adev->dev->kobj,
1075                                 &obj->sysfs_attr.attr,
1076                                 RAS_FS_NAME)) {
1077                 put_obj(obj);
1078                 return -EINVAL;
1079         }
1080
1081         obj->attr_inuse = 1;
1082
1083         return 0;
1084 }
1085
1086 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1087                 struct ras_common_if *head)
1088 {
1089         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1090
1091         if (!obj || !obj->attr_inuse)
1092                 return -EINVAL;
1093
1094         sysfs_remove_file_from_group(&adev->dev->kobj,
1095                                 &obj->sysfs_attr.attr,
1096                                 RAS_FS_NAME);
1097         obj->attr_inuse = 0;
1098         put_obj(obj);
1099
1100         return 0;
1101 }
1102
1103 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1104 {
1105         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1106         struct ras_manager *obj, *tmp;
1107
1108         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1109                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1110         }
1111
1112         if (amdgpu_bad_page_threshold != 0)
1113                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1114
1115         amdgpu_ras_sysfs_remove_feature_node(adev);
1116
1117         return 0;
1118 }
1119 /* sysfs end */
1120
1121 /**
1122  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1123  *
1124  * Normally when there is an uncorrectable error, the driver will reset
1125  * the GPU to recover.  However, in the event of an unrecoverable error,
1126  * the driver provides an interface to reboot the system automatically
1127  * in that event.
1128  *
1129  * The following file in debugfs provides that interface:
1130  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1131  *
1132  * Usage:
1133  *
1134  * .. code-block:: bash
1135  *
1136  *      echo true > .../ras/auto_reboot
1137  *
1138  */
1139 /* debugfs begin */
1140 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1141 {
1142         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1143         struct dentry *dir;
1144         struct drm_minor *minor = adev_to_drm(adev)->primary;
1145
1146         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1147         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1148                             &amdgpu_ras_debugfs_ctrl_ops);
1149         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1150                             &amdgpu_ras_debugfs_eeprom_ops);
1151
1152         /*
1153          * After one uncorrectable error happens, usually GPU recovery will
1154          * be scheduled. But due to the known problem in GPU recovery failing
1155          * to bring GPU back, below interface provides one direct way to
1156          * user to reboot system automatically in such case within
1157          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1158          * will never be called.
1159          */
1160         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1161
1162         /*
1163          * User could set this not to clean up hardware's error count register
1164          * of RAS IPs during ras recovery.
1165          */
1166         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1167                             &con->disable_ras_err_cnt_harvest);
1168         return dir;
1169 }
1170
1171 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1172                                       struct ras_fs_if *head,
1173                                       struct dentry *dir)
1174 {
1175         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1176
1177         if (!obj || !dir)
1178                 return;
1179
1180         get_obj(obj);
1181
1182         memcpy(obj->fs_data.debugfs_name,
1183                         head->debugfs_name,
1184                         sizeof(obj->fs_data.debugfs_name));
1185
1186         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1187                             obj, &amdgpu_ras_debugfs_ops);
1188 }
1189
1190 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1191 {
1192         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1193         struct dentry *dir;
1194         struct ras_manager *obj;
1195         struct ras_fs_if fs_info;
1196
1197         /*
1198          * it won't be called in resume path, no need to check
1199          * suspend and gpu reset status
1200          */
1201         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1202                 return;
1203
1204         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1205
1206         list_for_each_entry(obj, &con->head, node) {
1207                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1208                         (obj->attr_inuse == 1)) {
1209                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1210                                         ras_block_str(obj->head.block));
1211                         fs_info.head = obj->head;
1212                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1213                 }
1214         }
1215 }
1216
1217 /* debugfs end */
1218
1219 /* ras fs */
1220 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1221                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1222 static DEVICE_ATTR(features, S_IRUGO,
1223                 amdgpu_ras_sysfs_features_read, NULL);
1224 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1225 {
1226         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1227         struct attribute_group group = {
1228                 .name = RAS_FS_NAME,
1229         };
1230         struct attribute *attrs[] = {
1231                 &con->features_attr.attr,
1232                 NULL
1233         };
1234         struct bin_attribute *bin_attrs[] = {
1235                 NULL,
1236                 NULL,
1237         };
1238         int r;
1239
1240         /* add features entry */
1241         con->features_attr = dev_attr_features;
1242         group.attrs = attrs;
1243         sysfs_attr_init(attrs[0]);
1244
1245         if (amdgpu_bad_page_threshold != 0) {
1246                 /* add bad_page_features entry */
1247                 bin_attr_gpu_vram_bad_pages.private = NULL;
1248                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1249                 bin_attrs[0] = &con->badpages_attr;
1250                 group.bin_attrs = bin_attrs;
1251                 sysfs_bin_attr_init(bin_attrs[0]);
1252         }
1253
1254         r = sysfs_create_group(&adev->dev->kobj, &group);
1255         if (r)
1256                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1257
1258         return 0;
1259 }
1260
1261 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1262 {
1263         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1264         struct ras_manager *con_obj, *ip_obj, *tmp;
1265
1266         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1267                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1268                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1269                         if (ip_obj)
1270                                 put_obj(ip_obj);
1271                 }
1272         }
1273
1274         amdgpu_ras_sysfs_remove_all(adev);
1275         return 0;
1276 }
1277 /* ras fs end */
1278
1279 /* ih begin */
1280 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1281 {
1282         struct ras_ih_data *data = &obj->ih_data;
1283         struct amdgpu_iv_entry entry;
1284         int ret;
1285         struct ras_err_data err_data = {0, 0, 0, NULL};
1286
1287         while (data->rptr != data->wptr) {
1288                 rmb();
1289                 memcpy(&entry, &data->ring[data->rptr],
1290                                 data->element_size);
1291
1292                 wmb();
1293                 data->rptr = (data->aligned_element_size +
1294                                 data->rptr) % data->ring_size;
1295
1296                 /* Let IP handle its data, maybe we need get the output
1297                  * from the callback to udpate the error type/count, etc
1298                  */
1299                 if (data->cb) {
1300                         ret = data->cb(obj->adev, &err_data, &entry);
1301                         /* ue will trigger an interrupt, and in that case
1302                          * we need do a reset to recovery the whole system.
1303                          * But leave IP do that recovery, here we just dispatch
1304                          * the error.
1305                          */
1306                         if (ret == AMDGPU_RAS_SUCCESS) {
1307                                 /* these counts could be left as 0 if
1308                                  * some blocks do not count error number
1309                                  */
1310                                 obj->err_data.ue_count += err_data.ue_count;
1311                                 obj->err_data.ce_count += err_data.ce_count;
1312                         }
1313                 }
1314         }
1315 }
1316
1317 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1318 {
1319         struct ras_ih_data *data =
1320                 container_of(work, struct ras_ih_data, ih_work);
1321         struct ras_manager *obj =
1322                 container_of(data, struct ras_manager, ih_data);
1323
1324         amdgpu_ras_interrupt_handler(obj);
1325 }
1326
1327 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1328                 struct ras_dispatch_if *info)
1329 {
1330         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1331         struct ras_ih_data *data = &obj->ih_data;
1332
1333         if (!obj)
1334                 return -EINVAL;
1335
1336         if (data->inuse == 0)
1337                 return 0;
1338
1339         /* Might be overflow... */
1340         memcpy(&data->ring[data->wptr], info->entry,
1341                         data->element_size);
1342
1343         wmb();
1344         data->wptr = (data->aligned_element_size +
1345                         data->wptr) % data->ring_size;
1346
1347         schedule_work(&data->ih_work);
1348
1349         return 0;
1350 }
1351
1352 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1353                 struct ras_ih_if *info)
1354 {
1355         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1356         struct ras_ih_data *data;
1357
1358         if (!obj)
1359                 return -EINVAL;
1360
1361         data = &obj->ih_data;
1362         if (data->inuse == 0)
1363                 return 0;
1364
1365         cancel_work_sync(&data->ih_work);
1366
1367         kfree(data->ring);
1368         memset(data, 0, sizeof(*data));
1369         put_obj(obj);
1370
1371         return 0;
1372 }
1373
1374 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1375                 struct ras_ih_if *info)
1376 {
1377         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1378         struct ras_ih_data *data;
1379
1380         if (!obj) {
1381                 /* in case we registe the IH before enable ras feature */
1382                 obj = amdgpu_ras_create_obj(adev, &info->head);
1383                 if (!obj)
1384                         return -EINVAL;
1385         } else
1386                 get_obj(obj);
1387
1388         data = &obj->ih_data;
1389         /* add the callback.etc */
1390         *data = (struct ras_ih_data) {
1391                 .inuse = 0,
1392                 .cb = info->cb,
1393                 .element_size = sizeof(struct amdgpu_iv_entry),
1394                 .rptr = 0,
1395                 .wptr = 0,
1396         };
1397
1398         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1399
1400         data->aligned_element_size = ALIGN(data->element_size, 8);
1401         /* the ring can store 64 iv entries. */
1402         data->ring_size = 64 * data->aligned_element_size;
1403         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1404         if (!data->ring) {
1405                 put_obj(obj);
1406                 return -ENOMEM;
1407         }
1408
1409         /* IH is ready */
1410         data->inuse = 1;
1411
1412         return 0;
1413 }
1414
1415 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1416 {
1417         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1418         struct ras_manager *obj, *tmp;
1419
1420         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1421                 struct ras_ih_if info = {
1422                         .head = obj->head,
1423                 };
1424                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1425         }
1426
1427         return 0;
1428 }
1429 /* ih end */
1430
1431 /* traversal all IPs except NBIO to query error counter */
1432 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1433 {
1434         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1435         struct ras_manager *obj;
1436
1437         if (!con)
1438                 return;
1439
1440         list_for_each_entry(obj, &con->head, node) {
1441                 struct ras_query_if info = {
1442                         .head = obj->head,
1443                 };
1444
1445                 /*
1446                  * PCIE_BIF IP has one different isr by ras controller
1447                  * interrupt, the specific ras counter query will be
1448                  * done in that isr. So skip such block from common
1449                  * sync flood interrupt isr calling.
1450                  */
1451                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1452                         continue;
1453
1454                 amdgpu_ras_error_query(adev, &info);
1455         }
1456 }
1457
1458 /* Parse RdRspStatus and WrRspStatus */
1459 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1460                                           struct ras_query_if *info)
1461 {
1462         /*
1463          * Only two block need to query read/write
1464          * RspStatus at current state
1465          */
1466         switch (info->head.block) {
1467         case AMDGPU_RAS_BLOCK__GFX:
1468                 if (adev->gfx.funcs->query_ras_error_status)
1469                         adev->gfx.funcs->query_ras_error_status(adev);
1470                 break;
1471         case AMDGPU_RAS_BLOCK__MMHUB:
1472                 if (adev->mmhub.funcs->query_ras_error_status)
1473                         adev->mmhub.funcs->query_ras_error_status(adev);
1474                 break;
1475         default:
1476                 break;
1477         }
1478 }
1479
1480 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1481 {
1482         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1483         struct ras_manager *obj;
1484
1485         if (!con)
1486                 return;
1487
1488         list_for_each_entry(obj, &con->head, node) {
1489                 struct ras_query_if info = {
1490                         .head = obj->head,
1491                 };
1492
1493                 amdgpu_ras_error_status_query(adev, &info);
1494         }
1495 }
1496
1497 /* recovery begin */
1498
1499 /* return 0 on success.
1500  * caller need free bps.
1501  */
1502 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1503                 struct ras_badpage **bps, unsigned int *count)
1504 {
1505         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1506         struct ras_err_handler_data *data;
1507         int i = 0;
1508         int ret = 0, status;
1509
1510         if (!con || !con->eh_data || !bps || !count)
1511                 return -EINVAL;
1512
1513         mutex_lock(&con->recovery_lock);
1514         data = con->eh_data;
1515         if (!data || data->count == 0) {
1516                 *bps = NULL;
1517                 ret = -EINVAL;
1518                 goto out;
1519         }
1520
1521         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1522         if (!*bps) {
1523                 ret = -ENOMEM;
1524                 goto out;
1525         }
1526
1527         for (; i < data->count; i++) {
1528                 (*bps)[i] = (struct ras_badpage){
1529                         .bp = data->bps[i].retired_page,
1530                         .size = AMDGPU_GPU_PAGE_SIZE,
1531                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1532                 };
1533                 status = amdgpu_vram_mgr_query_page_status(
1534                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1535                                 data->bps[i].retired_page);
1536                 if (status == -EBUSY)
1537                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1538                 else if (status == -ENOENT)
1539                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1540         }
1541
1542         *count = data->count;
1543 out:
1544         mutex_unlock(&con->recovery_lock);
1545         return ret;
1546 }
1547
1548 static void amdgpu_ras_do_recovery(struct work_struct *work)
1549 {
1550         struct amdgpu_ras *ras =
1551                 container_of(work, struct amdgpu_ras, recovery_work);
1552         struct amdgpu_device *remote_adev = NULL;
1553         struct amdgpu_device *adev = ras->adev;
1554         struct list_head device_list, *device_list_handle =  NULL;
1555
1556         if (!ras->disable_ras_err_cnt_harvest) {
1557                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1558
1559                 /* Build list of devices to query RAS related errors */
1560                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1561                         device_list_handle = &hive->device_list;
1562                 } else {
1563                         INIT_LIST_HEAD(&device_list);
1564                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1565                         device_list_handle = &device_list;
1566                 }
1567
1568                 list_for_each_entry(remote_adev,
1569                                 device_list_handle, gmc.xgmi.head) {
1570                         amdgpu_ras_query_err_status(remote_adev);
1571                         amdgpu_ras_log_on_err_counter(remote_adev);
1572                 }
1573
1574                 amdgpu_put_xgmi_hive(hive);
1575         }
1576
1577         if (amdgpu_device_should_recover_gpu(ras->adev))
1578                 amdgpu_device_gpu_recover(ras->adev, NULL);
1579         atomic_set(&ras->in_recovery, 0);
1580 }
1581
1582 /* alloc/realloc bps array */
1583 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1584                 struct ras_err_handler_data *data, int pages)
1585 {
1586         unsigned int old_space = data->count + data->space_left;
1587         unsigned int new_space = old_space + pages;
1588         unsigned int align_space = ALIGN(new_space, 512);
1589         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1590
1591         if (!bps) {
1592                 kfree(bps);
1593                 return -ENOMEM;
1594         }
1595
1596         if (data->bps) {
1597                 memcpy(bps, data->bps,
1598                                 data->count * sizeof(*data->bps));
1599                 kfree(data->bps);
1600         }
1601
1602         data->bps = bps;
1603         data->space_left += align_space - old_space;
1604         return 0;
1605 }
1606
1607 /* it deal with vram only. */
1608 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1609                 struct eeprom_table_record *bps, int pages)
1610 {
1611         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1612         struct ras_err_handler_data *data;
1613         int ret = 0;
1614         uint32_t i;
1615
1616         if (!con || !con->eh_data || !bps || pages <= 0)
1617                 return 0;
1618
1619         mutex_lock(&con->recovery_lock);
1620         data = con->eh_data;
1621         if (!data)
1622                 goto out;
1623
1624         for (i = 0; i < pages; i++) {
1625                 if (amdgpu_ras_check_bad_page_unlock(con,
1626                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1627                         continue;
1628
1629                 if (!data->space_left &&
1630                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1631                         ret = -ENOMEM;
1632                         goto out;
1633                 }
1634
1635                 amdgpu_vram_mgr_reserve_range(
1636                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1637                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1638                         AMDGPU_GPU_PAGE_SIZE);
1639
1640                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1641                 data->count++;
1642                 data->space_left--;
1643         }
1644 out:
1645         mutex_unlock(&con->recovery_lock);
1646
1647         return ret;
1648 }
1649
1650 /*
1651  * write error record array to eeprom, the function should be
1652  * protected by recovery_lock
1653  */
1654 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1655 {
1656         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1657         struct ras_err_handler_data *data;
1658         struct amdgpu_ras_eeprom_control *control;
1659         int save_count;
1660
1661         if (!con || !con->eh_data)
1662                 return 0;
1663
1664         control = &con->eeprom_control;
1665         data = con->eh_data;
1666         save_count = data->count - control->num_recs;
1667         /* only new entries are saved */
1668         if (save_count > 0) {
1669                 if (amdgpu_ras_eeprom_process_recods(control,
1670                                                         &data->bps[control->num_recs],
1671                                                         true,
1672                                                         save_count)) {
1673                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1674                         return -EIO;
1675                 }
1676
1677                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1678         }
1679
1680         return 0;
1681 }
1682
1683 /*
1684  * read error record array in eeprom and reserve enough space for
1685  * storing new bad pages
1686  */
1687 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1688 {
1689         struct amdgpu_ras_eeprom_control *control =
1690                                         &adev->psp.ras.ras->eeprom_control;
1691         struct eeprom_table_record *bps = NULL;
1692         int ret = 0;
1693
1694         /* no bad page record, skip eeprom access */
1695         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1696                 return ret;
1697
1698         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1699         if (!bps)
1700                 return -ENOMEM;
1701
1702         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1703                 control->num_recs)) {
1704                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1705                 ret = -EIO;
1706                 goto out;
1707         }
1708
1709         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1710
1711 out:
1712         kfree(bps);
1713         return ret;
1714 }
1715
1716 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1717                                 uint64_t addr)
1718 {
1719         struct ras_err_handler_data *data = con->eh_data;
1720         int i;
1721
1722         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1723         for (i = 0; i < data->count; i++)
1724                 if (addr == data->bps[i].retired_page)
1725                         return true;
1726
1727         return false;
1728 }
1729
1730 /*
1731  * check if an address belongs to bad page
1732  *
1733  * Note: this check is only for umc block
1734  */
1735 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1736                                 uint64_t addr)
1737 {
1738         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1739         bool ret = false;
1740
1741         if (!con || !con->eh_data)
1742                 return ret;
1743
1744         mutex_lock(&con->recovery_lock);
1745         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1746         mutex_unlock(&con->recovery_lock);
1747         return ret;
1748 }
1749
1750 static uint32_t
1751 amdgpu_ras_calculate_badpags_threshold(struct amdgpu_device *adev)
1752 {
1753         int tmp_threshold = amdgpu_bad_page_threshold;
1754         u64 val;
1755         uint32_t max_length = 0;
1756
1757         max_length = amdgpu_ras_eeprom_get_record_max_length();
1758         /*
1759          * Justification of value bad_page_cnt_threshold in ras structure
1760          *
1761          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1762          * in eeprom, and introduce two scenarios accordingly.
1763          *
1764          * Bad page retirement enablement:
1765          *    - If amdgpu_bad_page_threshold = -1,
1766          *      bad_page_cnt_threshold = typical value by formula.
1767          *
1768          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1769          *      max record length in eeprom, use it directly.
1770          *
1771          * Bad page retirement disablement:
1772          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1773          *      functionality is disabled, and bad_page_cnt_threshold will
1774          *      take no effect.
1775          */
1776
1777         if (tmp_threshold < -1)
1778                 tmp_threshold = -1;
1779         else if (tmp_threshold > max_length)
1780                 tmp_threshold = max_length;
1781
1782         if (tmp_threshold == -1) {
1783                 val = adev->gmc.real_vram_size;
1784                 do_div(val, RAS_BAD_PAGE_RATE);
1785                 tmp_threshold = min(lower_32_bits(val), max_length);
1786         }
1787
1788         return tmp_threshold;
1789 }
1790
1791 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1792 {
1793         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1794         struct ras_err_handler_data **data;
1795         bool exc_err_limit = false;
1796         int ret;
1797
1798         if (con)
1799                 data = &con->eh_data;
1800         else
1801                 return 0;
1802
1803         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1804         if (!*data) {
1805                 ret = -ENOMEM;
1806                 goto out;
1807         }
1808
1809         mutex_init(&con->recovery_lock);
1810         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1811         atomic_set(&con->in_recovery, 0);
1812         con->adev = adev;
1813
1814         if (!con->bad_page_cnt_threshold) {
1815                 con->bad_page_cnt_threshold =
1816                         amdgpu_ras_calculate_badpags_threshold(adev);
1817
1818                 ret = amdgpu_vram_mgr_reserve_backup_pages(
1819                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1820                         con->bad_page_cnt_threshold);
1821                 if (ret)
1822                         goto out;
1823         }
1824
1825         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1826         /*
1827          * This calling fails when exc_err_limit is true or
1828          * ret != 0.
1829          */
1830         if (exc_err_limit || ret)
1831                 goto free;
1832
1833         if (con->eeprom_control.num_recs) {
1834                 ret = amdgpu_ras_load_bad_pages(adev);
1835                 if (ret)
1836                         goto free;
1837         }
1838
1839         return 0;
1840
1841 free:
1842         kfree((*data)->bps);
1843         kfree(*data);
1844         con->eh_data = NULL;
1845 out:
1846         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1847
1848         /*
1849          * Except error threshold exceeding case, other failure cases in this
1850          * function would not fail amdgpu driver init.
1851          */
1852         if (!exc_err_limit)
1853                 ret = 0;
1854         else
1855                 ret = -EINVAL;
1856
1857         return ret;
1858 }
1859
1860 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1861 {
1862         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1863         struct ras_err_handler_data *data = con->eh_data;
1864
1865         /* recovery_init failed to init it, fini is useless */
1866         if (!data)
1867                 return 0;
1868
1869         cancel_work_sync(&con->recovery_work);
1870
1871         mutex_lock(&con->recovery_lock);
1872         con->eh_data = NULL;
1873         kfree(data->bps);
1874         kfree(data);
1875         mutex_unlock(&con->recovery_lock);
1876
1877         return 0;
1878 }
1879 /* recovery end */
1880
1881 /* return 0 if ras will reset gpu and repost.*/
1882 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
1883                 unsigned int block)
1884 {
1885         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1886
1887         if (!ras)
1888                 return -EINVAL;
1889
1890         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
1891         return 0;
1892 }
1893
1894 static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev)
1895 {
1896         if (adev->asic_type != CHIP_VEGA10 &&
1897                 adev->asic_type != CHIP_VEGA20 &&
1898                 adev->asic_type != CHIP_ARCTURUS &&
1899                 adev->asic_type != CHIP_SIENNA_CICHLID)
1900                 return 1;
1901         else
1902                 return 0;
1903 }
1904
1905 /*
1906  * check hardware's ras ability which will be saved in hw_supported.
1907  * if hardware does not support ras, we can skip some ras initializtion and
1908  * forbid some ras operations from IP.
1909  * if software itself, say boot parameter, limit the ras ability. We still
1910  * need allow IP do some limited operations, like disable. In such case,
1911  * we have to initialize ras as normal. but need check if operation is
1912  * allowed or not in each function.
1913  */
1914 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
1915                 uint32_t *hw_supported, uint32_t *supported)
1916 {
1917         *hw_supported = 0;
1918         *supported = 0;
1919
1920         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
1921                 amdgpu_ras_check_asic_type(adev))
1922                 return;
1923
1924         if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
1925                 dev_info(adev->dev, "HBM ECC is active.\n");
1926                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
1927                                 1 << AMDGPU_RAS_BLOCK__DF);
1928         } else
1929                 dev_info(adev->dev, "HBM ECC is not presented.\n");
1930
1931         if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
1932                 dev_info(adev->dev, "SRAM ECC is active.\n");
1933                 *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
1934                                 1 << AMDGPU_RAS_BLOCK__DF);
1935         } else
1936                 dev_info(adev->dev, "SRAM ECC is not presented.\n");
1937
1938         /* hw_supported needs to be aligned with RAS block mask. */
1939         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
1940
1941         *supported = amdgpu_ras_enable == 0 ?
1942                         0 : *hw_supported & amdgpu_ras_mask;
1943         adev->ras_features = *supported;
1944 }
1945
1946 int amdgpu_ras_init(struct amdgpu_device *adev)
1947 {
1948         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1949         int r;
1950
1951         if (con)
1952                 return 0;
1953
1954         con = kmalloc(sizeof(struct amdgpu_ras) +
1955                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
1956                         GFP_KERNEL|__GFP_ZERO);
1957         if (!con)
1958                 return -ENOMEM;
1959
1960         con->objs = (struct ras_manager *)(con + 1);
1961
1962         amdgpu_ras_set_context(adev, con);
1963
1964         amdgpu_ras_check_supported(adev, &con->hw_supported,
1965                         &con->supported);
1966         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
1967                 r = 0;
1968                 goto release_con;
1969         }
1970
1971         con->features = 0;
1972         INIT_LIST_HEAD(&con->head);
1973         /* Might need get this flag from vbios. */
1974         con->flags = RAS_DEFAULT_FLAGS;
1975
1976         if (adev->nbio.funcs->init_ras_controller_interrupt) {
1977                 r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
1978                 if (r)
1979                         goto release_con;
1980         }
1981
1982         if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
1983                 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
1984                 if (r)
1985                         goto release_con;
1986         }
1987
1988         if (amdgpu_ras_fs_init(adev)) {
1989                 r = -EINVAL;
1990                 goto release_con;
1991         }
1992
1993         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
1994                         "hardware ability[%x] ras_mask[%x]\n",
1995                         con->hw_supported, con->supported);
1996         return 0;
1997 release_con:
1998         amdgpu_ras_set_context(adev, NULL);
1999         kfree(con);
2000
2001         return r;
2002 }
2003
2004 /* helper function to handle common stuff in ip late init phase */
2005 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2006                          struct ras_common_if *ras_block,
2007                          struct ras_fs_if *fs_info,
2008                          struct ras_ih_if *ih_info)
2009 {
2010         int r;
2011
2012         /* disable RAS feature per IP block if it is not supported */
2013         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2014                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2015                 return 0;
2016         }
2017
2018         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2019         if (r) {
2020                 if (r == -EAGAIN) {
2021                         /* request gpu reset. will run again */
2022                         amdgpu_ras_request_reset_on_boot(adev,
2023                                         ras_block->block);
2024                         return 0;
2025                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2026                         /* in resume phase, if fail to enable ras,
2027                          * clean up all ras fs nodes, and disable ras */
2028                         goto cleanup;
2029                 } else
2030                         return r;
2031         }
2032
2033         /* in resume phase, no need to create ras fs node */
2034         if (adev->in_suspend || amdgpu_in_reset(adev))
2035                 return 0;
2036
2037         if (ih_info->cb) {
2038                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2039                 if (r)
2040                         goto interrupt;
2041         }
2042
2043         r = amdgpu_ras_sysfs_create(adev, fs_info);
2044         if (r)
2045                 goto sysfs;
2046
2047         return 0;
2048 cleanup:
2049         amdgpu_ras_sysfs_remove(adev, ras_block);
2050 sysfs:
2051         if (ih_info->cb)
2052                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2053 interrupt:
2054         amdgpu_ras_feature_enable(adev, ras_block, 0);
2055         return r;
2056 }
2057
2058 /* helper function to remove ras fs node and interrupt handler */
2059 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2060                           struct ras_common_if *ras_block,
2061                           struct ras_ih_if *ih_info)
2062 {
2063         if (!ras_block || !ih_info)
2064                 return;
2065
2066         amdgpu_ras_sysfs_remove(adev, ras_block);
2067         if (ih_info->cb)
2068                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2069         amdgpu_ras_feature_enable(adev, ras_block, 0);
2070 }
2071
2072 /* do some init work after IP late init as dependence.
2073  * and it runs in resume/gpu reset/booting up cases.
2074  */
2075 void amdgpu_ras_resume(struct amdgpu_device *adev)
2076 {
2077         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2078         struct ras_manager *obj, *tmp;
2079
2080         if (!con)
2081                 return;
2082
2083         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2084                 /* Set up all other IPs which are not implemented. There is a
2085                  * tricky thing that IP's actual ras error type should be
2086                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2087                  * ERROR_NONE make sense anyway.
2088                  */
2089                 amdgpu_ras_enable_all_features(adev, 1);
2090
2091                 /* We enable ras on all hw_supported block, but as boot
2092                  * parameter might disable some of them and one or more IP has
2093                  * not implemented yet. So we disable them on behalf.
2094                  */
2095                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2096                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2097                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2098                                 /* there should be no any reference. */
2099                                 WARN_ON(alive_obj(obj));
2100                         }
2101                 }
2102         }
2103
2104         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2105                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2106                 /* setup ras obj state as disabled.
2107                  * for init_by_vbios case.
2108                  * if we want to enable ras, just enable it in a normal way.
2109                  * If we want do disable it, need setup ras obj as enabled,
2110                  * then issue another TA disable cmd.
2111                  * See feature_enable_on_boot
2112                  */
2113                 amdgpu_ras_disable_all_features(adev, 1);
2114                 amdgpu_ras_reset_gpu(adev);
2115         }
2116 }
2117
2118 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2119 {
2120         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2121
2122         if (!con)
2123                 return;
2124
2125         amdgpu_ras_disable_all_features(adev, 0);
2126         /* Make sure all ras objects are disabled. */
2127         if (con->features)
2128                 amdgpu_ras_disable_all_features(adev, 1);
2129 }
2130
2131 /* do some fini work before IP fini as dependence */
2132 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2133 {
2134         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2135
2136         if (!con)
2137                 return 0;
2138
2139         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2140         amdgpu_ras_disable_all_features(adev, 0);
2141         amdgpu_ras_recovery_fini(adev);
2142         return 0;
2143 }
2144
2145 int amdgpu_ras_fini(struct amdgpu_device *adev)
2146 {
2147         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2148
2149         if (!con)
2150                 return 0;
2151
2152         amdgpu_ras_fs_fini(adev);
2153         amdgpu_ras_interrupt_remove_all(adev);
2154
2155         WARN(con->features, "Feature mask is not cleared");
2156
2157         if (con->features)
2158                 amdgpu_ras_disable_all_features(adev, 1);
2159
2160         amdgpu_ras_set_context(adev, NULL);
2161         kfree(con);
2162
2163         return 0;
2164 }
2165
2166 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2167 {
2168         uint32_t hw_supported, supported;
2169
2170         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2171         if (!hw_supported)
2172                 return;
2173
2174         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2175                 dev_info(adev->dev, "uncorrectable hardware error"
2176                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2177
2178                 amdgpu_ras_reset_gpu(adev);
2179         }
2180 }
2181
2182 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2183 {
2184         if (adev->asic_type == CHIP_VEGA20 &&
2185             adev->pm.fw_version <= 0x283400) {
2186                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2187                                 amdgpu_ras_intr_triggered();
2188         }
2189
2190         return false;
2191 }