drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_gfx.h"
  29 #include "amdgpu_rlc.h"
  30 #include "amdgpu_ras.h"
  31 #include "amdgpu_xcp.h"
  32
  33 /* delay 0.1 second to enable gfx off feature */
  34 #define GFX_OFF_DELAY_ENABLE         msecs_to_jiffies(100)
  35
  36 #define GFX_OFF_NO_DELAY 0
  37
  38 /*
  39  * GPU GFX IP block helpers function.
  40  */
  41
  42 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
  43                                 int pipe, int queue)
  44 {
  45         int bit = 0;
  46
  47         bit += mec * adev->gfx.mec.num_pipe_per_mec
  48                 * adev->gfx.mec.num_queue_per_pipe;
  49         bit += pipe * adev->gfx.mec.num_queue_per_pipe;
  50         bit += queue;
  51
  52         return bit;
  53 }
  54
  55 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
  56                                  int *mec, int *pipe, int *queue)
  57 {
  58         *queue = bit % adev->gfx.mec.num_queue_per_pipe;
  59         *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
  60                 % adev->gfx.mec.num_pipe_per_mec;
  61         *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
  62                / adev->gfx.mec.num_pipe_per_mec;
  63
  64 }
  65
  66 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
  67                                      int xcc_id, int mec, int pipe, int queue)
  68 {
  69         return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
  70                         adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
  71 }
  72
  73 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
  74                                int me, int pipe, int queue)
  75 {
  76         int bit = 0;
  77
  78         bit += me * adev->gfx.me.num_pipe_per_me
  79                 * adev->gfx.me.num_queue_per_pipe;
  80         bit += pipe * adev->gfx.me.num_queue_per_pipe;
  81         bit += queue;
  82
  83         return bit;
  84 }
  85
  86 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
  87                                 int *me, int *pipe, int *queue)
  88 {
  89         *queue = bit % adev->gfx.me.num_queue_per_pipe;
  90         *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
  91                 % adev->gfx.me.num_pipe_per_me;
  92         *me = (bit / adev->gfx.me.num_queue_per_pipe)
  93                 / adev->gfx.me.num_pipe_per_me;
  94 }
  95
  96 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev,
  97                                     int me, int pipe, int queue)
  98 {
  99         return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
 100                         adev->gfx.me.queue_bitmap);
 101 }
 102
 103 /**
 104  * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
 105  *
 106  * @mask: array in which the per-shader array disable masks will be stored
 107  * @max_se: number of SEs
 108  * @max_sh: number of SHs
 109  *
 110  * The bitmask of CUs to be disabled in the shader array determined by se and
 111  * sh is stored in mask[se * max_sh + sh].
 112  */
 113 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
 114 {
 115         unsigned se, sh, cu;
 116         const char *p;
 117
 118         memset(mask, 0, sizeof(*mask) * max_se * max_sh);
 119
 120         if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
 121                 return;
 122
 123         p = amdgpu_disable_cu;
 124         for (;;) {
 125                 char *next;
 126                 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
 127                 if (ret < 3) {
 128                         DRM_ERROR("amdgpu: could not parse disable_cu\n");
 129                         return;
 130                 }
 131
 132                 if (se < max_se && sh < max_sh && cu < 16) {
 133                         DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
 134                         mask[se * max_sh + sh] |= 1u << cu;
 135                 } else {
 136                         DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
 137                                   se, sh, cu);
 138                 }
 139
 140                 next = strchr(p, ',');
 141                 if (!next)
 142                         break;
 143                 p = next + 1;
 144         }
 145 }
 146
 147 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev)
 148 {
 149         return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
 150 }
 151
 152 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
 153 {
 154         if (amdgpu_compute_multipipe != -1) {
 155                 DRM_INFO("amdgpu: forcing compute pipe policy %d\n",
 156                          amdgpu_compute_multipipe);
 157                 return amdgpu_compute_multipipe == 1;
 158         }
 159
 160         if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
 161                 return true;
 162
 163         /* FIXME: spreading the queues across pipes causes perf regressions
 164          * on POLARIS11 compute workloads */
 165         if (adev->asic_type == CHIP_POLARIS11)
 166                 return false;
 167
 168         return adev->gfx.mec.num_mec > 1;
 169 }
 170
 171 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
 172                                                 struct amdgpu_ring *ring)
 173 {
 174         int queue = ring->queue;
 175         int pipe = ring->pipe;
 176
 177         /* Policy: use pipe1 queue0 as high priority graphics queue if we
 178          * have more than one gfx pipe.
 179          */
 180         if (amdgpu_gfx_is_graphics_multipipe_capable(adev) &&
 181             adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
 182                 int me = ring->me;
 183                 int bit;
 184
 185                 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
 186                 if (ring == &adev->gfx.gfx_ring[bit])
 187                         return true;
 188         }
 189
 190         return false;
 191 }
 192
 193 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
 194                                                struct amdgpu_ring *ring)
 195 {
 196         /* Policy: use 1st queue as high priority compute queue if we
 197          * have more than one compute queue.
 198          */
 199         if (adev->gfx.num_compute_rings > 1 &&
 200             ring == &adev->gfx.compute_ring[0])
 201                 return true;
 202
 203         return false;
 204 }
 205
 206 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
 207 {
 208         int i, j, queue, pipe;
 209         bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
 210         int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
 211                                      adev->gfx.mec.num_queue_per_pipe,
 212                                      adev->gfx.num_compute_rings);
 213         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 214
 215         if (multipipe_policy) {
 216                 /* policy: make queues evenly cross all pipes on MEC1 only
 217                  * for multiple xcc, just use the original policy for simplicity */
 218                 for (j = 0; j < num_xcc; j++) {
 219                         for (i = 0; i < max_queues_per_mec; i++) {
 220                                 pipe = i % adev->gfx.mec.num_pipe_per_mec;
 221                                 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
 222                                          adev->gfx.mec.num_queue_per_pipe;
 223
 224                                 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
 225                                         adev->gfx.mec_bitmap[j].queue_bitmap);
 226                         }
 227                 }
 228         } else {
 229                 /* policy: amdgpu owns all queues in the given pipe */
 230                 for (j = 0; j < num_xcc; j++) {
 231                         for (i = 0; i < max_queues_per_mec; ++i)
 232                                 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
 233                 }
 234         }
 235
 236         for (j = 0; j < num_xcc; j++) {
 237                 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
 238                         bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
 239         }
 240 }
 241
 242 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
 243 {
 244         int i, queue, pipe;
 245         bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev);
 246         int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
 247                                         adev->gfx.me.num_queue_per_pipe;
 248
 249         if (multipipe_policy) {
 250                 /* policy: amdgpu owns the first queue per pipe at this stage
 251                  * will extend to mulitple queues per pipe later */
 252                 for (i = 0; i < max_queues_per_me; i++) {
 253                         pipe = i % adev->gfx.me.num_pipe_per_me;
 254                         queue = (i / adev->gfx.me.num_pipe_per_me) %
 255                                 adev->gfx.me.num_queue_per_pipe;
 256
 257                         set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
 258                                 adev->gfx.me.queue_bitmap);
 259                 }
 260         } else {
 261                 for (i = 0; i < max_queues_per_me; ++i)
 262                         set_bit(i, adev->gfx.me.queue_bitmap);
 263         }
 264
 265         /* update the number of active graphics rings */
 266         adev->gfx.num_gfx_rings =
 267                 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 268 }
 269
 270 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev,
 271                                   struct amdgpu_ring *ring, int xcc_id)
 272 {
 273         int queue_bit;
 274         int mec, pipe, queue;
 275
 276         queue_bit = adev->gfx.mec.num_mec
 277                     * adev->gfx.mec.num_pipe_per_mec
 278                     * adev->gfx.mec.num_queue_per_pipe;
 279
 280         while (--queue_bit >= 0) {
 281                 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 282                         continue;
 283
 284                 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 285
 286                 /*
 287                  * 1. Using pipes 2/3 from MEC 2 seems cause problems.
 288                  * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
 289                  * only can be issued on queue 0.
 290                  */
 291                 if ((mec == 1 && pipe > 1) || queue != 0)
 292                         continue;
 293
 294                 ring->me = mec + 1;
 295                 ring->pipe = pipe;
 296                 ring->queue = queue;
 297
 298                 return 0;
 299         }
 300
 301         dev_err(adev->dev, "Failed to find a queue for KIQ\n");
 302         return -EINVAL;
 303 }
 304
 305 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 306                              struct amdgpu_ring *ring,
 307                              struct amdgpu_irq_src *irq, int xcc_id)
 308 {
 309         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 310         int r = 0;
 311
 312         spin_lock_init(&kiq->ring_lock);
 313
 314         ring->adev = NULL;
 315         ring->ring_obj = NULL;
 316         ring->use_doorbell = true;
 317         ring->xcc_id = xcc_id;
 318         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 319         ring->doorbell_index = (adev->doorbell_index.kiq + xcc_id) << 1;
 320
 321         r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id);
 322         if (r)
 323                 return r;
 324
 325         ring->eop_gpu_addr = kiq->eop_gpu_addr;
 326         ring->no_scheduler = true;
 327         sprintf(ring->name, "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
 328         r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0,
 329                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 330         if (r)
 331                 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
 332
 333         return r;
 334 }
 335
 336 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 337 {
 338         amdgpu_ring_fini(ring);
 339 }
 340
 341 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id)
 342 {
 343         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 344
 345         amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL);
 346 }
 347
 348 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
 349                         unsigned hpd_size, int xcc_id)
 350 {
 351         int r;
 352         u32 *hpd;
 353         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 354
 355         r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE,
 356                                     AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj,
 357                                     &kiq->eop_gpu_addr, (void **)&hpd);
 358         if (r) {
 359                 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r);
 360                 return r;
 361         }
 362
 363         memset(hpd, 0, hpd_size);
 364
 365         r = amdgpu_bo_reserve(kiq->eop_obj, true);
 366         if (unlikely(r != 0))
 367                 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r);
 368         amdgpu_bo_kunmap(kiq->eop_obj);
 369         amdgpu_bo_unreserve(kiq->eop_obj);
 370
 371         return 0;
 372 }
 373
 374 /* create MQD for each compute/gfx queue */
 375 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
 376                            unsigned mqd_size, int xcc_id)
 377 {
 378         int r, i, j;
 379         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 380         struct amdgpu_ring *ring = &kiq->ring;
 381         u32 domain = AMDGPU_GEM_DOMAIN_GTT;
 382
 383         /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */
 384         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0))
 385                 domain |= AMDGPU_GEM_DOMAIN_VRAM;
 386
 387         /* create MQD for KIQ */
 388         if (!adev->enable_mes_kiq && !ring->mqd_obj) {
 389                 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must
 390                  * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD
 391                  * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for
 392                  * KIQ MQD no matter SRIOV or Bare-metal
 393                  */
 394                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 395                                             AMDGPU_GEM_DOMAIN_VRAM |
 396                                             AMDGPU_GEM_DOMAIN_GTT,
 397                                             &ring->mqd_obj,
 398                                             &ring->mqd_gpu_addr,
 399                                             &ring->mqd_ptr);
 400                 if (r) {
 401                         dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
 402                         return r;
 403                 }
 404
 405                 /* prepare MQD backup */
 406                 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL);
 407                 if (!kiq->mqd_backup)
 408                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 409         }
 410
 411         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 412                 /* create MQD for each KGQ */
 413                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 414                         ring = &adev->gfx.gfx_ring[i];
 415                         if (!ring->mqd_obj) {
 416                                 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 417                                                             domain, &ring->mqd_obj,
 418                                                             &ring->mqd_gpu_addr, &ring->mqd_ptr);
 419                                 if (r) {
 420                                         dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 421                                         return r;
 422                                 }
 423
 424                                 ring->mqd_size = mqd_size;
 425                                 /* prepare MQD backup */
 426                                 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
 427                                 if (!adev->gfx.me.mqd_backup[i])
 428                                         dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 429                         }
 430                 }
 431         }
 432
 433         /* create MQD for each KCQ */
 434         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 435                 j = i + xcc_id * adev->gfx.num_compute_rings;
 436                 ring = &adev->gfx.compute_ring[j];
 437                 if (!ring->mqd_obj) {
 438                         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
 439                                                     domain, &ring->mqd_obj,
 440                                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
 441                         if (r) {
 442                                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
 443                                 return r;
 444                         }
 445
 446                         ring->mqd_size = mqd_size;
 447                         /* prepare MQD backup */
 448                         adev->gfx.mec.mqd_backup[j + xcc_id * adev->gfx.num_compute_rings] = kmalloc(mqd_size, GFP_KERNEL);
 449                         if (!adev->gfx.mec.mqd_backup[j + xcc_id * adev->gfx.num_compute_rings])
 450                                 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name);
 451                 }
 452         }
 453
 454         return 0;
 455 }
 456
 457 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id)
 458 {
 459         struct amdgpu_ring *ring = NULL;
 460         int i, j;
 461         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 462
 463         if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) {
 464                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 465                         ring = &adev->gfx.gfx_ring[i];
 466                         kfree(adev->gfx.me.mqd_backup[i]);
 467                         amdgpu_bo_free_kernel(&ring->mqd_obj,
 468                                               &ring->mqd_gpu_addr,
 469                                               &ring->mqd_ptr);
 470                 }
 471         }
 472
 473         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 474                 j = i + xcc_id * adev->gfx.num_compute_rings;
 475                 ring = &adev->gfx.compute_ring[j];
 476                 kfree(adev->gfx.mec.mqd_backup[j]);
 477                 amdgpu_bo_free_kernel(&ring->mqd_obj,
 478                                       &ring->mqd_gpu_addr,
 479                                       &ring->mqd_ptr);
 480         }
 481
 482         ring = &kiq->ring;
 483         kfree(kiq->mqd_backup);
 484         amdgpu_bo_free_kernel(&ring->mqd_obj,
 485                               &ring->mqd_gpu_addr,
 486                               &ring->mqd_ptr);
 487 }
 488
 489 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id)
 490 {
 491         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 492         struct amdgpu_ring *kiq_ring = &kiq->ring;
 493         int i, r = 0;
 494         int j;
 495
 496         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 497                 return -EINVAL;
 498
 499         spin_lock(&kiq->ring_lock);
 500         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 501                                         adev->gfx.num_compute_rings)) {
 502                 spin_unlock(&kiq->ring_lock);
 503                 return -ENOMEM;
 504         }
 505
 506         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 507                 j = i + xcc_id * adev->gfx.num_compute_rings;
 508                 kiq->pmf->kiq_unmap_queues(kiq_ring,
 509                                            &adev->gfx.compute_ring[i],
 510                                            RESET_QUEUES, 0, 0);
 511         }
 512
 513         if (kiq_ring->sched.ready && !adev->job_hang)
 514                 r = amdgpu_ring_test_helper(kiq_ring);
 515         spin_unlock(&kiq->ring_lock);
 516
 517         return r;
 518 }
 519
 520 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id)
 521 {
 522         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 523         struct amdgpu_ring *kiq_ring = &kiq->ring;
 524         int i, r = 0;
 525         int j;
 526
 527         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
 528                 return -EINVAL;
 529
 530         spin_lock(&kiq->ring_lock);
 531         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 532                 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
 533                                                 adev->gfx.num_gfx_rings)) {
 534                         spin_unlock(&kiq->ring_lock);
 535                         return -ENOMEM;
 536                 }
 537
 538                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 539                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 540                         kiq->pmf->kiq_unmap_queues(kiq_ring,
 541                                                    &adev->gfx.gfx_ring[i],
 542                                                    PREEMPT_QUEUES, 0, 0);
 543                 }
 544         }
 545
 546         if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
 547                 r = amdgpu_ring_test_helper(kiq_ring);
 548         spin_unlock(&kiq->ring_lock);
 549
 550         return r;
 551 }
 552
 553 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
 554                                         int queue_bit)
 555 {
 556         int mec, pipe, queue;
 557         int set_resource_bit = 0;
 558
 559         amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
 560
 561         set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
 562
 563         return set_resource_bit;
 564 }
 565
 566 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id)
 567 {
 568         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 569         struct amdgpu_ring *kiq_ring = &kiq->ring;
 570         uint64_t queue_mask = 0;
 571         int r, i, j;
 572
 573         if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources)
 574                 return -EINVAL;
 575
 576         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
 577                 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
 578                         continue;
 579
 580                 /* This situation may be hit in the future if a new HW
 581                  * generation exposes more than 64 queues. If so, the
 582                  * definition of queue_mask needs updating */
 583                 if (WARN_ON(i > (sizeof(queue_mask)*8))) {
 584                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
 585                         break;
 586                 }
 587
 588                 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i));
 589         }
 590
 591         DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe,
 592                                                         kiq_ring->queue);
 593         spin_lock(&kiq->ring_lock);
 594         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 595                                         adev->gfx.num_compute_rings +
 596                                         kiq->pmf->set_resources_size);
 597         if (r) {
 598                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 599                 spin_unlock(&kiq->ring_lock);
 600                 return r;
 601         }
 602
 603         if (adev->enable_mes)
 604                 queue_mask = ~0ULL;
 605
 606         kiq->pmf->kiq_set_resources(kiq_ring, queue_mask);
 607         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 608                 j = i + xcc_id * adev->gfx.num_compute_rings;
 609                         kiq->pmf->kiq_map_queues(kiq_ring,
 610                                                  &adev->gfx.compute_ring[j]);
 611         }
 612
 613         r = amdgpu_ring_test_helper(kiq_ring);
 614         spin_unlock(&kiq->ring_lock);
 615         if (r)
 616                 DRM_ERROR("KCQ enable failed\n");
 617
 618         return r;
 619 }
 620
 621 int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id)
 622 {
 623         struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
 624         struct amdgpu_ring *kiq_ring = &kiq->ring;
 625         int r, i, j;
 626
 627         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 628                 return -EINVAL;
 629
 630         spin_lock(&kiq->ring_lock);
 631         /* No need to map kcq on the slave */
 632         if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {
 633                 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
 634                                                 adev->gfx.num_gfx_rings);
 635                 if (r) {
 636                         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 637                         spin_unlock(&kiq->ring_lock);
 638                         return r;
 639                 }
 640
 641                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 642                         j = i + xcc_id * adev->gfx.num_gfx_rings;
 643                         kiq->pmf->kiq_map_queues(kiq_ring,
 644                                                  &adev->gfx.gfx_ring[i]);
 645                 }
 646         }
 647
 648         r = amdgpu_ring_test_helper(kiq_ring);
 649         spin_unlock(&kiq->ring_lock);
 650         if (r)
 651                 DRM_ERROR("KCQ enable failed\n");
 652
 653         return r;
 654 }
 655
 656 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
 657  *
 658  * @adev: amdgpu_device pointer
 659  * @bool enable true: enable gfx off feature, false: disable gfx off feature
 660  *
 661  * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
 662  * 2. other client can send request to disable gfx off feature, the request should be honored.
 663  * 3. other client can cancel their request of disable gfx off feature
 664  * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
 665  */
 666
 667 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
 668 {
 669         unsigned long delay = GFX_OFF_DELAY_ENABLE;
 670
 671         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 672                 return;
 673
 674         mutex_lock(&adev->gfx.gfx_off_mutex);
 675
 676         if (enable) {
 677                 /* If the count is already 0, it means there's an imbalance bug somewhere.
 678                  * Note that the bug may be in a different caller than the one which triggers the
 679                  * WARN_ON_ONCE.
 680                  */
 681                 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
 682                         goto unlock;
 683
 684                 adev->gfx.gfx_off_req_count--;
 685
 686                 if (adev->gfx.gfx_off_req_count == 0 &&
 687                     !adev->gfx.gfx_off_state) {
 688                         /* If going to s2idle, no need to wait */
 689                         if (adev->in_s0ix) {
 690                                 if (!amdgpu_dpm_set_powergating_by_smu(adev,
 691                                                 AMD_IP_BLOCK_TYPE_GFX, true))
 692                                         adev->gfx.gfx_off_state = true;
 693                         } else {
 694                                 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
 695                                               delay);
 696                         }
 697                 }
 698         } else {
 699                 if (adev->gfx.gfx_off_req_count == 0) {
 700                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
 701
 702                         if (adev->gfx.gfx_off_state &&
 703                             !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) {
 704                                 adev->gfx.gfx_off_state = false;
 705
 706                                 if (adev->gfx.funcs->init_spm_golden) {
 707                                         dev_dbg(adev->dev,
 708                                                 "GFXOFF is disabled, re-init SPM golden settings\n");
 709                                         amdgpu_gfx_init_spm_golden(adev);
 710                                 }
 711                         }
 712                 }
 713
 714                 adev->gfx.gfx_off_req_count++;
 715         }
 716
 717 unlock:
 718         mutex_unlock(&adev->gfx.gfx_off_mutex);
 719 }
 720
 721 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value)
 722 {
 723         int r = 0;
 724
 725         mutex_lock(&adev->gfx.gfx_off_mutex);
 726
 727         r = amdgpu_dpm_set_residency_gfxoff(adev, value);
 728
 729         mutex_unlock(&adev->gfx.gfx_off_mutex);
 730
 731         return r;
 732 }
 733
 734 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value)
 735 {
 736         int r = 0;
 737
 738         mutex_lock(&adev->gfx.gfx_off_mutex);
 739
 740         r = amdgpu_dpm_get_residency_gfxoff(adev, value);
 741
 742         mutex_unlock(&adev->gfx.gfx_off_mutex);
 743
 744         return r;
 745 }
 746
 747 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value)
 748 {
 749         int r = 0;
 750
 751         mutex_lock(&adev->gfx.gfx_off_mutex);
 752
 753         r = amdgpu_dpm_get_entrycount_gfxoff(adev, value);
 754
 755         mutex_unlock(&adev->gfx.gfx_off_mutex);
 756
 757         return r;
 758 }
 759
 760 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
 761 {
 762
 763         int r = 0;
 764
 765         mutex_lock(&adev->gfx.gfx_off_mutex);
 766
 767         r = amdgpu_dpm_get_status_gfxoff(adev, value);
 768
 769         mutex_unlock(&adev->gfx.gfx_off_mutex);
 770
 771         return r;
 772 }
 773
 774 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 775 {
 776         int r;
 777
 778         if (amdgpu_ras_is_supported(adev, ras_block->block)) {
 779                 if (!amdgpu_persistent_edc_harvesting_supported(adev))
 780                         amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX);
 781
 782                 r = amdgpu_ras_block_late_init(adev, ras_block);
 783                 if (r)
 784                         return r;
 785
 786                 if (adev->gfx.cp_ecc_error_irq.funcs) {
 787                         r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
 788                         if (r)
 789                                 goto late_fini;
 790                 }
 791         } else {
 792                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
 793         }
 794
 795         return 0;
 796 late_fini:
 797         amdgpu_ras_block_late_fini(adev, ras_block);
 798         return r;
 799 }
 800
 801 int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev)
 802 {
 803         int err = 0;
 804         struct amdgpu_gfx_ras *ras = NULL;
 805
 806         /* adev->gfx.ras is NULL, which means gfx does not
 807          * support ras function, then do nothing here.
 808          */
 809         if (!adev->gfx.ras)
 810                 return 0;
 811
 812         ras = adev->gfx.ras;
 813
 814         err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
 815         if (err) {
 816                 dev_err(adev->dev, "Failed to register gfx ras block!\n");
 817                 return err;
 818         }
 819
 820         strcpy(ras->ras_block.ras_comm.name, "gfx");
 821         ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX;
 822         ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 823         adev->gfx.ras_if = &ras->ras_block.ras_comm;
 824
 825         /* If not define special ras_late_init function, use gfx default ras_late_init */
 826         if (!ras->ras_block.ras_late_init)
 827                 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init;
 828
 829         /* If not defined special ras_cb function, use default ras_cb */
 830         if (!ras->ras_block.ras_cb)
 831                 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb;
 832
 833         return 0;
 834 }
 835
 836 int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev,
 837                                                 struct amdgpu_iv_entry *entry)
 838 {
 839         if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
 840                 return adev->gfx.ras->poison_consumption_handler(adev, entry);
 841
 842         return 0;
 843 }
 844
 845 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
 846                 void *err_data,
 847                 struct amdgpu_iv_entry *entry)
 848 {
 849         /* TODO ue will trigger an interrupt.
 850          *
 851          * When “Full RAS” is enabled, the per-IP interrupt sources should
 852          * be disabled and the driver should only look for the aggregated
 853          * interrupt via sync flood
 854          */
 855         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
 856                 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
 857                 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
 858                     adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
 859                         adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
 860                 amdgpu_ras_reset_gpu(adev);
 861         }
 862         return AMDGPU_RAS_SUCCESS;
 863 }
 864
 865 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
 866                                   struct amdgpu_irq_src *source,
 867                                   struct amdgpu_iv_entry *entry)
 868 {
 869         struct ras_common_if *ras_if = adev->gfx.ras_if;
 870         struct ras_dispatch_if ih_data = {
 871                 .entry = entry,
 872         };
 873
 874         if (!ras_if)
 875                 return 0;
 876
 877         ih_data.head = *ras_if;
 878
 879         DRM_ERROR("CP ECC ERROR IRQ\n");
 880         amdgpu_ras_interrupt_dispatch(adev, &ih_data);
 881         return 0;
 882 }
 883
 884 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
 885 {
 886         signed long r, cnt = 0;
 887         unsigned long flags;
 888         uint32_t seq, reg_val_offs = 0, value = 0;
 889         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 890         struct amdgpu_ring *ring = &kiq->ring;
 891
 892         if (amdgpu_device_skip_hw_access(adev))
 893                 return 0;
 894
 895         if (adev->mes.ring.sched.ready)
 896                 return amdgpu_mes_rreg(adev, reg);
 897
 898         BUG_ON(!ring->funcs->emit_rreg);
 899
 900         spin_lock_irqsave(&kiq->ring_lock, flags);
 901         if (amdgpu_device_wb_get(adev, &reg_val_offs)) {
 902                 pr_err("critical bug! too many kiq readers\n");
 903                 goto failed_unlock;
 904         }
 905         amdgpu_ring_alloc(ring, 32);
 906         amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
 907         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 908         if (r)
 909                 goto failed_undo;
 910
 911         amdgpu_ring_commit(ring);
 912         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 913
 914         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 915
 916         /* don't wait anymore for gpu reset case because this way may
 917          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 918          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 919          * never return if we keep waiting in virt_kiq_rreg, which cause
 920          * gpu_recover() hang there.
 921          *
 922          * also don't wait anymore for IRQ context
 923          * */
 924         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 925                 goto failed_kiq_read;
 926
 927         might_sleep();
 928         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 929                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 930                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 931         }
 932
 933         if (cnt > MAX_KIQ_REG_TRY)
 934                 goto failed_kiq_read;
 935
 936         mb();
 937         value = adev->wb.wb[reg_val_offs];
 938         amdgpu_device_wb_free(adev, reg_val_offs);
 939         return value;
 940
 941 failed_undo:
 942         amdgpu_ring_undo(ring);
 943 failed_unlock:
 944         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 945 failed_kiq_read:
 946         if (reg_val_offs)
 947                 amdgpu_device_wb_free(adev, reg_val_offs);
 948         dev_err(adev->dev, "failed to read reg:%x\n", reg);
 949         return ~0;
 950 }
 951
 952 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 953 {
 954         signed long r, cnt = 0;
 955         unsigned long flags;
 956         uint32_t seq;
 957         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
 958         struct amdgpu_ring *ring = &kiq->ring;
 959
 960         BUG_ON(!ring->funcs->emit_wreg);
 961
 962         if (amdgpu_device_skip_hw_access(adev))
 963                 return;
 964
 965         if (adev->mes.ring.sched.ready) {
 966                 amdgpu_mes_wreg(adev, reg, v);
 967                 return;
 968         }
 969
 970         spin_lock_irqsave(&kiq->ring_lock, flags);
 971         amdgpu_ring_alloc(ring, 32);
 972         amdgpu_ring_emit_wreg(ring, reg, v);
 973         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 974         if (r)
 975                 goto failed_undo;
 976
 977         amdgpu_ring_commit(ring);
 978         spin_unlock_irqrestore(&kiq->ring_lock, flags);
 979
 980         r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 981
 982         /* don't wait anymore for gpu reset case because this way may
 983          * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
 984          * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
 985          * never return if we keep waiting in virt_kiq_rreg, which cause
 986          * gpu_recover() hang there.
 987          *
 988          * also don't wait anymore for IRQ context
 989          * */
 990         if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt()))
 991                 goto failed_kiq_write;
 992
 993         might_sleep();
 994         while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
 995
 996                 msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
 997                 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
 998         }
 999
1000         if (cnt > MAX_KIQ_REG_TRY)
1001                 goto failed_kiq_write;
1002
1003         return;
1004
1005 failed_undo:
1006         amdgpu_ring_undo(ring);
1007         spin_unlock_irqrestore(&kiq->ring_lock, flags);
1008 failed_kiq_write:
1009         dev_err(adev->dev, "failed to write reg:%x\n", reg);
1010 }
1011
1012 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev)
1013 {
1014         if (amdgpu_num_kcq == -1) {
1015                 return 8;
1016         } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) {
1017                 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");
1018                 return 8;
1019         }
1020         return amdgpu_num_kcq;
1021 }
1022
1023 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev,
1024                                   uint32_t ucode_id)
1025 {
1026         const struct gfx_firmware_header_v1_0 *cp_hdr;
1027         const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0;
1028         struct amdgpu_firmware_info *info = NULL;
1029         const struct firmware *ucode_fw;
1030         unsigned int fw_size;
1031
1032         switch (ucode_id) {
1033         case AMDGPU_UCODE_ID_CP_PFP:
1034                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1035                         adev->gfx.pfp_fw->data;
1036                 adev->gfx.pfp_fw_version =
1037                         le32_to_cpu(cp_hdr->header.ucode_version);
1038                 adev->gfx.pfp_feature_version =
1039                         le32_to_cpu(cp_hdr->ucode_feature_version);
1040                 ucode_fw = adev->gfx.pfp_fw;
1041                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1042                 break;
1043         case AMDGPU_UCODE_ID_CP_RS64_PFP:
1044                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1045                         adev->gfx.pfp_fw->data;
1046                 adev->gfx.pfp_fw_version =
1047                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1048                 adev->gfx.pfp_feature_version =
1049                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1050                 ucode_fw = adev->gfx.pfp_fw;
1051                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1052                 break;
1053         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
1054         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
1055                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1056                         adev->gfx.pfp_fw->data;
1057                 ucode_fw = adev->gfx.pfp_fw;
1058                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1059                 break;
1060         case AMDGPU_UCODE_ID_CP_ME:
1061                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1062                         adev->gfx.me_fw->data;
1063                 adev->gfx.me_fw_version =
1064                         le32_to_cpu(cp_hdr->header.ucode_version);
1065                 adev->gfx.me_feature_version =
1066                         le32_to_cpu(cp_hdr->ucode_feature_version);
1067                 ucode_fw = adev->gfx.me_fw;
1068                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1069                 break;
1070         case AMDGPU_UCODE_ID_CP_RS64_ME:
1071                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1072                         adev->gfx.me_fw->data;
1073                 adev->gfx.me_fw_version =
1074                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1075                 adev->gfx.me_feature_version =
1076                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1077                 ucode_fw = adev->gfx.me_fw;
1078                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1079                 break;
1080         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
1081         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
1082                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1083                         adev->gfx.me_fw->data;
1084                 ucode_fw = adev->gfx.me_fw;
1085                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1086                 break;
1087         case AMDGPU_UCODE_ID_CP_CE:
1088                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1089                         adev->gfx.ce_fw->data;
1090                 adev->gfx.ce_fw_version =
1091                         le32_to_cpu(cp_hdr->header.ucode_version);
1092                 adev->gfx.ce_feature_version =
1093                         le32_to_cpu(cp_hdr->ucode_feature_version);
1094                 ucode_fw = adev->gfx.ce_fw;
1095                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1096                 break;
1097         case AMDGPU_UCODE_ID_CP_MEC1:
1098                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1099                         adev->gfx.mec_fw->data;
1100                 adev->gfx.mec_fw_version =
1101                         le32_to_cpu(cp_hdr->header.ucode_version);
1102                 adev->gfx.mec_feature_version =
1103                         le32_to_cpu(cp_hdr->ucode_feature_version);
1104                 ucode_fw = adev->gfx.mec_fw;
1105                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1106                           le32_to_cpu(cp_hdr->jt_size) * 4;
1107                 break;
1108         case AMDGPU_UCODE_ID_CP_MEC1_JT:
1109                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1110                         adev->gfx.mec_fw->data;
1111                 ucode_fw = adev->gfx.mec_fw;
1112                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1113                 break;
1114         case AMDGPU_UCODE_ID_CP_MEC2:
1115                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1116                         adev->gfx.mec2_fw->data;
1117                 adev->gfx.mec2_fw_version =
1118                         le32_to_cpu(cp_hdr->header.ucode_version);
1119                 adev->gfx.mec2_feature_version =
1120                         le32_to_cpu(cp_hdr->ucode_feature_version);
1121                 ucode_fw = adev->gfx.mec2_fw;
1122                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1123                           le32_to_cpu(cp_hdr->jt_size) * 4;
1124                 break;
1125         case AMDGPU_UCODE_ID_CP_MEC2_JT:
1126                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1127                         adev->gfx.mec2_fw->data;
1128                 ucode_fw = adev->gfx.mec2_fw;
1129                 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4;
1130                 break;
1131         case AMDGPU_UCODE_ID_CP_RS64_MEC:
1132                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1133                         adev->gfx.mec_fw->data;
1134                 adev->gfx.mec_fw_version =
1135                         le32_to_cpu(cp_hdr_v2_0->header.ucode_version);
1136                 adev->gfx.mec_feature_version =
1137                         le32_to_cpu(cp_hdr_v2_0->ucode_feature_version);
1138                 ucode_fw = adev->gfx.mec_fw;
1139                 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes);
1140                 break;
1141         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
1142         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
1143         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
1144         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
1145                 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *)
1146                         adev->gfx.mec_fw->data;
1147                 ucode_fw = adev->gfx.mec_fw;
1148                 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes);
1149                 break;
1150         default:
1151                 break;
1152         }
1153
1154         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1155                 info = &adev->firmware.ucode[ucode_id];
1156                 info->ucode_id = ucode_id;
1157                 info->fw = ucode_fw;
1158                 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE);
1159         }
1160 }
1161
1162 bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id)
1163 {
1164         return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1165                         adev->gfx.num_xcc_per_xcp : 1));
1166 }
1167
1168 static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev,
1169                                                 struct device_attribute *addr,
1170                                                 char *buf)
1171 {
1172         struct drm_device *ddev = dev_get_drvdata(dev);
1173         struct amdgpu_device *adev = drm_to_adev(ddev);
1174         int mode;
1175         char *partition_mode;
1176
1177         mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr);
1178
1179         switch (mode) {
1180         case AMDGPU_SPX_PARTITION_MODE:
1181                 partition_mode = "SPX";
1182                 break;
1183         case AMDGPU_DPX_PARTITION_MODE:
1184                 partition_mode = "DPX";
1185                 break;
1186         case AMDGPU_TPX_PARTITION_MODE:
1187                 partition_mode = "TPX";
1188                 break;
1189         case AMDGPU_QPX_PARTITION_MODE:
1190                 partition_mode = "QPX";
1191                 break;
1192         case AMDGPU_CPX_PARTITION_MODE:
1193                 partition_mode = "CPX";
1194                 break;
1195         default:
1196                 partition_mode = "UNKNOWN";
1197                 break;
1198         }
1199
1200         return sysfs_emit(buf, "%s\n", partition_mode);
1201 }
1202
1203 static ssize_t amdgpu_gfx_get_current_memory_partition(struct device *dev,
1204                                                 struct device_attribute *addr,
1205                                                 char *buf)
1206 {
1207         struct drm_device *ddev = dev_get_drvdata(dev);
1208         struct amdgpu_device *adev = drm_to_adev(ddev);
1209         enum amdgpu_memory_partition mode;
1210         static const char *partition_modes[] = {
1211                 "UNKNOWN", "NPS1", "NPS2", "NPS4", "NPS8"
1212         };
1213         BUILD_BUG_ON(ARRAY_SIZE(partition_modes) <= AMDGPU_NPS8_PARTITION_MODE);
1214
1215         mode = min((int)adev->gfx.funcs->query_mem_partition_mode(adev),
1216                 AMDGPU_NPS8_PARTITION_MODE);
1217
1218         return sysfs_emit(buf, "%s\n", partition_modes[mode]);
1219 }
1220
1221 static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev,
1222                                                 struct device_attribute *addr,
1223                                                 const char *buf, size_t count)
1224 {
1225         struct drm_device *ddev = dev_get_drvdata(dev);
1226         struct amdgpu_device *adev = drm_to_adev(ddev);
1227         enum amdgpu_gfx_partition mode;
1228         int ret = 0, num_xcc;
1229
1230         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1231         if (num_xcc % 2 != 0)
1232                 return -EINVAL;
1233
1234         if (!strncasecmp("SPX", buf, strlen("SPX"))) {
1235                 mode = AMDGPU_SPX_PARTITION_MODE;
1236         } else if (!strncasecmp("DPX", buf, strlen("DPX"))) {
1237                 /*
1238                  * DPX mode needs AIDs to be in multiple of 2.
1239                  * Each AID connects 2 XCCs.
1240                  */
1241                 if (num_xcc%4)
1242                         return -EINVAL;
1243                 mode = AMDGPU_DPX_PARTITION_MODE;
1244         } else if (!strncasecmp("TPX", buf, strlen("TPX"))) {
1245                 if (num_xcc != 6)
1246                         return -EINVAL;
1247                 mode = AMDGPU_TPX_PARTITION_MODE;
1248         } else if (!strncasecmp("QPX", buf, strlen("QPX"))) {
1249                 if (num_xcc != 8)
1250                         return -EINVAL;
1251                 mode = AMDGPU_QPX_PARTITION_MODE;
1252         } else if (!strncasecmp("CPX", buf, strlen("CPX"))) {
1253                 mode = AMDGPU_CPX_PARTITION_MODE;
1254         } else {
1255                 return -EINVAL;
1256         }
1257
1258         ret = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, mode);
1259
1260         if (ret)
1261                 return ret;
1262
1263         return count;
1264 }
1265
1266 static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev,
1267                                                 struct device_attribute *addr,
1268                                                 char *buf)
1269 {
1270         struct drm_device *ddev = dev_get_drvdata(dev);
1271         struct amdgpu_device *adev = drm_to_adev(ddev);
1272         char *supported_partition;
1273
1274         /* TBD */
1275         switch (NUM_XCC(adev->gfx.xcc_mask)) {
1276         case 8:
1277                 supported_partition = "SPX, DPX, QPX, CPX";
1278                 break;
1279         case 6:
1280                 supported_partition = "SPX, TPX, CPX";
1281                 break;
1282         case 4:
1283                 supported_partition = "SPX, DPX, CPX";
1284                 break;
1285         /* this seems only existing in emulation phase */
1286         case 2:
1287                 supported_partition = "SPX, CPX";
1288                 break;
1289         default:
1290                 supported_partition = "Not supported";
1291                 break;
1292         }
1293
1294         return sysfs_emit(buf, "%s\n", supported_partition);
1295 }
1296
1297 static DEVICE_ATTR(current_compute_partition, S_IRUGO | S_IWUSR,
1298                    amdgpu_gfx_get_current_compute_partition,
1299                    amdgpu_gfx_set_compute_partition);
1300
1301 static DEVICE_ATTR(available_compute_partition, S_IRUGO,
1302                    amdgpu_gfx_get_available_compute_partition, NULL);
1303
1304 static DEVICE_ATTR(current_memory_partition, S_IRUGO,
1305                    amdgpu_gfx_get_current_memory_partition, NULL);
1306
1307 int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev)
1308 {
1309         int r;
1310
1311         r = device_create_file(adev->dev, &dev_attr_current_compute_partition);
1312         if (r)
1313                 return r;
1314
1315         r = device_create_file(adev->dev, &dev_attr_available_compute_partition);
1316         if (r)
1317                 return r;
1318
1319         r = device_create_file(adev->dev, &dev_attr_current_memory_partition);
1320         if (r)
1321                 return r;
1322
1323         return 0;
1324 }
1325
1326 void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev)
1327 {
1328         device_remove_file(adev->dev, &dev_attr_current_compute_partition);
1329         device_remove_file(adev->dev, &dev_attr_available_compute_partition);
1330         device_remove_file(adev->dev, &dev_attr_current_memory_partition);
1331 }