drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Authors:
   5  *      YT Shen <[email protected]>
   6  *      CK Hu <[email protected]>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/of_platform.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/soc/mediatek/mtk-cmdq.h>
  16 #include <drm/drm_print.h>
  17
  18 #include "mtk_drm_drv.h"
  19 #include "mtk_drm_plane.h"
  20 #include "mtk_drm_ddp_comp.h"
  21 #include "mtk_drm_crtc.h"
  22
  23 #define DISP_OD_EN                              0x0000
  24 #define DISP_OD_INTEN                           0x0008
  25 #define DISP_OD_INTSTA                          0x000c
  26 #define DISP_OD_CFG                             0x0020
  27 #define DISP_OD_SIZE                            0x0030
  28 #define DISP_DITHER_5                           0x0114
  29 #define DISP_DITHER_7                           0x011c
  30 #define DISP_DITHER_15                          0x013c
  31 #define DISP_DITHER_16                          0x0140
  32
  33 #define DISP_REG_UFO_START                      0x0000
  34
  35 #define DISP_AAL_EN                             0x0000
  36 #define DISP_AAL_SIZE                           0x0030
  37
  38 #define DISP_CCORR_EN                           0x0000
  39 #define CCORR_EN                                BIT(0)
  40 #define DISP_CCORR_CFG                          0x0020
  41 #define CCORR_RELAY_MODE                        BIT(0)
  42 #define CCORR_ENGINE_EN                         BIT(1)
  43 #define CCORR_GAMMA_OFF                         BIT(2)
  44 #define CCORR_WGAMUT_SRC_CLIP                   BIT(3)
  45 #define DISP_CCORR_SIZE                         0x0030
  46 #define DISP_CCORR_COEF_0                       0x0080
  47 #define DISP_CCORR_COEF_1                       0x0084
  48 #define DISP_CCORR_COEF_2                       0x0088
  49 #define DISP_CCORR_COEF_3                       0x008C
  50 #define DISP_CCORR_COEF_4                       0x0090
  51
  52 #define DISP_DITHER_EN                          0x0000
  53 #define DITHER_EN                               BIT(0)
  54 #define DISP_DITHER_CFG                         0x0020
  55 #define DITHER_RELAY_MODE                       BIT(0)
  56 #define DISP_DITHER_SIZE                        0x0030
  57
  58 #define DISP_GAMMA_EN                           0x0000
  59 #define DISP_GAMMA_CFG                          0x0020
  60 #define DISP_GAMMA_SIZE                         0x0030
  61 #define DISP_GAMMA_LUT                          0x0700
  62
  63 #define LUT_10BIT_MASK                          0x03ff
  64
  65 #define OD_RELAYMODE                            BIT(0)
  66
  67 #define UFO_BYPASS                              BIT(2)
  68
  69 #define AAL_EN                                  BIT(0)
  70
  71 #define GAMMA_EN                                BIT(0)
  72 #define GAMMA_LUT_EN                            BIT(1)
  73
  74 #define DISP_DITHERING                          BIT(2)
  75 #define DITHER_LSB_ERR_SHIFT_R(x)               (((x) & 0x7) << 28)
  76 #define DITHER_OVFLW_BIT_R(x)                   (((x) & 0x7) << 24)
  77 #define DITHER_ADD_LSHIFT_R(x)                  (((x) & 0x7) << 20)
  78 #define DITHER_ADD_RSHIFT_R(x)                  (((x) & 0x7) << 16)
  79 #define DITHER_NEW_BIT_MODE                     BIT(0)
  80 #define DITHER_LSB_ERR_SHIFT_B(x)               (((x) & 0x7) << 28)
  81 #define DITHER_OVFLW_BIT_B(x)                   (((x) & 0x7) << 24)
  82 #define DITHER_ADD_LSHIFT_B(x)                  (((x) & 0x7) << 20)
  83 #define DITHER_ADD_RSHIFT_B(x)                  (((x) & 0x7) << 16)
  84 #define DITHER_LSB_ERR_SHIFT_G(x)               (((x) & 0x7) << 12)
  85 #define DITHER_OVFLW_BIT_G(x)                   (((x) & 0x7) << 8)
  86 #define DITHER_ADD_LSHIFT_G(x)                  (((x) & 0x7) << 4)
  87 #define DITHER_ADD_RSHIFT_G(x)                  (((x) & 0x7) << 0)
  88
  89 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  90                    struct mtk_ddp_comp *comp, unsigned int offset)
  91 {
  92 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  93         if (cmdq_pkt)
  94                 cmdq_pkt_write(cmdq_pkt, comp->subsys,
  95                                comp->regs_pa + offset, value);
  96         else
  97 #endif
  98                 writel(value, comp->regs + offset);
  99 }
 100
 101 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
 102                            struct mtk_ddp_comp *comp,
 103                            unsigned int offset)
 104 {
 105 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 106         if (cmdq_pkt)
 107                 cmdq_pkt_write(cmdq_pkt, comp->subsys,
 108                                comp->regs_pa + offset, value);
 109         else
 110 #endif
 111                 writel_relaxed(value, comp->regs + offset);
 112 }
 113
 114 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt,
 115                         unsigned int value,
 116                         struct mtk_ddp_comp *comp,
 117                         unsigned int offset,
 118                         unsigned int mask)
 119 {
 120 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 121         if (cmdq_pkt) {
 122                 cmdq_pkt_write_mask(cmdq_pkt, comp->subsys,
 123                                     comp->regs_pa + offset, value, mask);
 124         } else {
 125 #endif
 126                 u32 tmp = readl(comp->regs + offset);
 127
 128                 tmp = (tmp & ~mask) | (value & mask);
 129                 writel(tmp, comp->regs + offset);
 130 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 131         }
 132 #endif
 133 }
 134
 135 void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
 136                     unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
 137 {
 138         /* If bpc equal to 0, the dithering function didn't be enabled */
 139         if (bpc == 0)
 140                 return;
 141
 142         if (bpc >= MTK_MIN_BPC) {
 143                 mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
 144                 mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
 145                 mtk_ddp_write(cmdq_pkt,
 146                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
 147                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
 148                               DITHER_NEW_BIT_MODE,
 149                               comp, DISP_DITHER_15);
 150                 mtk_ddp_write(cmdq_pkt,
 151                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
 152                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
 153                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
 154                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
 155                               comp, DISP_DITHER_16);
 156                 mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
 157         }
 158 }
 159
 160 static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
 161                           unsigned int h, unsigned int vrefresh,
 162                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 163 {
 164         mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
 165         mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
 166         mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
 167 }
 168
 169 static void mtk_od_start(struct mtk_ddp_comp *comp)
 170 {
 171         writel(1, comp->regs + DISP_OD_EN);
 172 }
 173
 174 static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
 175 {
 176         writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
 177 }
 178
 179 static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
 180                            unsigned int h, unsigned int vrefresh,
 181                            unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 182 {
 183         mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
 184 }
 185
 186 static void mtk_aal_start(struct mtk_ddp_comp *comp)
 187 {
 188         writel(AAL_EN, comp->regs + DISP_AAL_EN);
 189 }
 190
 191 static void mtk_aal_stop(struct mtk_ddp_comp *comp)
 192 {
 193         writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
 194 }
 195
 196 static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
 197                              unsigned int h, unsigned int vrefresh,
 198                              unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 199 {
 200         mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
 201         mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
 202 }
 203
 204 static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
 205 {
 206         writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
 207 }
 208
 209 static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
 210 {
 211         writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
 212 }
 213
 214 /* Converts a DRM S31.32 value to the HW S1.10 format. */
 215 static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
 216 {
 217         u16 r;
 218
 219         /* Sign bit. */
 220         r = in & BIT_ULL(63) ? BIT(11) : 0;
 221
 222         if ((in & GENMASK_ULL(62, 33)) > 0) {
 223                 /* identity value 0x100000000 -> 0x400, */
 224                 /* if bigger this, set it to max 0x7ff. */
 225                 r |= GENMASK(10, 0);
 226         } else {
 227                 /* take the 11 most important bits. */
 228                 r |= (in >> 22) & GENMASK(10, 0);
 229         }
 230
 231         return r;
 232 }
 233
 234 static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
 235                               struct drm_crtc_state *state)
 236 {
 237         struct drm_property_blob *blob = state->ctm;
 238         struct drm_color_ctm *ctm;
 239         const u64 *input;
 240         uint16_t coeffs[9] = { 0 };
 241         int i;
 242         struct cmdq_pkt *cmdq_pkt = NULL;
 243
 244         if (!blob)
 245                 return;
 246
 247         ctm = (struct drm_color_ctm *)blob->data;
 248         input = ctm->matrix;
 249
 250         for (i = 0; i < ARRAY_SIZE(coeffs); i++)
 251                 coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
 252
 253         mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
 254                       comp, DISP_CCORR_COEF_0);
 255         mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
 256                       comp, DISP_CCORR_COEF_1);
 257         mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
 258                       comp, DISP_CCORR_COEF_2);
 259         mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
 260                       comp, DISP_CCORR_COEF_3);
 261         mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
 262                       comp, DISP_CCORR_COEF_4);
 263 }
 264
 265 static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
 266                               unsigned int h, unsigned int vrefresh,
 267                               unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 268 {
 269         mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
 270         mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
 271 }
 272
 273 static void mtk_dither_start(struct mtk_ddp_comp *comp)
 274 {
 275         writel(DITHER_EN, comp->regs + DISP_DITHER_EN);
 276 }
 277
 278 static void mtk_dither_stop(struct mtk_ddp_comp *comp)
 279 {
 280         writel_relaxed(0x0, comp->regs + DISP_DITHER_EN);
 281 }
 282
 283 static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
 284                              unsigned int h, unsigned int vrefresh,
 285                              unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 286 {
 287         mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
 288         mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
 289 }
 290
 291 static void mtk_gamma_start(struct mtk_ddp_comp *comp)
 292 {
 293         writel(GAMMA_EN, comp->regs  + DISP_GAMMA_EN);
 294 }
 295
 296 static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
 297 {
 298         writel_relaxed(0x0, comp->regs  + DISP_GAMMA_EN);
 299 }
 300
 301 static void mtk_gamma_set(struct mtk_ddp_comp *comp,
 302                           struct drm_crtc_state *state)
 303 {
 304         unsigned int i, reg;
 305         struct drm_color_lut *lut;
 306         void __iomem *lut_base;
 307         u32 word;
 308
 309         if (state->gamma_lut) {
 310                 reg = readl(comp->regs + DISP_GAMMA_CFG);
 311                 reg = reg | GAMMA_LUT_EN;
 312                 writel(reg, comp->regs + DISP_GAMMA_CFG);
 313                 lut_base = comp->regs + DISP_GAMMA_LUT;
 314                 lut = (struct drm_color_lut *)state->gamma_lut->data;
 315                 for (i = 0; i < MTK_LUT_SIZE; i++) {
 316                         word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
 317                                 (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
 318                                 ((lut[i].blue >> 6) & LUT_10BIT_MASK);
 319                         writel(word, (lut_base + i * 4));
 320                 }
 321         }
 322 }
 323
 324 static const struct mtk_ddp_comp_funcs ddp_aal = {
 325         .gamma_set = mtk_gamma_set,
 326         .config = mtk_aal_config,
 327         .start = mtk_aal_start,
 328         .stop = mtk_aal_stop,
 329 };
 330
 331 static const struct mtk_ddp_comp_funcs ddp_ccorr = {
 332         .config = mtk_ccorr_config,
 333         .start = mtk_ccorr_start,
 334         .stop = mtk_ccorr_stop,
 335         .ctm_set = mtk_ccorr_ctm_set,
 336 };
 337
 338 static const struct mtk_ddp_comp_funcs ddp_dither = {
 339         .config = mtk_dither_config,
 340         .start = mtk_dither_start,
 341         .stop = mtk_dither_stop,
 342 };
 343
 344 static const struct mtk_ddp_comp_funcs ddp_gamma = {
 345         .gamma_set = mtk_gamma_set,
 346         .config = mtk_gamma_config,
 347         .start = mtk_gamma_start,
 348         .stop = mtk_gamma_stop,
 349 };
 350
 351 static const struct mtk_ddp_comp_funcs ddp_od = {
 352         .config = mtk_od_config,
 353         .start = mtk_od_start,
 354 };
 355
 356 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 357         .start = mtk_ufoe_start,
 358 };
 359
 360 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 361         [MTK_DISP_OVL] = "ovl",
 362         [MTK_DISP_OVL_2L] = "ovl_2l",
 363         [MTK_DISP_RDMA] = "rdma",
 364         [MTK_DISP_WDMA] = "wdma",
 365         [MTK_DISP_COLOR] = "color",
 366         [MTK_DISP_CCORR] = "ccorr",
 367         [MTK_DISP_AAL] = "aal",
 368         [MTK_DISP_GAMMA] = "gamma",
 369         [MTK_DISP_DITHER] = "dither",
 370         [MTK_DISP_UFOE] = "ufoe",
 371         [MTK_DSI] = "dsi",
 372         [MTK_DPI] = "dpi",
 373         [MTK_DISP_PWM] = "pwm",
 374         [MTK_DISP_MUTEX] = "mutex",
 375         [MTK_DISP_OD] = "od",
 376         [MTK_DISP_BLS] = "bls",
 377 };
 378
 379 struct mtk_ddp_comp_match {
 380         enum mtk_ddp_comp_type type;
 381         int alias_id;
 382         const struct mtk_ddp_comp_funcs *funcs;
 383 };
 384
 385 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 386         [DDP_COMPONENT_AAL0]    = { MTK_DISP_AAL,       0, &ddp_aal },
 387         [DDP_COMPONENT_AAL1]    = { MTK_DISP_AAL,       1, &ddp_aal },
 388         [DDP_COMPONENT_BLS]     = { MTK_DISP_BLS,       0, NULL },
 389         [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR,     0, &ddp_ccorr },
 390         [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR,     0, NULL },
 391         [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR,     1, NULL },
 392         [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,    0, &ddp_dither },
 393         [DDP_COMPONENT_DPI0]    = { MTK_DPI,            0, NULL },
 394         [DDP_COMPONENT_DPI1]    = { MTK_DPI,            1, NULL },
 395         [DDP_COMPONENT_DSI0]    = { MTK_DSI,            0, NULL },
 396         [DDP_COMPONENT_DSI1]    = { MTK_DSI,            1, NULL },
 397         [DDP_COMPONENT_DSI2]    = { MTK_DSI,            2, NULL },
 398         [DDP_COMPONENT_DSI3]    = { MTK_DSI,            3, NULL },
 399         [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA,     0, &ddp_gamma },
 400         [DDP_COMPONENT_OD0]     = { MTK_DISP_OD,        0, &ddp_od },
 401         [DDP_COMPONENT_OD1]     = { MTK_DISP_OD,        1, &ddp_od },
 402         [DDP_COMPONENT_OVL0]    = { MTK_DISP_OVL,       0, NULL },
 403         [DDP_COMPONENT_OVL1]    = { MTK_DISP_OVL,       1, NULL },
 404         [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,    0, NULL },
 405         [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,    1, NULL },
 406         [DDP_COMPONENT_PWM0]    = { MTK_DISP_PWM,       0, NULL },
 407         [DDP_COMPONENT_PWM1]    = { MTK_DISP_PWM,       1, NULL },
 408         [DDP_COMPONENT_PWM2]    = { MTK_DISP_PWM,       2, NULL },
 409         [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,      0, NULL },
 410         [DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,      1, NULL },
 411         [DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,      2, NULL },
 412         [DDP_COMPONENT_UFOE]    = { MTK_DISP_UFOE,      0, &ddp_ufoe },
 413         [DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,      0, NULL },
 414         [DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,      1, NULL },
 415 };
 416
 417 static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp,
 418                                      const enum mtk_ddp_comp_id *path,
 419                                      unsigned int path_len)
 420 {
 421         unsigned int i;
 422
 423         if (path == NULL)
 424                 return false;
 425
 426         for (i = 0U; i < path_len; i++)
 427                 if (ddp_comp.id == path[i])
 428                         return true;
 429
 430         return false;
 431 }
 432
 433 int mtk_ddp_comp_get_id(struct device_node *node,
 434                         enum mtk_ddp_comp_type comp_type)
 435 {
 436         int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
 437         int i;
 438
 439         for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
 440                 if (comp_type == mtk_ddp_matches[i].type &&
 441                     (id < 0 || id == mtk_ddp_matches[i].alias_id))
 442                         return i;
 443         }
 444
 445         return -EINVAL;
 446 }
 447
 448 unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
 449                                                 struct mtk_ddp_comp ddp_comp)
 450 {
 451         struct mtk_drm_private *private = drm->dev_private;
 452         unsigned int ret = 0;
 453
 454         if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, private->data->main_len))
 455                 ret = BIT(0);
 456         else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->ext_path,
 457                                           private->data->ext_len))
 458                 ret = BIT(1);
 459         else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->third_path,
 460                                           private->data->third_len))
 461                 ret = BIT(2);
 462         else
 463                 DRM_INFO("Failed to find comp in ddp table\n");
 464
 465         return ret;
 466 }
 467
 468 int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
 469                       struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
 470                       const struct mtk_ddp_comp_funcs *funcs)
 471 {
 472         enum mtk_ddp_comp_type type;
 473         struct device_node *larb_node;
 474         struct platform_device *larb_pdev;
 475 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 476         struct resource res;
 477         struct cmdq_client_reg cmdq_reg;
 478         int ret;
 479 #endif
 480
 481         if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
 482                 return -EINVAL;
 483
 484         type = mtk_ddp_matches[comp_id].type;
 485
 486         comp->id = comp_id;
 487         comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
 488
 489         if (comp_id == DDP_COMPONENT_BLS ||
 490             comp_id == DDP_COMPONENT_DPI0 ||
 491             comp_id == DDP_COMPONENT_DPI1 ||
 492             comp_id == DDP_COMPONENT_DSI0 ||
 493             comp_id == DDP_COMPONENT_DSI1 ||
 494             comp_id == DDP_COMPONENT_DSI2 ||
 495             comp_id == DDP_COMPONENT_DSI3 ||
 496             comp_id == DDP_COMPONENT_PWM0) {
 497                 comp->regs = NULL;
 498                 comp->clk = NULL;
 499                 comp->irq = 0;
 500                 return 0;
 501         }
 502
 503         comp->regs = of_iomap(node, 0);
 504         comp->irq = of_irq_get(node, 0);
 505         comp->clk = of_clk_get(node, 0);
 506         if (IS_ERR(comp->clk))
 507                 return PTR_ERR(comp->clk);
 508
 509         /* Only DMA capable components need the LARB property */
 510         comp->larb_dev = NULL;
 511         if (type != MTK_DISP_OVL &&
 512             type != MTK_DISP_OVL_2L &&
 513             type != MTK_DISP_RDMA &&
 514             type != MTK_DISP_WDMA)
 515                 return 0;
 516
 517         larb_node = of_parse_phandle(node, "mediatek,larb", 0);
 518         if (!larb_node) {
 519                 dev_err(dev,
 520                         "Missing mediadek,larb phandle in %pOF node\n", node);
 521                 return -EINVAL;
 522         }
 523
 524         larb_pdev = of_find_device_by_node(larb_node);
 525         if (!larb_pdev) {
 526                 dev_warn(dev, "Waiting for larb device %pOF\n", larb_node);
 527                 of_node_put(larb_node);
 528                 return -EPROBE_DEFER;
 529         }
 530         of_node_put(larb_node);
 531
 532         comp->larb_dev = &larb_pdev->dev;
 533
 534 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 535         if (of_address_to_resource(node, 0, &res) != 0) {
 536                 dev_err(dev, "Missing reg in %s node\n", node->full_name);
 537                 put_device(&larb_pdev->dev);
 538                 return -EINVAL;
 539         }
 540         comp->regs_pa = res.start;
 541
 542         ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0);
 543         if (ret)
 544                 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
 545         else
 546                 comp->subsys = cmdq_reg.subsys;
 547 #endif
 548         return 0;
 549 }
 550
 551 int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
 552 {
 553         struct mtk_drm_private *private = drm->dev_private;
 554
 555         if (private->ddp_comp[comp->id])
 556                 return -EBUSY;
 557
 558         private->ddp_comp[comp->id] = comp;
 559         return 0;
 560 }
 561
 562 void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
 563 {
 564         struct mtk_drm_private *private = drm->dev_private;
 565
 566         private->ddp_comp[comp->id] = NULL;
 567 }