2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <asm/paccess.h>
11 #include <asm/pci/bridge.h>
12 #include <asm/sn/arch.h>
13 #include <asm/sn/intr.h>
14 #include <asm/sn/sn0/hub.h>
17 * Most of the IOC3 PCI config register aren't present
18 * we emulate what is needed for a normal PCI enumeration
20 static u32 emulate_ioc3_cfg(int where, int size)
22 if (size == 1 && where == 0x3d)
24 else if (size == 2 && where == 0x3c)
26 else if (size == 4 && where == 0x3c)
33 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
34 * not really documented, so right now I can't write code which uses it.
35 * Therefore we use type 0 accesses for now even though they won't work
36 * correctly for PCI-to-PCI bridges.
38 * The function is complicated by the ultimate brokenness of the IOC3 chip
39 * which is used in SGI systems. The IOC3 can only handle 32-bit PCI
40 * accesses and does only decode parts of it's address space.
43 static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
44 int where, int size, u32 * value)
46 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
47 struct bridge_regs *bridge = bc->base;
48 int slot = PCI_SLOT(devfn);
49 int fn = PCI_FUNC(devfn);
54 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
55 if (get_dbe(cf, (u32 *) addr))
56 return PCIBIOS_DEVICE_NOT_FOUND;
59 * IOC3 is broken beyond belief ... Don't even give the
60 * generic PCI code a chance to look at it for real ...
62 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
65 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
68 res = get_dbe(*value, (u8 *) addr);
70 res = get_dbe(*value, (u16 *) addr);
72 res = get_dbe(*value, (u32 *) addr);
74 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
79 * IOC3 special handling
81 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
82 *value = emulate_ioc3_cfg(where, size);
83 return PCIBIOS_SUCCESSFUL;
86 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
88 if (get_dbe(cf, (u32 *) addr))
89 return PCIBIOS_DEVICE_NOT_FOUND;
91 shift = ((where & 3) << 3);
92 mask = (0xffffffffU >> ((4 - size) << 3));
93 *value = (cf >> shift) & mask;
95 return PCIBIOS_SUCCESSFUL;
98 static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
99 int where, int size, u32 * value)
101 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
102 struct bridge_regs *bridge = bc->base;
103 int busno = bus->number;
104 int slot = PCI_SLOT(devfn);
105 int fn = PCI_FUNC(devfn);
110 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
111 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
112 if (get_dbe(cf, (u32 *) addr))
113 return PCIBIOS_DEVICE_NOT_FOUND;
116 * IOC3 is broken beyond belief ... Don't even give the
117 * generic PCI code a chance to look at it for real ...
119 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
122 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
123 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
126 res = get_dbe(*value, (u8 *) addr);
128 res = get_dbe(*value, (u16 *) addr);
130 res = get_dbe(*value, (u32 *) addr);
132 return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
137 * IOC3 special handling
139 if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {
140 *value = emulate_ioc3_cfg(where, size);
141 return PCIBIOS_SUCCESSFUL;
144 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
145 addr = &bridge->b_type1_cfg.c[(fn << 8) | where];
147 if (get_dbe(cf, (u32 *) addr))
148 return PCIBIOS_DEVICE_NOT_FOUND;
150 shift = ((where & 3) << 3);
151 mask = (0xffffffffU >> ((4 - size) << 3));
152 *value = (cf >> shift) & mask;
154 return PCIBIOS_SUCCESSFUL;
157 static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
158 int where, int size, u32 * value)
160 if (!pci_is_root_bus(bus))
161 return pci_conf1_read_config(bus, devfn, where, size, value);
163 return pci_conf0_read_config(bus, devfn, where, size, value);
166 static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
167 int where, int size, u32 value)
169 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
170 struct bridge_regs *bridge = bc->base;
171 int slot = PCI_SLOT(devfn);
172 int fn = PCI_FUNC(devfn);
174 u32 cf, shift, mask, smask;
177 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
178 if (get_dbe(cf, (u32 *) addr))
179 return PCIBIOS_DEVICE_NOT_FOUND;
182 * IOC3 is broken beyond belief ... Don't even give the
183 * generic PCI code a chance to look at it for real ...
185 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
188 addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
191 res = put_dbe(value, (u8 *) addr);
192 } else if (size == 2) {
193 res = put_dbe(value, (u16 *) addr);
195 res = put_dbe(value, (u32 *) addr);
199 return PCIBIOS_DEVICE_NOT_FOUND;
201 return PCIBIOS_SUCCESSFUL;
206 * IOC3 special handling
208 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
209 return PCIBIOS_SUCCESSFUL;
211 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
213 if (get_dbe(cf, (u32 *) addr))
214 return PCIBIOS_DEVICE_NOT_FOUND;
216 shift = ((where & 3) << 3);
217 mask = (0xffffffffU >> ((4 - size) << 3));
218 smask = mask << shift;
220 cf = (cf & ~smask) | ((value & mask) << shift);
221 if (put_dbe(cf, (u32 *) addr))
222 return PCIBIOS_DEVICE_NOT_FOUND;
224 return PCIBIOS_SUCCESSFUL;
227 static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
228 int where, int size, u32 value)
230 struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
231 struct bridge_regs *bridge = bc->base;
232 int slot = PCI_SLOT(devfn);
233 int fn = PCI_FUNC(devfn);
234 int busno = bus->number;
236 u32 cf, shift, mask, smask;
239 bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
240 addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
241 if (get_dbe(cf, (u32 *) addr))
242 return PCIBIOS_DEVICE_NOT_FOUND;
245 * IOC3 is broken beyond belief ... Don't even give the
246 * generic PCI code a chance to look at it for real ...
248 if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16)))
251 addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
254 res = put_dbe(value, (u8 *) addr);
255 } else if (size == 2) {
256 res = put_dbe(value, (u16 *) addr);
258 res = put_dbe(value, (u32 *) addr);
262 return PCIBIOS_DEVICE_NOT_FOUND;
264 return PCIBIOS_SUCCESSFUL;
269 * IOC3 special handling
271 if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
272 return PCIBIOS_SUCCESSFUL;
274 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
276 if (get_dbe(cf, (u32 *) addr))
277 return PCIBIOS_DEVICE_NOT_FOUND;
279 shift = ((where & 3) << 3);
280 mask = (0xffffffffU >> ((4 - size) << 3));
281 smask = mask << shift;
283 cf = (cf & ~smask) | ((value & mask) << shift);
284 if (put_dbe(cf, (u32 *) addr))
285 return PCIBIOS_DEVICE_NOT_FOUND;
287 return PCIBIOS_SUCCESSFUL;
290 static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
291 int where, int size, u32 value)
293 if (!pci_is_root_bus(bus))
294 return pci_conf1_write_config(bus, devfn, where, size, value);
296 return pci_conf0_write_config(bus, devfn, where, size, value);
299 struct pci_ops bridge_pci_ops = {
300 .read = pci_read_config,
301 .write = pci_write_config,