drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "si/sid.h"
  30 #include "r600_dpm.h"
  31 #include "si_dpm.h"
  32 #include "atom.h"
  33 #include "../include/pptable.h"
  34 #include <linux/math64.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/firmware.h>
  37
  38 #define MC_CG_ARB_FREQ_F0           0x0a
  39 #define MC_CG_ARB_FREQ_F1           0x0b
  40 #define MC_CG_ARB_FREQ_F2           0x0c
  41 #define MC_CG_ARB_FREQ_F3           0x0d
  42
  43 #define SMC_RAM_END                 0x20000
  44
  45 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  46
  47
  48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  55
  56 #define BIOS_SCRATCH_4                                    0x5cd
  57
  58 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
  59 MODULE_FIRMWARE("radeon/tahiti_k_smc.bin");
  60 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
  61 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
  62 MODULE_FIRMWARE("radeon/verde_smc.bin");
  63 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
  64 MODULE_FIRMWARE("radeon/oland_smc.bin");
  65 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
  66 MODULE_FIRMWARE("radeon/hainan_smc.bin");
  67 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
  68
  69 union power_info {
  70         struct _ATOM_POWERPLAY_INFO info;
  71         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  72         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  73         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  74         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  75         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  76         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  77         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  78 };
  79
  80 union fan_info {
  81         struct _ATOM_PPLIB_FANTABLE fan;
  82         struct _ATOM_PPLIB_FANTABLE2 fan2;
  83         struct _ATOM_PPLIB_FANTABLE3 fan3;
  84 };
  85
  86 union pplib_clock_info {
  87         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  88         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  89         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  90         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  91         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  92 };
  93
  94 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  95 {
  96         R600_UTC_DFLT_00,
  97         R600_UTC_DFLT_01,
  98         R600_UTC_DFLT_02,
  99         R600_UTC_DFLT_03,
 100         R600_UTC_DFLT_04,
 101         R600_UTC_DFLT_05,
 102         R600_UTC_DFLT_06,
 103         R600_UTC_DFLT_07,
 104         R600_UTC_DFLT_08,
 105         R600_UTC_DFLT_09,
 106         R600_UTC_DFLT_10,
 107         R600_UTC_DFLT_11,
 108         R600_UTC_DFLT_12,
 109         R600_UTC_DFLT_13,
 110         R600_UTC_DFLT_14,
 111 };
 112
 113 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 114 {
 115         R600_DTC_DFLT_00,
 116         R600_DTC_DFLT_01,
 117         R600_DTC_DFLT_02,
 118         R600_DTC_DFLT_03,
 119         R600_DTC_DFLT_04,
 120         R600_DTC_DFLT_05,
 121         R600_DTC_DFLT_06,
 122         R600_DTC_DFLT_07,
 123         R600_DTC_DFLT_08,
 124         R600_DTC_DFLT_09,
 125         R600_DTC_DFLT_10,
 126         R600_DTC_DFLT_11,
 127         R600_DTC_DFLT_12,
 128         R600_DTC_DFLT_13,
 129         R600_DTC_DFLT_14,
 130 };
 131
 132 static const struct si_cac_config_reg cac_weights_tahiti[] =
 133 {
 134         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 135         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 136         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 137         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 138         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 139         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 140         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 143         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 144         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 145         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 146         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 147         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 149         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 152         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 153         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 154         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 155         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 156         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 157         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 165         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 166         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 169         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 172         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 174         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 188         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 189         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 190         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 191         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 192         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 193         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 194         { 0xFFFFFFFF }
 195 };
 196
 197 static const struct si_cac_config_reg lcac_tahiti[] =
 198 {
 199         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 200         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 201         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 202         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 203         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 204         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 205         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 206         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 207         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 208         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 209         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 210         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 211         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 212         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 213         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 214         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 215         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 216         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 217         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 218         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 219         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 220         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 221         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 222         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 223         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 224         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 225         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 226         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 227         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 228         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 229         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 230         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 231         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 232         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 233         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 234         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 235         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 236         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 237         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 238         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 239         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 240         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 241         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 242         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 243         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 244         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 245         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 246         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 247         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 248         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 249         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 250         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 251         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 252         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 253         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 254         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 255         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 256         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 257         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 258         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 259         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 260         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 261         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 262         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 263         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 264         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 265         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 266         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 267         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 268         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 269         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 270         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 271         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 272         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 273         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 274         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 275         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 276         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 277         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 278         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 279         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 280         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 281         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 282         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 283         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 284         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 285         { 0xFFFFFFFF }
 286
 287 };
 288
 289 static const struct si_cac_config_reg cac_override_tahiti[] =
 290 {
 291         { 0xFFFFFFFF }
 292 };
 293
 294 static const struct si_powertune_data powertune_data_tahiti =
 295 {
 296         ((1 << 16) | 27027),
 297         6,
 298         0,
 299         4,
 300         95,
 301         {
 302                 0UL,
 303                 0UL,
 304                 4521550UL,
 305                 309631529UL,
 306                 -1270850L,
 307                 4513710L,
 308                 40
 309         },
 310         595000000UL,
 311         12,
 312         {
 313                 0,
 314                 0,
 315                 0,
 316                 0,
 317                 0,
 318                 0,
 319                 0,
 320                 0
 321         },
 322         true
 323 };
 324
 325 static const struct si_dte_data dte_data_tahiti =
 326 {
 327         { 1159409, 0, 0, 0, 0 },
 328         { 777, 0, 0, 0, 0 },
 329         2,
 330         54000,
 331         127000,
 332         25,
 333         2,
 334         10,
 335         13,
 336         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 337         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 338         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 339         85,
 340         false
 341 };
 342
 343 #if 0
 344 static const struct si_dte_data dte_data_tahiti_le =
 345 {
 346         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 347         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 348         0x5,
 349         0xAFC8,
 350         0x64,
 351         0x32,
 352         1,
 353         0,
 354         0x10,
 355         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 356         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 357         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 358         85,
 359         true
 360 };
 361 #endif
 362
 363 static const struct si_dte_data dte_data_tahiti_pro =
 364 {
 365         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 366         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 367         5,
 368         45000,
 369         100,
 370         0xA,
 371         1,
 372         0,
 373         0x10,
 374         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 375         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 376         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 377         90,
 378         true
 379 };
 380
 381 static const struct si_dte_data dte_data_new_zealand =
 382 {
 383         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 384         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 385         0x5,
 386         0xAFC8,
 387         0x69,
 388         0x32,
 389         1,
 390         0,
 391         0x10,
 392         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 393         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 394         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 395         85,
 396         true
 397 };
 398
 399 static const struct si_dte_data dte_data_aruba_pro =
 400 {
 401         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 402         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 403         5,
 404         45000,
 405         100,
 406         0xA,
 407         1,
 408         0,
 409         0x10,
 410         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 411         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 412         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 413         90,
 414         true
 415 };
 416
 417 static const struct si_dte_data dte_data_malta =
 418 {
 419         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 420         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 421         5,
 422         45000,
 423         100,
 424         0xA,
 425         1,
 426         0,
 427         0x10,
 428         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 429         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 430         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 431         90,
 432         true
 433 };
 434
 435 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 436 {
 437         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 438         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 439         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 440         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 441         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 442         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 443         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 444         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 445         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 446         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 447         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 448         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 449         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 450         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 451         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 452         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 454         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 455         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 456         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 457         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 458         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 459         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 460         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 461         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 462         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 463         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 464         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 465         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 467         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 468         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 470         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 472         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 473         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 474         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 489         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 490         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 491         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 492         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 493         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 494         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 495         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 496         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg lcac_pitcairn[] =
 501 {
 502         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 503         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 504         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 505         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 506         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 507         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 508         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 509         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 510         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 511         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 512         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 513         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 514         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 515         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 516         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 517         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 518         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 519         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 520         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 521         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 522         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 523         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 524         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 525         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 526         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 527         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 528         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 529         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 530         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 531         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 532         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 533         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 534         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 535         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 536         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 537         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 538         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 539         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 540         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 541         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 542         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 543         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 544         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 545         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 546         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 547         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 548         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 549         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 550         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 551         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 552         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 553         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 554         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 555         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 556         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 557         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 558         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 559         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 560         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 561         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 562         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 563         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 564         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 565         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 566         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 567         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 568         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 569         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 570         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 571         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 572         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 573         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 574         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 575         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 576         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 577         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 578         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 579         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 580         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 581         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 582         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 583         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 584         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 585         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 586         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 587         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 588         { 0xFFFFFFFF }
 589 };
 590
 591 static const struct si_cac_config_reg cac_override_pitcairn[] =
 592 {
 593     { 0xFFFFFFFF }
 594 };
 595
 596 static const struct si_powertune_data powertune_data_pitcairn =
 597 {
 598         ((1 << 16) | 27027),
 599         5,
 600         0,
 601         6,
 602         100,
 603         {
 604                 51600000UL,
 605                 1800000UL,
 606                 7194395UL,
 607                 309631529UL,
 608                 -1270850L,
 609                 4513710L,
 610                 100
 611         },
 612         117830498UL,
 613         12,
 614         {
 615                 0,
 616                 0,
 617                 0,
 618                 0,
 619                 0,
 620                 0,
 621                 0,
 622                 0
 623         },
 624         true
 625 };
 626
 627 static const struct si_dte_data dte_data_pitcairn =
 628 {
 629         { 0, 0, 0, 0, 0 },
 630         { 0, 0, 0, 0, 0 },
 631         0,
 632         0,
 633         0,
 634         0,
 635         0,
 636         0,
 637         0,
 638         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 639         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 640         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 641         0,
 642         false
 643 };
 644
 645 static const struct si_dte_data dte_data_curacao_xt =
 646 {
 647         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 648         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 649         5,
 650         45000,
 651         100,
 652         0xA,
 653         1,
 654         0,
 655         0x10,
 656         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 657         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 658         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 659         90,
 660         true
 661 };
 662
 663 static const struct si_dte_data dte_data_curacao_pro =
 664 {
 665         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 666         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 667         5,
 668         45000,
 669         100,
 670         0xA,
 671         1,
 672         0,
 673         0x10,
 674         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 675         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 676         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 677         90,
 678         true
 679 };
 680
 681 static const struct si_dte_data dte_data_neptune_xt =
 682 {
 683         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 684         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 685         5,
 686         45000,
 687         100,
 688         0xA,
 689         1,
 690         0,
 691         0x10,
 692         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 693         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 694         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 695         90,
 696         true
 697 };
 698
 699 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 700 {
 701         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 702         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 703         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 704         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 705         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 706         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 707         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 708         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 709         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 710         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 711         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 712         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 713         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 714         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 716         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 717         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 718         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 719         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 720         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 721         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 722         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 723         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 724         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 725         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 726         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 727         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 728         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 730         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 731         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 732         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 733         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 734         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 735         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 736         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 737         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 739         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 741         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 742         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 753         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 754         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 755         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 756         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 757         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 758         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 759         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 760         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 761         { 0xFFFFFFFF }
 762 };
 763
 764 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 765 {
 766         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 767         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 768         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 769         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 770         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 771         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 772         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 773         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 774         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 775         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 776         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 777         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 778         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 779         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 781         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 782         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 783         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 784         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 785         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 786         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 787         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 788         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 789         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 790         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 791         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 792         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 793         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 795         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 796         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 797         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 798         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 799         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 800         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 801         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 802         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 804         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 806         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 807         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 818         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 819         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 820         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 821         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 822         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 823         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 824         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 825         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 826         { 0xFFFFFFFF }
 827 };
 828
 829 static const struct si_cac_config_reg cac_weights_heathrow[] =
 830 {
 831         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 832         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 833         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 834         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 835         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 836         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 837         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 838         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 839         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 840         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 841         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 842         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 843         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 844         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 846         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 847         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 848         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 849         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 850         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 851         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 852         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 853         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 854         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 855         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 856         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 857         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 858         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 860         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 861         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 862         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 863         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 864         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 865         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 866         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 867         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 869         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 871         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 872         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 883         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 884         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 885         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 886         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 887         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 888         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 889         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 890         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 891         { 0xFFFFFFFF }
 892 };
 893
 894 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 895 {
 896         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 897         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 898         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 899         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 900         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 901         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 902         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 903         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 904         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 905         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 906         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 907         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 908         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 909         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 911         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 912         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 913         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 914         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 915         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 916         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 917         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 918         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 919         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 920         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 921         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 922         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 923         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 925         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 926         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 927         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 928         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 929         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 930         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 931         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 932         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 934         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 936         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 937         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 948         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 949         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 950         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 951         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 952         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 953         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 954         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 955         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 956         { 0xFFFFFFFF }
 957 };
 958
 959 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 960 {
 961         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 962         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 963         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 964         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 965         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 966         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 967         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 968         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 969         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 970         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 971         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 972         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 973         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 974         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 975         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 976         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 977         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 978         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 979         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 980         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 981         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 982         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 983         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 984         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 985         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 986         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 987         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 988         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 989         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 991         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 992         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 993         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 994         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 995         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 996         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 997         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 999         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021         { 0xFFFFFFFF }
1022 };
1023
1024 static const struct si_cac_config_reg lcac_cape_verde[] =
1025 {
1026         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080         { 0xFFFFFFFF }
1081 };
1082
1083 static const struct si_cac_config_reg cac_override_cape_verde[] =
1084 {
1085     { 0xFFFFFFFF }
1086 };
1087
1088 static const struct si_powertune_data powertune_data_cape_verde =
1089 {
1090         ((1 << 16) | 0x6993),
1091         5,
1092         0,
1093         7,
1094         105,
1095         {
1096                 0UL,
1097                 0UL,
1098                 7194395UL,
1099                 309631529UL,
1100                 -1270850L,
1101                 4513710L,
1102                 100
1103         },
1104         117830498UL,
1105         12,
1106         {
1107                 0,
1108                 0,
1109                 0,
1110                 0,
1111                 0,
1112                 0,
1113                 0,
1114                 0
1115         },
1116         true
1117 };
1118
1119 static const struct si_dte_data dte_data_cape_verde =
1120 {
1121         { 0, 0, 0, 0, 0 },
1122         { 0, 0, 0, 0, 0 },
1123         0,
1124         0,
1125         0,
1126         0,
1127         0,
1128         0,
1129         0,
1130         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133         0,
1134         false
1135 };
1136
1137 static const struct si_dte_data dte_data_venus_xtx =
1138 {
1139         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141         5,
1142         55000,
1143         0x69,
1144         0xA,
1145         1,
1146         0,
1147         0x3,
1148         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151         90,
1152         true
1153 };
1154
1155 static const struct si_dte_data dte_data_venus_xt =
1156 {
1157         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159         5,
1160         55000,
1161         0x69,
1162         0xA,
1163         1,
1164         0,
1165         0x3,
1166         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169         90,
1170         true
1171 };
1172
1173 static const struct si_dte_data dte_data_venus_pro =
1174 {
1175         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177         5,
1178         55000,
1179         0x69,
1180         0xA,
1181         1,
1182         0,
1183         0x3,
1184         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187         90,
1188         true
1189 };
1190
1191 static const struct si_cac_config_reg cac_weights_oland[] =
1192 {
1193         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253         { 0xFFFFFFFF }
1254 };
1255
1256 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257 {
1258         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318         { 0xFFFFFFFF }
1319 };
1320
1321 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322 {
1323         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383         { 0xFFFFFFFF }
1384 };
1385
1386 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387 {
1388         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448         { 0xFFFFFFFF }
1449 };
1450
1451 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452 {
1453         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513         { 0xFFFFFFFF }
1514 };
1515
1516 static const struct si_cac_config_reg lcac_oland[] =
1517 {
1518         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560         { 0xFFFFFFFF }
1561 };
1562
1563 static const struct si_cac_config_reg lcac_mars_pro[] =
1564 {
1565         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607         { 0xFFFFFFFF }
1608 };
1609
1610 static const struct si_cac_config_reg cac_override_oland[] =
1611 {
1612         { 0xFFFFFFFF }
1613 };
1614
1615 static const struct si_powertune_data powertune_data_oland =
1616 {
1617         ((1 << 16) | 0x6993),
1618         5,
1619         0,
1620         7,
1621         105,
1622         {
1623                 0UL,
1624                 0UL,
1625                 7194395UL,
1626                 309631529UL,
1627                 -1270850L,
1628                 4513710L,
1629                 100
1630         },
1631         117830498UL,
1632         12,
1633         {
1634                 0,
1635                 0,
1636                 0,
1637                 0,
1638                 0,
1639                 0,
1640                 0,
1641                 0
1642         },
1643         true
1644 };
1645
1646 static const struct si_powertune_data powertune_data_mars_pro =
1647 {
1648         ((1 << 16) | 0x6993),
1649         5,
1650         0,
1651         7,
1652         105,
1653         {
1654                 0UL,
1655                 0UL,
1656                 7194395UL,
1657                 309631529UL,
1658                 -1270850L,
1659                 4513710L,
1660                 100
1661         },
1662         117830498UL,
1663         12,
1664         {
1665                 0,
1666                 0,
1667                 0,
1668                 0,
1669                 0,
1670                 0,
1671                 0,
1672                 0
1673         },
1674         true
1675 };
1676
1677 static const struct si_dte_data dte_data_oland =
1678 {
1679         { 0, 0, 0, 0, 0 },
1680         { 0, 0, 0, 0, 0 },
1681         0,
1682         0,
1683         0,
1684         0,
1685         0,
1686         0,
1687         0,
1688         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691         0,
1692         false
1693 };
1694
1695 static const struct si_dte_data dte_data_mars_pro =
1696 {
1697         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699         5,
1700         55000,
1701         105,
1702         0xA,
1703         1,
1704         0,
1705         0x10,
1706         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709         90,
1710         true
1711 };
1712
1713 static const struct si_dte_data dte_data_sun_xt =
1714 {
1715         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717         5,
1718         55000,
1719         105,
1720         0xA,
1721         1,
1722         0,
1723         0x10,
1724         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727         90,
1728         true
1729 };
1730
1731
1732 static const struct si_cac_config_reg cac_weights_hainan[] =
1733 {
1734         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794         { 0xFFFFFFFF }
1795 };
1796
1797 static const struct si_powertune_data powertune_data_hainan =
1798 {
1799         ((1 << 16) | 0x6993),
1800         5,
1801         0,
1802         9,
1803         105,
1804         {
1805                 0UL,
1806                 0UL,
1807                 7194395UL,
1808                 309631529UL,
1809                 -1270850L,
1810                 4513710L,
1811                 100
1812         },
1813         117830498UL,
1814         12,
1815         {
1816                 0,
1817                 0,
1818                 0,
1819                 0,
1820                 0,
1821                 0,
1822                 0,
1823                 0
1824         },
1825         true
1826 };
1827
1828 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833 static int si_populate_voltage_value(struct amdgpu_device *adev,
1834                                      const struct atom_voltage_table *table,
1835                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838                                     u16 *std_voltage);
1839 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840                                       u16 reg_offset, u32 value);
1841 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842                                          struct rv7xx_pl *pl,
1843                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845                                     u32 engine_clock,
1846                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854 {
1855         struct si_power_info *pi = adev->pm.dpm.priv;
1856         return pi;
1857 }
1858
1859 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1861 {
1862         s64 kt, kv, leakage_w, i_leakage, vddc;
1863         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864         s64 tmp;
1865
1866         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867         vddc = div64_s64(drm_int2fixp(v), 1000);
1868         temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874         t_ref = drm_int2fixp(coeff->t_ref);
1875
1876         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883         *leakage = drm_fixp2int(leakage_w * 1000);
1884 }
1885
1886 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887                                              const struct ni_leakage_coeffients *coeff,
1888                                              u16 v,
1889                                              s32 t,
1890                                              u32 i_leakage,
1891                                              u32 *leakage)
1892 {
1893         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894 }
1895
1896 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897                                                const u32 fixed_kt, u16 v,
1898                                                u32 ileakage, u32 *leakage)
1899 {
1900         s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903         vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911         *leakage = drm_fixp2int(leakage_w * 1000);
1912 }
1913
1914 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915                                        const struct ni_leakage_coeffients *coeff,
1916                                        const u32 fixed_kt,
1917                                        u16 v,
1918                                        u32 i_leakage,
1919                                        u32 *leakage)
1920 {
1921         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922 }
1923
1924
1925 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926                                    struct si_dte_data *dte_data)
1927 {
1928         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930         u32 k = dte_data->k;
1931         u32 t_max = dte_data->max_t;
1932         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933         u32 t_0 = dte_data->t0;
1934         u32 i;
1935
1936         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937                 dte_data->tdep_count = 3;
1938
1939                 for (i = 0; i < k; i++) {
1940                         dte_data->r[i] =
1941                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942                                 (p_limit2  * (u32)100);
1943                 }
1944
1945                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948                         dte_data->tdep_r[i] = dte_data->r[4];
1949                 }
1950         } else {
1951                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952         }
1953 }
1954
1955 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956 {
1957         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959         return pi;
1960 }
1961
1962 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963 {
1964         struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966         return pi;
1967 }
1968
1969 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970 {
1971         struct  si_ps *ps = aps->ps_priv;
1972
1973         return ps;
1974 }
1975
1976 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977 {
1978         struct ni_power_info *ni_pi = ni_get_pi(adev);
1979         struct si_power_info *si_pi = si_get_pi(adev);
1980         bool update_dte_from_pl2 = false;
1981
1982         if (adev->asic_type == CHIP_TAHITI) {
1983                 si_pi->cac_weights = cac_weights_tahiti;
1984                 si_pi->lcac_config = lcac_tahiti;
1985                 si_pi->cac_override = cac_override_tahiti;
1986                 si_pi->powertune_data = &powertune_data_tahiti;
1987                 si_pi->dte_data = dte_data_tahiti;
1988
1989                 switch (adev->pdev->device) {
1990                 case 0x6798:
1991                         si_pi->dte_data.enable_dte_by_default = true;
1992                         break;
1993                 case 0x6799:
1994                         si_pi->dte_data = dte_data_new_zealand;
1995                         break;
1996                 case 0x6790:
1997                 case 0x6791:
1998                 case 0x6792:
1999                 case 0x679E:
2000                         si_pi->dte_data = dte_data_aruba_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x679B:
2004                         si_pi->dte_data = dte_data_malta;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x679A:
2008                         si_pi->dte_data = dte_data_tahiti_pro;
2009                         update_dte_from_pl2 = true;
2010                         break;
2011                 default:
2012                         if (si_pi->dte_data.enable_dte_by_default == true)
2013                                 DRM_ERROR("DTE is not enabled!\n");
2014                         break;
2015                 }
2016         } else if (adev->asic_type == CHIP_PITCAIRN) {
2017                 si_pi->cac_weights = cac_weights_pitcairn;
2018                 si_pi->lcac_config = lcac_pitcairn;
2019                 si_pi->cac_override = cac_override_pitcairn;
2020                 si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022                 switch (adev->pdev->device) {
2023                 case 0x6810:
2024                 case 0x6818:
2025                         si_pi->dte_data = dte_data_curacao_xt;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6819:
2029                 case 0x6811:
2030                         si_pi->dte_data = dte_data_curacao_pro;
2031                         update_dte_from_pl2 = true;
2032                         break;
2033                 case 0x6800:
2034                 case 0x6806:
2035                         si_pi->dte_data = dte_data_neptune_xt;
2036                         update_dte_from_pl2 = true;
2037                         break;
2038                 default:
2039                         si_pi->dte_data = dte_data_pitcairn;
2040                         break;
2041                 }
2042         } else if (adev->asic_type == CHIP_VERDE) {
2043                 si_pi->lcac_config = lcac_cape_verde;
2044                 si_pi->cac_override = cac_override_cape_verde;
2045                 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047                 switch (adev->pdev->device) {
2048                 case 0x683B:
2049                 case 0x683F:
2050                 case 0x6829:
2051                 case 0x6835:
2052                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2053                         si_pi->dte_data = dte_data_cape_verde;
2054                         break;
2055                 case 0x682C:
2056                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2057                         si_pi->dte_data = dte_data_sun_xt;
2058                         break;
2059                 case 0x6825:
2060                 case 0x6827:
2061                         si_pi->cac_weights = cac_weights_heathrow;
2062                         si_pi->dte_data = dte_data_cape_verde;
2063                         break;
2064                 case 0x6824:
2065                 case 0x682D:
2066                         si_pi->cac_weights = cac_weights_chelsea_xt;
2067                         si_pi->dte_data = dte_data_cape_verde;
2068                         break;
2069                 case 0x682F:
2070                         si_pi->cac_weights = cac_weights_chelsea_pro;
2071                         si_pi->dte_data = dte_data_cape_verde;
2072                         break;
2073                 case 0x6820:
2074                         si_pi->cac_weights = cac_weights_heathrow;
2075                         si_pi->dte_data = dte_data_venus_xtx;
2076                         break;
2077                 case 0x6821:
2078                         si_pi->cac_weights = cac_weights_heathrow;
2079                         si_pi->dte_data = dte_data_venus_xt;
2080                         break;
2081                 case 0x6823:
2082                 case 0x682B:
2083                 case 0x6822:
2084                 case 0x682A:
2085                         si_pi->cac_weights = cac_weights_chelsea_pro;
2086                         si_pi->dte_data = dte_data_venus_pro;
2087                         break;
2088                 default:
2089                         si_pi->cac_weights = cac_weights_cape_verde;
2090                         si_pi->dte_data = dte_data_cape_verde;
2091                         break;
2092                 }
2093         } else if (adev->asic_type == CHIP_OLAND) {
2094                 si_pi->lcac_config = lcac_mars_pro;
2095                 si_pi->cac_override = cac_override_oland;
2096                 si_pi->powertune_data = &powertune_data_mars_pro;
2097                 si_pi->dte_data = dte_data_mars_pro;
2098
2099                 switch (adev->pdev->device) {
2100                 case 0x6601:
2101                 case 0x6621:
2102                 case 0x6603:
2103                 case 0x6605:
2104                         si_pi->cac_weights = cac_weights_mars_pro;
2105                         update_dte_from_pl2 = true;
2106                         break;
2107                 case 0x6600:
2108                 case 0x6606:
2109                 case 0x6620:
2110                 case 0x6604:
2111                         si_pi->cac_weights = cac_weights_mars_xt;
2112                         update_dte_from_pl2 = true;
2113                         break;
2114                 case 0x6611:
2115                 case 0x6613:
2116                 case 0x6608:
2117                         si_pi->cac_weights = cac_weights_oland_pro;
2118                         update_dte_from_pl2 = true;
2119                         break;
2120                 case 0x6610:
2121                         si_pi->cac_weights = cac_weights_oland_xt;
2122                         update_dte_from_pl2 = true;
2123                         break;
2124                 default:
2125                         si_pi->cac_weights = cac_weights_oland;
2126                         si_pi->lcac_config = lcac_oland;
2127                         si_pi->cac_override = cac_override_oland;
2128                         si_pi->powertune_data = &powertune_data_oland;
2129                         si_pi->dte_data = dte_data_oland;
2130                         break;
2131                 }
2132         } else if (adev->asic_type == CHIP_HAINAN) {
2133                 si_pi->cac_weights = cac_weights_hainan;
2134                 si_pi->lcac_config = lcac_oland;
2135                 si_pi->cac_override = cac_override_oland;
2136                 si_pi->powertune_data = &powertune_data_hainan;
2137                 si_pi->dte_data = dte_data_sun_xt;
2138                 update_dte_from_pl2 = true;
2139         } else {
2140                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141                 return;
2142         }
2143
2144         ni_pi->enable_power_containment = false;
2145         ni_pi->enable_cac = false;
2146         ni_pi->enable_sq_ramping = false;
2147         si_pi->enable_dte = false;
2148
2149         if (si_pi->powertune_data->enable_powertune_by_default) {
2150                 ni_pi->enable_power_containment = true;
2151                 ni_pi->enable_cac = true;
2152                 if (si_pi->dte_data.enable_dte_by_default) {
2153                         si_pi->enable_dte = true;
2154                         if (update_dte_from_pl2)
2155                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157                 }
2158                 ni_pi->enable_sq_ramping = true;
2159         }
2160
2161         ni_pi->driver_calculate_cac_leakage = true;
2162         ni_pi->cac_configuration_required = true;
2163
2164         if (ni_pi->cac_configuration_required) {
2165                 ni_pi->support_cac_long_term_average = true;
2166                 si_pi->dyn_powertune_data.l2_lta_window_size =
2167                         si_pi->powertune_data->l2_lta_window_size_default;
2168                 si_pi->dyn_powertune_data.lts_truncate =
2169                         si_pi->powertune_data->lts_truncate_default;
2170         } else {
2171                 ni_pi->support_cac_long_term_average = false;
2172                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173                 si_pi->dyn_powertune_data.lts_truncate = 0;
2174         }
2175
2176         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177 }
2178
2179 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180 {
2181         return 1;
2182 }
2183
2184 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185 {
2186         u32 xclk;
2187         u32 wintime;
2188         u32 cac_window;
2189         u32 cac_window_size;
2190
2191         xclk = amdgpu_asic_get_xclk(adev);
2192
2193         if (xclk == 0)
2194                 return 0;
2195
2196         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199         wintime = (cac_window_size * 100) / xclk;
2200
2201         return wintime;
2202 }
2203
2204 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205 {
2206         return power_in_watts;
2207 }
2208
2209 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210                                             bool adjust_polarity,
2211                                             u32 tdp_adjustment,
2212                                             u32 *tdp_limit,
2213                                             u32 *near_tdp_limit)
2214 {
2215         u32 adjustment_delta, max_tdp_limit;
2216
2217         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218                 return -EINVAL;
2219
2220         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222         if (adjust_polarity) {
2223                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225         } else {
2226                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2228                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230                 else
2231                         *near_tdp_limit = 0;
2232         }
2233
2234         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235                 return -EINVAL;
2236         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237                 return -EINVAL;
2238
2239         return 0;
2240 }
2241
2242 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243                                       struct amdgpu_ps *amdgpu_state)
2244 {
2245         struct ni_power_info *ni_pi = ni_get_pi(adev);
2246         struct si_power_info *si_pi = si_get_pi(adev);
2247
2248         if (ni_pi->enable_power_containment) {
2249                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250                 PP_SIslands_PAPMParameters *papm_parm;
2251                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253                 u32 tdp_limit;
2254                 u32 near_tdp_limit;
2255                 int ret;
2256
2257                 if (scaling_factor == 0)
2258                         return -EINVAL;
2259
2260                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262                 ret = si_calculate_adjusted_tdp_limits(adev,
2263                                                        false, /* ??? */
2264                                                        adev->pm.dpm.tdp_adjustment,
2265                                                        &tdp_limit,
2266                                                        &near_tdp_limit);
2267                 if (ret)
2268                         return ret;
2269
2270                 smc_table->dpm2Params.TDPLimit =
2271                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272                 smc_table->dpm2Params.NearTDPLimit =
2273                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274                 smc_table->dpm2Params.SafePowerLimit =
2275                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
2277                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281                                                   sizeof(u32) * 3,
2282                                                   si_pi->sram_end);
2283                 if (ret)
2284                         return ret;
2285
2286                 if (si_pi->enable_ppm) {
2287                         papm_parm = &si_pi->papm_parm;
2288                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293                         papm_parm->PlatformPowerLimit = 0xffffffff;
2294                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
2296                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297                                                           (u8 *)papm_parm,
2298                                                           sizeof(PP_SIslands_PAPMParameters),
2299                                                           si_pi->sram_end);
2300                         if (ret)
2301                                 return ret;
2302                 }
2303         }
2304         return 0;
2305 }
2306
2307 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308                                         struct amdgpu_ps *amdgpu_state)
2309 {
2310         struct ni_power_info *ni_pi = ni_get_pi(adev);
2311         struct si_power_info *si_pi = si_get_pi(adev);
2312
2313         if (ni_pi->enable_power_containment) {
2314                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316                 int ret;
2317
2318                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320                 smc_table->dpm2Params.NearTDPLimit =
2321                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322                 smc_table->dpm2Params.SafePowerLimit =
2323                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
2325                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326                                                   (si_pi->state_table_start +
2327                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330                                                   sizeof(u32) * 2,
2331                                                   si_pi->sram_end);
2332                 if (ret)
2333                         return ret;
2334         }
2335
2336         return 0;
2337 }
2338
2339 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340                                                const u16 prev_std_vddc,
2341                                                const u16 curr_std_vddc)
2342 {
2343         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344         u64 prev_vddc = (u64)prev_std_vddc;
2345         u64 curr_vddc = (u64)curr_std_vddc;
2346         u64 pwr_efficiency_ratio, n, d;
2347
2348         if ((prev_vddc == 0) || (curr_vddc == 0))
2349                 return 0;
2350
2351         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352         d = prev_vddc * prev_vddc;
2353         pwr_efficiency_ratio = div64_u64(n, d);
2354
2355         if (pwr_efficiency_ratio > (u64)0xFFFF)
2356                 return 0;
2357
2358         return (u16)pwr_efficiency_ratio;
2359 }
2360
2361 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362                                             struct amdgpu_ps *amdgpu_state)
2363 {
2364         struct si_power_info *si_pi = si_get_pi(adev);
2365
2366         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367             amdgpu_state->vclk && amdgpu_state->dclk)
2368                 return true;
2369
2370         return false;
2371 }
2372
2373 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374 {
2375         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377         return pi;
2378 }
2379
2380 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381                                                 struct amdgpu_ps *amdgpu_state,
2382                                                 SISLANDS_SMC_SWSTATE *smc_state)
2383 {
2384         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385         struct ni_power_info *ni_pi = ni_get_pi(adev);
2386         struct  si_ps *state = si_get_ps(amdgpu_state);
2387         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388         u32 prev_sclk;
2389         u32 max_sclk;
2390         u32 min_sclk;
2391         u16 prev_std_vddc;
2392         u16 curr_std_vddc;
2393         int i;
2394         u16 pwr_efficiency_ratio;
2395         u8 max_ps_percent;
2396         bool disable_uvd_power_tune;
2397         int ret;
2398
2399         if (ni_pi->enable_power_containment == false)
2400                 return 0;
2401
2402         if (state->performance_level_count == 0)
2403                 return -EINVAL;
2404
2405         if (smc_state->levelCount != state->performance_level_count)
2406                 return -EINVAL;
2407
2408         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410         smc_state->levels[0].dpm2.MaxPS = 0;
2411         smc_state->levels[0].dpm2.NearTDPDec = 0;
2412         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416         for (i = 1; i < state->performance_level_count; i++) {
2417                 prev_sclk = state->performance_levels[i-1].sclk;
2418                 max_sclk  = state->performance_levels[i].sclk;
2419                 if (i == 1)
2420                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421                 else
2422                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424                 if (prev_sclk > max_sclk)
2425                         return -EINVAL;
2426
2427                 if ((max_ps_percent == 0) ||
2428                     (prev_sclk == max_sclk) ||
2429                     disable_uvd_power_tune)
2430                         min_sclk = max_sclk;
2431                 else if (i == 1)
2432                         min_sclk = prev_sclk;
2433                 else
2434                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2435
2436                 if (min_sclk < state->performance_levels[0].sclk)
2437                         min_sclk = state->performance_levels[0].sclk;
2438
2439                 if (min_sclk == 0)
2440                         return -EINVAL;
2441
2442                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443                                                 state->performance_levels[i-1].vddc, &vddc);
2444                 if (ret)
2445                         return ret;
2446
2447                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448                 if (ret)
2449                         return ret;
2450
2451                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452                                                 state->performance_levels[i].vddc, &vddc);
2453                 if (ret)
2454                         return ret;
2455
2456                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457                 if (ret)
2458                         return ret;
2459
2460                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461                                                                            prev_std_vddc, curr_std_vddc);
2462
2463                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468         }
2469
2470         return 0;
2471 }
2472
2473 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474                                          struct amdgpu_ps *amdgpu_state,
2475                                          SISLANDS_SMC_SWSTATE *smc_state)
2476 {
2477         struct ni_power_info *ni_pi = ni_get_pi(adev);
2478         struct  si_ps *state = si_get_ps(amdgpu_state);
2479         u32 sq_power_throttle, sq_power_throttle2;
2480         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481         int i;
2482
2483         if (state->performance_level_count == 0)
2484                 return -EINVAL;
2485
2486         if (smc_state->levelCount != state->performance_level_count)
2487                 return -EINVAL;
2488
2489         if (adev->pm.dpm.sq_ramping_threshold == 0)
2490                 return -EINVAL;
2491
2492         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493                 enable_sq_ramping = false;
2494
2495         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496                 enable_sq_ramping = false;
2497
2498         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499                 enable_sq_ramping = false;
2500
2501         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502                 enable_sq_ramping = false;
2503
2504         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505                 enable_sq_ramping = false;
2506
2507         for (i = 0; i < state->performance_level_count; i++) {
2508                 sq_power_throttle = 0;
2509                 sq_power_throttle2 = 0;
2510
2511                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512                     enable_sq_ramping) {
2513                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518                 } else {
2519                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521                 }
2522
2523                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525         }
2526
2527         return 0;
2528 }
2529
2530 static int si_enable_power_containment(struct amdgpu_device *adev,
2531                                        struct amdgpu_ps *amdgpu_new_state,
2532                                        bool enable)
2533 {
2534         struct ni_power_info *ni_pi = ni_get_pi(adev);
2535         PPSMC_Result smc_result;
2536         int ret = 0;
2537
2538         if (ni_pi->enable_power_containment) {
2539                 if (enable) {
2540                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2541                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2542                                 if (smc_result != PPSMC_Result_OK) {
2543                                         ret = -EINVAL;
2544                                         ni_pi->pc_enabled = false;
2545                                 } else {
2546                                         ni_pi->pc_enabled = true;
2547                                 }
2548                         }
2549                 } else {
2550                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2551                         if (smc_result != PPSMC_Result_OK)
2552                                 ret = -EINVAL;
2553                         ni_pi->pc_enabled = false;
2554                 }
2555         }
2556
2557         return ret;
2558 }
2559
2560 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561 {
2562         struct si_power_info *si_pi = si_get_pi(adev);
2563         int ret = 0;
2564         struct si_dte_data *dte_data = &si_pi->dte_data;
2565         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566         u32 table_size;
2567         u8 tdep_count;
2568         u32 i;
2569
2570         if (dte_data == NULL)
2571                 si_pi->enable_dte = false;
2572
2573         if (si_pi->enable_dte == false)
2574                 return 0;
2575
2576         if (dte_data->k <= 0)
2577                 return -EINVAL;
2578
2579         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580         if (dte_tables == NULL) {
2581                 si_pi->enable_dte = false;
2582                 return -ENOMEM;
2583         }
2584
2585         table_size = dte_data->k;
2586
2587         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590         tdep_count = dte_data->tdep_count;
2591         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594         dte_tables->K = cpu_to_be32(table_size);
2595         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597         dte_tables->WindowSize = dte_data->window_size;
2598         dte_tables->temp_select = dte_data->temp_select;
2599         dte_tables->DTE_mode = dte_data->dte_mode;
2600         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602         if (tdep_count > 0)
2603                 table_size--;
2604
2605         for (i = 0; i < table_size; i++) {
2606                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2608         }
2609
2610         dte_tables->Tdep_count = tdep_count;
2611
2612         for (i = 0; i < (u32)tdep_count; i++) {
2613                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616         }
2617
2618         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619                                           (u8 *)dte_tables,
2620                                           sizeof(Smc_SIslands_DTE_Configuration),
2621                                           si_pi->sram_end);
2622         kfree(dte_tables);
2623
2624         return ret;
2625 }
2626
2627 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628                                           u16 *max, u16 *min)
2629 {
2630         struct si_power_info *si_pi = si_get_pi(adev);
2631         struct amdgpu_cac_leakage_table *table =
2632                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633         u32 i;
2634         u32 v0_loadline;
2635
2636         if (table == NULL)
2637                 return -EINVAL;
2638
2639         *max = 0;
2640         *min = 0xFFFF;
2641
2642         for (i = 0; i < table->count; i++) {
2643                 if (table->entries[i].vddc > *max)
2644                         *max = table->entries[i].vddc;
2645                 if (table->entries[i].vddc < *min)
2646                         *min = table->entries[i].vddc;
2647         }
2648
2649         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650                 return -EINVAL;
2651
2652         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654         if (v0_loadline > 0xFFFFUL)
2655                 return -EINVAL;
2656
2657         *min = (u16)v0_loadline;
2658
2659         if ((*min > *max) || (*max == 0) || (*min == 0))
2660                 return -EINVAL;
2661
2662         return 0;
2663 }
2664
2665 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666 {
2667         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669 }
2670
2671 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672                                      PP_SIslands_CacConfig *cac_tables,
2673                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674                                      u16 t0, u16 t_step)
2675 {
2676         struct si_power_info *si_pi = si_get_pi(adev);
2677         u32 leakage;
2678         unsigned int i, j;
2679         s32 t;
2680         u32 smc_leakage;
2681         u32 scaling_factor;
2682         u16 voltage;
2683
2684         scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687                 t = (1000 * (i * t_step + t0));
2688
2689                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690                         voltage = vddc_max - (vddc_step * j);
2691
2692                         si_calculate_leakage_for_v_and_t(adev,
2693                                                          &si_pi->powertune_data->leakage_coefficients,
2694                                                          voltage,
2695                                                          t,
2696                                                          si_pi->dyn_powertune_data.cac_leakage,
2697                                                          &leakage);
2698
2699                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701                         if (smc_leakage > 0xFFFF)
2702                                 smc_leakage = 0xFFFF;
2703
2704                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705                                 cpu_to_be16((u16)smc_leakage);
2706                 }
2707         }
2708         return 0;
2709 }
2710
2711 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712                                             PP_SIslands_CacConfig *cac_tables,
2713                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714 {
2715         struct si_power_info *si_pi = si_get_pi(adev);
2716         u32 leakage;
2717         unsigned int i, j;
2718         u32 smc_leakage;
2719         u32 scaling_factor;
2720         u16 voltage;
2721
2722         scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725                 voltage = vddc_max - (vddc_step * j);
2726
2727                 si_calculate_leakage_for_v(adev,
2728                                            &si_pi->powertune_data->leakage_coefficients,
2729                                            si_pi->powertune_data->fixed_kt,
2730                                            voltage,
2731                                            si_pi->dyn_powertune_data.cac_leakage,
2732                                            &leakage);
2733
2734                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736                 if (smc_leakage > 0xFFFF)
2737                         smc_leakage = 0xFFFF;
2738
2739                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741                                 cpu_to_be16((u16)smc_leakage);
2742         }
2743         return 0;
2744 }
2745
2746 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747 {
2748         struct ni_power_info *ni_pi = ni_get_pi(adev);
2749         struct si_power_info *si_pi = si_get_pi(adev);
2750         PP_SIslands_CacConfig *cac_tables = NULL;
2751         u16 vddc_max, vddc_min, vddc_step;
2752         u16 t0, t_step;
2753         u32 load_line_slope, reg;
2754         int ret = 0;
2755         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757         if (ni_pi->enable_cac == false)
2758                 return 0;
2759
2760         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761         if (!cac_tables)
2762                 return -ENOMEM;
2763
2764         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766         WREG32(CG_CAC_CTRL, reg);
2767
2768         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769         si_pi->dyn_powertune_data.dc_pwr_value =
2770                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777         if (ret)
2778                 goto done_free;
2779
2780         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782         t_step = 4;
2783         t0 = 60;
2784
2785         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786                 ret = si_init_dte_leakage_table(adev, cac_tables,
2787                                                 vddc_max, vddc_min, vddc_step,
2788                                                 t0, t_step);
2789         else
2790                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791                                                        vddc_max, vddc_min, vddc_step);
2792         if (ret)
2793                 goto done_free;
2794
2795         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804         cac_tables->calculation_repeats = cpu_to_be32(2);
2805         cac_tables->dc_cac = cpu_to_be32(0);
2806         cac_tables->log2_PG_LKG_SCALE = 12;
2807         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
2811         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2812                                           (u8 *)cac_tables,
2813                                           sizeof(PP_SIslands_CacConfig),
2814                                           si_pi->sram_end);
2815
2816         if (ret)
2817                 goto done_free;
2818
2819         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2820
2821 done_free:
2822         if (ret) {
2823                 ni_pi->enable_cac = false;
2824                 ni_pi->enable_power_containment = false;
2825         }
2826
2827         kfree(cac_tables);
2828
2829         return ret;
2830 }
2831
2832 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2833                                            const struct si_cac_config_reg *cac_config_regs)
2834 {
2835         const struct si_cac_config_reg *config_regs = cac_config_regs;
2836         u32 data = 0, offset;
2837
2838         if (!config_regs)
2839                 return -EINVAL;
2840
2841         while (config_regs->offset != 0xFFFFFFFF) {
2842                 switch (config_regs->type) {
2843                 case SISLANDS_CACCONFIG_CGIND:
2844                         offset = SMC_CG_IND_START + config_regs->offset;
2845                         if (offset < SMC_CG_IND_END)
2846                                 data = RREG32_SMC(offset);
2847                         break;
2848                 default:
2849                         data = RREG32(config_regs->offset);
2850                         break;
2851                 }
2852
2853                 data &= ~config_regs->mask;
2854                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2855
2856                 switch (config_regs->type) {
2857                 case SISLANDS_CACCONFIG_CGIND:
2858                         offset = SMC_CG_IND_START + config_regs->offset;
2859                         if (offset < SMC_CG_IND_END)
2860                                 WREG32_SMC(offset, data);
2861                         break;
2862                 default:
2863                         WREG32(config_regs->offset, data);
2864                         break;
2865                 }
2866                 config_regs++;
2867         }
2868         return 0;
2869 }
2870
2871 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2872 {
2873         struct ni_power_info *ni_pi = ni_get_pi(adev);
2874         struct si_power_info *si_pi = si_get_pi(adev);
2875         int ret;
2876
2877         if ((ni_pi->enable_cac == false) ||
2878             (ni_pi->cac_configuration_required == false))
2879                 return 0;
2880
2881         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2882         if (ret)
2883                 return ret;
2884         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2885         if (ret)
2886                 return ret;
2887         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2888         if (ret)
2889                 return ret;
2890
2891         return 0;
2892 }
2893
2894 static int si_enable_smc_cac(struct amdgpu_device *adev,
2895                              struct amdgpu_ps *amdgpu_new_state,
2896                              bool enable)
2897 {
2898         struct ni_power_info *ni_pi = ni_get_pi(adev);
2899         struct si_power_info *si_pi = si_get_pi(adev);
2900         PPSMC_Result smc_result;
2901         int ret = 0;
2902
2903         if (ni_pi->enable_cac) {
2904                 if (enable) {
2905                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2906                                 if (ni_pi->support_cac_long_term_average) {
2907                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2908                                         if (smc_result != PPSMC_Result_OK)
2909                                                 ni_pi->support_cac_long_term_average = false;
2910                                 }
2911
2912                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2913                                 if (smc_result != PPSMC_Result_OK) {
2914                                         ret = -EINVAL;
2915                                         ni_pi->cac_enabled = false;
2916                                 } else {
2917                                         ni_pi->cac_enabled = true;
2918                                 }
2919
2920                                 if (si_pi->enable_dte) {
2921                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2922                                         if (smc_result != PPSMC_Result_OK)
2923                                                 ret = -EINVAL;
2924                                 }
2925                         }
2926                 } else if (ni_pi->cac_enabled) {
2927                         if (si_pi->enable_dte)
2928                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2929
2930                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2931
2932                         ni_pi->cac_enabled = false;
2933
2934                         if (ni_pi->support_cac_long_term_average)
2935                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2936                 }
2937         }
2938         return ret;
2939 }
2940
2941 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2942 {
2943         struct ni_power_info *ni_pi = ni_get_pi(adev);
2944         struct si_power_info *si_pi = si_get_pi(adev);
2945         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2946         SISLANDS_SMC_SCLK_VALUE sclk_params;
2947         u32 fb_div, p_div;
2948         u32 clk_s, clk_v;
2949         u32 sclk = 0;
2950         int ret = 0;
2951         u32 tmp;
2952         int i;
2953
2954         if (si_pi->spll_table_start == 0)
2955                 return -EINVAL;
2956
2957         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2958         if (spll_table == NULL)
2959                 return -ENOMEM;
2960
2961         for (i = 0; i < 256; i++) {
2962                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2963                 if (ret)
2964                         break;
2965                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2966                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2967                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2968                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2969
2970                 fb_div &= ~0x00001FFF;
2971                 fb_div >>= 1;
2972                 clk_v >>= 6;
2973
2974                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2975                         ret = -EINVAL;
2976                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2977                         ret = -EINVAL;
2978                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2979                         ret = -EINVAL;
2980                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2981                         ret = -EINVAL;
2982
2983                 if (ret)
2984                         break;
2985
2986                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2987                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2988                 spll_table->freq[i] = cpu_to_be32(tmp);
2989
2990                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2991                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2992                 spll_table->ss[i] = cpu_to_be32(tmp);
2993
2994                 sclk += 512;
2995         }
2996
2997
2998         if (!ret)
2999                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3000                                                   (u8 *)spll_table,
3001                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002                                                   si_pi->sram_end);
3003
3004         if (ret)
3005                 ni_pi->enable_power_containment = false;
3006
3007         kfree(spll_table);
3008
3009         return ret;
3010 }
3011
3012 struct si_dpm_quirk {
3013         u32 chip_vendor;
3014         u32 chip_device;
3015         u32 subsys_vendor;
3016         u32 subsys_device;
3017         u32 max_sclk;
3018         u32 max_mclk;
3019 };
3020
3021 /* cards with dpm stability problems */
3022 static struct si_dpm_quirk si_dpm_quirk_list[] = {
3023         /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
3024         { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 },
3025         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 },
3026         { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 120000 },
3027         { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 },
3028         { PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
3029         { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
3030         { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
3031         { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
3032         { 0, 0, 0, 0 },
3033 };
3034
3035 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3036                                                    u16 vce_voltage)
3037 {
3038         u16 highest_leakage = 0;
3039         struct si_power_info *si_pi = si_get_pi(adev);
3040         int i;
3041
3042         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3043                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3044                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3045         }
3046
3047         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3048                 return highest_leakage;
3049
3050         return vce_voltage;
3051 }
3052
3053 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3054                                     u32 evclk, u32 ecclk, u16 *voltage)
3055 {
3056         u32 i;
3057         int ret = -EINVAL;
3058         struct amdgpu_vce_clock_voltage_dependency_table *table =
3059                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3060
3061         if (((evclk == 0) && (ecclk == 0)) ||
3062             (table && (table->count == 0))) {
3063                 *voltage = 0;
3064                 return 0;
3065         }
3066
3067         for (i = 0; i < table->count; i++) {
3068                 if ((evclk <= table->entries[i].evclk) &&
3069                     (ecclk <= table->entries[i].ecclk)) {
3070                         *voltage = table->entries[i].v;
3071                         ret = 0;
3072                         break;
3073                 }
3074         }
3075
3076         /* if no match return the highest voltage */
3077         if (ret)
3078                 *voltage = table->entries[table->count - 1].v;
3079
3080         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3081
3082         return ret;
3083 }
3084
3085 static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3086 {
3087
3088         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3089         /* we never hit the non-gddr5 limit so disable it */
3090         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3091
3092         if (vblank_time < switch_limit)
3093                 return true;
3094         else
3095                 return false;
3096
3097 }
3098
3099 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3100                                 u32 arb_freq_src, u32 arb_freq_dest)
3101 {
3102         u32 mc_arb_dram_timing;
3103         u32 mc_arb_dram_timing2;
3104         u32 burst_time;
3105         u32 mc_cg_config;
3106
3107         switch (arb_freq_src) {
3108         case MC_CG_ARB_FREQ_F0:
3109                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3110                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3111                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3112                 break;
3113         case MC_CG_ARB_FREQ_F1:
3114                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3115                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3116                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3117                 break;
3118         case MC_CG_ARB_FREQ_F2:
3119                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3120                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3121                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3122                 break;
3123         case MC_CG_ARB_FREQ_F3:
3124                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3125                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3126                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3127                 break;
3128         default:
3129                 return -EINVAL;
3130         }
3131
3132         switch (arb_freq_dest) {
3133         case MC_CG_ARB_FREQ_F0:
3134                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3135                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3136                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3137                 break;
3138         case MC_CG_ARB_FREQ_F1:
3139                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3140                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3141                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3142                 break;
3143         case MC_CG_ARB_FREQ_F2:
3144                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3145                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3146                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3147                 break;
3148         case MC_CG_ARB_FREQ_F3:
3149                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3150                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3151                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3152                 break;
3153         default:
3154                 return -EINVAL;
3155         }
3156
3157         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3158         WREG32(MC_CG_CONFIG, mc_cg_config);
3159         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3160
3161         return 0;
3162 }
3163
3164 static void ni_update_current_ps(struct amdgpu_device *adev,
3165                           struct amdgpu_ps *rps)
3166 {
3167         struct si_ps *new_ps = si_get_ps(rps);
3168         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3169         struct ni_power_info *ni_pi = ni_get_pi(adev);
3170
3171         eg_pi->current_rps = *rps;
3172         ni_pi->current_ps = *new_ps;
3173         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3174         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3175 }
3176
3177 static void ni_update_requested_ps(struct amdgpu_device *adev,
3178                             struct amdgpu_ps *rps)
3179 {
3180         struct si_ps *new_ps = si_get_ps(rps);
3181         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3182         struct ni_power_info *ni_pi = ni_get_pi(adev);
3183
3184         eg_pi->requested_rps = *rps;
3185         ni_pi->requested_ps = *new_ps;
3186         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3187         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3188 }
3189
3190 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3191                                            struct amdgpu_ps *new_ps,
3192                                            struct amdgpu_ps *old_ps)
3193 {
3194         struct si_ps *new_state = si_get_ps(new_ps);
3195         struct si_ps *current_state = si_get_ps(old_ps);
3196
3197         if ((new_ps->vclk == old_ps->vclk) &&
3198             (new_ps->dclk == old_ps->dclk))
3199                 return;
3200
3201         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3202             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3203                 return;
3204
3205         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3206 }
3207
3208 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3209                                           struct amdgpu_ps *new_ps,
3210                                           struct amdgpu_ps *old_ps)
3211 {
3212         struct si_ps *new_state = si_get_ps(new_ps);
3213         struct si_ps *current_state = si_get_ps(old_ps);
3214
3215         if ((new_ps->vclk == old_ps->vclk) &&
3216             (new_ps->dclk == old_ps->dclk))
3217                 return;
3218
3219         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3220             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3221                 return;
3222
3223         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3224 }
3225
3226 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3227 {
3228         unsigned int i;
3229
3230         for (i = 0; i < table->count; i++)
3231                 if (voltage <= table->entries[i].value)
3232                         return table->entries[i].value;
3233
3234         return table->entries[table->count - 1].value;
3235 }
3236
3237 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3238                                 u32 max_clock, u32 requested_clock)
3239 {
3240         unsigned int i;
3241
3242         if ((clocks == NULL) || (clocks->count == 0))
3243                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3244
3245         for (i = 0; i < clocks->count; i++) {
3246                 if (clocks->values[i] >= requested_clock)
3247                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3248         }
3249
3250         return (clocks->values[clocks->count - 1] < max_clock) ?
3251                 clocks->values[clocks->count - 1] : max_clock;
3252 }
3253
3254 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3255                               u32 max_mclk, u32 requested_mclk)
3256 {
3257         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3258                                     max_mclk, requested_mclk);
3259 }
3260
3261 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3262                               u32 max_sclk, u32 requested_sclk)
3263 {
3264         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3265                                     max_sclk, requested_sclk);
3266 }
3267
3268 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3269                                                             u32 *max_clock)
3270 {
3271         u32 i, clock = 0;
3272
3273         if ((table == NULL) || (table->count == 0)) {
3274                 *max_clock = clock;
3275                 return;
3276         }
3277
3278         for (i = 0; i < table->count; i++) {
3279                 if (clock < table->entries[i].clk)
3280                         clock = table->entries[i].clk;
3281         }
3282         *max_clock = clock;
3283 }
3284
3285 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3286                                                u32 clock, u16 max_voltage, u16 *voltage)
3287 {
3288         u32 i;
3289
3290         if ((table == NULL) || (table->count == 0))
3291                 return;
3292
3293         for (i= 0; i < table->count; i++) {
3294                 if (clock <= table->entries[i].clk) {
3295                         if (*voltage < table->entries[i].v)
3296                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3297                                            table->entries[i].v : max_voltage);
3298                         return;
3299                 }
3300         }
3301
3302         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3303 }
3304
3305 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3306                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3307                                           struct rv7xx_pl *pl)
3308 {
3309
3310         if ((pl->mclk == 0) || (pl->sclk == 0))
3311                 return;
3312
3313         if (pl->mclk == pl->sclk)
3314                 return;
3315
3316         if (pl->mclk > pl->sclk) {
3317                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3318                         pl->sclk = btc_get_valid_sclk(adev,
3319                                                       max_limits->sclk,
3320                                                       (pl->mclk +
3321                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3322                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3323         } else {
3324                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3325                         pl->mclk = btc_get_valid_mclk(adev,
3326                                                       max_limits->mclk,
3327                                                       pl->sclk -
3328                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3329         }
3330 }
3331
3332 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3333                                           u16 max_vddc, u16 max_vddci,
3334                                           u16 *vddc, u16 *vddci)
3335 {
3336         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3337         u16 new_voltage;
3338
3339         if ((0 == *vddc) || (0 == *vddci))
3340                 return;
3341
3342         if (*vddc > *vddci) {
3343                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3344                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3345                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3346                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3347                 }
3348         } else {
3349                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3350                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3351                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3352                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3353                 }
3354         }
3355 }
3356
3357 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3358                                                u32 sys_mask,
3359                                                enum amdgpu_pcie_gen asic_gen,
3360                                                enum amdgpu_pcie_gen default_gen)
3361 {
3362         switch (asic_gen) {
3363         case AMDGPU_PCIE_GEN1:
3364                 return AMDGPU_PCIE_GEN1;
3365         case AMDGPU_PCIE_GEN2:
3366                 return AMDGPU_PCIE_GEN2;
3367         case AMDGPU_PCIE_GEN3:
3368                 return AMDGPU_PCIE_GEN3;
3369         default:
3370                 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3371                         return AMDGPU_PCIE_GEN3;
3372                 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3373                         return AMDGPU_PCIE_GEN2;
3374                 else
3375                         return AMDGPU_PCIE_GEN1;
3376         }
3377         return AMDGPU_PCIE_GEN1;
3378 }
3379
3380 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3381                             u32 *p, u32 *u)
3382 {
3383         u32 b_c = 0;
3384         u32 i_c;
3385         u32 tmp;
3386
3387         i_c = (i * r_c) / 100;
3388         tmp = i_c >> p_b;
3389
3390         while (tmp) {
3391                 b_c++;
3392                 tmp >>= 1;
3393         }
3394
3395         *u = (b_c + 1) / 2;
3396         *p = i_c / (1 << (2 * (*u)));
3397 }
3398
3399 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3400 {
3401         u32 k, a, ah, al;
3402         u32 t1;
3403
3404         if ((fl == 0) || (fh == 0) || (fl > fh))
3405                 return -EINVAL;
3406
3407         k = (100 * fh) / fl;
3408         t1 = (t * (k - 100));
3409         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3410         a = (a + 5) / 10;
3411         ah = ((a * t) + 5000) / 10000;
3412         al = a - ah;
3413
3414         *th = t - ah;
3415         *tl = t + al;
3416
3417         return 0;
3418 }
3419
3420 static bool r600_is_uvd_state(u32 class, u32 class2)
3421 {
3422         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3423                 return true;
3424         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3425                 return true;
3426         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3427                 return true;
3428         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3429                 return true;
3430         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3431                 return true;
3432         return false;
3433 }
3434
3435 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3436 {
3437         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3438 }
3439
3440 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3441 {
3442         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3443         u16 vddc;
3444
3445         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3446                 pi->max_vddc = 0;
3447         else
3448                 pi->max_vddc = vddc;
3449 }
3450
3451 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3452 {
3453         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3454         struct amdgpu_atom_ss ss;
3455
3456         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3457                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3458         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3459                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3460
3461         if (pi->sclk_ss || pi->mclk_ss)
3462                 pi->dynamic_ss = true;
3463         else
3464                 pi->dynamic_ss = false;
3465 }
3466
3467
3468 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3469                                         struct amdgpu_ps *rps)
3470 {
3471         struct  si_ps *ps = si_get_ps(rps);
3472         struct amdgpu_clock_and_voltage_limits *max_limits;
3473         bool disable_mclk_switching = false;
3474         bool disable_sclk_switching = false;
3475         u32 mclk, sclk;
3476         u16 vddc, vddci, min_vce_voltage = 0;
3477         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3478         u32 max_sclk = 0, max_mclk = 0;
3479         int i;
3480         struct si_dpm_quirk *p = si_dpm_quirk_list;
3481
3482         /* Apply dpm quirks */
3483         while (p && p->chip_device != 0) {
3484                 if (adev->pdev->vendor == p->chip_vendor &&
3485                     adev->pdev->device == p->chip_device &&
3486                     adev->pdev->subsystem_vendor == p->subsys_vendor &&
3487                     adev->pdev->subsystem_device == p->subsys_device) {
3488                         max_sclk = p->max_sclk;
3489                         max_mclk = p->max_mclk;
3490                         break;
3491                 }
3492                 ++p;
3493         }
3494         /* limit mclk on all R7 370 parts for stability */
3495         if (adev->pdev->device == 0x6811 &&
3496             adev->pdev->revision == 0x81)
3497                 max_mclk = 120000;
3498         /* limit sclk/mclk on Jet parts for stability */
3499         if (adev->pdev->device == 0x6665 &&
3500             adev->pdev->revision == 0xc3) {
3501                 max_sclk = 75000;
3502                 max_mclk = 80000;
3503         }
3504         /* Limit clocks for some HD8600 parts */
3505         if (adev->pdev->device == 0x6660 &&
3506             adev->pdev->revision == 0x83) {
3507                 max_sclk = 75000;
3508                 max_mclk = 80000;
3509         }
3510
3511         if (rps->vce_active) {
3512                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3513                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3514                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3515                                          &min_vce_voltage);
3516         } else {
3517                 rps->evclk = 0;
3518                 rps->ecclk = 0;
3519         }
3520
3521         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3522             si_dpm_vblank_too_short(adev))
3523                 disable_mclk_switching = true;
3524
3525         if (rps->vclk || rps->dclk) {
3526                 disable_mclk_switching = true;
3527                 disable_sclk_switching = true;
3528         }
3529
3530         if (adev->pm.dpm.ac_power)
3531                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3532         else
3533                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3534
3535         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3536                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3537                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3538         }
3539         if (adev->pm.dpm.ac_power == false) {
3540                 for (i = 0; i < ps->performance_level_count; i++) {
3541                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3542                                 ps->performance_levels[i].mclk = max_limits->mclk;
3543                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3544                                 ps->performance_levels[i].sclk = max_limits->sclk;
3545                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3546                                 ps->performance_levels[i].vddc = max_limits->vddc;
3547                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3548                                 ps->performance_levels[i].vddci = max_limits->vddci;
3549                 }
3550         }
3551
3552         /* limit clocks to max supported clocks based on voltage dependency tables */
3553         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3554                                                         &max_sclk_vddc);
3555         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3556                                                         &max_mclk_vddci);
3557         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3558                                                         &max_mclk_vddc);
3559
3560         for (i = 0; i < ps->performance_level_count; i++) {
3561                 if (max_sclk_vddc) {
3562                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3563                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3564                 }
3565                 if (max_mclk_vddci) {
3566                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3567                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3568                 }
3569                 if (max_mclk_vddc) {
3570                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3571                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3572                 }
3573                 if (max_mclk) {
3574                         if (ps->performance_levels[i].mclk > max_mclk)
3575                                 ps->performance_levels[i].mclk = max_mclk;
3576                 }
3577                 if (max_sclk) {
3578                         if (ps->performance_levels[i].sclk > max_sclk)
3579                                 ps->performance_levels[i].sclk = max_sclk;
3580                 }
3581         }
3582
3583         /* XXX validate the min clocks required for display */
3584
3585         if (disable_mclk_switching) {
3586                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3587                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3588         } else {
3589                 mclk = ps->performance_levels[0].mclk;
3590                 vddci = ps->performance_levels[0].vddci;
3591         }
3592
3593         if (disable_sclk_switching) {
3594                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3595                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3596         } else {
3597                 sclk = ps->performance_levels[0].sclk;
3598                 vddc = ps->performance_levels[0].vddc;
3599         }
3600
3601         if (rps->vce_active) {
3602                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3603                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3604                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3605                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3606         }
3607
3608         /* adjusted low state */
3609         ps->performance_levels[0].sclk = sclk;
3610         ps->performance_levels[0].mclk = mclk;
3611         ps->performance_levels[0].vddc = vddc;
3612         ps->performance_levels[0].vddci = vddci;
3613
3614         if (disable_sclk_switching) {
3615                 sclk = ps->performance_levels[0].sclk;
3616                 for (i = 1; i < ps->performance_level_count; i++) {
3617                         if (sclk < ps->performance_levels[i].sclk)
3618                                 sclk = ps->performance_levels[i].sclk;
3619                 }
3620                 for (i = 0; i < ps->performance_level_count; i++) {
3621                         ps->performance_levels[i].sclk = sclk;
3622                         ps->performance_levels[i].vddc = vddc;
3623                 }
3624         } else {
3625                 for (i = 1; i < ps->performance_level_count; i++) {
3626                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3627                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3628                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3629                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3630                 }
3631         }
3632
3633         if (disable_mclk_switching) {
3634                 mclk = ps->performance_levels[0].mclk;
3635                 for (i = 1; i < ps->performance_level_count; i++) {
3636                         if (mclk < ps->performance_levels[i].mclk)
3637                                 mclk = ps->performance_levels[i].mclk;
3638                 }
3639                 for (i = 0; i < ps->performance_level_count; i++) {
3640                         ps->performance_levels[i].mclk = mclk;
3641                         ps->performance_levels[i].vddci = vddci;
3642                 }
3643         } else {
3644                 for (i = 1; i < ps->performance_level_count; i++) {
3645                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3646                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3647                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3648                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3649                 }
3650         }
3651
3652         for (i = 0; i < ps->performance_level_count; i++)
3653                 btc_adjust_clock_combinations(adev, max_limits,
3654                                               &ps->performance_levels[i]);
3655
3656         for (i = 0; i < ps->performance_level_count; i++) {
3657                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3658                         ps->performance_levels[i].vddc = min_vce_voltage;
3659                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3660                                                    ps->performance_levels[i].sclk,
3661                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3662                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3663                                                    ps->performance_levels[i].mclk,
3664                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3665                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3666                                                    ps->performance_levels[i].mclk,
3667                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3668                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3669                                                    adev->clock.current_dispclk,
3670                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3671         }
3672
3673         for (i = 0; i < ps->performance_level_count; i++) {
3674                 btc_apply_voltage_delta_rules(adev,
3675                                               max_limits->vddc, max_limits->vddci,
3676                                               &ps->performance_levels[i].vddc,
3677                                               &ps->performance_levels[i].vddci);
3678         }
3679
3680         ps->dc_compatible = true;
3681         for (i = 0; i < ps->performance_level_count; i++) {
3682                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3683                         ps->dc_compatible = false;
3684         }
3685 }
3686
3687 #if 0
3688 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3689                                      u16 reg_offset, u32 *value)
3690 {
3691         struct si_power_info *si_pi = si_get_pi(adev);
3692
3693         return amdgpu_si_read_smc_sram_dword(adev,
3694                                              si_pi->soft_regs_start + reg_offset, value,
3695                                              si_pi->sram_end);
3696 }
3697 #endif
3698
3699 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3700                                       u16 reg_offset, u32 value)
3701 {
3702         struct si_power_info *si_pi = si_get_pi(adev);
3703
3704         return amdgpu_si_write_smc_sram_dword(adev,
3705                                               si_pi->soft_regs_start + reg_offset,
3706                                               value, si_pi->sram_end);
3707 }
3708
3709 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3710 {
3711         bool ret = false;
3712         u32 tmp, width, row, column, bank, density;
3713         bool is_memory_gddr5, is_special;
3714
3715         tmp = RREG32(MC_SEQ_MISC0);
3716         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3717         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3718                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3719
3720         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3721         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3722
3723         tmp = RREG32(MC_ARB_RAMCFG);
3724         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3725         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3726         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3727
3728         density = (1 << (row + column - 20 + bank)) * width;
3729
3730         if ((adev->pdev->device == 0x6819) &&
3731             is_memory_gddr5 && is_special && (density == 0x400))
3732                 ret = true;
3733
3734         return ret;
3735 }
3736
3737 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3738 {
3739         struct si_power_info *si_pi = si_get_pi(adev);
3740         u16 vddc, count = 0;
3741         int i, ret;
3742
3743         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3744                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3745
3746                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3747                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3748                         si_pi->leakage_voltage.entries[count].leakage_index =
3749                                 SISLANDS_LEAKAGE_INDEX0 + i;
3750                         count++;
3751                 }
3752         }
3753         si_pi->leakage_voltage.count = count;
3754 }
3755
3756 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3757                                                      u32 index, u16 *leakage_voltage)
3758 {
3759         struct si_power_info *si_pi = si_get_pi(adev);
3760         int i;
3761
3762         if (leakage_voltage == NULL)
3763                 return -EINVAL;
3764
3765         if ((index & 0xff00) != 0xff00)
3766                 return -EINVAL;
3767
3768         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3769                 return -EINVAL;
3770
3771         if (index < SISLANDS_LEAKAGE_INDEX0)
3772                 return -EINVAL;
3773
3774         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3775                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3776                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3777                         return 0;
3778                 }
3779         }
3780         return -EAGAIN;
3781 }
3782
3783 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3784 {
3785         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3786         bool want_thermal_protection;
3787         enum amdgpu_dpm_event_src dpm_event_src;
3788
3789         switch (sources) {
3790         case 0:
3791         default:
3792                 want_thermal_protection = false;
3793                 break;
3794         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3795                 want_thermal_protection = true;
3796                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3797                 break;
3798         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3799                 want_thermal_protection = true;
3800                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3801                 break;
3802         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3803               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3804                 want_thermal_protection = true;
3805                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3806                 break;
3807         }
3808
3809         if (want_thermal_protection) {
3810                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3811                 if (pi->thermal_protection)
3812                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3813         } else {
3814                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3815         }
3816 }
3817
3818 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3819                                            enum amdgpu_dpm_auto_throttle_src source,
3820                                            bool enable)
3821 {
3822         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3823
3824         if (enable) {
3825                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3826                         pi->active_auto_throttle_sources |= 1 << source;
3827                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3828                 }
3829         } else {
3830                 if (pi->active_auto_throttle_sources & (1 << source)) {
3831                         pi->active_auto_throttle_sources &= ~(1 << source);
3832                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3833                 }
3834         }
3835 }
3836
3837 static void si_start_dpm(struct amdgpu_device *adev)
3838 {
3839         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3840 }
3841
3842 static void si_stop_dpm(struct amdgpu_device *adev)
3843 {
3844         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3845 }
3846
3847 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3848 {
3849         if (enable)
3850                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3851         else
3852                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3853
3854 }
3855
3856 #if 0
3857 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3858                                                u32 thermal_level)
3859 {
3860         PPSMC_Result ret;
3861
3862         if (thermal_level == 0) {
3863                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3864                 if (ret == PPSMC_Result_OK)
3865                         return 0;
3866                 else
3867                         return -EINVAL;
3868         }
3869         return 0;
3870 }
3871
3872 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3873 {
3874         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3875 }
3876 #endif
3877
3878 #if 0
3879 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3880 {
3881         if (ac_power)
3882                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3883                         0 : -EINVAL;
3884
3885         return 0;
3886 }
3887 #endif
3888
3889 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3890                                                       PPSMC_Msg msg, u32 parameter)
3891 {
3892         WREG32(SMC_SCRATCH0, parameter);
3893         return amdgpu_si_send_msg_to_smc(adev, msg);
3894 }
3895
3896 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3897 {
3898         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3899                 return -EINVAL;
3900
3901         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3902                 0 : -EINVAL;
3903 }
3904
3905 static int si_dpm_force_performance_level(struct amdgpu_device *adev,
3906                                    enum amdgpu_dpm_forced_level level)
3907 {
3908         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3909         struct  si_ps *ps = si_get_ps(rps);
3910         u32 levels = ps->performance_level_count;
3911
3912         if (level == AMDGPU_DPM_FORCED_LEVEL_HIGH) {
3913                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3914                         return -EINVAL;
3915
3916                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3917                         return -EINVAL;
3918         } else if (level == AMDGPU_DPM_FORCED_LEVEL_LOW) {
3919                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3920                         return -EINVAL;
3921
3922                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3923                         return -EINVAL;
3924         } else if (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) {
3925                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3926                         return -EINVAL;
3927
3928                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3929                         return -EINVAL;
3930         }
3931
3932         adev->pm.dpm.forced_level = level;
3933
3934         return 0;
3935 }
3936
3937 #if 0
3938 static int si_set_boot_state(struct amdgpu_device *adev)
3939 {
3940         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3941                 0 : -EINVAL;
3942 }
3943 #endif
3944
3945 static int si_set_sw_state(struct amdgpu_device *adev)
3946 {
3947         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3948                 0 : -EINVAL;
3949 }
3950
3951 static int si_halt_smc(struct amdgpu_device *adev)
3952 {
3953         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3954                 return -EINVAL;
3955
3956         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3957                 0 : -EINVAL;
3958 }
3959
3960 static int si_resume_smc(struct amdgpu_device *adev)
3961 {
3962         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3963                 return -EINVAL;
3964
3965         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3966                 0 : -EINVAL;
3967 }
3968
3969 static void si_dpm_start_smc(struct amdgpu_device *adev)
3970 {
3971         amdgpu_si_program_jump_on_start(adev);
3972         amdgpu_si_start_smc(adev);
3973         amdgpu_si_smc_clock(adev, true);
3974 }
3975
3976 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3977 {
3978         amdgpu_si_reset_smc(adev);
3979         amdgpu_si_smc_clock(adev, false);
3980 }
3981
3982 static int si_process_firmware_header(struct amdgpu_device *adev)
3983 {
3984         struct si_power_info *si_pi = si_get_pi(adev);
3985         u32 tmp;
3986         int ret;
3987
3988         ret = amdgpu_si_read_smc_sram_dword(adev,
3989                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3990                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3991                                             &tmp, si_pi->sram_end);
3992         if (ret)
3993                 return ret;
3994
3995         si_pi->state_table_start = tmp;
3996
3997         ret = amdgpu_si_read_smc_sram_dword(adev,
3998                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3999                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
4000                                             &tmp, si_pi->sram_end);
4001         if (ret)
4002                 return ret;
4003
4004         si_pi->soft_regs_start = tmp;
4005
4006         ret = amdgpu_si_read_smc_sram_dword(adev,
4007                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4008                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
4009                                             &tmp, si_pi->sram_end);
4010         if (ret)
4011                 return ret;
4012
4013         si_pi->mc_reg_table_start = tmp;
4014
4015         ret = amdgpu_si_read_smc_sram_dword(adev,
4016                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4017                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
4018                                             &tmp, si_pi->sram_end);
4019         if (ret)
4020                 return ret;
4021
4022         si_pi->fan_table_start = tmp;
4023
4024         ret = amdgpu_si_read_smc_sram_dword(adev,
4025                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4026                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
4027                                             &tmp, si_pi->sram_end);
4028         if (ret)
4029                 return ret;
4030
4031         si_pi->arb_table_start = tmp;
4032
4033         ret = amdgpu_si_read_smc_sram_dword(adev,
4034                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4035                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4036                                             &tmp, si_pi->sram_end);
4037         if (ret)
4038                 return ret;
4039
4040         si_pi->cac_table_start = tmp;
4041
4042         ret = amdgpu_si_read_smc_sram_dword(adev,
4043                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4044                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4045                                             &tmp, si_pi->sram_end);
4046         if (ret)
4047                 return ret;
4048
4049         si_pi->dte_table_start = tmp;
4050
4051         ret = amdgpu_si_read_smc_sram_dword(adev,
4052                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4053                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4054                                             &tmp, si_pi->sram_end);
4055         if (ret)
4056                 return ret;
4057
4058         si_pi->spll_table_start = tmp;
4059
4060         ret = amdgpu_si_read_smc_sram_dword(adev,
4061                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4062                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4063                                             &tmp, si_pi->sram_end);
4064         if (ret)
4065                 return ret;
4066
4067         si_pi->papm_cfg_table_start = tmp;
4068
4069         return ret;
4070 }
4071
4072 static void si_read_clock_registers(struct amdgpu_device *adev)
4073 {
4074         struct si_power_info *si_pi = si_get_pi(adev);
4075
4076         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4077         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4078         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4079         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4080         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4081         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4082         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4083         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4084         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4085         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4086         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4087         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4088         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4089         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4090         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4091 }
4092
4093 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4094                                           bool enable)
4095 {
4096         if (enable)
4097                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4098         else
4099                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4100 }
4101
4102 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4103 {
4104         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4105 }
4106
4107 #if 0
4108 static int si_enter_ulp_state(struct amdgpu_device *adev)
4109 {
4110         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4111
4112         udelay(25000);
4113
4114         return 0;
4115 }
4116
4117 static int si_exit_ulp_state(struct amdgpu_device *adev)
4118 {
4119         int i;
4120
4121         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4122
4123         udelay(7000);
4124
4125         for (i = 0; i < adev->usec_timeout; i++) {
4126                 if (RREG32(SMC_RESP_0) == 1)
4127                         break;
4128                 udelay(1000);
4129         }
4130
4131         return 0;
4132 }
4133 #endif
4134
4135 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4136                                      bool has_display)
4137 {
4138         PPSMC_Msg msg = has_display ?
4139                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4140
4141         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4142                 0 : -EINVAL;
4143 }
4144
4145 static void si_program_response_times(struct amdgpu_device *adev)
4146 {
4147         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4148         u32 vddc_dly, acpi_dly, vbi_dly;
4149         u32 reference_clock;
4150
4151         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4152
4153         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4154         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4155
4156         if (voltage_response_time == 0)
4157                 voltage_response_time = 1000;
4158
4159         acpi_delay_time = 15000;
4160         vbi_time_out = 100000;
4161
4162         reference_clock = amdgpu_asic_get_xclk(adev);
4163
4164         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4165         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4166         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4167
4168         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4169         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4170         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4171         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4172 }
4173
4174 static void si_program_ds_registers(struct amdgpu_device *adev)
4175 {
4176         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4177         u32 tmp;
4178
4179         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4180         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4181                 tmp = 0x10;
4182         else
4183                 tmp = 0x1;
4184
4185         if (eg_pi->sclk_deep_sleep) {
4186                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4187                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4188                          ~AUTOSCALE_ON_SS_CLEAR);
4189         }
4190 }
4191
4192 static void si_program_display_gap(struct amdgpu_device *adev)
4193 {
4194         u32 tmp, pipe;
4195         int i;
4196
4197         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4198         if (adev->pm.dpm.new_active_crtc_count > 0)
4199                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4200         else
4201                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4202
4203         if (adev->pm.dpm.new_active_crtc_count > 1)
4204                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4205         else
4206                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4207
4208         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4209
4210         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4211         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4212
4213         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4214             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4215                 /* find the first active crtc */
4216                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4217                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4218                                 break;
4219                 }
4220                 if (i == adev->mode_info.num_crtc)
4221                         pipe = 0;
4222                 else
4223                         pipe = i;
4224
4225                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4226                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4227                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4228         }
4229
4230         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4231          * This can be a problem on PowerXpress systems or if you want to use the card
4232          * for offscreen rendering or compute if there are no crtcs enabled.
4233          */
4234         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4235 }
4236
4237 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4238 {
4239         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4240
4241         if (enable) {
4242                 if (pi->sclk_ss)
4243                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4244         } else {
4245                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4246                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4247         }
4248 }
4249
4250 static void si_setup_bsp(struct amdgpu_device *adev)
4251 {
4252         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4253         u32 xclk = amdgpu_asic_get_xclk(adev);
4254
4255         r600_calculate_u_and_p(pi->asi,
4256                                xclk,
4257                                16,
4258                                &pi->bsp,
4259                                &pi->bsu);
4260
4261         r600_calculate_u_and_p(pi->pasi,
4262                                xclk,
4263                                16,
4264                                &pi->pbsp,
4265                                &pi->pbsu);
4266
4267
4268         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4269         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4270
4271         WREG32(CG_BSP, pi->dsp);
4272 }
4273
4274 static void si_program_git(struct amdgpu_device *adev)
4275 {
4276         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4277 }
4278
4279 static void si_program_tp(struct amdgpu_device *adev)
4280 {
4281         int i;
4282         enum r600_td td = R600_TD_DFLT;
4283
4284         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4285                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4286
4287         if (td == R600_TD_AUTO)
4288                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4289         else
4290                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4291
4292         if (td == R600_TD_UP)
4293                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4294
4295         if (td == R600_TD_DOWN)
4296                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4297 }
4298
4299 static void si_program_tpp(struct amdgpu_device *adev)
4300 {
4301         WREG32(CG_TPC, R600_TPC_DFLT);
4302 }
4303
4304 static void si_program_sstp(struct amdgpu_device *adev)
4305 {
4306         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4307 }
4308
4309 static void si_enable_display_gap(struct amdgpu_device *adev)
4310 {
4311         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4312
4313         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4314         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4315                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4316
4317         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4318         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4319                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4320         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4321 }
4322
4323 static void si_program_vc(struct amdgpu_device *adev)
4324 {
4325         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4326
4327         WREG32(CG_FTV, pi->vrc);
4328 }
4329
4330 static void si_clear_vc(struct amdgpu_device *adev)
4331 {
4332         WREG32(CG_FTV, 0);
4333 }
4334
4335 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4336 {
4337         u8 mc_para_index;
4338
4339         if (memory_clock < 10000)
4340                 mc_para_index = 0;
4341         else if (memory_clock >= 80000)
4342                 mc_para_index = 0x0f;
4343         else
4344                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4345         return mc_para_index;
4346 }
4347
4348 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4349 {
4350         u8 mc_para_index;
4351
4352         if (strobe_mode) {
4353                 if (memory_clock < 12500)
4354                         mc_para_index = 0x00;
4355                 else if (memory_clock > 47500)
4356                         mc_para_index = 0x0f;
4357                 else
4358                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4359         } else {
4360                 if (memory_clock < 65000)
4361                         mc_para_index = 0x00;
4362                 else if (memory_clock > 135000)
4363                         mc_para_index = 0x0f;
4364                 else
4365                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4366         }
4367         return mc_para_index;
4368 }
4369
4370 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4371 {
4372         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4373         bool strobe_mode = false;
4374         u8 result = 0;
4375
4376         if (mclk <= pi->mclk_strobe_mode_threshold)
4377                 strobe_mode = true;
4378
4379         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4380                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4381         else
4382                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4383
4384         if (strobe_mode)
4385                 result |= SISLANDS_SMC_STROBE_ENABLE;
4386
4387         return result;
4388 }
4389
4390 static int si_upload_firmware(struct amdgpu_device *adev)
4391 {
4392         struct si_power_info *si_pi = si_get_pi(adev);
4393
4394         amdgpu_si_reset_smc(adev);
4395         amdgpu_si_smc_clock(adev, false);
4396
4397         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4398 }
4399
4400 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4401                                               const struct atom_voltage_table *table,
4402                                               const struct amdgpu_phase_shedding_limits_table *limits)
4403 {
4404         u32 data, num_bits, num_levels;
4405
4406         if ((table == NULL) || (limits == NULL))
4407                 return false;
4408
4409         data = table->mask_low;
4410
4411         num_bits = hweight32(data);
4412
4413         if (num_bits == 0)
4414                 return false;
4415
4416         num_levels = (1 << num_bits);
4417
4418         if (table->count != num_levels)
4419                 return false;
4420
4421         if (limits->count != (num_levels - 1))
4422                 return false;
4423
4424         return true;
4425 }
4426
4427 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4428                                               u32 max_voltage_steps,
4429                                               struct atom_voltage_table *voltage_table)
4430 {
4431         unsigned int i, diff;
4432
4433         if (voltage_table->count <= max_voltage_steps)
4434                 return;
4435
4436         diff = voltage_table->count - max_voltage_steps;
4437
4438         for (i= 0; i < max_voltage_steps; i++)
4439                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4440
4441         voltage_table->count = max_voltage_steps;
4442 }
4443
4444 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4445                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4446                                      struct atom_voltage_table *voltage_table)
4447 {
4448         u32 i;
4449
4450         if (voltage_dependency_table == NULL)
4451                 return -EINVAL;
4452
4453         voltage_table->mask_low = 0;
4454         voltage_table->phase_delay = 0;
4455
4456         voltage_table->count = voltage_dependency_table->count;
4457         for (i = 0; i < voltage_table->count; i++) {
4458                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4459                 voltage_table->entries[i].smio_low = 0;
4460         }
4461
4462         return 0;
4463 }
4464
4465 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4466 {
4467         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4468         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4469         struct si_power_info *si_pi = si_get_pi(adev);
4470         int ret;
4471
4472         if (pi->voltage_control) {
4473                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4474                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4475                 if (ret)
4476                         return ret;
4477
4478                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4479                         si_trim_voltage_table_to_fit_state_table(adev,
4480                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4481                                                                  &eg_pi->vddc_voltage_table);
4482         } else if (si_pi->voltage_control_svi2) {
4483                 ret = si_get_svi2_voltage_table(adev,
4484                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4485                                                 &eg_pi->vddc_voltage_table);
4486                 if (ret)
4487                         return ret;
4488         } else {
4489                 return -EINVAL;
4490         }
4491
4492         if (eg_pi->vddci_control) {
4493                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4494                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4495                 if (ret)
4496                         return ret;
4497
4498                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4499                         si_trim_voltage_table_to_fit_state_table(adev,
4500                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4501                                                                  &eg_pi->vddci_voltage_table);
4502         }
4503         if (si_pi->vddci_control_svi2) {
4504                 ret = si_get_svi2_voltage_table(adev,
4505                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4506                                                 &eg_pi->vddci_voltage_table);
4507                 if (ret)
4508                         return ret;
4509         }
4510
4511         if (pi->mvdd_control) {
4512                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4513                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4514
4515                 if (ret) {
4516                         pi->mvdd_control = false;
4517                         return ret;
4518                 }
4519
4520                 if (si_pi->mvdd_voltage_table.count == 0) {
4521                         pi->mvdd_control = false;
4522                         return -EINVAL;
4523                 }
4524
4525                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4526                         si_trim_voltage_table_to_fit_state_table(adev,
4527                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4528                                                                  &si_pi->mvdd_voltage_table);
4529         }
4530
4531         if (si_pi->vddc_phase_shed_control) {
4532                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4533                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4534                 if (ret)
4535                         si_pi->vddc_phase_shed_control = false;
4536
4537                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4538                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4539                         si_pi->vddc_phase_shed_control = false;
4540         }
4541
4542         return 0;
4543 }
4544
4545 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4546                                           const struct atom_voltage_table *voltage_table,
4547                                           SISLANDS_SMC_STATETABLE *table)
4548 {
4549         unsigned int i;
4550
4551         for (i = 0; i < voltage_table->count; i++)
4552                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4553 }
4554
4555 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4556                                           SISLANDS_SMC_STATETABLE *table)
4557 {
4558         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4559         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4560         struct si_power_info *si_pi = si_get_pi(adev);
4561         u8 i;
4562
4563         if (si_pi->voltage_control_svi2) {
4564                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4565                         si_pi->svc_gpio_id);
4566                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4567                         si_pi->svd_gpio_id);
4568                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4569                                            2);
4570         } else {
4571                 if (eg_pi->vddc_voltage_table.count) {
4572                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4573                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4574                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4575
4576                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4577                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4578                                         table->maxVDDCIndexInPPTable = i;
4579                                         break;
4580                                 }
4581                         }
4582                 }
4583
4584                 if (eg_pi->vddci_voltage_table.count) {
4585                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4586
4587                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4588                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4589                 }
4590
4591
4592                 if (si_pi->mvdd_voltage_table.count) {
4593                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4594
4595                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4596                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4597                 }
4598
4599                 if (si_pi->vddc_phase_shed_control) {
4600                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4601                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4602                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4603
4604                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4605                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4606
4607                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4608                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4609                         } else {
4610                                 si_pi->vddc_phase_shed_control = false;
4611                         }
4612                 }
4613         }
4614
4615         return 0;
4616 }
4617
4618 static int si_populate_voltage_value(struct amdgpu_device *adev,
4619                                      const struct atom_voltage_table *table,
4620                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4621 {
4622         unsigned int i;
4623
4624         for (i = 0; i < table->count; i++) {
4625                 if (value <= table->entries[i].value) {
4626                         voltage->index = (u8)i;
4627                         voltage->value = cpu_to_be16(table->entries[i].value);
4628                         break;
4629                 }
4630         }
4631
4632         if (i >= table->count)
4633                 return -EINVAL;
4634
4635         return 0;
4636 }
4637
4638 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4639                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4640 {
4641         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4642         struct si_power_info *si_pi = si_get_pi(adev);
4643
4644         if (pi->mvdd_control) {
4645                 if (mclk <= pi->mvdd_split_frequency)
4646                         voltage->index = 0;
4647                 else
4648                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4649
4650                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4651         }
4652         return 0;
4653 }
4654
4655 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4656                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4657                                     u16 *std_voltage)
4658 {
4659         u16 v_index;
4660         bool voltage_found = false;
4661         *std_voltage = be16_to_cpu(voltage->value);
4662
4663         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4664                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4665                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4666                                 return -EINVAL;
4667
4668                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4669                                 if (be16_to_cpu(voltage->value) ==
4670                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4671                                         voltage_found = true;
4672                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4673                                                 *std_voltage =
4674                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4675                                         else
4676                                                 *std_voltage =
4677                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4678                                         break;
4679                                 }
4680                         }
4681
4682                         if (!voltage_found) {
4683                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4684                                         if (be16_to_cpu(voltage->value) <=
4685                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4686                                                 voltage_found = true;
4687                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4688                                                         *std_voltage =
4689                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4690                                                 else
4691                                                         *std_voltage =
4692                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4693                                                 break;
4694                                         }
4695                                 }
4696                         }
4697                 } else {
4698                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4699                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4700                 }
4701         }
4702
4703         return 0;
4704 }
4705
4706 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4707                                          u16 value, u8 index,
4708                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4709 {
4710         voltage->index = index;
4711         voltage->value = cpu_to_be16(value);
4712
4713         return 0;
4714 }
4715
4716 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4717                                             const struct amdgpu_phase_shedding_limits_table *limits,
4718                                             u16 voltage, u32 sclk, u32 mclk,
4719                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4720 {
4721         unsigned int i;
4722
4723         for (i = 0; i < limits->count; i++) {
4724                 if ((voltage <= limits->entries[i].voltage) &&
4725                     (sclk <= limits->entries[i].sclk) &&
4726                     (mclk <= limits->entries[i].mclk))
4727                         break;
4728         }
4729
4730         smc_voltage->phase_settings = (u8)i;
4731
4732         return 0;
4733 }
4734
4735 static int si_init_arb_table_index(struct amdgpu_device *adev)
4736 {
4737         struct si_power_info *si_pi = si_get_pi(adev);
4738         u32 tmp;
4739         int ret;
4740
4741         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4742                                             &tmp, si_pi->sram_end);
4743         if (ret)
4744                 return ret;
4745
4746         tmp &= 0x00FFFFFF;
4747         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4748
4749         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4750                                               tmp, si_pi->sram_end);
4751 }
4752
4753 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4754 {
4755         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4756 }
4757
4758 static int si_reset_to_default(struct amdgpu_device *adev)
4759 {
4760         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4761                 0 : -EINVAL;
4762 }
4763
4764 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4765 {
4766         struct si_power_info *si_pi = si_get_pi(adev);
4767         u32 tmp;
4768         int ret;
4769
4770         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4771                                             &tmp, si_pi->sram_end);
4772         if (ret)
4773                 return ret;
4774
4775         tmp = (tmp >> 24) & 0xff;
4776
4777         if (tmp == MC_CG_ARB_FREQ_F0)
4778                 return 0;
4779
4780         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4781 }
4782
4783 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4784                                             u32 engine_clock)
4785 {
4786         u32 dram_rows;
4787         u32 dram_refresh_rate;
4788         u32 mc_arb_rfsh_rate;
4789         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4790
4791         if (tmp >= 4)
4792                 dram_rows = 16384;
4793         else
4794                 dram_rows = 1 << (tmp + 10);
4795
4796         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4797         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4798
4799         return mc_arb_rfsh_rate;
4800 }
4801
4802 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4803                                                 struct rv7xx_pl *pl,
4804                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4805 {
4806         u32 dram_timing;
4807         u32 dram_timing2;
4808         u32 burst_time;
4809
4810         arb_regs->mc_arb_rfsh_rate =
4811                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4812
4813         amdgpu_atombios_set_engine_dram_timings(adev,
4814                                             pl->sclk,
4815                                             pl->mclk);
4816
4817         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4818         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4819         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4820
4821         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4822         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4823         arb_regs->mc_arb_burst_time = (u8)burst_time;
4824
4825         return 0;
4826 }
4827
4828 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4829                                                   struct amdgpu_ps *amdgpu_state,
4830                                                   unsigned int first_arb_set)
4831 {
4832         struct si_power_info *si_pi = si_get_pi(adev);
4833         struct  si_ps *state = si_get_ps(amdgpu_state);
4834         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4835         int i, ret = 0;
4836
4837         for (i = 0; i < state->performance_level_count; i++) {
4838                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4839                 if (ret)
4840                         break;
4841                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4842                                                   si_pi->arb_table_start +
4843                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4844                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4845                                                   (u8 *)&arb_regs,
4846                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4847                                                   si_pi->sram_end);
4848                 if (ret)
4849                         break;
4850         }
4851
4852         return ret;
4853 }
4854
4855 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4856                                                struct amdgpu_ps *amdgpu_new_state)
4857 {
4858         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4859                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4860 }
4861
4862 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4863                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4864 {
4865         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4866         struct si_power_info *si_pi = si_get_pi(adev);
4867
4868         if (pi->mvdd_control)
4869                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4870                                                  si_pi->mvdd_bootup_value, voltage);
4871
4872         return 0;
4873 }
4874
4875 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4876                                          struct amdgpu_ps *amdgpu_initial_state,
4877                                          SISLANDS_SMC_STATETABLE *table)
4878 {
4879         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4880         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4881         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4882         struct si_power_info *si_pi = si_get_pi(adev);
4883         u32 reg;
4884         int ret;
4885
4886         table->initialState.levels[0].mclk.vDLL_CNTL =
4887                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4888         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4889                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4890         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4891                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4892         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4893                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4894         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4895                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4896         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4897                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4898         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4899                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4900         table->initialState.levels[0].mclk.vMPLL_SS =
4901                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4902         table->initialState.levels[0].mclk.vMPLL_SS2 =
4903                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4904
4905         table->initialState.levels[0].mclk.mclk_value =
4906                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4907
4908         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4909                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4910         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4911                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4912         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4913                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4914         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4915                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4916         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4917                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4918         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4919                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4920
4921         table->initialState.levels[0].sclk.sclk_value =
4922                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4923
4924         table->initialState.levels[0].arbRefreshState =
4925                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4926
4927         table->initialState.levels[0].ACIndex = 0;
4928
4929         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4930                                         initial_state->performance_levels[0].vddc,
4931                                         &table->initialState.levels[0].vddc);
4932
4933         if (!ret) {
4934                 u16 std_vddc;
4935
4936                 ret = si_get_std_voltage_value(adev,
4937                                                &table->initialState.levels[0].vddc,
4938                                                &std_vddc);
4939                 if (!ret)
4940                         si_populate_std_voltage_value(adev, std_vddc,
4941                                                       table->initialState.levels[0].vddc.index,
4942                                                       &table->initialState.levels[0].std_vddc);
4943         }
4944
4945         if (eg_pi->vddci_control)
4946                 si_populate_voltage_value(adev,
4947                                           &eg_pi->vddci_voltage_table,
4948                                           initial_state->performance_levels[0].vddci,
4949                                           &table->initialState.levels[0].vddci);
4950
4951         if (si_pi->vddc_phase_shed_control)
4952                 si_populate_phase_shedding_value(adev,
4953                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4954                                                  initial_state->performance_levels[0].vddc,
4955                                                  initial_state->performance_levels[0].sclk,
4956                                                  initial_state->performance_levels[0].mclk,
4957                                                  &table->initialState.levels[0].vddc);
4958
4959         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4960
4961         reg = CG_R(0xffff) | CG_L(0);
4962         table->initialState.levels[0].aT = cpu_to_be32(reg);
4963         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4964         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4965
4966         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4967                 table->initialState.levels[0].strobeMode =
4968                         si_get_strobe_mode_settings(adev,
4969                                                     initial_state->performance_levels[0].mclk);
4970
4971                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4972                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4973                 else
4974                         table->initialState.levels[0].mcFlags =  0;
4975         }
4976
4977         table->initialState.levelCount = 1;
4978
4979         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4980
4981         table->initialState.levels[0].dpm2.MaxPS = 0;
4982         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4983         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4984         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4985         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4986
4987         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4988         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4989
4990         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4991         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4992
4993         return 0;
4994 }
4995
4996 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4997                                       SISLANDS_SMC_STATETABLE *table)
4998 {
4999         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5000         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5001         struct si_power_info *si_pi = si_get_pi(adev);
5002         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5003         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5004         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5005         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5006         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5007         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5008         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5009         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5010         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5011         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5012         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5013         u32 reg;
5014         int ret;
5015
5016         table->ACPIState = table->initialState;
5017
5018         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
5019
5020         if (pi->acpi_vddc) {
5021                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5022                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
5023                 if (!ret) {
5024                         u16 std_vddc;
5025
5026                         ret = si_get_std_voltage_value(adev,
5027                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5028                         if (!ret)
5029                                 si_populate_std_voltage_value(adev, std_vddc,
5030                                                               table->ACPIState.levels[0].vddc.index,
5031                                                               &table->ACPIState.levels[0].std_vddc);
5032                 }
5033                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5034
5035                 if (si_pi->vddc_phase_shed_control) {
5036                         si_populate_phase_shedding_value(adev,
5037                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5038                                                          pi->acpi_vddc,
5039                                                          0,
5040                                                          0,
5041                                                          &table->ACPIState.levels[0].vddc);
5042                 }
5043         } else {
5044                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5045                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5046                 if (!ret) {
5047                         u16 std_vddc;
5048
5049                         ret = si_get_std_voltage_value(adev,
5050                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5051
5052                         if (!ret)
5053                                 si_populate_std_voltage_value(adev, std_vddc,
5054                                                               table->ACPIState.levels[0].vddc.index,
5055                                                               &table->ACPIState.levels[0].std_vddc);
5056                 }
5057                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5058                                                                                     si_pi->sys_pcie_mask,
5059                                                                                     si_pi->boot_pcie_gen,
5060                                                                                     AMDGPU_PCIE_GEN1);
5061
5062                 if (si_pi->vddc_phase_shed_control)
5063                         si_populate_phase_shedding_value(adev,
5064                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5065                                                          pi->min_vddc_in_table,
5066                                                          0,
5067                                                          0,
5068                                                          &table->ACPIState.levels[0].vddc);
5069         }
5070
5071         if (pi->acpi_vddc) {
5072                 if (eg_pi->acpi_vddci)
5073                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5074                                                   eg_pi->acpi_vddci,
5075                                                   &table->ACPIState.levels[0].vddci);
5076         }
5077
5078         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5079         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5080
5081         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5082
5083         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5084         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5085
5086         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5087                 cpu_to_be32(dll_cntl);
5088         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5089                 cpu_to_be32(mclk_pwrmgt_cntl);
5090         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5091                 cpu_to_be32(mpll_ad_func_cntl);
5092         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5093                 cpu_to_be32(mpll_dq_func_cntl);
5094         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5095                 cpu_to_be32(mpll_func_cntl);
5096         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5097                 cpu_to_be32(mpll_func_cntl_1);
5098         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5099                 cpu_to_be32(mpll_func_cntl_2);
5100         table->ACPIState.levels[0].mclk.vMPLL_SS =
5101                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5102         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5103                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5104
5105         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5106                 cpu_to_be32(spll_func_cntl);
5107         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5108                 cpu_to_be32(spll_func_cntl_2);
5109         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5110                 cpu_to_be32(spll_func_cntl_3);
5111         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5112                 cpu_to_be32(spll_func_cntl_4);
5113
5114         table->ACPIState.levels[0].mclk.mclk_value = 0;
5115         table->ACPIState.levels[0].sclk.sclk_value = 0;
5116
5117         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5118
5119         if (eg_pi->dynamic_ac_timing)
5120                 table->ACPIState.levels[0].ACIndex = 0;
5121
5122         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5123         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5124         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5125         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5126         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5127
5128         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5129         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5130
5131         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5132         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5133
5134         return 0;
5135 }
5136
5137 static int si_populate_ulv_state(struct amdgpu_device *adev,
5138                                  SISLANDS_SMC_SWSTATE *state)
5139 {
5140         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5141         struct si_power_info *si_pi = si_get_pi(adev);
5142         struct si_ulv_param *ulv = &si_pi->ulv;
5143         u32 sclk_in_sr = 1350; /* ??? */
5144         int ret;
5145
5146         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5147                                             &state->levels[0]);
5148         if (!ret) {
5149                 if (eg_pi->sclk_deep_sleep) {
5150                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5151                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5152                         else
5153                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5154                 }
5155                 if (ulv->one_pcie_lane_in_ulv)
5156                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5157                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5158                 state->levels[0].ACIndex = 1;
5159                 state->levels[0].std_vddc = state->levels[0].vddc;
5160                 state->levelCount = 1;
5161
5162                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5163         }
5164
5165         return ret;
5166 }
5167
5168 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5169 {
5170         struct si_power_info *si_pi = si_get_pi(adev);
5171         struct si_ulv_param *ulv = &si_pi->ulv;
5172         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5173         int ret;
5174
5175         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5176                                                    &arb_regs);
5177         if (ret)
5178                 return ret;
5179
5180         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5181                                    ulv->volt_change_delay);
5182
5183         ret = amdgpu_si_copy_bytes_to_smc(adev,
5184                                           si_pi->arb_table_start +
5185                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5186                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5187                                           (u8 *)&arb_regs,
5188                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5189                                           si_pi->sram_end);
5190
5191         return ret;
5192 }
5193
5194 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5195 {
5196         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5197
5198         pi->mvdd_split_frequency = 30000;
5199 }
5200
5201 static int si_init_smc_table(struct amdgpu_device *adev)
5202 {
5203         struct si_power_info *si_pi = si_get_pi(adev);
5204         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5205         const struct si_ulv_param *ulv = &si_pi->ulv;
5206         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5207         int ret;
5208         u32 lane_width;
5209         u32 vr_hot_gpio;
5210
5211         si_populate_smc_voltage_tables(adev, table);
5212
5213         switch (adev->pm.int_thermal_type) {
5214         case THERMAL_TYPE_SI:
5215         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5216                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5217                 break;
5218         case THERMAL_TYPE_NONE:
5219                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5220                 break;
5221         default:
5222                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5223                 break;
5224         }
5225
5226         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5227                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5228
5229         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5230                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5231                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5232         }
5233
5234         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5235                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5236
5237         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5238                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5239
5240         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5241                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5242
5243         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5244                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5245                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5246                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5247                                            vr_hot_gpio);
5248         }
5249
5250         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5251         if (ret)
5252                 return ret;
5253
5254         ret = si_populate_smc_acpi_state(adev, table);
5255         if (ret)
5256                 return ret;
5257
5258         table->driverState = table->initialState;
5259
5260         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5261                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5262         if (ret)
5263                 return ret;
5264
5265         if (ulv->supported && ulv->pl.vddc) {
5266                 ret = si_populate_ulv_state(adev, &table->ULVState);
5267                 if (ret)
5268                         return ret;
5269
5270                 ret = si_program_ulv_memory_timing_parameters(adev);
5271                 if (ret)
5272                         return ret;
5273
5274                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5275                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5276
5277                 lane_width = amdgpu_get_pcie_lanes(adev);
5278                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5279         } else {
5280                 table->ULVState = table->initialState;
5281         }
5282
5283         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5284                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5285                                            si_pi->sram_end);
5286 }
5287
5288 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5289                                     u32 engine_clock,
5290                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5291 {
5292         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5293         struct si_power_info *si_pi = si_get_pi(adev);
5294         struct atom_clock_dividers dividers;
5295         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5296         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5297         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5298         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5299         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5300         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5301         u64 tmp;
5302         u32 reference_clock = adev->clock.spll.reference_freq;
5303         u32 reference_divider;
5304         u32 fbdiv;
5305         int ret;
5306
5307         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5308                                              engine_clock, false, &dividers);
5309         if (ret)
5310                 return ret;
5311
5312         reference_divider = 1 + dividers.ref_div;
5313
5314         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5315         do_div(tmp, reference_clock);
5316         fbdiv = (u32) tmp;
5317
5318         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5319         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5320         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5321
5322         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5323         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5324
5325         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5326         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5327         spll_func_cntl_3 |= SPLL_DITHEN;
5328
5329         if (pi->sclk_ss) {
5330                 struct amdgpu_atom_ss ss;
5331                 u32 vco_freq = engine_clock * dividers.post_div;
5332
5333                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5334                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5335                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5336                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5337
5338                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5339                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5340                         cg_spll_spread_spectrum |= SSEN;
5341
5342                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5343                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5344                 }
5345         }
5346
5347         sclk->sclk_value = engine_clock;
5348         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5349         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5350         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5351         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5352         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5353         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5354
5355         return 0;
5356 }
5357
5358 static int si_populate_sclk_value(struct amdgpu_device *adev,
5359                                   u32 engine_clock,
5360                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5361 {
5362         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5363         int ret;
5364
5365         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5366         if (!ret) {
5367                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5368                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5369                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5370                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5371                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5372                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5373                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5374         }
5375
5376         return ret;
5377 }
5378
5379 static int si_populate_mclk_value(struct amdgpu_device *adev,
5380                                   u32 engine_clock,
5381                                   u32 memory_clock,
5382                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5383                                   bool strobe_mode,
5384                                   bool dll_state_on)
5385 {
5386         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5387         struct si_power_info *si_pi = si_get_pi(adev);
5388         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5389         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5390         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5391         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5392         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5393         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5394         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5395         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5396         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5397         struct atom_mpll_param mpll_param;
5398         int ret;
5399
5400         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5401         if (ret)
5402                 return ret;
5403
5404         mpll_func_cntl &= ~BWCTRL_MASK;
5405         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5406
5407         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5408         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5409                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5410
5411         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5412         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5413
5414         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5415                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5416                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5417                         YCLK_POST_DIV(mpll_param.post_div);
5418         }
5419
5420         if (pi->mclk_ss) {
5421                 struct amdgpu_atom_ss ss;
5422                 u32 freq_nom;
5423                 u32 tmp;
5424                 u32 reference_clock = adev->clock.mpll.reference_freq;
5425
5426                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5427                         freq_nom = memory_clock * 4;
5428                 else
5429                         freq_nom = memory_clock * 2;
5430
5431                 tmp = freq_nom / reference_clock;
5432                 tmp = tmp * tmp;
5433                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5434                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5435                         u32 clks = reference_clock * 5 / ss.rate;
5436                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5437
5438                         mpll_ss1 &= ~CLKV_MASK;
5439                         mpll_ss1 |= CLKV(clkv);
5440
5441                         mpll_ss2 &= ~CLKS_MASK;
5442                         mpll_ss2 |= CLKS(clks);
5443                 }
5444         }
5445
5446         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5447         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5448
5449         if (dll_state_on)
5450                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5451         else
5452                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5453
5454         mclk->mclk_value = cpu_to_be32(memory_clock);
5455         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5456         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5457         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5458         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5459         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5460         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5461         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5462         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5463         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5464
5465         return 0;
5466 }
5467
5468 static void si_populate_smc_sp(struct amdgpu_device *adev,
5469                                struct amdgpu_ps *amdgpu_state,
5470                                SISLANDS_SMC_SWSTATE *smc_state)
5471 {
5472         struct  si_ps *ps = si_get_ps(amdgpu_state);
5473         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5474         int i;
5475
5476         for (i = 0; i < ps->performance_level_count - 1; i++)
5477                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5478
5479         smc_state->levels[ps->performance_level_count - 1].bSP =
5480                 cpu_to_be32(pi->psp);
5481 }
5482
5483 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5484                                          struct rv7xx_pl *pl,
5485                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5486 {
5487         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5488         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5489         struct si_power_info *si_pi = si_get_pi(adev);
5490         int ret;
5491         bool dll_state_on;
5492         u16 std_vddc;
5493         bool gmc_pg = false;
5494
5495         if (eg_pi->pcie_performance_request &&
5496             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5497                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5498         else
5499                 level->gen2PCIE = (u8)pl->pcie_gen;
5500
5501         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5502         if (ret)
5503                 return ret;
5504
5505         level->mcFlags =  0;
5506
5507         if (pi->mclk_stutter_mode_threshold &&
5508             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5509             !eg_pi->uvd_enabled &&
5510             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5511             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5512                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5513
5514                 if (gmc_pg)
5515                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5516         }
5517
5518         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5519                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5520                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5521
5522                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5523                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5524
5525                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5526
5527                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5528                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5529                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5530                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5531                         else
5532                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5533                 } else {
5534                         dll_state_on = false;
5535                 }
5536         } else {
5537                 level->strobeMode = si_get_strobe_mode_settings(adev,
5538                                                                 pl->mclk);
5539
5540                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5541         }
5542
5543         ret = si_populate_mclk_value(adev,
5544                                      pl->sclk,
5545                                      pl->mclk,
5546                                      &level->mclk,
5547                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5548         if (ret)
5549                 return ret;
5550
5551         ret = si_populate_voltage_value(adev,
5552                                         &eg_pi->vddc_voltage_table,
5553                                         pl->vddc, &level->vddc);
5554         if (ret)
5555                 return ret;
5556
5557
5558         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5559         if (ret)
5560                 return ret;
5561
5562         ret = si_populate_std_voltage_value(adev, std_vddc,
5563                                             level->vddc.index, &level->std_vddc);
5564         if (ret)
5565                 return ret;
5566
5567         if (eg_pi->vddci_control) {
5568                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5569                                                 pl->vddci, &level->vddci);
5570                 if (ret)
5571                         return ret;
5572         }
5573
5574         if (si_pi->vddc_phase_shed_control) {
5575                 ret = si_populate_phase_shedding_value(adev,
5576                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5577                                                        pl->vddc,
5578                                                        pl->sclk,
5579                                                        pl->mclk,
5580                                                        &level->vddc);
5581                 if (ret)
5582                         return ret;
5583         }
5584
5585         level->MaxPoweredUpCU = si_pi->max_cu;
5586
5587         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5588
5589         return ret;
5590 }
5591
5592 static int si_populate_smc_t(struct amdgpu_device *adev,
5593                              struct amdgpu_ps *amdgpu_state,
5594                              SISLANDS_SMC_SWSTATE *smc_state)
5595 {
5596         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5597         struct  si_ps *state = si_get_ps(amdgpu_state);
5598         u32 a_t;
5599         u32 t_l, t_h;
5600         u32 high_bsp;
5601         int i, ret;
5602
5603         if (state->performance_level_count >= 9)
5604                 return -EINVAL;
5605
5606         if (state->performance_level_count < 2) {
5607                 a_t = CG_R(0xffff) | CG_L(0);
5608                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5609                 return 0;
5610         }
5611
5612         smc_state->levels[0].aT = cpu_to_be32(0);
5613
5614         for (i = 0; i <= state->performance_level_count - 2; i++) {
5615                 ret = r600_calculate_at(
5616                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5617                         100 * R600_AH_DFLT,
5618                         state->performance_levels[i + 1].sclk,
5619                         state->performance_levels[i].sclk,
5620                         &t_l,
5621                         &t_h);
5622
5623                 if (ret) {
5624                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5625                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5626                 }
5627
5628                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5629                 a_t |= CG_R(t_l * pi->bsp / 20000);
5630                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5631
5632                 high_bsp = (i == state->performance_level_count - 2) ?
5633                         pi->pbsp : pi->bsp;
5634                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5635                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5636         }
5637
5638         return 0;
5639 }
5640
5641 static int si_disable_ulv(struct amdgpu_device *adev)
5642 {
5643         struct si_power_info *si_pi = si_get_pi(adev);
5644         struct si_ulv_param *ulv = &si_pi->ulv;
5645
5646         if (ulv->supported)
5647                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5648                         0 : -EINVAL;
5649
5650         return 0;
5651 }
5652
5653 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5654                                        struct amdgpu_ps *amdgpu_state)
5655 {
5656         const struct si_power_info *si_pi = si_get_pi(adev);
5657         const struct si_ulv_param *ulv = &si_pi->ulv;
5658         const struct  si_ps *state = si_get_ps(amdgpu_state);
5659         int i;
5660
5661         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5662                 return false;
5663
5664         /* XXX validate against display requirements! */
5665
5666         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5667                 if (adev->clock.current_dispclk <=
5668                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5669                         if (ulv->pl.vddc <
5670                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5671                                 return false;
5672                 }
5673         }
5674
5675         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5676                 return false;
5677
5678         return true;
5679 }
5680
5681 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5682                                                        struct amdgpu_ps *amdgpu_new_state)
5683 {
5684         const struct si_power_info *si_pi = si_get_pi(adev);
5685         const struct si_ulv_param *ulv = &si_pi->ulv;
5686
5687         if (ulv->supported) {
5688                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5689                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5690                                 0 : -EINVAL;
5691         }
5692         return 0;
5693 }
5694
5695 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5696                                          struct amdgpu_ps *amdgpu_state,
5697                                          SISLANDS_SMC_SWSTATE *smc_state)
5698 {
5699         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5700         struct ni_power_info *ni_pi = ni_get_pi(adev);
5701         struct si_power_info *si_pi = si_get_pi(adev);
5702         struct  si_ps *state = si_get_ps(amdgpu_state);
5703         int i, ret;
5704         u32 threshold;
5705         u32 sclk_in_sr = 1350; /* ??? */
5706
5707         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5708                 return -EINVAL;
5709
5710         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5711
5712         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5713                 eg_pi->uvd_enabled = true;
5714                 if (eg_pi->smu_uvd_hs)
5715                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5716         } else {
5717                 eg_pi->uvd_enabled = false;
5718         }
5719
5720         if (state->dc_compatible)
5721                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5722
5723         smc_state->levelCount = 0;
5724         for (i = 0; i < state->performance_level_count; i++) {
5725                 if (eg_pi->sclk_deep_sleep) {
5726                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5727                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5728                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5729                                 else
5730                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5731                         }
5732                 }
5733
5734                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5735                                                     &smc_state->levels[i]);
5736                 smc_state->levels[i].arbRefreshState =
5737                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5738
5739                 if (ret)
5740                         return ret;
5741
5742                 if (ni_pi->enable_power_containment)
5743                         smc_state->levels[i].displayWatermark =
5744                                 (state->performance_levels[i].sclk < threshold) ?
5745                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5746                 else
5747                         smc_state->levels[i].displayWatermark = (i < 2) ?
5748                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5749
5750                 if (eg_pi->dynamic_ac_timing)
5751                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5752                 else
5753                         smc_state->levels[i].ACIndex = 0;
5754
5755                 smc_state->levelCount++;
5756         }
5757
5758         si_write_smc_soft_register(adev,
5759                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5760                                    threshold / 512);
5761
5762         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5763
5764         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5765         if (ret)
5766                 ni_pi->enable_power_containment = false;
5767
5768         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5769         if (ret)
5770                 ni_pi->enable_sq_ramping = false;
5771
5772         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5773 }
5774
5775 static int si_upload_sw_state(struct amdgpu_device *adev,
5776                               struct amdgpu_ps *amdgpu_new_state)
5777 {
5778         struct si_power_info *si_pi = si_get_pi(adev);
5779         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5780         int ret;
5781         u32 address = si_pi->state_table_start +
5782                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5783         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5784                 ((new_state->performance_level_count - 1) *
5785                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5786         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5787
5788         memset(smc_state, 0, state_size);
5789
5790         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5791         if (ret)
5792                 return ret;
5793
5794         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5795                                            state_size, si_pi->sram_end);
5796 }
5797
5798 static int si_upload_ulv_state(struct amdgpu_device *adev)
5799 {
5800         struct si_power_info *si_pi = si_get_pi(adev);
5801         struct si_ulv_param *ulv = &si_pi->ulv;
5802         int ret = 0;
5803
5804         if (ulv->supported && ulv->pl.vddc) {
5805                 u32 address = si_pi->state_table_start +
5806                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5807                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5808                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5809
5810                 memset(smc_state, 0, state_size);
5811
5812                 ret = si_populate_ulv_state(adev, smc_state);
5813                 if (!ret)
5814                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5815                                                           state_size, si_pi->sram_end);
5816         }
5817
5818         return ret;
5819 }
5820
5821 static int si_upload_smc_data(struct amdgpu_device *adev)
5822 {
5823         struct amdgpu_crtc *amdgpu_crtc = NULL;
5824         int i;
5825
5826         if (adev->pm.dpm.new_active_crtc_count == 0)
5827                 return 0;
5828
5829         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5830                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5831                         amdgpu_crtc = adev->mode_info.crtcs[i];
5832                         break;
5833                 }
5834         }
5835
5836         if (amdgpu_crtc == NULL)
5837                 return 0;
5838
5839         if (amdgpu_crtc->line_time <= 0)
5840                 return 0;
5841
5842         if (si_write_smc_soft_register(adev,
5843                                        SI_SMC_SOFT_REGISTER_crtc_index,
5844                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5845                 return 0;
5846
5847         if (si_write_smc_soft_register(adev,
5848                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5849                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5850                 return 0;
5851
5852         if (si_write_smc_soft_register(adev,
5853                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5854                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5855                 return 0;
5856
5857         return 0;
5858 }
5859
5860 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5861                                        struct si_mc_reg_table *table)
5862 {
5863         u8 i, j, k;
5864         u32 temp_reg;
5865
5866         for (i = 0, j = table->last; i < table->last; i++) {
5867                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5868                         return -EINVAL;
5869                 switch (table->mc_reg_address[i].s1) {
5870                 case MC_SEQ_MISC1:
5871                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5872                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5873                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5874                         for (k = 0; k < table->num_entries; k++)
5875                                 table->mc_reg_table_entry[k].mc_data[j] =
5876                                         ((temp_reg & 0xffff0000)) |
5877                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5878                         j++;
5879                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5880                                 return -EINVAL;
5881
5882                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5883                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5884                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5885                         for (k = 0; k < table->num_entries; k++) {
5886                                 table->mc_reg_table_entry[k].mc_data[j] =
5887                                         (temp_reg & 0xffff0000) |
5888                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5889                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5890                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5891                         }
5892                         j++;
5893                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5894                                 return -EINVAL;
5895
5896                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5897                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5898                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5899                                 for (k = 0; k < table->num_entries; k++)
5900                                         table->mc_reg_table_entry[k].mc_data[j] =
5901                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5902                                 j++;
5903                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5904                                         return -EINVAL;
5905                         }
5906                         break;
5907                 case MC_SEQ_RESERVE_M:
5908                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5909                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5910                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5911                         for(k = 0; k < table->num_entries; k++)
5912                                 table->mc_reg_table_entry[k].mc_data[j] =
5913                                         (temp_reg & 0xffff0000) |
5914                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5915                         j++;
5916                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5917                                 return -EINVAL;
5918                         break;
5919                 default:
5920                         break;
5921                 }
5922         }
5923
5924         table->last = j;
5925
5926         return 0;
5927 }
5928
5929 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5930 {
5931         bool result = true;
5932         switch (in_reg) {
5933         case  MC_SEQ_RAS_TIMING:
5934                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5935                 break;
5936         case MC_SEQ_CAS_TIMING:
5937                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5938                 break;
5939         case MC_SEQ_MISC_TIMING:
5940                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5941                 break;
5942         case MC_SEQ_MISC_TIMING2:
5943                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5944                 break;
5945         case MC_SEQ_RD_CTL_D0:
5946                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5947                 break;
5948         case MC_SEQ_RD_CTL_D1:
5949                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5950                 break;
5951         case MC_SEQ_WR_CTL_D0:
5952                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5953                 break;
5954         case MC_SEQ_WR_CTL_D1:
5955                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5956                 break;
5957         case MC_PMG_CMD_EMRS:
5958                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5959                 break;
5960         case MC_PMG_CMD_MRS:
5961                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5962                 break;
5963         case MC_PMG_CMD_MRS1:
5964                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5965                 break;
5966         case MC_SEQ_PMG_TIMING:
5967                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5968                 break;
5969         case MC_PMG_CMD_MRS2:
5970                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5971                 break;
5972         case MC_SEQ_WR_CTL_2:
5973                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5974                 break;
5975         default:
5976                 result = false;
5977                 break;
5978         }
5979
5980         return result;
5981 }
5982
5983 static void si_set_valid_flag(struct si_mc_reg_table *table)
5984 {
5985         u8 i, j;
5986
5987         for (i = 0; i < table->last; i++) {
5988                 for (j = 1; j < table->num_entries; j++) {
5989                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5990                                 table->valid_flag |= 1 << i;
5991                                 break;
5992                         }
5993                 }
5994         }
5995 }
5996
5997 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5998 {
5999         u32 i;
6000         u16 address;
6001
6002         for (i = 0; i < table->last; i++)
6003                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
6004                         address : table->mc_reg_address[i].s1;
6005
6006 }
6007
6008 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
6009                                       struct si_mc_reg_table *si_table)
6010 {
6011         u8 i, j;
6012
6013         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6014                 return -EINVAL;
6015         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
6016                 return -EINVAL;
6017
6018         for (i = 0; i < table->last; i++)
6019                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
6020         si_table->last = table->last;
6021
6022         for (i = 0; i < table->num_entries; i++) {
6023                 si_table->mc_reg_table_entry[i].mclk_max =
6024                         table->mc_reg_table_entry[i].mclk_max;
6025                 for (j = 0; j < table->last; j++) {
6026                         si_table->mc_reg_table_entry[i].mc_data[j] =
6027                                 table->mc_reg_table_entry[i].mc_data[j];
6028                 }
6029         }
6030         si_table->num_entries = table->num_entries;
6031
6032         return 0;
6033 }
6034
6035 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6036 {
6037         struct si_power_info *si_pi = si_get_pi(adev);
6038         struct atom_mc_reg_table *table;
6039         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6040         u8 module_index = rv770_get_memory_module_index(adev);
6041         int ret;
6042
6043         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6044         if (!table)
6045                 return -ENOMEM;
6046
6047         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6048         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6049         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6050         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6051         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6052         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6053         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6054         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6055         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6056         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6057         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6058         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6059         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6060         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6061
6062         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6063         if (ret)
6064                 goto init_mc_done;
6065
6066         ret = si_copy_vbios_mc_reg_table(table, si_table);
6067         if (ret)
6068                 goto init_mc_done;
6069
6070         si_set_s0_mc_reg_index(si_table);
6071
6072         ret = si_set_mc_special_registers(adev, si_table);
6073         if (ret)
6074                 goto init_mc_done;
6075
6076         si_set_valid_flag(si_table);
6077
6078 init_mc_done:
6079         kfree(table);
6080
6081         return ret;
6082
6083 }
6084
6085 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6086                                          SMC_SIslands_MCRegisters *mc_reg_table)
6087 {
6088         struct si_power_info *si_pi = si_get_pi(adev);
6089         u32 i, j;
6090
6091         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6092                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6093                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6094                                 break;
6095                         mc_reg_table->address[i].s0 =
6096                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6097                         mc_reg_table->address[i].s1 =
6098                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6099                         i++;
6100                 }
6101         }
6102         mc_reg_table->last = (u8)i;
6103 }
6104
6105 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6106                                     SMC_SIslands_MCRegisterSet *data,
6107                                     u32 num_entries, u32 valid_flag)
6108 {
6109         u32 i, j;
6110
6111         for(i = 0, j = 0; j < num_entries; j++) {
6112                 if (valid_flag & (1 << j)) {
6113                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6114                         i++;
6115                 }
6116         }
6117 }
6118
6119 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6120                                                  struct rv7xx_pl *pl,
6121                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6122 {
6123         struct si_power_info *si_pi = si_get_pi(adev);
6124         u32 i = 0;
6125
6126         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6127                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6128                         break;
6129         }
6130
6131         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6132                 --i;
6133
6134         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6135                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6136                                 si_pi->mc_reg_table.valid_flag);
6137 }
6138
6139 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6140                                            struct amdgpu_ps *amdgpu_state,
6141                                            SMC_SIslands_MCRegisters *mc_reg_table)
6142 {
6143         struct si_ps *state = si_get_ps(amdgpu_state);
6144         int i;
6145
6146         for (i = 0; i < state->performance_level_count; i++) {
6147                 si_convert_mc_reg_table_entry_to_smc(adev,
6148                                                      &state->performance_levels[i],
6149                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6150         }
6151 }
6152
6153 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6154                                     struct amdgpu_ps *amdgpu_boot_state)
6155 {
6156         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6157         struct si_power_info *si_pi = si_get_pi(adev);
6158         struct si_ulv_param *ulv = &si_pi->ulv;
6159         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6160
6161         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6162
6163         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6164
6165         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6166
6167         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6168                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6169
6170         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6171                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6172                                 si_pi->mc_reg_table.last,
6173                                 si_pi->mc_reg_table.valid_flag);
6174
6175         if (ulv->supported && ulv->pl.vddc != 0)
6176                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6177                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6178         else
6179                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6180                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6181                                         si_pi->mc_reg_table.last,
6182                                         si_pi->mc_reg_table.valid_flag);
6183
6184         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6185
6186         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6187                                            (u8 *)smc_mc_reg_table,
6188                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6189 }
6190
6191 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6192                                   struct amdgpu_ps *amdgpu_new_state)
6193 {
6194         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6195         struct si_power_info *si_pi = si_get_pi(adev);
6196         u32 address = si_pi->mc_reg_table_start +
6197                 offsetof(SMC_SIslands_MCRegisters,
6198                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6199         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6200
6201         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6202
6203         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6204
6205         return amdgpu_si_copy_bytes_to_smc(adev, address,
6206                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6207                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6208                                            si_pi->sram_end);
6209 }
6210
6211 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6212 {
6213         if (enable)
6214                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6215         else
6216                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6217 }
6218
6219 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6220                                                       struct amdgpu_ps *amdgpu_state)
6221 {
6222         struct si_ps *state = si_get_ps(amdgpu_state);
6223         int i;
6224         u16 pcie_speed, max_speed = 0;
6225
6226         for (i = 0; i < state->performance_level_count; i++) {
6227                 pcie_speed = state->performance_levels[i].pcie_gen;
6228                 if (max_speed < pcie_speed)
6229                         max_speed = pcie_speed;
6230         }
6231         return max_speed;
6232 }
6233
6234 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6235 {
6236         u32 speed_cntl;
6237
6238         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6239         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6240
6241         return (u16)speed_cntl;
6242 }
6243
6244 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6245                                                              struct amdgpu_ps *amdgpu_new_state,
6246                                                              struct amdgpu_ps *amdgpu_current_state)
6247 {
6248         struct si_power_info *si_pi = si_get_pi(adev);
6249         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6250         enum amdgpu_pcie_gen current_link_speed;
6251
6252         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6253                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6254         else
6255                 current_link_speed = si_pi->force_pcie_gen;
6256
6257         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6258         si_pi->pspp_notify_required = false;
6259         if (target_link_speed > current_link_speed) {
6260                 switch (target_link_speed) {
6261 #if defined(CONFIG_ACPI)
6262                 case AMDGPU_PCIE_GEN3:
6263                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6264                                 break;
6265                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6266                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6267                                 break;
6268                 case AMDGPU_PCIE_GEN2:
6269                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6270                                 break;
6271 #endif
6272                 default:
6273                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6274                         break;
6275                 }
6276         } else {
6277                 if (target_link_speed < current_link_speed)
6278                         si_pi->pspp_notify_required = true;
6279         }
6280 }
6281
6282 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6283                                                            struct amdgpu_ps *amdgpu_new_state,
6284                                                            struct amdgpu_ps *amdgpu_current_state)
6285 {
6286         struct si_power_info *si_pi = si_get_pi(adev);
6287         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6288         u8 request;
6289
6290         if (si_pi->pspp_notify_required) {
6291                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6292                         request = PCIE_PERF_REQ_PECI_GEN3;
6293                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6294                         request = PCIE_PERF_REQ_PECI_GEN2;
6295                 else
6296                         request = PCIE_PERF_REQ_PECI_GEN1;
6297
6298                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6299                     (si_get_current_pcie_speed(adev) > 0))
6300                         return;
6301
6302 #if defined(CONFIG_ACPI)
6303                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6304 #endif
6305         }
6306 }
6307
6308 #if 0
6309 static int si_ds_request(struct amdgpu_device *adev,
6310                          bool ds_status_on, u32 count_write)
6311 {
6312         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6313
6314         if (eg_pi->sclk_deep_sleep) {
6315                 if (ds_status_on)
6316                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6317                                 PPSMC_Result_OK) ?
6318                                 0 : -EINVAL;
6319                 else
6320                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6321                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6322         }
6323         return 0;
6324 }
6325 #endif
6326
6327 static void si_set_max_cu_value(struct amdgpu_device *adev)
6328 {
6329         struct si_power_info *si_pi = si_get_pi(adev);
6330
6331         if (adev->asic_type == CHIP_VERDE) {
6332                 switch (adev->pdev->device) {
6333                 case 0x6820:
6334                 case 0x6825:
6335                 case 0x6821:
6336                 case 0x6823:
6337                 case 0x6827:
6338                         si_pi->max_cu = 10;
6339                         break;
6340                 case 0x682D:
6341                 case 0x6824:
6342                 case 0x682F:
6343                 case 0x6826:
6344                         si_pi->max_cu = 8;
6345                         break;
6346                 case 0x6828:
6347                 case 0x6830:
6348                 case 0x6831:
6349                 case 0x6838:
6350                 case 0x6839:
6351                 case 0x683D:
6352                         si_pi->max_cu = 10;
6353                         break;
6354                 case 0x683B:
6355                 case 0x683F:
6356                 case 0x6829:
6357                         si_pi->max_cu = 8;
6358                         break;
6359                 default:
6360                         si_pi->max_cu = 0;
6361                         break;
6362                 }
6363         } else {
6364                 si_pi->max_cu = 0;
6365         }
6366 }
6367
6368 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6369                                                              struct amdgpu_clock_voltage_dependency_table *table)
6370 {
6371         u32 i;
6372         int j;
6373         u16 leakage_voltage;
6374
6375         if (table) {
6376                 for (i = 0; i < table->count; i++) {
6377                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6378                                                                           table->entries[i].v,
6379                                                                           &leakage_voltage)) {
6380                         case 0:
6381                                 table->entries[i].v = leakage_voltage;
6382                                 break;
6383                         case -EAGAIN:
6384                                 return -EINVAL;
6385                         case -EINVAL:
6386                         default:
6387                                 break;
6388                         }
6389                 }
6390
6391                 for (j = (table->count - 2); j >= 0; j--) {
6392                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6393                                 table->entries[j].v : table->entries[j + 1].v;
6394                 }
6395         }
6396         return 0;
6397 }
6398
6399 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6400 {
6401         int ret = 0;
6402
6403         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6404                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6405         if (ret)
6406                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6407         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6408                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6409         if (ret)
6410                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6411         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6412                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6413         if (ret)
6414                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6415         return ret;
6416 }
6417
6418 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6419                                           struct amdgpu_ps *amdgpu_new_state,
6420                                           struct amdgpu_ps *amdgpu_current_state)
6421 {
6422         u32 lane_width;
6423         u32 new_lane_width =
6424                 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6425         u32 current_lane_width =
6426                 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6427
6428         if (new_lane_width != current_lane_width) {
6429                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6430                 lane_width = amdgpu_get_pcie_lanes(adev);
6431                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6432         }
6433 }
6434
6435 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6436 {
6437         si_read_clock_registers(adev);
6438         si_enable_acpi_power_management(adev);
6439 }
6440
6441 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6442                                    bool enable)
6443 {
6444         u32 thermal_int = RREG32(CG_THERMAL_INT);
6445
6446         if (enable) {
6447                 PPSMC_Result result;
6448
6449                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6450                 WREG32(CG_THERMAL_INT, thermal_int);
6451                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6452                 if (result != PPSMC_Result_OK) {
6453                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6454                         return -EINVAL;
6455                 }
6456         } else {
6457                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6458                 WREG32(CG_THERMAL_INT, thermal_int);
6459         }
6460
6461         return 0;
6462 }
6463
6464 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6465                                             int min_temp, int max_temp)
6466 {
6467         int low_temp = 0 * 1000;
6468         int high_temp = 255 * 1000;
6469
6470         if (low_temp < min_temp)
6471                 low_temp = min_temp;
6472         if (high_temp > max_temp)
6473                 high_temp = max_temp;
6474         if (high_temp < low_temp) {
6475                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6476                 return -EINVAL;
6477         }
6478
6479         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6480         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6481         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6482
6483         adev->pm.dpm.thermal.min_temp = low_temp;
6484         adev->pm.dpm.thermal.max_temp = high_temp;
6485
6486         return 0;
6487 }
6488
6489 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6490 {
6491         struct si_power_info *si_pi = si_get_pi(adev);
6492         u32 tmp;
6493
6494         if (si_pi->fan_ctrl_is_in_default_mode) {
6495                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6496                 si_pi->fan_ctrl_default_mode = tmp;
6497                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6498                 si_pi->t_min = tmp;
6499                 si_pi->fan_ctrl_is_in_default_mode = false;
6500         }
6501
6502         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6503         tmp |= TMIN(0);
6504         WREG32(CG_FDO_CTRL2, tmp);
6505
6506         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6507         tmp |= FDO_PWM_MODE(mode);
6508         WREG32(CG_FDO_CTRL2, tmp);
6509 }
6510
6511 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6512 {
6513         struct si_power_info *si_pi = si_get_pi(adev);
6514         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6515         u32 duty100;
6516         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6517         u16 fdo_min, slope1, slope2;
6518         u32 reference_clock, tmp;
6519         int ret;
6520         u64 tmp64;
6521
6522         if (!si_pi->fan_table_start) {
6523                 adev->pm.dpm.fan.ucode_fan_control = false;
6524                 return 0;
6525         }
6526
6527         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6528
6529         if (duty100 == 0) {
6530                 adev->pm.dpm.fan.ucode_fan_control = false;
6531                 return 0;
6532         }
6533
6534         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6535         do_div(tmp64, 10000);
6536         fdo_min = (u16)tmp64;
6537
6538         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6539         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6540
6541         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6542         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6543
6544         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6545         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6546
6547         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6548         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6549         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6550         fan_table.slope1 = cpu_to_be16(slope1);
6551         fan_table.slope2 = cpu_to_be16(slope2);
6552         fan_table.fdo_min = cpu_to_be16(fdo_min);
6553         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6554         fan_table.hys_up = cpu_to_be16(1);
6555         fan_table.hys_slope = cpu_to_be16(1);
6556         fan_table.temp_resp_lim = cpu_to_be16(5);
6557         reference_clock = amdgpu_asic_get_xclk(adev);
6558
6559         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6560                                                 reference_clock) / 1600);
6561         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6562
6563         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6564         fan_table.temp_src = (uint8_t)tmp;
6565
6566         ret = amdgpu_si_copy_bytes_to_smc(adev,
6567                                           si_pi->fan_table_start,
6568                                           (u8 *)(&fan_table),
6569                                           sizeof(fan_table),
6570                                           si_pi->sram_end);
6571
6572         if (ret) {
6573                 DRM_ERROR("Failed to load fan table to the SMC.");
6574                 adev->pm.dpm.fan.ucode_fan_control = false;
6575         }
6576
6577         return ret;
6578 }
6579
6580 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6581 {
6582         struct si_power_info *si_pi = si_get_pi(adev);
6583         PPSMC_Result ret;
6584
6585         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6586         if (ret == PPSMC_Result_OK) {
6587                 si_pi->fan_is_controlled_by_smc = true;
6588                 return 0;
6589         } else {
6590                 return -EINVAL;
6591         }
6592 }
6593
6594 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6595 {
6596         struct si_power_info *si_pi = si_get_pi(adev);
6597         PPSMC_Result ret;
6598
6599         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6600
6601         if (ret == PPSMC_Result_OK) {
6602                 si_pi->fan_is_controlled_by_smc = false;
6603                 return 0;
6604         } else {
6605                 return -EINVAL;
6606         }
6607 }
6608
6609 static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6610                                       u32 *speed)
6611 {
6612         u32 duty, duty100;
6613         u64 tmp64;
6614
6615         if (adev->pm.no_fan)
6616                 return -ENOENT;
6617
6618         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6619         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6620
6621         if (duty100 == 0)
6622                 return -EINVAL;
6623
6624         tmp64 = (u64)duty * 100;
6625         do_div(tmp64, duty100);
6626         *speed = (u32)tmp64;
6627
6628         if (*speed > 100)
6629                 *speed = 100;
6630
6631         return 0;
6632 }
6633
6634 static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6635                                       u32 speed)
6636 {
6637         struct si_power_info *si_pi = si_get_pi(adev);
6638         u32 tmp;
6639         u32 duty, duty100;
6640         u64 tmp64;
6641
6642         if (adev->pm.no_fan)
6643                 return -ENOENT;
6644
6645         if (si_pi->fan_is_controlled_by_smc)
6646                 return -EINVAL;
6647
6648         if (speed > 100)
6649                 return -EINVAL;
6650
6651         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6652
6653         if (duty100 == 0)
6654                 return -EINVAL;
6655
6656         tmp64 = (u64)speed * duty100;
6657         do_div(tmp64, 100);
6658         duty = (u32)tmp64;
6659
6660         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6661         tmp |= FDO_STATIC_DUTY(duty);
6662         WREG32(CG_FDO_CTRL0, tmp);
6663
6664         return 0;
6665 }
6666
6667 static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6668 {
6669         if (mode) {
6670                 /* stop auto-manage */
6671                 if (adev->pm.dpm.fan.ucode_fan_control)
6672                         si_fan_ctrl_stop_smc_fan_control(adev);
6673                 si_fan_ctrl_set_static_mode(adev, mode);
6674         } else {
6675                 /* restart auto-manage */
6676                 if (adev->pm.dpm.fan.ucode_fan_control)
6677                         si_thermal_start_smc_fan_control(adev);
6678                 else
6679                         si_fan_ctrl_set_default_mode(adev);
6680         }
6681 }
6682
6683 static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6684 {
6685         struct si_power_info *si_pi = si_get_pi(adev);
6686         u32 tmp;
6687
6688         if (si_pi->fan_is_controlled_by_smc)
6689                 return 0;
6690
6691         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6692         return (tmp >> FDO_PWM_MODE_SHIFT);
6693 }
6694
6695 #if 0
6696 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6697                                          u32 *speed)
6698 {
6699         u32 tach_period;
6700         u32 xclk = amdgpu_asic_get_xclk(adev);
6701
6702         if (adev->pm.no_fan)
6703                 return -ENOENT;
6704
6705         if (adev->pm.fan_pulses_per_revolution == 0)
6706                 return -ENOENT;
6707
6708         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6709         if (tach_period == 0)
6710                 return -ENOENT;
6711
6712         *speed = 60 * xclk * 10000 / tach_period;
6713
6714         return 0;
6715 }
6716
6717 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6718                                          u32 speed)
6719 {
6720         u32 tach_period, tmp;
6721         u32 xclk = amdgpu_asic_get_xclk(adev);
6722
6723         if (adev->pm.no_fan)
6724                 return -ENOENT;
6725
6726         if (adev->pm.fan_pulses_per_revolution == 0)
6727                 return -ENOENT;
6728
6729         if ((speed < adev->pm.fan_min_rpm) ||
6730             (speed > adev->pm.fan_max_rpm))
6731                 return -EINVAL;
6732
6733         if (adev->pm.dpm.fan.ucode_fan_control)
6734                 si_fan_ctrl_stop_smc_fan_control(adev);
6735
6736         tach_period = 60 * xclk * 10000 / (8 * speed);
6737         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6738         tmp |= TARGET_PERIOD(tach_period);
6739         WREG32(CG_TACH_CTRL, tmp);
6740
6741         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6742
6743         return 0;
6744 }
6745 #endif
6746
6747 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6748 {
6749         struct si_power_info *si_pi = si_get_pi(adev);
6750         u32 tmp;
6751
6752         if (!si_pi->fan_ctrl_is_in_default_mode) {
6753                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6754                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6755                 WREG32(CG_FDO_CTRL2, tmp);
6756
6757                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6758                 tmp |= TMIN(si_pi->t_min);
6759                 WREG32(CG_FDO_CTRL2, tmp);
6760                 si_pi->fan_ctrl_is_in_default_mode = true;
6761         }
6762 }
6763
6764 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6765 {
6766         if (adev->pm.dpm.fan.ucode_fan_control) {
6767                 si_fan_ctrl_start_smc_fan_control(adev);
6768                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6769         }
6770 }
6771
6772 static void si_thermal_initialize(struct amdgpu_device *adev)
6773 {
6774         u32 tmp;
6775
6776         if (adev->pm.fan_pulses_per_revolution) {
6777                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6778                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6779                 WREG32(CG_TACH_CTRL, tmp);
6780         }
6781
6782         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6783         tmp |= TACH_PWM_RESP_RATE(0x28);
6784         WREG32(CG_FDO_CTRL2, tmp);
6785 }
6786
6787 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6788 {
6789         int ret;
6790
6791         si_thermal_initialize(adev);
6792         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6793         if (ret)
6794                 return ret;
6795         ret = si_thermal_enable_alert(adev, true);
6796         if (ret)
6797                 return ret;
6798         if (adev->pm.dpm.fan.ucode_fan_control) {
6799                 ret = si_halt_smc(adev);
6800                 if (ret)
6801                         return ret;
6802                 ret = si_thermal_setup_fan_table(adev);
6803                 if (ret)
6804                         return ret;
6805                 ret = si_resume_smc(adev);
6806                 if (ret)
6807                         return ret;
6808                 si_thermal_start_smc_fan_control(adev);
6809         }
6810
6811         return 0;
6812 }
6813
6814 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6815 {
6816         if (!adev->pm.no_fan) {
6817                 si_fan_ctrl_set_default_mode(adev);
6818                 si_fan_ctrl_stop_smc_fan_control(adev);
6819         }
6820 }
6821
6822 static int si_dpm_enable(struct amdgpu_device *adev)
6823 {
6824         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6825         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6826         struct si_power_info *si_pi = si_get_pi(adev);
6827         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6828         int ret;
6829
6830         if (amdgpu_si_is_smc_running(adev))
6831                 return -EINVAL;
6832         if (pi->voltage_control || si_pi->voltage_control_svi2)
6833                 si_enable_voltage_control(adev, true);
6834         if (pi->mvdd_control)
6835                 si_get_mvdd_configuration(adev);
6836         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6837                 ret = si_construct_voltage_tables(adev);
6838                 if (ret) {
6839                         DRM_ERROR("si_construct_voltage_tables failed\n");
6840                         return ret;
6841                 }
6842         }
6843         if (eg_pi->dynamic_ac_timing) {
6844                 ret = si_initialize_mc_reg_table(adev);
6845                 if (ret)
6846                         eg_pi->dynamic_ac_timing = false;
6847         }
6848         if (pi->dynamic_ss)
6849                 si_enable_spread_spectrum(adev, true);
6850         if (pi->thermal_protection)
6851                 si_enable_thermal_protection(adev, true);
6852         si_setup_bsp(adev);
6853         si_program_git(adev);
6854         si_program_tp(adev);
6855         si_program_tpp(adev);
6856         si_program_sstp(adev);
6857         si_enable_display_gap(adev);
6858         si_program_vc(adev);
6859         ret = si_upload_firmware(adev);
6860         if (ret) {
6861                 DRM_ERROR("si_upload_firmware failed\n");
6862                 return ret;
6863         }
6864         ret = si_process_firmware_header(adev);
6865         if (ret) {
6866                 DRM_ERROR("si_process_firmware_header failed\n");
6867                 return ret;
6868         }
6869         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6870         if (ret) {
6871                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6872                 return ret;
6873         }
6874         ret = si_init_smc_table(adev);
6875         if (ret) {
6876                 DRM_ERROR("si_init_smc_table failed\n");
6877                 return ret;
6878         }
6879         ret = si_init_smc_spll_table(adev);
6880         if (ret) {
6881                 DRM_ERROR("si_init_smc_spll_table failed\n");
6882                 return ret;
6883         }
6884         ret = si_init_arb_table_index(adev);
6885         if (ret) {
6886                 DRM_ERROR("si_init_arb_table_index failed\n");
6887                 return ret;
6888         }
6889         if (eg_pi->dynamic_ac_timing) {
6890                 ret = si_populate_mc_reg_table(adev, boot_ps);
6891                 if (ret) {
6892                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6893                         return ret;
6894                 }
6895         }
6896         ret = si_initialize_smc_cac_tables(adev);
6897         if (ret) {
6898                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6899                 return ret;
6900         }
6901         ret = si_initialize_hardware_cac_manager(adev);
6902         if (ret) {
6903                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6904                 return ret;
6905         }
6906         ret = si_initialize_smc_dte_tables(adev);
6907         if (ret) {
6908                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6909                 return ret;
6910         }
6911         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6912         if (ret) {
6913                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6914                 return ret;
6915         }
6916         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6917         if (ret) {
6918                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6919                 return ret;
6920         }
6921         si_program_response_times(adev);
6922         si_program_ds_registers(adev);
6923         si_dpm_start_smc(adev);
6924         ret = si_notify_smc_display_change(adev, false);
6925         if (ret) {
6926                 DRM_ERROR("si_notify_smc_display_change failed\n");
6927                 return ret;
6928         }
6929         si_enable_sclk_control(adev, true);
6930         si_start_dpm(adev);
6931
6932         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6933         si_thermal_start_thermal_controller(adev);
6934         ni_update_current_ps(adev, boot_ps);
6935
6936         return 0;
6937 }
6938
6939 static int si_set_temperature_range(struct amdgpu_device *adev)
6940 {
6941         int ret;
6942
6943         ret = si_thermal_enable_alert(adev, false);
6944         if (ret)
6945                 return ret;
6946         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6947         if (ret)
6948                 return ret;
6949         ret = si_thermal_enable_alert(adev, true);
6950         if (ret)
6951                 return ret;
6952
6953         return ret;
6954 }
6955
6956 static void si_dpm_disable(struct amdgpu_device *adev)
6957 {
6958         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6959         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6960
6961         if (!amdgpu_si_is_smc_running(adev))
6962                 return;
6963         si_thermal_stop_thermal_controller(adev);
6964         si_disable_ulv(adev);
6965         si_clear_vc(adev);
6966         if (pi->thermal_protection)
6967                 si_enable_thermal_protection(adev, false);
6968         si_enable_power_containment(adev, boot_ps, false);
6969         si_enable_smc_cac(adev, boot_ps, false);
6970         si_enable_spread_spectrum(adev, false);
6971         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6972         si_stop_dpm(adev);
6973         si_reset_to_default(adev);
6974         si_dpm_stop_smc(adev);
6975         si_force_switch_to_arb_f0(adev);
6976
6977         ni_update_current_ps(adev, boot_ps);
6978 }
6979
6980 static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6981 {
6982         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6983         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6984         struct amdgpu_ps *new_ps = &requested_ps;
6985
6986         ni_update_requested_ps(adev, new_ps);
6987         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6988
6989         return 0;
6990 }
6991
6992 static int si_power_control_set_level(struct amdgpu_device *adev)
6993 {
6994         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6995         int ret;
6996
6997         ret = si_restrict_performance_levels_before_switch(adev);
6998         if (ret)
6999                 return ret;
7000         ret = si_halt_smc(adev);
7001         if (ret)
7002                 return ret;
7003         ret = si_populate_smc_tdp_limits(adev, new_ps);
7004         if (ret)
7005                 return ret;
7006         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
7007         if (ret)
7008                 return ret;
7009         ret = si_resume_smc(adev);
7010         if (ret)
7011                 return ret;
7012         ret = si_set_sw_state(adev);
7013         if (ret)
7014                 return ret;
7015         return 0;
7016 }
7017
7018 static int si_dpm_set_power_state(struct amdgpu_device *adev)
7019 {
7020         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7021         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7022         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7023         int ret;
7024
7025         ret = si_disable_ulv(adev);
7026         if (ret) {
7027                 DRM_ERROR("si_disable_ulv failed\n");
7028                 return ret;
7029         }
7030         ret = si_restrict_performance_levels_before_switch(adev);
7031         if (ret) {
7032                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7033                 return ret;
7034         }
7035         if (eg_pi->pcie_performance_request)
7036                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7037         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7038         ret = si_enable_power_containment(adev, new_ps, false);
7039         if (ret) {
7040                 DRM_ERROR("si_enable_power_containment failed\n");
7041                 return ret;
7042         }
7043         ret = si_enable_smc_cac(adev, new_ps, false);
7044         if (ret) {
7045                 DRM_ERROR("si_enable_smc_cac failed\n");
7046                 return ret;
7047         }
7048         ret = si_halt_smc(adev);
7049         if (ret) {
7050                 DRM_ERROR("si_halt_smc failed\n");
7051                 return ret;
7052         }
7053         ret = si_upload_sw_state(adev, new_ps);
7054         if (ret) {
7055                 DRM_ERROR("si_upload_sw_state failed\n");
7056                 return ret;
7057         }
7058         ret = si_upload_smc_data(adev);
7059         if (ret) {
7060                 DRM_ERROR("si_upload_smc_data failed\n");
7061                 return ret;
7062         }
7063         ret = si_upload_ulv_state(adev);
7064         if (ret) {
7065                 DRM_ERROR("si_upload_ulv_state failed\n");
7066                 return ret;
7067         }
7068         if (eg_pi->dynamic_ac_timing) {
7069                 ret = si_upload_mc_reg_table(adev, new_ps);
7070                 if (ret) {
7071                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7072                         return ret;
7073                 }
7074         }
7075         ret = si_program_memory_timing_parameters(adev, new_ps);
7076         if (ret) {
7077                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7078                 return ret;
7079         }
7080         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7081
7082         ret = si_resume_smc(adev);
7083         if (ret) {
7084                 DRM_ERROR("si_resume_smc failed\n");
7085                 return ret;
7086         }
7087         ret = si_set_sw_state(adev);
7088         if (ret) {
7089                 DRM_ERROR("si_set_sw_state failed\n");
7090                 return ret;
7091         }
7092         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7093         if (eg_pi->pcie_performance_request)
7094                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7095         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7096         if (ret) {
7097                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7098                 return ret;
7099         }
7100         ret = si_enable_smc_cac(adev, new_ps, true);
7101         if (ret) {
7102                 DRM_ERROR("si_enable_smc_cac failed\n");
7103                 return ret;
7104         }
7105         ret = si_enable_power_containment(adev, new_ps, true);
7106         if (ret) {
7107                 DRM_ERROR("si_enable_power_containment failed\n");
7108                 return ret;
7109         }
7110
7111         ret = si_power_control_set_level(adev);
7112         if (ret) {
7113                 DRM_ERROR("si_power_control_set_level failed\n");
7114                 return ret;
7115         }
7116
7117         return 0;
7118 }
7119
7120 static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7121 {
7122         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7123         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7124
7125         ni_update_current_ps(adev, new_ps);
7126 }
7127
7128 #if 0
7129 void si_dpm_reset_asic(struct amdgpu_device *adev)
7130 {
7131         si_restrict_performance_levels_before_switch(adev);
7132         si_disable_ulv(adev);
7133         si_set_boot_state(adev);
7134 }
7135 #endif
7136
7137 static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7138 {
7139         si_program_display_gap(adev);
7140 }
7141
7142
7143 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7144                                           struct amdgpu_ps *rps,
7145                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7146                                           u8 table_rev)
7147 {
7148         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7149         rps->class = le16_to_cpu(non_clock_info->usClassification);
7150         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7151
7152         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7153                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7154                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7155         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7156                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7157                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7158         } else {
7159                 rps->vclk = 0;
7160                 rps->dclk = 0;
7161         }
7162
7163         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7164                 adev->pm.dpm.boot_ps = rps;
7165         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7166                 adev->pm.dpm.uvd_ps = rps;
7167 }
7168
7169 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7170                                       struct amdgpu_ps *rps, int index,
7171                                       union pplib_clock_info *clock_info)
7172 {
7173         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7174         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7175         struct si_power_info *si_pi = si_get_pi(adev);
7176         struct  si_ps *ps = si_get_ps(rps);
7177         u16 leakage_voltage;
7178         struct rv7xx_pl *pl = &ps->performance_levels[index];
7179         int ret;
7180
7181         ps->performance_level_count = index + 1;
7182
7183         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7184         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7185         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7186         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7187
7188         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7189         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7190         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7191         pl->pcie_gen = r600_get_pcie_gen_support(adev,
7192                                                  si_pi->sys_pcie_mask,
7193                                                  si_pi->boot_pcie_gen,
7194                                                  clock_info->si.ucPCIEGen);
7195
7196         /* patch up vddc if necessary */
7197         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7198                                                         &leakage_voltage);
7199         if (ret == 0)
7200                 pl->vddc = leakage_voltage;
7201
7202         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7203                 pi->acpi_vddc = pl->vddc;
7204                 eg_pi->acpi_vddci = pl->vddci;
7205                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7206         }
7207
7208         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7209             index == 0) {
7210                 /* XXX disable for A0 tahiti */
7211                 si_pi->ulv.supported = false;
7212                 si_pi->ulv.pl = *pl;
7213                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7214                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7215                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7216                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7217         }
7218
7219         if (pi->min_vddc_in_table > pl->vddc)
7220                 pi->min_vddc_in_table = pl->vddc;
7221
7222         if (pi->max_vddc_in_table < pl->vddc)
7223                 pi->max_vddc_in_table = pl->vddc;
7224
7225         /* patch up boot state */
7226         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7227                 u16 vddc, vddci, mvdd;
7228                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7229                 pl->mclk = adev->clock.default_mclk;
7230                 pl->sclk = adev->clock.default_sclk;
7231                 pl->vddc = vddc;
7232                 pl->vddci = vddci;
7233                 si_pi->mvdd_bootup_value = mvdd;
7234         }
7235
7236         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7237             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7238                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7239                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7240                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7241                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7242         }
7243 }
7244
7245 union pplib_power_state {
7246         struct _ATOM_PPLIB_STATE v1;
7247         struct _ATOM_PPLIB_STATE_V2 v2;
7248 };
7249
7250 static int si_parse_power_table(struct amdgpu_device *adev)
7251 {
7252         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7253         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7254         union pplib_power_state *power_state;
7255         int i, j, k, non_clock_array_index, clock_array_index;
7256         union pplib_clock_info *clock_info;
7257         struct _StateArray *state_array;
7258         struct _ClockInfoArray *clock_info_array;
7259         struct _NonClockInfoArray *non_clock_info_array;
7260         union power_info *power_info;
7261         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7262         u16 data_offset;
7263         u8 frev, crev;
7264         u8 *power_state_offset;
7265         struct  si_ps *ps;
7266
7267         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7268                                    &frev, &crev, &data_offset))
7269                 return -EINVAL;
7270         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7271
7272         amdgpu_add_thermal_controller(adev);
7273
7274         state_array = (struct _StateArray *)
7275                 (mode_info->atom_context->bios + data_offset +
7276                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7277         clock_info_array = (struct _ClockInfoArray *)
7278                 (mode_info->atom_context->bios + data_offset +
7279                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7280         non_clock_info_array = (struct _NonClockInfoArray *)
7281                 (mode_info->atom_context->bios + data_offset +
7282                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7283
7284         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7285                                   state_array->ucNumEntries, GFP_KERNEL);
7286         if (!adev->pm.dpm.ps)
7287                 return -ENOMEM;
7288         power_state_offset = (u8 *)state_array->states;
7289         for (i = 0; i < state_array->ucNumEntries; i++) {
7290                 u8 *idx;
7291                 power_state = (union pplib_power_state *)power_state_offset;
7292                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7293                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7294                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7295                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7296                 if (ps == NULL) {
7297                         kfree(adev->pm.dpm.ps);
7298                         return -ENOMEM;
7299                 }
7300                 adev->pm.dpm.ps[i].ps_priv = ps;
7301                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7302                                               non_clock_info,
7303                                               non_clock_info_array->ucEntrySize);
7304                 k = 0;
7305                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7306                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7307                         clock_array_index = idx[j];
7308                         if (clock_array_index >= clock_info_array->ucNumEntries)
7309                                 continue;
7310                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7311                                 break;
7312                         clock_info = (union pplib_clock_info *)
7313                                 ((u8 *)&clock_info_array->clockInfo[0] +
7314                                  (clock_array_index * clock_info_array->ucEntrySize));
7315                         si_parse_pplib_clock_info(adev,
7316                                                   &adev->pm.dpm.ps[i], k,
7317                                                   clock_info);
7318                         k++;
7319                 }
7320                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7321         }
7322         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7323
7324         /* fill in the vce power states */
7325         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7326                 u32 sclk, mclk;
7327                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7328                 clock_info = (union pplib_clock_info *)
7329                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7330                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7331                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7332                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7333                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7334                 adev->pm.dpm.vce_states[i].sclk = sclk;
7335                 adev->pm.dpm.vce_states[i].mclk = mclk;
7336         }
7337
7338         return 0;
7339 }
7340
7341 static int si_dpm_init(struct amdgpu_device *adev)
7342 {
7343         struct rv7xx_power_info *pi;
7344         struct evergreen_power_info *eg_pi;
7345         struct ni_power_info *ni_pi;
7346         struct si_power_info *si_pi;
7347         struct atom_clock_dividers dividers;
7348         int ret;
7349         u32 mask;
7350
7351         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7352         if (si_pi == NULL)
7353                 return -ENOMEM;
7354         adev->pm.dpm.priv = si_pi;
7355         ni_pi = &si_pi->ni;
7356         eg_pi = &ni_pi->eg;
7357         pi = &eg_pi->rv7xx;
7358
7359         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7360         if (ret)
7361                 si_pi->sys_pcie_mask = 0;
7362         else
7363                 si_pi->sys_pcie_mask = mask;
7364         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7365         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7366
7367         si_set_max_cu_value(adev);
7368
7369         rv770_get_max_vddc(adev);
7370         si_get_leakage_vddc(adev);
7371         si_patch_dependency_tables_based_on_leakage(adev);
7372
7373         pi->acpi_vddc = 0;
7374         eg_pi->acpi_vddci = 0;
7375         pi->min_vddc_in_table = 0;
7376         pi->max_vddc_in_table = 0;
7377
7378         ret = amdgpu_get_platform_caps(adev);
7379         if (ret)
7380                 return ret;
7381
7382         ret = amdgpu_parse_extended_power_table(adev);
7383         if (ret)
7384                 return ret;
7385
7386         ret = si_parse_power_table(adev);
7387         if (ret)
7388                 return ret;
7389
7390         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7391                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7392         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7393                 amdgpu_free_extended_power_table(adev);
7394                 return -ENOMEM;
7395         }
7396         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7397         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7398         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7399         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7400         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7401         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7402         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7403         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7404         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7405
7406         if (adev->pm.dpm.voltage_response_time == 0)
7407                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7408         if (adev->pm.dpm.backbias_response_time == 0)
7409                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7410
7411         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7412                                              0, false, &dividers);
7413         if (ret)
7414                 pi->ref_div = dividers.ref_div + 1;
7415         else
7416                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7417
7418         eg_pi->smu_uvd_hs = false;
7419
7420         pi->mclk_strobe_mode_threshold = 40000;
7421         if (si_is_special_1gb_platform(adev))
7422                 pi->mclk_stutter_mode_threshold = 0;
7423         else
7424                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7425         pi->mclk_edc_enable_threshold = 40000;
7426         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7427
7428         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7429
7430         pi->voltage_control =
7431                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7432                                             VOLTAGE_OBJ_GPIO_LUT);
7433         if (!pi->voltage_control) {
7434                 si_pi->voltage_control_svi2 =
7435                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7436                                                     VOLTAGE_OBJ_SVID2);
7437                 if (si_pi->voltage_control_svi2)
7438                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7439                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7440         }
7441
7442         pi->mvdd_control =
7443                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7444                                             VOLTAGE_OBJ_GPIO_LUT);
7445
7446         eg_pi->vddci_control =
7447                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7448                                             VOLTAGE_OBJ_GPIO_LUT);
7449         if (!eg_pi->vddci_control)
7450                 si_pi->vddci_control_svi2 =
7451                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7452                                                     VOLTAGE_OBJ_SVID2);
7453
7454         si_pi->vddc_phase_shed_control =
7455                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7456                                             VOLTAGE_OBJ_PHASE_LUT);
7457
7458         rv770_get_engine_memory_ss(adev);
7459
7460         pi->asi = RV770_ASI_DFLT;
7461         pi->pasi = CYPRESS_HASI_DFLT;
7462         pi->vrc = SISLANDS_VRC_DFLT;
7463
7464         pi->gfx_clock_gating = true;
7465
7466         eg_pi->sclk_deep_sleep = true;
7467         si_pi->sclk_deep_sleep_above_low = false;
7468
7469         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7470                 pi->thermal_protection = true;
7471         else
7472                 pi->thermal_protection = false;
7473
7474         eg_pi->dynamic_ac_timing = true;
7475
7476         eg_pi->light_sleep = true;
7477 #if defined(CONFIG_ACPI)
7478         eg_pi->pcie_performance_request =
7479                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7480 #else
7481         eg_pi->pcie_performance_request = false;
7482 #endif
7483
7484         si_pi->sram_end = SMC_RAM_END;
7485
7486         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7487         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7488         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7489         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7490         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7491         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7492         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7493
7494         si_initialize_powertune_defaults(adev);
7495
7496         /* make sure dc limits are valid */
7497         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7498             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7499                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7500                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7501
7502         si_pi->fan_ctrl_is_in_default_mode = true;
7503
7504         return 0;
7505 }
7506
7507 static void si_dpm_fini(struct amdgpu_device *adev)
7508 {
7509         int i;
7510
7511         if (adev->pm.dpm.ps)
7512                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7513                         kfree(adev->pm.dpm.ps[i].ps_priv);
7514         kfree(adev->pm.dpm.ps);
7515         kfree(adev->pm.dpm.priv);
7516         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7517         amdgpu_free_extended_power_table(adev);
7518 }
7519
7520 static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7521                                                     struct seq_file *m)
7522 {
7523         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7524         struct amdgpu_ps *rps = &eg_pi->current_rps;
7525         struct  si_ps *ps = si_get_ps(rps);
7526         struct rv7xx_pl *pl;
7527         u32 current_index =
7528                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7529                 CURRENT_STATE_INDEX_SHIFT;
7530
7531         if (current_index >= ps->performance_level_count) {
7532                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7533         } else {
7534                 pl = &ps->performance_levels[current_index];
7535                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7536                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7537                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7538         }
7539 }
7540
7541 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7542                                       struct amdgpu_irq_src *source,
7543                                       unsigned type,
7544                                       enum amdgpu_interrupt_state state)
7545 {
7546         u32 cg_thermal_int;
7547
7548         switch (type) {
7549         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7550                 switch (state) {
7551                 case AMDGPU_IRQ_STATE_DISABLE:
7552                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7553                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7554                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7555                         break;
7556                 case AMDGPU_IRQ_STATE_ENABLE:
7557                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7558                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7559                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7560                         break;
7561                 default:
7562                         break;
7563                 }
7564                 break;
7565
7566         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7567                 switch (state) {
7568                 case AMDGPU_IRQ_STATE_DISABLE:
7569                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7570                         cg_thermal_int |= THERM_INT_MASK_LOW;
7571                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7572                         break;
7573                 case AMDGPU_IRQ_STATE_ENABLE:
7574                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7575                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7576                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7577                         break;
7578                 default:
7579                         break;
7580                 }
7581                 break;
7582
7583         default:
7584                 break;
7585         }
7586         return 0;
7587 }
7588
7589 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7590                                     struct amdgpu_irq_src *source,
7591                                     struct amdgpu_iv_entry *entry)
7592 {
7593         bool queue_thermal = false;
7594
7595         if (entry == NULL)
7596                 return -EINVAL;
7597
7598         switch (entry->src_id) {
7599         case 230: /* thermal low to high */
7600                 DRM_DEBUG("IH: thermal low to high\n");
7601                 adev->pm.dpm.thermal.high_to_low = false;
7602                 queue_thermal = true;
7603                 break;
7604         case 231: /* thermal high to low */
7605                 DRM_DEBUG("IH: thermal high to low\n");
7606                 adev->pm.dpm.thermal.high_to_low = true;
7607                 queue_thermal = true;
7608                 break;
7609         default:
7610                 break;
7611         }
7612
7613         if (queue_thermal)
7614                 schedule_work(&adev->pm.dpm.thermal.work);
7615
7616         return 0;
7617 }
7618
7619 static int si_dpm_late_init(void *handle)
7620 {
7621         int ret;
7622         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7623
7624         if (!amdgpu_dpm)
7625                 return 0;
7626
7627         /* init the sysfs and debugfs files late */
7628         ret = amdgpu_pm_sysfs_init(adev);
7629         if (ret)
7630                 return ret;
7631
7632         ret = si_set_temperature_range(adev);
7633         if (ret)
7634                 return ret;
7635 #if 0 //TODO ?
7636         si_dpm_powergate_uvd(adev, true);
7637 #endif
7638         return 0;
7639 }
7640
7641 /**
7642  * si_dpm_init_microcode - load ucode images from disk
7643  *
7644  * @adev: amdgpu_device pointer
7645  *
7646  * Use the firmware interface to load the ucode images into
7647  * the driver (not loaded into hw).
7648  * Returns 0 on success, error on failure.
7649  */
7650 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7651 {
7652         const char *chip_name;
7653         char fw_name[30];
7654         int err;
7655
7656         DRM_DEBUG("\n");
7657         switch (adev->asic_type) {
7658         case CHIP_TAHITI:
7659                 chip_name = "tahiti";
7660                 break;
7661         case CHIP_PITCAIRN:
7662                 if ((adev->pdev->revision == 0x81) ||
7663                     (adev->pdev->device == 0x6810) ||
7664                     (adev->pdev->device == 0x6811) ||
7665                     (adev->pdev->device == 0x6816) ||
7666                     (adev->pdev->device == 0x6817) ||
7667                     (adev->pdev->device == 0x6806))
7668                         chip_name = "pitcairn_k";
7669                 else
7670                         chip_name = "pitcairn";
7671                 break;
7672         case CHIP_VERDE:
7673                 if ((adev->pdev->revision == 0x81) ||
7674                     (adev->pdev->revision == 0x83) ||
7675                     (adev->pdev->revision == 0x87) ||
7676                     (adev->pdev->device == 0x6820) ||
7677                     (adev->pdev->device == 0x6821) ||
7678                     (adev->pdev->device == 0x6822) ||
7679                     (adev->pdev->device == 0x6823) ||
7680                     (adev->pdev->device == 0x682A) ||
7681                     (adev->pdev->device == 0x682B))
7682                         chip_name = "verde_k";
7683                 else
7684                         chip_name = "verde";
7685                 break;
7686         case CHIP_OLAND:
7687                 if ((adev->pdev->revision == 0xC7) ||
7688                     (adev->pdev->revision == 0x80) ||
7689                     (adev->pdev->revision == 0x81) ||
7690                     (adev->pdev->revision == 0x83) ||
7691                     (adev->pdev->device == 0x6604) ||
7692                     (adev->pdev->device == 0x6605))
7693                         chip_name = "oland_k";
7694                 else
7695                         chip_name = "oland";
7696                 break;
7697         case CHIP_HAINAN:
7698                 if ((adev->pdev->revision == 0x81) ||
7699                     (adev->pdev->revision == 0x83) ||
7700                     (adev->pdev->revision == 0xC3) ||
7701                     (adev->pdev->device == 0x6664) ||
7702                     (adev->pdev->device == 0x6665) ||
7703                     (adev->pdev->device == 0x6667))
7704                         chip_name = "hainan_k";
7705                 else
7706                         chip_name = "hainan";
7707                 break;
7708         default: BUG();
7709         }
7710
7711         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7712         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7713         if (err)
7714                 goto out;
7715         err = amdgpu_ucode_validate(adev->pm.fw);
7716
7717 out:
7718         if (err) {
7719                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7720                           err, fw_name);
7721                 release_firmware(adev->pm.fw);
7722                 adev->pm.fw = NULL;
7723         }
7724         return err;
7725
7726 }
7727
7728 static int si_dpm_sw_init(void *handle)
7729 {
7730         int ret;
7731         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7732
7733         ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7734         if (ret)
7735                 return ret;
7736
7737         ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7738         if (ret)
7739                 return ret;
7740
7741         /* default to balanced state */
7742         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7743         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7744         adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
7745         adev->pm.default_sclk = adev->clock.default_sclk;
7746         adev->pm.default_mclk = adev->clock.default_mclk;
7747         adev->pm.current_sclk = adev->clock.default_sclk;
7748         adev->pm.current_mclk = adev->clock.default_mclk;
7749         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7750
7751         if (amdgpu_dpm == 0)
7752                 return 0;
7753
7754         ret = si_dpm_init_microcode(adev);
7755         if (ret)
7756                 return ret;
7757
7758         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7759         mutex_lock(&adev->pm.mutex);
7760         ret = si_dpm_init(adev);
7761         if (ret)
7762                 goto dpm_failed;
7763         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7764         if (amdgpu_dpm == 1)
7765                 amdgpu_pm_print_power_states(adev);
7766         mutex_unlock(&adev->pm.mutex);
7767         DRM_INFO("amdgpu: dpm initialized\n");
7768
7769         return 0;
7770
7771 dpm_failed:
7772         si_dpm_fini(adev);
7773         mutex_unlock(&adev->pm.mutex);
7774         DRM_ERROR("amdgpu: dpm initialization failed\n");
7775         return ret;
7776 }
7777
7778 static int si_dpm_sw_fini(void *handle)
7779 {
7780         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7781
7782         mutex_lock(&adev->pm.mutex);
7783         amdgpu_pm_sysfs_fini(adev);
7784         si_dpm_fini(adev);
7785         mutex_unlock(&adev->pm.mutex);
7786
7787         return 0;
7788 }
7789
7790 static int si_dpm_hw_init(void *handle)
7791 {
7792         int ret;
7793
7794         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7795
7796         if (!amdgpu_dpm)
7797                 return 0;
7798
7799         mutex_lock(&adev->pm.mutex);
7800         si_dpm_setup_asic(adev);
7801         ret = si_dpm_enable(adev);
7802         if (ret)
7803                 adev->pm.dpm_enabled = false;
7804         else
7805                 adev->pm.dpm_enabled = true;
7806         mutex_unlock(&adev->pm.mutex);
7807
7808         return ret;
7809 }
7810
7811 static int si_dpm_hw_fini(void *handle)
7812 {
7813         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7814
7815         if (adev->pm.dpm_enabled) {
7816                 mutex_lock(&adev->pm.mutex);
7817                 si_dpm_disable(adev);
7818                 mutex_unlock(&adev->pm.mutex);
7819         }
7820
7821         return 0;
7822 }
7823
7824 static int si_dpm_suspend(void *handle)
7825 {
7826         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7827
7828         if (adev->pm.dpm_enabled) {
7829                 mutex_lock(&adev->pm.mutex);
7830                 /* disable dpm */
7831                 si_dpm_disable(adev);
7832                 /* reset the power state */
7833                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7834                 mutex_unlock(&adev->pm.mutex);
7835         }
7836         return 0;
7837 }
7838
7839 static int si_dpm_resume(void *handle)
7840 {
7841         int ret;
7842         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7843
7844         if (adev->pm.dpm_enabled) {
7845                 /* asic init will reset to the boot state */
7846                 mutex_lock(&adev->pm.mutex);
7847                 si_dpm_setup_asic(adev);
7848                 ret = si_dpm_enable(adev);
7849                 if (ret)
7850                         adev->pm.dpm_enabled = false;
7851                 else
7852                         adev->pm.dpm_enabled = true;
7853                 mutex_unlock(&adev->pm.mutex);
7854                 if (adev->pm.dpm_enabled)
7855                         amdgpu_pm_compute_clocks(adev);
7856         }
7857         return 0;
7858 }
7859
7860 static bool si_dpm_is_idle(void *handle)
7861 {
7862         /* XXX */
7863         return true;
7864 }
7865
7866 static int si_dpm_wait_for_idle(void *handle)
7867 {
7868         /* XXX */
7869         return 0;
7870 }
7871
7872 static int si_dpm_soft_reset(void *handle)
7873 {
7874         return 0;
7875 }
7876
7877 static int si_dpm_set_clockgating_state(void *handle,
7878                                         enum amd_clockgating_state state)
7879 {
7880         return 0;
7881 }
7882
7883 static int si_dpm_set_powergating_state(void *handle,
7884                                         enum amd_powergating_state state)
7885 {
7886         return 0;
7887 }
7888
7889 /* get temperature in millidegrees */
7890 static int si_dpm_get_temp(struct amdgpu_device *adev)
7891 {
7892         u32 temp;
7893         int actual_temp = 0;
7894
7895         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7896                 CTF_TEMP_SHIFT;
7897
7898         if (temp & 0x200)
7899                 actual_temp = 255;
7900         else
7901                 actual_temp = temp & 0x1ff;
7902
7903         actual_temp = (actual_temp * 1000);
7904
7905         return actual_temp;
7906 }
7907
7908 static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7909 {
7910         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7911         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7912
7913         if (low)
7914                 return requested_state->performance_levels[0].sclk;
7915         else
7916                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7917 }
7918
7919 static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7920 {
7921         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7922         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7923
7924         if (low)
7925                 return requested_state->performance_levels[0].mclk;
7926         else
7927                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7928 }
7929
7930 static void si_dpm_print_power_state(struct amdgpu_device *adev,
7931                                      struct amdgpu_ps *rps)
7932 {
7933         struct  si_ps *ps = si_get_ps(rps);
7934         struct rv7xx_pl *pl;
7935         int i;
7936
7937         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7938         amdgpu_dpm_print_cap_info(rps->caps);
7939         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7940         for (i = 0; i < ps->performance_level_count; i++) {
7941                 pl = &ps->performance_levels[i];
7942                 if (adev->asic_type >= CHIP_TAHITI)
7943                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7944                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7945                 else
7946                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7947                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7948         }
7949         amdgpu_dpm_print_ps_status(adev, rps);
7950 }
7951
7952 static int si_dpm_early_init(void *handle)
7953 {
7954
7955         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7956
7957         si_dpm_set_dpm_funcs(adev);
7958         si_dpm_set_irq_funcs(adev);
7959         return 0;
7960 }
7961
7962 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7963                                                 const struct rv7xx_pl *si_cpl2)
7964 {
7965         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7966                   (si_cpl1->sclk == si_cpl2->sclk) &&
7967                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7968                   (si_cpl1->vddc == si_cpl2->vddc) &&
7969                   (si_cpl1->vddci == si_cpl2->vddci));
7970 }
7971
7972 static int si_check_state_equal(struct amdgpu_device *adev,
7973                                 struct amdgpu_ps *cps,
7974                                 struct amdgpu_ps *rps,
7975                                 bool *equal)
7976 {
7977         struct si_ps *si_cps;
7978         struct si_ps *si_rps;
7979         int i;
7980
7981         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7982                 return -EINVAL;
7983
7984         si_cps = si_get_ps(cps);
7985         si_rps = si_get_ps(rps);
7986
7987         if (si_cps == NULL) {
7988                 printk("si_cps is NULL\n");
7989                 *equal = false;
7990                 return 0;
7991         }
7992
7993         if (si_cps->performance_level_count != si_rps->performance_level_count) {
7994                 *equal = false;
7995                 return 0;
7996         }
7997
7998         for (i = 0; i < si_cps->performance_level_count; i++) {
7999                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
8000                                         &(si_rps->performance_levels[i]))) {
8001                         *equal = false;
8002                         return 0;
8003                 }
8004         }
8005
8006         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8007         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8008         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8009
8010         return 0;
8011 }
8012
8013
8014 const struct amd_ip_funcs si_dpm_ip_funcs = {
8015         .name = "si_dpm",
8016         .early_init = si_dpm_early_init,
8017         .late_init = si_dpm_late_init,
8018         .sw_init = si_dpm_sw_init,
8019         .sw_fini = si_dpm_sw_fini,
8020         .hw_init = si_dpm_hw_init,
8021         .hw_fini = si_dpm_hw_fini,
8022         .suspend = si_dpm_suspend,
8023         .resume = si_dpm_resume,
8024         .is_idle = si_dpm_is_idle,
8025         .wait_for_idle = si_dpm_wait_for_idle,
8026         .soft_reset = si_dpm_soft_reset,
8027         .set_clockgating_state = si_dpm_set_clockgating_state,
8028         .set_powergating_state = si_dpm_set_powergating_state,
8029 };
8030
8031 static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8032         .get_temperature = &si_dpm_get_temp,
8033         .pre_set_power_state = &si_dpm_pre_set_power_state,
8034         .set_power_state = &si_dpm_set_power_state,
8035         .post_set_power_state = &si_dpm_post_set_power_state,
8036         .display_configuration_changed = &si_dpm_display_configuration_changed,
8037         .get_sclk = &si_dpm_get_sclk,
8038         .get_mclk = &si_dpm_get_mclk,
8039         .print_power_state = &si_dpm_print_power_state,
8040         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8041         .force_performance_level = &si_dpm_force_performance_level,
8042         .vblank_too_short = &si_dpm_vblank_too_short,
8043         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8044         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8045         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8046         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8047         .check_state_equal = &si_check_state_equal,
8048         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8049 };
8050
8051 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8052 {
8053         if (adev->pm.funcs == NULL)
8054                 adev->pm.funcs = &si_dpm_funcs;
8055 }
8056
8057 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8058         .set = si_dpm_set_interrupt_state,
8059         .process = si_dpm_process_interrupt,
8060 };
8061
8062 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8063 {
8064         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8065         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8066 }
8067
8068 const struct amdgpu_ip_block_version si_dpm_ip_block =
8069 {
8070         .type = AMD_IP_BLOCK_TYPE_SMC,
8071         .major = 6,
8072         .minor = 0,
8073         .rev = 0,
8074         .funcs = &si_dpm_ip_funcs,
8075 };