drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef __AMDGPU_DPM_H__
  24 #define __AMDGPU_DPM_H__
  25
  26 enum amdgpu_int_thermal_type {
  27         THERMAL_TYPE_NONE,
  28         THERMAL_TYPE_EXTERNAL,
  29         THERMAL_TYPE_EXTERNAL_GPIO,
  30         THERMAL_TYPE_RV6XX,
  31         THERMAL_TYPE_RV770,
  32         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
  33         THERMAL_TYPE_EVERGREEN,
  34         THERMAL_TYPE_SUMO,
  35         THERMAL_TYPE_NI,
  36         THERMAL_TYPE_SI,
  37         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
  38         THERMAL_TYPE_CI,
  39         THERMAL_TYPE_KV,
  40 };
  41
  42 enum amdgpu_dpm_auto_throttle_src {
  43         AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
  44         AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
  45 };
  46
  47 enum amdgpu_dpm_event_src {
  48         AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
  49         AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
  50         AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
  51         AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
  52         AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
  53 };
  54
  55 struct amdgpu_ps {
  56         u32 caps; /* vbios flags */
  57         u32 class; /* vbios flags */
  58         u32 class2; /* vbios flags */
  59         /* UVD clocks */
  60         u32 vclk;
  61         u32 dclk;
  62         /* VCE clocks */
  63         u32 evclk;
  64         u32 ecclk;
  65         bool vce_active;
  66         enum amd_vce_level vce_level;
  67         /* asic priv */
  68         void *ps_priv;
  69 };
  70
  71 struct amdgpu_dpm_thermal {
  72         /* thermal interrupt work */
  73         struct work_struct work;
  74         /* low temperature threshold */
  75         int                min_temp;
  76         /* high temperature threshold */
  77         int                max_temp;
  78         /* was last interrupt low to high or high to low */
  79         bool               high_to_low;
  80         /* interrupt source */
  81         struct amdgpu_irq_src   irq;
  82 };
  83
  84 enum amdgpu_clk_action
  85 {
  86         AMDGPU_SCLK_UP = 1,
  87         AMDGPU_SCLK_DOWN
  88 };
  89
  90 struct amdgpu_blacklist_clocks
  91 {
  92         u32 sclk;
  93         u32 mclk;
  94         enum amdgpu_clk_action action;
  95 };
  96
  97 struct amdgpu_clock_and_voltage_limits {
  98         u32 sclk;
  99         u32 mclk;
 100         u16 vddc;
 101         u16 vddci;
 102 };
 103
 104 struct amdgpu_clock_array {
 105         u32 count;
 106         u32 *values;
 107 };
 108
 109 struct amdgpu_clock_voltage_dependency_entry {
 110         u32 clk;
 111         u16 v;
 112 };
 113
 114 struct amdgpu_clock_voltage_dependency_table {
 115         u32 count;
 116         struct amdgpu_clock_voltage_dependency_entry *entries;
 117 };
 118
 119 union amdgpu_cac_leakage_entry {
 120         struct {
 121                 u16 vddc;
 122                 u32 leakage;
 123         };
 124         struct {
 125                 u16 vddc1;
 126                 u16 vddc2;
 127                 u16 vddc3;
 128         };
 129 };
 130
 131 struct amdgpu_cac_leakage_table {
 132         u32 count;
 133         union amdgpu_cac_leakage_entry *entries;
 134 };
 135
 136 struct amdgpu_phase_shedding_limits_entry {
 137         u16 voltage;
 138         u32 sclk;
 139         u32 mclk;
 140 };
 141
 142 struct amdgpu_phase_shedding_limits_table {
 143         u32 count;
 144         struct amdgpu_phase_shedding_limits_entry *entries;
 145 };
 146
 147 struct amdgpu_uvd_clock_voltage_dependency_entry {
 148         u32 vclk;
 149         u32 dclk;
 150         u16 v;
 151 };
 152
 153 struct amdgpu_uvd_clock_voltage_dependency_table {
 154         u8 count;
 155         struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
 156 };
 157
 158 struct amdgpu_vce_clock_voltage_dependency_entry {
 159         u32 ecclk;
 160         u32 evclk;
 161         u16 v;
 162 };
 163
 164 struct amdgpu_vce_clock_voltage_dependency_table {
 165         u8 count;
 166         struct amdgpu_vce_clock_voltage_dependency_entry *entries;
 167 };
 168
 169 struct amdgpu_ppm_table {
 170         u8 ppm_design;
 171         u16 cpu_core_number;
 172         u32 platform_tdp;
 173         u32 small_ac_platform_tdp;
 174         u32 platform_tdc;
 175         u32 small_ac_platform_tdc;
 176         u32 apu_tdp;
 177         u32 dgpu_tdp;
 178         u32 dgpu_ulv_power;
 179         u32 tj_max;
 180 };
 181
 182 struct amdgpu_cac_tdp_table {
 183         u16 tdp;
 184         u16 configurable_tdp;
 185         u16 tdc;
 186         u16 battery_power_limit;
 187         u16 small_power_limit;
 188         u16 low_cac_leakage;
 189         u16 high_cac_leakage;
 190         u16 maximum_power_delivery_limit;
 191 };
 192
 193 struct amdgpu_dpm_dynamic_state {
 194         struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
 195         struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
 196         struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
 197         struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
 198         struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
 199         struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
 200         struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
 201         struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
 202         struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
 203         struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
 204         struct amdgpu_clock_array valid_sclk_values;
 205         struct amdgpu_clock_array valid_mclk_values;
 206         struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
 207         struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
 208         u32 mclk_sclk_ratio;
 209         u32 sclk_mclk_delta;
 210         u16 vddc_vddci_delta;
 211         u16 min_vddc_for_pcie_gen2;
 212         struct amdgpu_cac_leakage_table cac_leakage_table;
 213         struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
 214         struct amdgpu_ppm_table *ppm_table;
 215         struct amdgpu_cac_tdp_table *cac_tdp_table;
 216 };
 217
 218 struct amdgpu_dpm_fan {
 219         u16 t_min;
 220         u16 t_med;
 221         u16 t_high;
 222         u16 pwm_min;
 223         u16 pwm_med;
 224         u16 pwm_high;
 225         u8 t_hyst;
 226         u32 cycle_delay;
 227         u16 t_max;
 228         u8 control_mode;
 229         u16 default_max_fan_pwm;
 230         u16 default_fan_output_sensitivity;
 231         u16 fan_output_sensitivity;
 232         bool ucode_fan_control;
 233 };
 234
 235 enum amdgpu_pcie_gen {
 236         AMDGPU_PCIE_GEN1 = 0,
 237         AMDGPU_PCIE_GEN2 = 1,
 238         AMDGPU_PCIE_GEN3 = 2,
 239         AMDGPU_PCIE_GEN_INVALID = 0xffff
 240 };
 241
 242 enum amdgpu_dpm_forced_level {
 243         AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
 244         AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
 245         AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
 246         AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
 247 };
 248
 249 struct amdgpu_dpm_funcs {
 250         int (*get_temperature)(struct amdgpu_device *adev);
 251         int (*pre_set_power_state)(struct amdgpu_device *adev);
 252         int (*set_power_state)(struct amdgpu_device *adev);
 253         void (*post_set_power_state)(struct amdgpu_device *adev);
 254         void (*display_configuration_changed)(struct amdgpu_device *adev);
 255         u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
 256         u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
 257         void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
 258         void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
 259         int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
 260         bool (*vblank_too_short)(struct amdgpu_device *adev);
 261         void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
 262         void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
 263         void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
 264         void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
 265         u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
 266         int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
 267         int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
 268         int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
 269         int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
 270         int (*get_sclk_od)(struct amdgpu_device *adev);
 271         int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
 272         int (*get_mclk_od)(struct amdgpu_device *adev);
 273         int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
 274         int (*check_state_equal)(struct amdgpu_device *adev,
 275                                 struct amdgpu_ps *cps,
 276                                 struct amdgpu_ps *rps,
 277                                 bool *equal);
 278
 279         struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);
 280 };
 281
 282 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
 283 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
 284 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
 285 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
 286 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
 287 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
 288 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
 289
 290 #define amdgpu_dpm_read_sensor(adev, idx, value) \
 291         ((adev)->pp_enabled ? \
 292                 (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
 293                 -EINVAL)
 294
 295 #define amdgpu_dpm_get_temperature(adev) \
 296         ((adev)->pp_enabled ?                                           \
 297               (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
 298               (adev)->pm.funcs->get_temperature((adev)))
 299
 300 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
 301         ((adev)->pp_enabled ?                                           \
 302               (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
 303               (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
 304
 305 #define amdgpu_dpm_get_fan_control_mode(adev) \
 306         ((adev)->pp_enabled ?                                           \
 307               (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
 308               (adev)->pm.funcs->get_fan_control_mode((adev)))
 309
 310 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
 311         ((adev)->pp_enabled ?                                           \
 312               (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
 313               (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
 314
 315 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
 316         ((adev)->pp_enabled ?                                           \
 317               (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
 318               (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
 319
 320 #define amdgpu_dpm_get_sclk(adev, l) \
 321         ((adev)->pp_enabled ?                                           \
 322               (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
 323                 (adev)->pm.funcs->get_sclk((adev), (l)))
 324
 325 #define amdgpu_dpm_get_mclk(adev, l)  \
 326         ((adev)->pp_enabled ?                                           \
 327               (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
 328               (adev)->pm.funcs->get_mclk((adev), (l)))
 329
 330
 331 #define amdgpu_dpm_force_performance_level(adev, l) \
 332         ((adev)->pp_enabled ?                                           \
 333               (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
 334               (adev)->pm.funcs->force_performance_level((adev), (l)))
 335
 336 #define amdgpu_dpm_powergate_uvd(adev, g) \
 337         ((adev)->pp_enabled ?                                           \
 338               (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
 339               (adev)->pm.funcs->powergate_uvd((adev), (g)))
 340
 341 #define amdgpu_dpm_powergate_vce(adev, g) \
 342         ((adev)->pp_enabled ?                                           \
 343               (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
 344               (adev)->pm.funcs->powergate_vce((adev), (g)))
 345
 346 #define amdgpu_dpm_get_current_power_state(adev) \
 347         (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
 348
 349 #define amdgpu_dpm_get_performance_level(adev) \
 350         (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
 351
 352 #define amdgpu_dpm_get_pp_num_states(adev, data) \
 353         (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
 354
 355 #define amdgpu_dpm_get_pp_table(adev, table) \
 356         (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
 357
 358 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
 359         (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
 360
 361 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
 362         (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
 363
 364 #define amdgpu_dpm_force_clock_level(adev, type, level) \
 365                 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
 366
 367 #define amdgpu_dpm_get_sclk_od(adev) \
 368         (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
 369
 370 #define amdgpu_dpm_set_sclk_od(adev, value) \
 371         (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
 372
 373 #define amdgpu_dpm_get_mclk_od(adev) \
 374         ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
 375
 376 #define amdgpu_dpm_set_mclk_od(adev, value) \
 377         ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
 378
 379 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output)         \
 380         (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
 381
 382 #define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
 383
 384 #define amdgpu_dpm_get_vce_clock_state(adev, i)                         \
 385         ((adev)->pp_enabled ?                                           \
 386          (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
 387          (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
 388
 389 struct amdgpu_dpm {
 390         struct amdgpu_ps        *ps;
 391         /* number of valid power states */
 392         int                     num_ps;
 393         /* current power state that is active */
 394         struct amdgpu_ps        *current_ps;
 395         /* requested power state */
 396         struct amdgpu_ps        *requested_ps;
 397         /* boot up power state */
 398         struct amdgpu_ps        *boot_ps;
 399         /* default uvd power state */
 400         struct amdgpu_ps        *uvd_ps;
 401         /* vce requirements */
 402         u32                  num_of_vce_states;
 403         struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
 404         enum amd_vce_level vce_level;
 405         enum amd_pm_state_type state;
 406         enum amd_pm_state_type user_state;
 407         u32                     platform_caps;
 408         u32                     voltage_response_time;
 409         u32                     backbias_response_time;
 410         void                    *priv;
 411         u32                     new_active_crtcs;
 412         int                     new_active_crtc_count;
 413         u32                     current_active_crtcs;
 414         int                     current_active_crtc_count;
 415         struct amdgpu_dpm_dynamic_state dyn_state;
 416         struct amdgpu_dpm_fan fan;
 417         u32 tdp_limit;
 418         u32 near_tdp_limit;
 419         u32 near_tdp_limit_adjusted;
 420         u32 sq_ramping_threshold;
 421         u32 cac_leakage;
 422         u16 tdp_od_limit;
 423         u32 tdp_adjustment;
 424         u16 load_line_slope;
 425         bool power_control;
 426         bool ac_power;
 427         /* special states active */
 428         bool                    thermal_active;
 429         bool                    uvd_active;
 430         bool                    vce_active;
 431         /* thermal handling */
 432         struct amdgpu_dpm_thermal thermal;
 433         /* forced levels */
 434         enum amdgpu_dpm_forced_level forced_level;
 435 };
 436
 437 struct amdgpu_pm {
 438         struct mutex            mutex;
 439         u32                     current_sclk;
 440         u32                     current_mclk;
 441         u32                     default_sclk;
 442         u32                     default_mclk;
 443         struct amdgpu_i2c_chan *i2c_bus;
 444         /* internal thermal controller on rv6xx+ */
 445         enum amdgpu_int_thermal_type int_thermal_type;
 446         struct device           *int_hwmon_dev;
 447         /* fan control parameters */
 448         bool                    no_fan;
 449         u8                      fan_pulses_per_revolution;
 450         u8                      fan_min_rpm;
 451         u8                      fan_max_rpm;
 452         /* dpm */
 453         bool                    dpm_enabled;
 454         bool                    sysfs_initialized;
 455         struct amdgpu_dpm       dpm;
 456         const struct firmware   *fw;    /* SMC firmware */
 457         uint32_t                fw_version;
 458         const struct amdgpu_dpm_funcs *funcs;
 459         uint32_t                pcie_gen_mask;
 460         uint32_t                pcie_mlw_mask;
 461         struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
 462 };
 463
 464 #define R600_SSTU_DFLT                               0
 465 #define R600_SST_DFLT                                0x00C8
 466
 467 /* XXX are these ok? */
 468 #define R600_TEMP_RANGE_MIN (90 * 1000)
 469 #define R600_TEMP_RANGE_MAX (120 * 1000)
 470
 471 #define FDO_PWM_MODE_STATIC  1
 472 #define FDO_PWM_MODE_STATIC_RPM 5
 473
 474 enum amdgpu_td {
 475         AMDGPU_TD_AUTO,
 476         AMDGPU_TD_UP,
 477         AMDGPU_TD_DOWN,
 478 };
 479
 480 enum amdgpu_display_watermark {
 481         AMDGPU_DISPLAY_WATERMARK_LOW = 0,
 482         AMDGPU_DISPLAY_WATERMARK_HIGH = 1,
 483 };
 484
 485 enum amdgpu_display_gap
 486 {
 487     AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0,
 488     AMDGPU_PM_DISPLAY_GAP_VBLANK       = 1,
 489     AMDGPU_PM_DISPLAY_GAP_WATERMARK    = 2,
 490     AMDGPU_PM_DISPLAY_GAP_IGNORE       = 3,
 491 };
 492
 493 void amdgpu_dpm_print_class_info(u32 class, u32 class2);
 494 void amdgpu_dpm_print_cap_info(u32 caps);
 495 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev,
 496                                 struct amdgpu_ps *rps);
 497 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev);
 498 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev);
 499 bool amdgpu_is_uvd_state(u32 class, u32 class2);
 500 void amdgpu_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
 501                               u32 *p, u32 *u);
 502 int amdgpu_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th);
 503
 504 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor);
 505
 506 int amdgpu_get_platform_caps(struct amdgpu_device *adev);
 507
 508 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev);
 509 void amdgpu_free_extended_power_table(struct amdgpu_device *adev);
 510
 511 void amdgpu_add_thermal_controller(struct amdgpu_device *adev);
 512
 513 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
 514                                                  u32 sys_mask,
 515                                                  enum amdgpu_pcie_gen asic_gen,
 516                                                  enum amdgpu_pcie_gen default_gen);
 517
 518 u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
 519                                  u16 asic_lanes,
 520                                  u16 default_lanes);
 521 u8 amdgpu_encode_pci_lane_width(u32 lanes);
 522
 523 struct amd_vce_state*
 524 amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);
 525
 526 #endif