drivers/gpu/drm/i915/display/intel_dp_mst.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *             2014 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_probe_helper.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_reg.h"
  33 #include "intel_atomic.h"
  34 #include "intel_audio.h"
  35 #include "intel_connector.h"
  36 #include "intel_crtc.h"
  37 #include "intel_ddi.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dp.h"
  41 #include "intel_dp_hdcp.h"
  42 #include "intel_dp_mst.h"
  43 #include "intel_dpio_phy.h"
  44 #include "intel_hdcp.h"
  45 #include "intel_hotplug.h"
  46 #include "skl_scaler.h"
  47
  48 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
  49                                                 struct intel_crtc_state *crtc_state,
  50                                                 int max_bpp,
  51                                                 int min_bpp,
  52                                                 struct link_config_limits *limits,
  53                                                 struct drm_connector_state *conn_state,
  54                                                 int step,
  55                                                 bool dsc)
  56 {
  57         struct drm_atomic_state *state = crtc_state->uapi.state;
  58         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
  59         struct intel_dp *intel_dp = &intel_mst->primary->dp;
  60         struct drm_dp_mst_topology_state *mst_state;
  61         struct intel_connector *connector =
  62                 to_intel_connector(conn_state->connector);
  63         struct drm_i915_private *i915 = to_i915(connector->base.dev);
  64         const struct drm_display_mode *adjusted_mode =
  65                 &crtc_state->hw.adjusted_mode;
  66         int bpp, slots = -EINVAL;
  67         int ret = 0;
  68
  69         mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
  70         if (IS_ERR(mst_state))
  71                 return PTR_ERR(mst_state);
  72
  73         crtc_state->lane_count = limits->max_lane_count;
  74         crtc_state->port_clock = limits->max_rate;
  75
  76         // TODO: Handle pbn_div changes by adding a new MST helper
  77         if (!mst_state->pbn_div) {
  78                 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
  79                                                               crtc_state->port_clock,
  80                                                               crtc_state->lane_count);
  81         }
  82
  83         for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
  84                 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
  85                                                        dsc ? bpp << 4 : bpp,
  86                                                        dsc);
  87
  88                 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
  89
  90                 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
  91                                                       connector->port,
  92                                                       crtc_state->pbn);
  93                 if (slots == -EDEADLK)
  94                         return slots;
  95
  96                 if (slots >= 0) {
  97                         ret = drm_dp_mst_atomic_check(state);
  98                         /*
  99                          * If we got slots >= 0 and we can fit those based on check
 100                          * then we can exit the loop. Otherwise keep trying.
 101                          */
 102                         if (!ret)
 103                                 break;
 104                 }
 105         }
 106
 107         /* Despite slots are non-zero, we still failed the atomic check */
 108         if (ret && slots >= 0)
 109                 slots = ret;
 110
 111         if (slots < 0) {
 112                 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 113                             slots);
 114         } else {
 115                 if (!dsc)
 116                         crtc_state->pipe_bpp = bpp;
 117                 else
 118                         crtc_state->dsc.compressed_bpp = bpp;
 119                 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 120         }
 121
 122         return slots;
 123 }
 124
 125 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 126                                             struct intel_crtc_state *crtc_state,
 127                                             struct drm_connector_state *conn_state,
 128                                             struct link_config_limits *limits)
 129 {
 130         const struct drm_display_mode *adjusted_mode =
 131                 &crtc_state->hw.adjusted_mode;
 132         int slots = -EINVAL;
 133
 134         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
 135                                                      limits->min_bpp, limits,
 136                                                      conn_state, 2 * 3, false);
 137
 138         if (slots < 0)
 139                 return slots;
 140
 141         intel_link_compute_m_n(crtc_state->pipe_bpp,
 142                                crtc_state->lane_count,
 143                                adjusted_mode->crtc_clock,
 144                                crtc_state->port_clock,
 145                                &crtc_state->dp_m_n,
 146                                crtc_state->fec_enable);
 147         crtc_state->dp_m_n.tu = slots;
 148
 149         return 0;
 150 }
 151
 152 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 153                                                 struct intel_crtc_state *crtc_state,
 154                                                 struct drm_connector_state *conn_state,
 155                                                 struct link_config_limits *limits)
 156 {
 157         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 158         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 159         struct intel_connector *connector =
 160                 to_intel_connector(conn_state->connector);
 161         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 162         const struct drm_display_mode *adjusted_mode =
 163                 &crtc_state->hw.adjusted_mode;
 164         int slots = -EINVAL;
 165         int i, num_bpc;
 166         u8 dsc_bpc[3] = {0};
 167         int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 168         u8 dsc_max_bpc;
 169         bool need_timeslot_recalc = false;
 170         u32 last_compressed_bpp;
 171
 172         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 173         if (DISPLAY_VER(i915) >= 12)
 174                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
 175         else
 176                 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
 177
 178         max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
 179         min_bpp = limits->min_bpp;
 180
 181         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
 182                                                        dsc_bpc);
 183
 184         drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
 185                     min_bpp, max_bpp);
 186
 187         sink_max_bpp = dsc_bpc[0] * 3;
 188         sink_min_bpp = sink_max_bpp;
 189
 190         for (i = 1; i < num_bpc; i++) {
 191                 if (sink_min_bpp > dsc_bpc[i] * 3)
 192                         sink_min_bpp = dsc_bpc[i] * 3;
 193                 if (sink_max_bpp < dsc_bpc[i] * 3)
 194                         sink_max_bpp = dsc_bpc[i] * 3;
 195         }
 196
 197         drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
 198                     sink_min_bpp, sink_max_bpp);
 199
 200         if (min_bpp < sink_min_bpp)
 201                 min_bpp = sink_min_bpp;
 202
 203         if (max_bpp > sink_max_bpp)
 204                 max_bpp = sink_max_bpp;
 205
 206         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
 207                                                      min_bpp, limits,
 208                                                      conn_state, 2 * 3, true);
 209
 210         if (slots < 0)
 211                 return slots;
 212
 213         last_compressed_bpp = crtc_state->dsc.compressed_bpp;
 214
 215         crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
 216                                                                         last_compressed_bpp,
 217                                                                         crtc_state->pipe_bpp);
 218
 219         if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
 220                 need_timeslot_recalc = true;
 221
 222         /*
 223          * Apparently some MST hubs dislike if vcpi slots are not matching precisely
 224          * the actual compressed bpp we use.
 225          */
 226         if (need_timeslot_recalc) {
 227                 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 228                                                              crtc_state->dsc.compressed_bpp,
 229                                                              crtc_state->dsc.compressed_bpp,
 230                                                              limits, conn_state, 2 * 3, true);
 231                 if (slots < 0)
 232                         return slots;
 233         }
 234
 235         intel_link_compute_m_n(crtc_state->pipe_bpp,
 236                                crtc_state->lane_count,
 237                                adjusted_mode->crtc_clock,
 238                                crtc_state->port_clock,
 239                                &crtc_state->dp_m_n,
 240                                crtc_state->fec_enable);
 241         crtc_state->dp_m_n.tu = slots;
 242
 243         return 0;
 244 }
 245 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 246                                      struct intel_crtc_state *crtc_state,
 247                                      struct drm_connector_state *conn_state)
 248 {
 249         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 250         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 251         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 252         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 253         struct drm_dp_mst_topology_state *topology_state;
 254         u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
 255                 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 256
 257         topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
 258         if (IS_ERR(topology_state)) {
 259                 drm_dbg_kms(&i915->drm, "slot update failed\n");
 260                 return PTR_ERR(topology_state);
 261         }
 262
 263         drm_dp_mst_update_slots(topology_state, link_coding_cap);
 264
 265         return 0;
 266 }
 267
 268 static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
 269 {
 270         const struct intel_digital_connector_state *intel_conn_state =
 271                 to_intel_digital_connector_state(conn_state);
 272         struct intel_connector *connector =
 273                 to_intel_connector(conn_state->connector);
 274
 275         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
 276                 return connector->port->has_audio;
 277         else
 278                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
 279 }
 280
 281 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 282                                        struct intel_crtc_state *pipe_config,
 283                                        struct drm_connector_state *conn_state)
 284 {
 285         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 286         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 287         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 288         const struct drm_display_mode *adjusted_mode =
 289                 &pipe_config->hw.adjusted_mode;
 290         struct link_config_limits limits;
 291         int ret;
 292
 293         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 294                 return -EINVAL;
 295
 296         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 297         pipe_config->has_pch_encoder = false;
 298
 299         pipe_config->has_audio =
 300                 intel_dp_mst_has_audio(conn_state) &&
 301                 intel_audio_compute_config(encoder, pipe_config, conn_state);
 302
 303         /*
 304          * for MST we always configure max link bw - the spec doesn't
 305          * seem to suggest we should do otherwise.
 306          */
 307         limits.min_rate =
 308         limits.max_rate = intel_dp_max_link_rate(intel_dp);
 309
 310         limits.min_lane_count =
 311         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 312
 313         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
 314         /*
 315          * FIXME: If all the streams can't fit into the link with
 316          * their current pipe_bpp we should reduce pipe_bpp across
 317          * the board until things start to fit. Until then we
 318          * limit to <= 8bpc since that's what was hardcoded for all
 319          * MST streams previously. This hack should be removed once
 320          * we have the proper retry logic in place.
 321          */
 322         limits.max_bpp = min(pipe_config->pipe_bpp, 24);
 323
 324         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
 325
 326         ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
 327                                                conn_state, &limits);
 328
 329         if (ret == -EDEADLK)
 330                 return ret;
 331
 332         /* enable compression if the mode doesn't fit available BW */
 333         drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
 334         if (ret || intel_dp->force_dsc_en) {
 335                 /*
 336                  * Try to get at least some timeslots and then see, if
 337                  * we can fit there with DSC.
 338                  */
 339                 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
 340
 341                 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
 342                                                            conn_state, &limits);
 343                 if (ret < 0)
 344                         return ret;
 345
 346                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
 347                                                   conn_state, &limits,
 348                                                   pipe_config->dp_m_n.tu, false);
 349         }
 350
 351         if (ret)
 352                 return ret;
 353
 354         ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
 355         if (ret)
 356                 return ret;
 357
 358         pipe_config->limited_color_range =
 359                 intel_dp_limited_color_range(pipe_config, conn_state);
 360
 361         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 362                 pipe_config->lane_lat_optim_mask =
 363                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 364
 365         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 366
 367         return 0;
 368 }
 369
 370 /*
 371  * Iterate over all connectors and return a mask of
 372  * all CPU transcoders streaming over the same DP link.
 373  */
 374 static unsigned int
 375 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
 376                              struct intel_dp *mst_port)
 377 {
 378         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 379         const struct intel_digital_connector_state *conn_state;
 380         struct intel_connector *connector;
 381         u8 transcoders = 0;
 382         int i;
 383
 384         if (DISPLAY_VER(dev_priv) < 12)
 385                 return 0;
 386
 387         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 388                 const struct intel_crtc_state *crtc_state;
 389                 struct intel_crtc *crtc;
 390
 391                 if (connector->mst_port != mst_port || !conn_state->base.crtc)
 392                         continue;
 393
 394                 crtc = to_intel_crtc(conn_state->base.crtc);
 395                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 396
 397                 if (!crtc_state->hw.active)
 398                         continue;
 399
 400                 transcoders |= BIT(crtc_state->cpu_transcoder);
 401         }
 402
 403         return transcoders;
 404 }
 405
 406 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
 407                                             struct intel_crtc_state *crtc_state,
 408                                             struct drm_connector_state *conn_state)
 409 {
 410         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 411         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 412         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 413
 414         /* lowest numbered transcoder will be designated master */
 415         crtc_state->mst_master_transcoder =
 416                 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
 423  * that shares the same MST stream as mode changed,
 424  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
 425  * a fastset when possible.
 426  */
 427 static int
 428 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
 429                                        struct intel_atomic_state *state)
 430 {
 431         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 432         struct drm_connector_list_iter connector_list_iter;
 433         struct intel_connector *connector_iter;
 434         int ret = 0;
 435
 436         if (DISPLAY_VER(dev_priv) < 12)
 437                 return  0;
 438
 439         if (!intel_connector_needs_modeset(state, &connector->base))
 440                 return 0;
 441
 442         drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
 443         for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
 444                 struct intel_digital_connector_state *conn_iter_state;
 445                 struct intel_crtc_state *crtc_state;
 446                 struct intel_crtc *crtc;
 447
 448                 if (connector_iter->mst_port != connector->mst_port ||
 449                     connector_iter == connector)
 450                         continue;
 451
 452                 conn_iter_state = intel_atomic_get_digital_connector_state(state,
 453                                                                            connector_iter);
 454                 if (IS_ERR(conn_iter_state)) {
 455                         ret = PTR_ERR(conn_iter_state);
 456                         break;
 457                 }
 458
 459                 if (!conn_iter_state->base.crtc)
 460                         continue;
 461
 462                 crtc = to_intel_crtc(conn_iter_state->base.crtc);
 463                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 464                 if (IS_ERR(crtc_state)) {
 465                         ret = PTR_ERR(crtc_state);
 466                         break;
 467                 }
 468
 469                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 470                 if (ret)
 471                         break;
 472                 crtc_state->uapi.mode_changed = true;
 473         }
 474         drm_connector_list_iter_end(&connector_list_iter);
 475
 476         return ret;
 477 }
 478
 479 static int
 480 intel_dp_mst_atomic_check(struct drm_connector *connector,
 481                           struct drm_atomic_state *_state)
 482 {
 483         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 484         struct intel_connector *intel_connector =
 485                 to_intel_connector(connector);
 486         int ret;
 487
 488         ret = intel_digital_connector_atomic_check(connector, &state->base);
 489         if (ret)
 490                 return ret;
 491
 492         ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
 493         if (ret)
 494                 return ret;
 495
 496         return drm_dp_atomic_release_time_slots(&state->base,
 497                                                 &intel_connector->mst_port->mst_mgr,
 498                                                 intel_connector->port);
 499 }
 500
 501 static void clear_act_sent(struct intel_encoder *encoder,
 502                            const struct intel_crtc_state *crtc_state)
 503 {
 504         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 505
 506         intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 507                        DP_TP_STATUS_ACT_SENT);
 508 }
 509
 510 static void wait_for_act_sent(struct intel_encoder *encoder,
 511                               const struct intel_crtc_state *crtc_state)
 512 {
 513         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 514         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 515         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 516
 517         if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 518                                   DP_TP_STATUS_ACT_SENT, 1))
 519                 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 520
 521         drm_dp_check_act_status(&intel_dp->mst_mgr);
 522 }
 523
 524 static void intel_mst_disable_dp(struct intel_atomic_state *state,
 525                                  struct intel_encoder *encoder,
 526                                  const struct intel_crtc_state *old_crtc_state,
 527                                  const struct drm_connector_state *old_conn_state)
 528 {
 529         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 530         struct intel_digital_port *dig_port = intel_mst->primary;
 531         struct intel_dp *intel_dp = &dig_port->dp;
 532         struct intel_connector *connector =
 533                 to_intel_connector(old_conn_state->connector);
 534         struct drm_dp_mst_topology_state *old_mst_state =
 535                 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 536         struct drm_dp_mst_topology_state *new_mst_state =
 537                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 538         const struct drm_dp_mst_atomic_payload *old_payload =
 539                 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
 540         struct drm_dp_mst_atomic_payload *new_payload =
 541                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
 542         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 543
 544         drm_dbg_kms(&i915->drm, "active links %d\n",
 545                     intel_dp->active_mst_links);
 546
 547         intel_hdcp_disable(intel_mst->connector);
 548
 549         drm_dp_remove_payload(&intel_dp->mst_mgr, new_mst_state,
 550                               old_payload, new_payload);
 551
 552         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
 553 }
 554
 555 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 556                                       struct intel_encoder *encoder,
 557                                       const struct intel_crtc_state *old_crtc_state,
 558                                       const struct drm_connector_state *old_conn_state)
 559 {
 560         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 561         struct intel_digital_port *dig_port = intel_mst->primary;
 562         struct intel_dp *intel_dp = &dig_port->dp;
 563         struct intel_connector *connector =
 564                 to_intel_connector(old_conn_state->connector);
 565         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 566         bool last_mst_stream;
 567
 568         intel_dp->active_mst_links--;
 569         last_mst_stream = intel_dp->active_mst_links == 0;
 570         drm_WARN_ON(&dev_priv->drm,
 571                     DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
 572                     !intel_dp_mst_is_master_trans(old_crtc_state));
 573
 574         intel_crtc_vblank_off(old_crtc_state);
 575
 576         intel_disable_transcoder(old_crtc_state);
 577
 578         clear_act_sent(encoder, old_crtc_state);
 579
 580         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
 581                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
 582
 583         wait_for_act_sent(encoder, old_crtc_state);
 584
 585         intel_ddi_disable_transcoder_func(old_crtc_state);
 586
 587         if (DISPLAY_VER(dev_priv) >= 9)
 588                 skl_scaler_disable(old_crtc_state);
 589         else
 590                 ilk_pfit_disable(old_crtc_state);
 591
 592         /*
 593          * Power down mst path before disabling the port, otherwise we end
 594          * up getting interrupts from the sink upon detecting link loss.
 595          */
 596         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
 597                                      false);
 598
 599         /*
 600          * BSpec 4287: disable DIP after the transcoder is disabled and before
 601          * the transcoder clock select is set to none.
 602          */
 603         if (last_mst_stream)
 604                 intel_dp_set_infoframes(&dig_port->base, false,
 605                                         old_crtc_state, NULL);
 606         /*
 607          * From TGL spec: "If multi-stream slave transcoder: Configure
 608          * Transcoder Clock Select to direct no clock to the transcoder"
 609          *
 610          * From older GENs spec: "Configure Transcoder Clock Select to direct
 611          * no clock to the transcoder"
 612          */
 613         if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
 614                 intel_ddi_disable_transcoder_clock(old_crtc_state);
 615
 616
 617         intel_mst->connector = NULL;
 618         if (last_mst_stream)
 619                 dig_port->base.post_disable(state, &dig_port->base,
 620                                                   old_crtc_state, NULL);
 621
 622         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 623                     intel_dp->active_mst_links);
 624 }
 625
 626 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
 627                                         struct intel_encoder *encoder,
 628                                         const struct intel_crtc_state *pipe_config,
 629                                         const struct drm_connector_state *conn_state)
 630 {
 631         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 632         struct intel_digital_port *dig_port = intel_mst->primary;
 633         struct intel_dp *intel_dp = &dig_port->dp;
 634
 635         if (intel_dp->active_mst_links == 0)
 636                 dig_port->base.pre_pll_enable(state, &dig_port->base,
 637                                                     pipe_config, NULL);
 638 }
 639
 640 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 641                                     struct intel_encoder *encoder,
 642                                     const struct intel_crtc_state *pipe_config,
 643                                     const struct drm_connector_state *conn_state)
 644 {
 645         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 646         struct intel_digital_port *dig_port = intel_mst->primary;
 647         struct intel_dp *intel_dp = &dig_port->dp;
 648         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 649         struct intel_connector *connector =
 650                 to_intel_connector(conn_state->connector);
 651         struct drm_dp_mst_topology_state *mst_state =
 652                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 653         int ret;
 654         bool first_mst_stream;
 655
 656         /* MST encoders are bound to a crtc, not to a connector,
 657          * force the mapping here for get_hw_state.
 658          */
 659         connector->encoder = encoder;
 660         intel_mst->connector = connector;
 661         first_mst_stream = intel_dp->active_mst_links == 0;
 662         drm_WARN_ON(&dev_priv->drm,
 663                     DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
 664                     !intel_dp_mst_is_master_trans(pipe_config));
 665
 666         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 667                     intel_dp->active_mst_links);
 668
 669         if (first_mst_stream)
 670                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 671
 672         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 673
 674         if (first_mst_stream)
 675                 dig_port->base.pre_enable(state, &dig_port->base,
 676                                                 pipe_config, NULL);
 677
 678         intel_dp->active_mst_links++;
 679
 680         ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
 681                                        drm_atomic_get_mst_payload_state(mst_state, connector->port));
 682         if (ret < 0)
 683                 drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
 684                         connector->base.name, ret);
 685
 686         /*
 687          * Before Gen 12 this is not done as part of
 688          * dig_port->base.pre_enable() and should be done here. For
 689          * Gen 12+ the step in which this should be done is different for the
 690          * first MST stream, so it's done on the DDI for the first stream and
 691          * here for the following ones.
 692          */
 693         if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
 694                 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
 695
 696         intel_ddi_set_dp_msa(pipe_config, conn_state);
 697 }
 698
 699 static void intel_mst_enable_dp(struct intel_atomic_state *state,
 700                                 struct intel_encoder *encoder,
 701                                 const struct intel_crtc_state *pipe_config,
 702                                 const struct drm_connector_state *conn_state)
 703 {
 704         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 705         struct intel_digital_port *dig_port = intel_mst->primary;
 706         struct intel_dp *intel_dp = &dig_port->dp;
 707         struct intel_connector *connector = to_intel_connector(conn_state->connector);
 708         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 709         struct drm_dp_mst_topology_state *mst_state =
 710                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 711         enum transcoder trans = pipe_config->cpu_transcoder;
 712
 713         drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
 714
 715         clear_act_sent(encoder, pipe_config);
 716
 717         if (intel_dp_is_uhbr(pipe_config)) {
 718                 const struct drm_display_mode *adjusted_mode =
 719                         &pipe_config->hw.adjusted_mode;
 720                 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
 721
 722                 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
 723                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
 724                 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
 725                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
 726         }
 727
 728         intel_ddi_enable_transcoder_func(encoder, pipe_config);
 729
 730         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
 731                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 732
 733         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 734                     intel_dp->active_mst_links);
 735
 736         wait_for_act_sent(encoder, pipe_config);
 737
 738         drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
 739                                  drm_atomic_get_mst_payload_state(mst_state, connector->port));
 740
 741         if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
 742                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
 743                              FECSTALL_DIS_DPTSTREAM_DPTTG);
 744         else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
 745                 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
 746                              FECSTALL_DIS_DPTSTREAM_DPTTG);
 747
 748         intel_enable_transcoder(pipe_config);
 749
 750         intel_crtc_vblank_on(pipe_config);
 751
 752         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 753
 754         /* Enable hdcp if it's desired */
 755         if (conn_state->content_protection ==
 756             DRM_MODE_CONTENT_PROTECTION_DESIRED)
 757                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
 758                                   pipe_config,
 759                                   (u8)conn_state->hdcp_content_type);
 760 }
 761
 762 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
 763                                       enum pipe *pipe)
 764 {
 765         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 766         *pipe = intel_mst->pipe;
 767         if (intel_mst->connector)
 768                 return true;
 769         return false;
 770 }
 771
 772 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 773                                         struct intel_crtc_state *pipe_config)
 774 {
 775         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 776         struct intel_digital_port *dig_port = intel_mst->primary;
 777
 778         dig_port->base.get_config(&dig_port->base, pipe_config);
 779 }
 780
 781 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
 782                                                struct intel_crtc_state *crtc_state)
 783 {
 784         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 785         struct intel_digital_port *dig_port = intel_mst->primary;
 786
 787         return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
 788 }
 789
 790 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
 791 {
 792         struct intel_connector *intel_connector = to_intel_connector(connector);
 793         struct intel_dp *intel_dp = intel_connector->mst_port;
 794         struct edid *edid;
 795         int ret;
 796
 797         if (drm_connector_is_unregistered(connector))
 798                 return intel_connector_update_modes(connector, NULL);
 799
 800         edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port);
 801         ret = intel_connector_update_modes(connector, edid);
 802         kfree(edid);
 803
 804         return ret;
 805 }
 806
 807 static int
 808 intel_dp_mst_connector_late_register(struct drm_connector *connector)
 809 {
 810         struct intel_connector *intel_connector = to_intel_connector(connector);
 811         int ret;
 812
 813         ret = drm_dp_mst_connector_late_register(connector,
 814                                                  intel_connector->port);
 815         if (ret < 0)
 816                 return ret;
 817
 818         ret = intel_connector_register(connector);
 819         if (ret < 0)
 820                 drm_dp_mst_connector_early_unregister(connector,
 821                                                       intel_connector->port);
 822
 823         return ret;
 824 }
 825
 826 static void
 827 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
 828 {
 829         struct intel_connector *intel_connector = to_intel_connector(connector);
 830
 831         intel_connector_unregister(connector);
 832         drm_dp_mst_connector_early_unregister(connector,
 833                                               intel_connector->port);
 834 }
 835
 836 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
 837         .fill_modes = drm_helper_probe_single_connector_modes,
 838         .atomic_get_property = intel_digital_connector_atomic_get_property,
 839         .atomic_set_property = intel_digital_connector_atomic_set_property,
 840         .late_register = intel_dp_mst_connector_late_register,
 841         .early_unregister = intel_dp_mst_connector_early_unregister,
 842         .destroy = intel_connector_destroy,
 843         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 844         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 845 };
 846
 847 static int intel_dp_mst_get_modes(struct drm_connector *connector)
 848 {
 849         return intel_dp_mst_get_ddc_modes(connector);
 850 }
 851
 852 static int
 853 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 854                             struct drm_display_mode *mode,
 855                             struct drm_modeset_acquire_ctx *ctx,
 856                             enum drm_mode_status *status)
 857 {
 858         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 859         struct intel_connector *intel_connector = to_intel_connector(connector);
 860         struct intel_dp *intel_dp = intel_connector->mst_port;
 861         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 862         struct drm_dp_mst_port *port = intel_connector->port;
 863         const int min_bpp = 18;
 864         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 865         int max_rate, mode_rate, max_lanes, max_link_clock;
 866         int ret;
 867         bool dsc = false, bigjoiner = false;
 868         u16 dsc_max_output_bpp = 0;
 869         u8 dsc_slice_count = 0;
 870         int target_clock = mode->clock;
 871
 872         if (drm_connector_is_unregistered(connector)) {
 873                 *status = MODE_ERROR;
 874                 return 0;
 875         }
 876
 877         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 878                 *status = MODE_NO_DBLESCAN;
 879                 return 0;
 880         }
 881
 882         max_link_clock = intel_dp_max_link_rate(intel_dp);
 883         max_lanes = intel_dp_max_lane_count(intel_dp);
 884
 885         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 886         mode_rate = intel_dp_link_required(mode->clock, min_bpp);
 887
 888         ret = drm_modeset_lock(&mgr->base.lock, ctx);
 889         if (ret)
 890                 return ret;
 891
 892         if (mode_rate > max_rate || mode->clock > max_dotclk ||
 893             drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
 894                 *status = MODE_CLOCK_HIGH;
 895                 return 0;
 896         }
 897
 898         if (mode->clock < 10000) {
 899                 *status = MODE_CLOCK_LOW;
 900                 return 0;
 901         }
 902
 903         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 904                 *status = MODE_H_ILLEGAL;
 905                 return 0;
 906         }
 907
 908         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 909                 bigjoiner = true;
 910                 max_dotclk *= 2;
 911         }
 912
 913         if (DISPLAY_VER(dev_priv) >= 10 &&
 914             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 915                 /*
 916                  * TBD pass the connector BPC,
 917                  * for now U8_MAX so that max BPC on that platform would be picked
 918                  */
 919                 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
 920
 921                 if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 922                         dsc_max_output_bpp =
 923                                 intel_dp_dsc_get_output_bpp(dev_priv,
 924                                                             max_link_clock,
 925                                                             max_lanes,
 926                                                             target_clock,
 927                                                             mode->hdisplay,
 928                                                             bigjoiner,
 929                                                             pipe_bpp, 64) >> 4;
 930                         dsc_slice_count =
 931                                 intel_dp_dsc_get_slice_count(intel_dp,
 932                                                              target_clock,
 933                                                              mode->hdisplay,
 934                                                              bigjoiner);
 935                 }
 936
 937                 dsc = dsc_max_output_bpp && dsc_slice_count;
 938         }
 939
 940         /*
 941          * Big joiner configuration needs DSC for TGL which is not true for
 942          * XE_LPD where uncompressed joiner is supported.
 943          */
 944         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
 945                 return MODE_CLOCK_HIGH;
 946
 947         if (mode_rate > max_rate && !dsc)
 948                 return MODE_CLOCK_HIGH;
 949
 950         *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
 951         return 0;
 952 }
 953
 954 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
 955                                                          struct drm_atomic_state *state)
 956 {
 957         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
 958                                                                                          connector);
 959         struct intel_connector *intel_connector = to_intel_connector(connector);
 960         struct intel_dp *intel_dp = intel_connector->mst_port;
 961         struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
 962
 963         return &intel_dp->mst_encoders[crtc->pipe]->base.base;
 964 }
 965
 966 static int
 967 intel_dp_mst_detect(struct drm_connector *connector,
 968                     struct drm_modeset_acquire_ctx *ctx, bool force)
 969 {
 970         struct drm_i915_private *i915 = to_i915(connector->dev);
 971         struct intel_connector *intel_connector = to_intel_connector(connector);
 972         struct intel_dp *intel_dp = intel_connector->mst_port;
 973
 974         if (!INTEL_DISPLAY_ENABLED(i915))
 975                 return connector_status_disconnected;
 976
 977         if (drm_connector_is_unregistered(connector))
 978                 return connector_status_disconnected;
 979
 980         return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
 981                                       intel_connector->port);
 982 }
 983
 984 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
 985         .get_modes = intel_dp_mst_get_modes,
 986         .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
 987         .atomic_best_encoder = intel_mst_atomic_best_encoder,
 988         .atomic_check = intel_dp_mst_atomic_check,
 989         .detect_ctx = intel_dp_mst_detect,
 990 };
 991
 992 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 993 {
 994         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
 995
 996         drm_encoder_cleanup(encoder);
 997         kfree(intel_mst);
 998 }
 999
1000 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1001         .destroy = intel_dp_mst_encoder_destroy,
1002 };
1003
1004 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1005 {
1006         if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1007                 enum pipe pipe;
1008                 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1009                         return false;
1010                 return true;
1011         }
1012         return false;
1013 }
1014
1015 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1016                                        struct drm_connector *connector,
1017                                        const char *pathprop)
1018 {
1019         struct drm_i915_private *i915 = to_i915(connector->dev);
1020
1021         drm_object_attach_property(&connector->base,
1022                                    i915->drm.mode_config.path_property, 0);
1023         drm_object_attach_property(&connector->base,
1024                                    i915->drm.mode_config.tile_property, 0);
1025
1026         intel_attach_force_audio_property(connector);
1027         intel_attach_broadcast_rgb_property(connector);
1028
1029         /*
1030          * Reuse the prop from the SST connector because we're
1031          * not allowed to create new props after device registration.
1032          */
1033         connector->max_bpc_property =
1034                 intel_dp->attached_connector->base.max_bpc_property;
1035         if (connector->max_bpc_property)
1036                 drm_connector_attach_max_bpc_property(connector, 6, 12);
1037
1038         return drm_connector_set_path_property(connector, pathprop);
1039 }
1040
1041 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1042                                                         struct drm_dp_mst_port *port,
1043                                                         const char *pathprop)
1044 {
1045         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1046         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1047         struct drm_device *dev = dig_port->base.base.dev;
1048         struct drm_i915_private *dev_priv = to_i915(dev);
1049         struct intel_connector *intel_connector;
1050         struct drm_connector *connector;
1051         enum pipe pipe;
1052         int ret;
1053
1054         intel_connector = intel_connector_alloc();
1055         if (!intel_connector)
1056                 return NULL;
1057
1058         intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1059         intel_connector->mst_port = intel_dp;
1060         intel_connector->port = port;
1061         drm_dp_mst_get_port_malloc(port);
1062
1063         connector = &intel_connector->base;
1064         ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1065                                  DRM_MODE_CONNECTOR_DisplayPort);
1066         if (ret) {
1067                 drm_dp_mst_put_port_malloc(port);
1068                 intel_connector_free(intel_connector);
1069                 return NULL;
1070         }
1071
1072         drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1073
1074         for_each_pipe(dev_priv, pipe) {
1075                 struct drm_encoder *enc =
1076                         &intel_dp->mst_encoders[pipe]->base.base;
1077
1078                 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1079                 if (ret)
1080                         goto err;
1081         }
1082
1083         ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1084         if (ret)
1085                 goto err;
1086
1087         ret = intel_dp_hdcp_init(dig_port, intel_connector);
1088         if (ret)
1089                 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1090                             connector->name, connector->base.id);
1091
1092         return connector;
1093
1094 err:
1095         drm_connector_cleanup(connector);
1096         return NULL;
1097 }
1098
1099 static void
1100 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1101 {
1102         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1103
1104         intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1105 }
1106
1107 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1108         .add_connector = intel_dp_add_mst_connector,
1109         .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1110 };
1111
1112 static struct intel_dp_mst_encoder *
1113 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1114 {
1115         struct intel_dp_mst_encoder *intel_mst;
1116         struct intel_encoder *intel_encoder;
1117         struct drm_device *dev = dig_port->base.base.dev;
1118
1119         intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1120
1121         if (!intel_mst)
1122                 return NULL;
1123
1124         intel_mst->pipe = pipe;
1125         intel_encoder = &intel_mst->base;
1126         intel_mst->primary = dig_port;
1127
1128         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1129                          DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1130
1131         intel_encoder->type = INTEL_OUTPUT_DP_MST;
1132         intel_encoder->power_domain = dig_port->base.power_domain;
1133         intel_encoder->port = dig_port->base.port;
1134         intel_encoder->cloneable = 0;
1135         /*
1136          * This is wrong, but broken userspace uses the intersection
1137          * of possible_crtcs of all the encoders of a given connector
1138          * to figure out which crtcs can drive said connector. What
1139          * should be used instead is the union of possible_crtcs.
1140          * To keep such userspace functioning we must misconfigure
1141          * this to make sure the intersection is not empty :(
1142          */
1143         intel_encoder->pipe_mask = ~0;
1144
1145         intel_encoder->compute_config = intel_dp_mst_compute_config;
1146         intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1147         intel_encoder->disable = intel_mst_disable_dp;
1148         intel_encoder->post_disable = intel_mst_post_disable_dp;
1149         intel_encoder->update_pipe = intel_ddi_update_pipe;
1150         intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1151         intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1152         intel_encoder->enable = intel_mst_enable_dp;
1153         intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1154         intel_encoder->get_config = intel_dp_mst_enc_get_config;
1155         intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1156
1157         return intel_mst;
1158
1159 }
1160
1161 static bool
1162 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1163 {
1164         struct intel_dp *intel_dp = &dig_port->dp;
1165         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1166         enum pipe pipe;
1167
1168         for_each_pipe(dev_priv, pipe)
1169                 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1170         return true;
1171 }
1172
1173 int
1174 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1175 {
1176         return dig_port->dp.active_mst_links;
1177 }
1178
1179 int
1180 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1181 {
1182         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1183         struct intel_dp *intel_dp = &dig_port->dp;
1184         enum port port = dig_port->base.port;
1185         int ret;
1186
1187         if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1188                 return 0;
1189
1190         if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1191                 return 0;
1192
1193         if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1194                 return 0;
1195
1196         intel_dp->mst_mgr.cbs = &mst_cbs;
1197
1198         /* create encoders */
1199         intel_dp_create_fake_mst_encoders(dig_port);
1200         ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1201                                            &intel_dp->aux, 16, 3, conn_base_id);
1202         if (ret) {
1203                 intel_dp->mst_mgr.cbs = NULL;
1204                 return ret;
1205         }
1206
1207         return 0;
1208 }
1209
1210 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1211 {
1212         return intel_dp->mst_mgr.cbs;
1213 }
1214
1215 void
1216 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1217 {
1218         struct intel_dp *intel_dp = &dig_port->dp;
1219
1220         if (!intel_dp_mst_source_support(intel_dp))
1221                 return;
1222
1223         drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1224         /* encoders will get killed by normal cleanup */
1225
1226         intel_dp->mst_mgr.cbs = NULL;
1227 }
1228
1229 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1230 {
1231         return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1232 }
1233
1234 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1235 {
1236         return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1237                crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1238 }
1239
1240 /**
1241  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1242  * @state: atomic state
1243  * @connector: connector to add the state for
1244  * @crtc: the CRTC @connector is attached to
1245  *
1246  * Add the MST topology state for @connector to @state.
1247  *
1248  * Returns 0 on success, negative error code on failure.
1249  */
1250 static int
1251 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1252                                               struct intel_connector *connector,
1253                                               struct intel_crtc *crtc)
1254 {
1255         struct drm_dp_mst_topology_state *mst_state;
1256
1257         if (!connector->mst_port)
1258                 return 0;
1259
1260         mst_state = drm_atomic_get_mst_topology_state(&state->base,
1261                                                       &connector->mst_port->mst_mgr);
1262         if (IS_ERR(mst_state))
1263                 return PTR_ERR(mst_state);
1264
1265         mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1266
1267         return 0;
1268 }
1269
1270 /**
1271  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1272  * @state: atomic state
1273  * @crtc: CRTC to add the state for
1274  *
1275  * Add the MST topology state for @crtc to @state.
1276  *
1277  * Returns 0 on success, negative error code on failure.
1278  */
1279 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1280                                              struct intel_crtc *crtc)
1281 {
1282         struct drm_connector *_connector;
1283         struct drm_connector_state *conn_state;
1284         int i;
1285
1286         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1287                 struct intel_connector *connector = to_intel_connector(_connector);
1288                 int ret;
1289
1290                 if (conn_state->crtc != &crtc->base)
1291                         continue;
1292
1293                 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1294                 if (ret)
1295                         return ret;
1296         }
1297
1298         return 0;
1299 }