drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 114
 115 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 121 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 123 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 125 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 127 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 129 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 131 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 134
 135 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 137 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 139 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 141 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 143 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 145 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 147
 148 #define mmCPG_PSP_DEBUG                         0x5c10
 149 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 150 #define mmCPC_PSP_DEBUG                         0x5c11
 151 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 154
 155 //CC_GC_SA_UNIT_DISABLE
 156 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 160 //GC_USER_SA_UNIT_DISABLE
 161 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 165 //PA_SC_ENHANCE_3
 166 #define mmPA_SC_ENHANCE_3                       0x1085
 167 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 170
 171 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 173
 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 178
 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 181
 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 184
 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 191
 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 203
 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 210
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 217
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 224
 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 231
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 238
 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 245
 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 252
 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 259
 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 266
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 273
 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 275 {
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 316 };
 317
 318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 319 {
 320         /* Pending on emulation bring up */
 321 };
 322
 323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 324 {
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 };
1378
1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 {
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 };
1420
1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 {
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 {
1469         /* Pending on emulation bring up */
1470 };
1471
1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 {
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 };
2095
2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 {
2098         /* Pending on emulation bring up */
2099 };
2100
2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 {
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 };
3156
3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 {
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 };
3203
3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 {
3206         /* Pending on emulation bring up */
3207 };
3208
3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 {
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252
3253         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3255 };
3256
3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 {
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283
3284         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3286 };
3287
3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 {
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 };
3311
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 {
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3350 };
3351
3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 };
3386
3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 };
3423
3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 {
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 };
3449
3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 };
3474
3475 #define DEFAULT_SH_MEM_CONFIG \
3476         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480
3481 /* TODO: pending on golden setting value of gb address config */
3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483
3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490                                  struct amdgpu_cu_info *cu_info);
3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493                                    u32 sh_num, u32 instance);
3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495
3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507                                            uint16_t pasid, uint32_t flush_type,
3508                                            bool all_hub, uint8_t dst_sel);
3509
3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511 {
3512         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3513         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3514                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3515         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3516         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3517         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3518         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3519         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3520         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3521 }
3522
3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524                                  struct amdgpu_ring *ring)
3525 {
3526         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527         uint64_t wptr_addr = ring->wptr_gpu_addr;
3528         uint32_t eng_sel = 0;
3529
3530         switch (ring->funcs->type) {
3531         case AMDGPU_RING_TYPE_COMPUTE:
3532                 eng_sel = 0;
3533                 break;
3534         case AMDGPU_RING_TYPE_GFX:
3535                 eng_sel = 4;
3536                 break;
3537         case AMDGPU_RING_TYPE_MES:
3538                 eng_sel = 5;
3539                 break;
3540         default:
3541                 WARN_ON(1);
3542         }
3543
3544         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3545         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3548                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3549                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3550                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3551                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3552                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3553                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3554                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3555                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3556         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3557         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3558         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3559         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3560         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3561 }
3562
3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564                                    struct amdgpu_ring *ring,
3565                                    enum amdgpu_unmap_queues_action action,
3566                                    u64 gpu_addr, u64 seq)
3567 {
3568         struct amdgpu_device *adev = kiq_ring->adev;
3569         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570
3571         if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573                 return;
3574         }
3575
3576         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3577         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3579                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3580                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3581                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3582         amdgpu_ring_write(kiq_ring,
3583                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3584
3585         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3587                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3588                 amdgpu_ring_write(kiq_ring, seq);
3589         } else {
3590                 amdgpu_ring_write(kiq_ring, 0);
3591                 amdgpu_ring_write(kiq_ring, 0);
3592                 amdgpu_ring_write(kiq_ring, 0);
3593         }
3594 }
3595
3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597                                    struct amdgpu_ring *ring,
3598                                    u64 addr,
3599                                    u64 seq)
3600 {
3601         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602
3603         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3604         amdgpu_ring_write(kiq_ring,
3605                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3606                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3607                           PACKET3_QUERY_STATUS_COMMAND(2));
3608         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3610                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3611         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3612         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3613         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3614         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3615 }
3616
3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618                                 uint16_t pasid, uint32_t flush_type,
3619                                 bool all_hub)
3620 {
3621         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622 }
3623
3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625         .kiq_set_resources = gfx10_kiq_set_resources,
3626         .kiq_map_queues = gfx10_kiq_map_queues,
3627         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628         .kiq_query_status = gfx10_kiq_query_status,
3629         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630         .set_resources_size = 8,
3631         .map_queues_size = 7,
3632         .unmap_queues_size = 6,
3633         .query_status_size = 7,
3634         .invalidate_tlbs_size = 2,
3635 };
3636
3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638 {
3639         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640 }
3641
3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643 {
3644         switch (adev->ip_versions[GC_HWIP][0]) {
3645         case IP_VERSION(10, 1, 10):
3646                 soc15_program_register_sequence(adev,
3647                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3648                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3649                 break;
3650         case IP_VERSION(10, 1, 1):
3651                 soc15_program_register_sequence(adev,
3652                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3653                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3654                 break;
3655         case IP_VERSION(10, 1, 2):
3656                 soc15_program_register_sequence(adev,
3657                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3658                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3659                 break;
3660         default:
3661                 break;
3662         }
3663 }
3664
3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666 {
3667         switch (adev->ip_versions[GC_HWIP][0]) {
3668         case IP_VERSION(10, 1, 10):
3669                 soc15_program_register_sequence(adev,
3670                                                 golden_settings_gc_10_1,
3671                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3672                 soc15_program_register_sequence(adev,
3673                                                 golden_settings_gc_10_0_nv10,
3674                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3675                 break;
3676         case IP_VERSION(10, 1, 1):
3677                 soc15_program_register_sequence(adev,
3678                                                 golden_settings_gc_10_1_1,
3679                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3680                 soc15_program_register_sequence(adev,
3681                                                 golden_settings_gc_10_1_nv14,
3682                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3683                 break;
3684         case IP_VERSION(10, 1, 2):
3685                 soc15_program_register_sequence(adev,
3686                                                 golden_settings_gc_10_1_2,
3687                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3688                 soc15_program_register_sequence(adev,
3689                                                 golden_settings_gc_10_1_2_nv12,
3690                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3691                 break;
3692         case IP_VERSION(10, 3, 0):
3693                 soc15_program_register_sequence(adev,
3694                                                 golden_settings_gc_10_3,
3695                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3696                 soc15_program_register_sequence(adev,
3697                                                 golden_settings_gc_10_3_sienna_cichlid,
3698                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3699                 break;
3700         case IP_VERSION(10, 3, 2):
3701                 soc15_program_register_sequence(adev,
3702                                                 golden_settings_gc_10_3_2,
3703                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3704                 break;
3705         case IP_VERSION(10, 3, 1):
3706                 soc15_program_register_sequence(adev,
3707                                                 golden_settings_gc_10_3_vangogh,
3708                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3709                 break;
3710         case IP_VERSION(10, 3, 3):
3711                 soc15_program_register_sequence(adev,
3712                                                 golden_settings_gc_10_3_3,
3713                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3714                 break;
3715         case IP_VERSION(10, 3, 4):
3716                 soc15_program_register_sequence(adev,
3717                                                 golden_settings_gc_10_3_4,
3718                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3719                 break;
3720         case IP_VERSION(10, 3, 5):
3721                 soc15_program_register_sequence(adev,
3722                                                 golden_settings_gc_10_3_5,
3723                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3724                 break;
3725         case IP_VERSION(10, 1, 3):
3726         case IP_VERSION(10, 1, 4):
3727                 soc15_program_register_sequence(adev,
3728                                                 golden_settings_gc_10_0_cyan_skillfish,
3729                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3730                 break;
3731         case IP_VERSION(10, 3, 6):
3732                 soc15_program_register_sequence(adev,
3733                                                 golden_settings_gc_10_3_6,
3734                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3735                 break;
3736         case IP_VERSION(10, 3, 7):
3737                 soc15_program_register_sequence(adev,
3738                                                 golden_settings_gc_10_3_7,
3739                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3740                 break;
3741         default:
3742                 break;
3743         }
3744         gfx_v10_0_init_spm_golden_registers(adev);
3745 }
3746
3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748                                        bool wc, uint32_t reg, uint32_t val)
3749 {
3750         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3752                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3753         amdgpu_ring_write(ring, reg);
3754         amdgpu_ring_write(ring, 0);
3755         amdgpu_ring_write(ring, val);
3756 }
3757
3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759                                   int mem_space, int opt, uint32_t addr0,
3760                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3761                                   uint32_t inv)
3762 {
3763         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3764         amdgpu_ring_write(ring,
3765                           /* memory (1) or register (0) */
3766                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3767                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3768                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3769                            WAIT_REG_MEM_ENGINE(eng_sel)));
3770
3771         if (mem_space)
3772                 BUG_ON(addr0 & 0x3); /* Dword align */
3773         amdgpu_ring_write(ring, addr0);
3774         amdgpu_ring_write(ring, addr1);
3775         amdgpu_ring_write(ring, ref);
3776         amdgpu_ring_write(ring, mask);
3777         amdgpu_ring_write(ring, inv); /* poll interval */
3778 }
3779
3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781 {
3782         struct amdgpu_device *adev = ring->adev;
3783         uint32_t tmp = 0;
3784         unsigned i;
3785         int r;
3786
3787         WREG32_SOC15(GC, 0, mmSCRATCH_REG0, 0xCAFEDEAD);
3788         r = amdgpu_ring_alloc(ring, 3);
3789         if (r) {
3790                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3791                           ring->idx, r);
3792                 return r;
3793         }
3794
3795         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3796         amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0) -
3797                           PACKET3_SET_UCONFIG_REG_START);
3798         amdgpu_ring_write(ring, 0xDEADBEEF);
3799         amdgpu_ring_commit(ring);
3800
3801         for (i = 0; i < adev->usec_timeout; i++) {
3802                 tmp = RREG32_SOC15(GC, 0, mmSCRATCH_REG0);
3803                 if (tmp == 0xDEADBEEF)
3804                         break;
3805                 if (amdgpu_emu_mode == 1)
3806                         msleep(1);
3807                 else
3808                         udelay(1);
3809         }
3810
3811         if (i >= adev->usec_timeout)
3812                 r = -ETIMEDOUT;
3813
3814         return r;
3815 }
3816
3817 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3818 {
3819         struct amdgpu_device *adev = ring->adev;
3820         struct amdgpu_ib ib;
3821         struct dma_fence *f = NULL;
3822         unsigned index;
3823         uint64_t gpu_addr;
3824         volatile uint32_t *cpu_ptr;
3825         long r;
3826
3827         memset(&ib, 0, sizeof(ib));
3828
3829         if (ring->is_mes_queue) {
3830                 uint32_t padding, offset;
3831
3832                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3833                 padding = amdgpu_mes_ctx_get_offs(ring,
3834                                                   AMDGPU_MES_CTX_PADDING_OFFS);
3835
3836                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3837                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3838
3839                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3840                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3841                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3842         } else {
3843                 r = amdgpu_device_wb_get(adev, &index);
3844                 if (r)
3845                         return r;
3846
3847                 gpu_addr = adev->wb.gpu_addr + (index * 4);
3848                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3849                 cpu_ptr = &adev->wb.wb[index];
3850
3851                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3852                 if (r) {
3853                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3854                         goto err1;
3855                 }
3856         }
3857
3858         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3859         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3860         ib.ptr[2] = lower_32_bits(gpu_addr);
3861         ib.ptr[3] = upper_32_bits(gpu_addr);
3862         ib.ptr[4] = 0xDEADBEEF;
3863         ib.length_dw = 5;
3864
3865         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3866         if (r)
3867                 goto err2;
3868
3869         r = dma_fence_wait_timeout(f, false, timeout);
3870         if (r == 0) {
3871                 r = -ETIMEDOUT;
3872                 goto err2;
3873         } else if (r < 0) {
3874                 goto err2;
3875         }
3876
3877         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3878                 r = 0;
3879         else
3880                 r = -EINVAL;
3881 err2:
3882         if (!ring->is_mes_queue)
3883                 amdgpu_ib_free(adev, &ib, NULL);
3884         dma_fence_put(f);
3885 err1:
3886         if (!ring->is_mes_queue)
3887                 amdgpu_device_wb_free(adev, index);
3888         return r;
3889 }
3890
3891 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3892 {
3893         release_firmware(adev->gfx.pfp_fw);
3894         adev->gfx.pfp_fw = NULL;
3895         release_firmware(adev->gfx.me_fw);
3896         adev->gfx.me_fw = NULL;
3897         release_firmware(adev->gfx.ce_fw);
3898         adev->gfx.ce_fw = NULL;
3899         release_firmware(adev->gfx.rlc_fw);
3900         adev->gfx.rlc_fw = NULL;
3901         release_firmware(adev->gfx.mec_fw);
3902         adev->gfx.mec_fw = NULL;
3903         release_firmware(adev->gfx.mec2_fw);
3904         adev->gfx.mec2_fw = NULL;
3905
3906         kfree(adev->gfx.rlc.register_list_format);
3907 }
3908
3909 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3910 {
3911         adev->gfx.cp_fw_write_wait = false;
3912
3913         switch (adev->ip_versions[GC_HWIP][0]) {
3914         case IP_VERSION(10, 1, 10):
3915         case IP_VERSION(10, 1, 2):
3916         case IP_VERSION(10, 1, 1):
3917         case IP_VERSION(10, 1, 3):
3918         case IP_VERSION(10, 1, 4):
3919                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3920                     (adev->gfx.me_feature_version >= 27) &&
3921                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3922                     (adev->gfx.pfp_feature_version >= 27) &&
3923                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3924                     (adev->gfx.mec_feature_version >= 27))
3925                         adev->gfx.cp_fw_write_wait = true;
3926                 break;
3927         case IP_VERSION(10, 3, 0):
3928         case IP_VERSION(10, 3, 2):
3929         case IP_VERSION(10, 3, 1):
3930         case IP_VERSION(10, 3, 4):
3931         case IP_VERSION(10, 3, 5):
3932         case IP_VERSION(10, 3, 6):
3933         case IP_VERSION(10, 3, 3):
3934         case IP_VERSION(10, 3, 7):
3935                 adev->gfx.cp_fw_write_wait = true;
3936                 break;
3937         default:
3938                 break;
3939         }
3940
3941         if (!adev->gfx.cp_fw_write_wait)
3942                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3943 }
3944
3945
3946 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3947 {
3948         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3949
3950         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3951         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3952         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3953         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3954         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3955         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3956         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3957         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3958         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3959         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3960         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3961         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3962         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3963         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3964                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3965 }
3966
3967 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3968 {
3969         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3970
3971         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3972         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3973         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3974         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3975         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3976 }
3977
3978 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3979 {
3980         bool ret = false;
3981
3982         switch (adev->pdev->revision) {
3983         case 0xc2:
3984         case 0xc3:
3985                 ret = true;
3986                 break;
3987         default:
3988                 ret = false;
3989                 break;
3990         }
3991
3992         return ret ;
3993 }
3994
3995 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3996 {
3997         switch (adev->ip_versions[GC_HWIP][0]) {
3998         case IP_VERSION(10, 1, 10):
3999                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4000                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4001                 break;
4002         default:
4003                 break;
4004         }
4005 }
4006
4007 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4008 {
4009         const char *chip_name;
4010         char fw_name[40];
4011         char *wks = "";
4012         int err;
4013         struct amdgpu_firmware_info *info = NULL;
4014         const struct common_firmware_header *header = NULL;
4015         const struct gfx_firmware_header_v1_0 *cp_hdr;
4016         const struct rlc_firmware_header_v2_0 *rlc_hdr;
4017         unsigned int *tmp = NULL;
4018         unsigned int i = 0;
4019         uint16_t version_major;
4020         uint16_t version_minor;
4021
4022         DRM_DEBUG("\n");
4023
4024         switch (adev->ip_versions[GC_HWIP][0]) {
4025         case IP_VERSION(10, 1, 10):
4026                 chip_name = "navi10";
4027                 break;
4028         case IP_VERSION(10, 1, 1):
4029                 chip_name = "navi14";
4030                 if (!(adev->pdev->device == 0x7340 &&
4031                       adev->pdev->revision != 0x00))
4032                         wks = "_wks";
4033                 break;
4034         case IP_VERSION(10, 1, 2):
4035                 chip_name = "navi12";
4036                 break;
4037         case IP_VERSION(10, 3, 0):
4038                 chip_name = "sienna_cichlid";
4039                 break;
4040         case IP_VERSION(10, 3, 2):
4041                 chip_name = "navy_flounder";
4042                 break;
4043         case IP_VERSION(10, 3, 1):
4044                 chip_name = "vangogh";
4045                 break;
4046         case IP_VERSION(10, 3, 4):
4047                 chip_name = "dimgrey_cavefish";
4048                 break;
4049         case IP_VERSION(10, 3, 5):
4050                 chip_name = "beige_goby";
4051                 break;
4052         case IP_VERSION(10, 3, 3):
4053                 chip_name = "yellow_carp";
4054                 break;
4055         case IP_VERSION(10, 3, 6):
4056                 chip_name = "gc_10_3_6";
4057                 break;
4058         case IP_VERSION(10, 1, 3):
4059         case IP_VERSION(10, 1, 4):
4060                 chip_name = "cyan_skillfish2";
4061                 break;
4062         case IP_VERSION(10, 3, 7):
4063                 chip_name = "gc_10_3_7";
4064                 break;
4065         default:
4066                 BUG();
4067         }
4068
4069         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4070         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4071         if (err)
4072                 goto out;
4073         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4074         if (err)
4075                 goto out;
4076         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4077         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4078         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4079
4080         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4081         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4082         if (err)
4083                 goto out;
4084         err = amdgpu_ucode_validate(adev->gfx.me_fw);
4085         if (err)
4086                 goto out;
4087         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4088         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4089         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4090
4091         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4092         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4093         if (err)
4094                 goto out;
4095         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4096         if (err)
4097                 goto out;
4098         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4099         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4100         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4101
4102         if (!amdgpu_sriov_vf(adev)) {
4103                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4104                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4105                 if (err)
4106                         goto out;
4107                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4108                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4109                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4110                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4111
4112                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4113                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4114                 adev->gfx.rlc.save_and_restore_offset =
4115                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4116                 adev->gfx.rlc.clear_state_descriptor_offset =
4117                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4118                 adev->gfx.rlc.avail_scratch_ram_locations =
4119                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4120                 adev->gfx.rlc.reg_restore_list_size =
4121                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4122                 adev->gfx.rlc.reg_list_format_start =
4123                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4124                 adev->gfx.rlc.reg_list_format_separate_start =
4125                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4126                 adev->gfx.rlc.starting_offsets_start =
4127                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4128                 adev->gfx.rlc.reg_list_format_size_bytes =
4129                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4130                 adev->gfx.rlc.reg_list_size_bytes =
4131                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4132                 adev->gfx.rlc.register_list_format =
4133                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4134                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4135                 if (!adev->gfx.rlc.register_list_format) {
4136                         err = -ENOMEM;
4137                         goto out;
4138                 }
4139
4140                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4141                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4142                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4143                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4144
4145                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4146
4147                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4148                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4149                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4150                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4151
4152                 if (version_major == 2) {
4153                         if (version_minor >= 1)
4154                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4155                         if (version_minor == 2)
4156                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4157                 }
4158         }
4159
4160         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4161         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4162         if (err)
4163                 goto out;
4164         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4165         if (err)
4166                 goto out;
4167         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4168         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4169         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4170
4171         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4172         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4173         if (!err) {
4174                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4175                 if (err)
4176                         goto out;
4177                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4178                 adev->gfx.mec2_fw->data;
4179                 adev->gfx.mec2_fw_version =
4180                 le32_to_cpu(cp_hdr->header.ucode_version);
4181                 adev->gfx.mec2_feature_version =
4182                 le32_to_cpu(cp_hdr->ucode_feature_version);
4183         } else {
4184                 err = 0;
4185                 adev->gfx.mec2_fw = NULL;
4186         }
4187
4188         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4189                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4190                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4191                 info->fw = adev->gfx.pfp_fw;
4192                 header = (const struct common_firmware_header *)info->fw->data;
4193                 adev->firmware.fw_size +=
4194                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4195
4196                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4197                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4198                 info->fw = adev->gfx.me_fw;
4199                 header = (const struct common_firmware_header *)info->fw->data;
4200                 adev->firmware.fw_size +=
4201                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4202
4203                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4204                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4205                 info->fw = adev->gfx.ce_fw;
4206                 header = (const struct common_firmware_header *)info->fw->data;
4207                 adev->firmware.fw_size +=
4208                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4209
4210                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4211                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4212                 info->fw = adev->gfx.rlc_fw;
4213                 if (info->fw) {
4214                         header = (const struct common_firmware_header *)info->fw->data;
4215                         adev->firmware.fw_size +=
4216                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4217                 }
4218                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4219                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4220                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4221                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4222                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4223                         info->fw = adev->gfx.rlc_fw;
4224                         adev->firmware.fw_size +=
4225                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4226
4227                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4228                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4229                         info->fw = adev->gfx.rlc_fw;
4230                         adev->firmware.fw_size +=
4231                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4232
4233                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4234                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4235                         info->fw = adev->gfx.rlc_fw;
4236                         adev->firmware.fw_size +=
4237                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4238
4239                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4240                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4241                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4242                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4243                                 info->fw = adev->gfx.rlc_fw;
4244                                 adev->firmware.fw_size +=
4245                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4246
4247                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4248                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4249                                 info->fw = adev->gfx.rlc_fw;
4250                                 adev->firmware.fw_size +=
4251                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4252                         }
4253                 }
4254
4255                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4256                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4257                 info->fw = adev->gfx.mec_fw;
4258                 header = (const struct common_firmware_header *)info->fw->data;
4259                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4260                 adev->firmware.fw_size +=
4261                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4262                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4263
4264                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4265                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4266                 info->fw = adev->gfx.mec_fw;
4267                 adev->firmware.fw_size +=
4268                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4269
4270                 if (adev->gfx.mec2_fw) {
4271                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4272                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4273                         info->fw = adev->gfx.mec2_fw;
4274                         header = (const struct common_firmware_header *)info->fw->data;
4275                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4276                         adev->firmware.fw_size +=
4277                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4278                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4279                                       PAGE_SIZE);
4280                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4281                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4282                         info->fw = adev->gfx.mec2_fw;
4283                         adev->firmware.fw_size +=
4284                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4285                                       PAGE_SIZE);
4286                 }
4287         }
4288
4289         gfx_v10_0_check_fw_write_wait(adev);
4290 out:
4291         if (err) {
4292                 dev_err(adev->dev,
4293                         "gfx10: Failed to load firmware \"%s\"\n",
4294                         fw_name);
4295                 release_firmware(adev->gfx.pfp_fw);
4296                 adev->gfx.pfp_fw = NULL;
4297                 release_firmware(adev->gfx.me_fw);
4298                 adev->gfx.me_fw = NULL;
4299                 release_firmware(adev->gfx.ce_fw);
4300                 adev->gfx.ce_fw = NULL;
4301                 release_firmware(adev->gfx.rlc_fw);
4302                 adev->gfx.rlc_fw = NULL;
4303                 release_firmware(adev->gfx.mec_fw);
4304                 adev->gfx.mec_fw = NULL;
4305                 release_firmware(adev->gfx.mec2_fw);
4306                 adev->gfx.mec2_fw = NULL;
4307         }
4308
4309         gfx_v10_0_check_gfxoff_flag(adev);
4310
4311         return err;
4312 }
4313
4314 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4315 {
4316         u32 count = 0;
4317         const struct cs_section_def *sect = NULL;
4318         const struct cs_extent_def *ext = NULL;
4319
4320         /* begin clear state */
4321         count += 2;
4322         /* context control state */
4323         count += 3;
4324
4325         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4326                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4327                         if (sect->id == SECT_CONTEXT)
4328                                 count += 2 + ext->reg_count;
4329                         else
4330                                 return 0;
4331                 }
4332         }
4333
4334         /* set PA_SC_TILE_STEERING_OVERRIDE */
4335         count += 3;
4336         /* end clear state */
4337         count += 2;
4338         /* clear state */
4339         count += 2;
4340
4341         return count;
4342 }
4343
4344 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4345                                     volatile u32 *buffer)
4346 {
4347         u32 count = 0, i;
4348         const struct cs_section_def *sect = NULL;
4349         const struct cs_extent_def *ext = NULL;
4350         int ctx_reg_offset;
4351
4352         if (adev->gfx.rlc.cs_data == NULL)
4353                 return;
4354         if (buffer == NULL)
4355                 return;
4356
4357         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4358         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4359
4360         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4361         buffer[count++] = cpu_to_le32(0x80000000);
4362         buffer[count++] = cpu_to_le32(0x80000000);
4363
4364         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4365                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4366                         if (sect->id == SECT_CONTEXT) {
4367                                 buffer[count++] =
4368                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4369                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4370                                                 PACKET3_SET_CONTEXT_REG_START);
4371                                 for (i = 0; i < ext->reg_count; i++)
4372                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4373                         } else {
4374                                 return;
4375                         }
4376                 }
4377         }
4378
4379         ctx_reg_offset =
4380                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4381         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4382         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4383         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4384
4385         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4386         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4387
4388         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4389         buffer[count++] = cpu_to_le32(0);
4390 }
4391
4392 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4393 {
4394         /* clear state block */
4395         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4396                         &adev->gfx.rlc.clear_state_gpu_addr,
4397                         (void **)&adev->gfx.rlc.cs_ptr);
4398
4399         /* jump table block */
4400         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4401                         &adev->gfx.rlc.cp_table_gpu_addr,
4402                         (void **)&adev->gfx.rlc.cp_table_ptr);
4403 }
4404
4405 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4406 {
4407         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4408
4409         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4410         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4411         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4412         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4413         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4414         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4415         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4416         switch (adev->ip_versions[GC_HWIP][0]) {
4417                 case IP_VERSION(10, 3, 0):
4418                         reg_access_ctrl->spare_int =
4419                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4420                         break;
4421                 default:
4422                         reg_access_ctrl->spare_int =
4423                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4424                         break;
4425         }
4426         adev->gfx.rlc.rlcg_reg_access_supported = true;
4427 }
4428
4429 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4430 {
4431         const struct cs_section_def *cs_data;
4432         int r;
4433
4434         adev->gfx.rlc.cs_data = gfx10_cs_data;
4435
4436         cs_data = adev->gfx.rlc.cs_data;
4437
4438         if (cs_data) {
4439                 /* init clear state block */
4440                 r = amdgpu_gfx_rlc_init_csb(adev);
4441                 if (r)
4442                         return r;
4443         }
4444
4445         /* init spm vmid with 0xf */
4446         if (adev->gfx.rlc.funcs->update_spm_vmid)
4447                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4448
4449
4450         return 0;
4451 }
4452
4453 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4454 {
4455         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4456         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4457 }
4458
4459 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4460 {
4461         int r;
4462
4463         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4464
4465         amdgpu_gfx_graphics_queue_acquire(adev);
4466
4467         r = gfx_v10_0_init_microcode(adev);
4468         if (r)
4469                 DRM_ERROR("Failed to load gfx firmware!\n");
4470
4471         return r;
4472 }
4473
4474 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4475 {
4476         int r;
4477         u32 *hpd;
4478         const __le32 *fw_data = NULL;
4479         unsigned fw_size;
4480         u32 *fw = NULL;
4481         size_t mec_hpd_size;
4482
4483         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4484
4485         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4486
4487         /* take ownership of the relevant compute queues */
4488         amdgpu_gfx_compute_queue_acquire(adev);
4489         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4490
4491         if (mec_hpd_size) {
4492                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4493                                               AMDGPU_GEM_DOMAIN_GTT,
4494                                               &adev->gfx.mec.hpd_eop_obj,
4495                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4496                                               (void **)&hpd);
4497                 if (r) {
4498                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4499                         gfx_v10_0_mec_fini(adev);
4500                         return r;
4501                 }
4502
4503                 memset(hpd, 0, mec_hpd_size);
4504
4505                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4506                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4507         }
4508
4509         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4510                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4511
4512                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4513                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4514                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4515
4516                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4517                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4518                                               &adev->gfx.mec.mec_fw_obj,
4519                                               &adev->gfx.mec.mec_fw_gpu_addr,
4520                                               (void **)&fw);
4521                 if (r) {
4522                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4523                         gfx_v10_0_mec_fini(adev);
4524                         return r;
4525                 }
4526
4527                 memcpy(fw, fw_data, fw_size);
4528
4529                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4530                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4531         }
4532
4533         return 0;
4534 }
4535
4536 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4537 {
4538         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4539                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4540                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4541         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4542 }
4543
4544 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4545                            uint32_t thread, uint32_t regno,
4546                            uint32_t num, uint32_t *out)
4547 {
4548         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4549                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4550                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4551                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4552                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4553         while (num--)
4554                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4555 }
4556
4557 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4558 {
4559         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4560          * field when performing a select_se_sh so it should be
4561          * zero here */
4562         WARN_ON(simd != 0);
4563
4564         /* type 2 wave data */
4565         dst[(*no_fields)++] = 2;
4566         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4567         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4568         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4569         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4570         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4571         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4572         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4573         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4574         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4575         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4576         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4577         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4578         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4579         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4580         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4581         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4582 }
4583
4584 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4585                                      uint32_t wave, uint32_t start,
4586                                      uint32_t size, uint32_t *dst)
4587 {
4588         WARN_ON(simd != 0);
4589
4590         wave_read_regs(
4591                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4592                 dst);
4593 }
4594
4595 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4596                                       uint32_t wave, uint32_t thread,
4597                                       uint32_t start, uint32_t size,
4598                                       uint32_t *dst)
4599 {
4600         wave_read_regs(
4601                 adev, wave, thread,
4602                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4603 }
4604
4605 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4606                                        u32 me, u32 pipe, u32 q, u32 vm)
4607 {
4608         nv_grbm_select(adev, me, pipe, q, vm);
4609 }
4610
4611 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4612                                           bool enable)
4613 {
4614         uint32_t data, def;
4615
4616         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4617
4618         if (enable)
4619                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4620         else
4621                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4622
4623         if (data != def)
4624                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4625 }
4626
4627 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4628         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4629         .select_se_sh = &gfx_v10_0_select_se_sh,
4630         .read_wave_data = &gfx_v10_0_read_wave_data,
4631         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4632         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4633         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4634         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4635         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4636 };
4637
4638 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4639 {
4640         u32 gb_addr_config;
4641
4642         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4643
4644         switch (adev->ip_versions[GC_HWIP][0]) {
4645         case IP_VERSION(10, 1, 10):
4646         case IP_VERSION(10, 1, 1):
4647         case IP_VERSION(10, 1, 2):
4648                 adev->gfx.config.max_hw_contexts = 8;
4649                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4650                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4651                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4652                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4653                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4654                 break;
4655         case IP_VERSION(10, 3, 0):
4656         case IP_VERSION(10, 3, 2):
4657         case IP_VERSION(10, 3, 1):
4658         case IP_VERSION(10, 3, 4):
4659         case IP_VERSION(10, 3, 5):
4660         case IP_VERSION(10, 3, 6):
4661         case IP_VERSION(10, 3, 3):
4662         case IP_VERSION(10, 3, 7):
4663                 adev->gfx.config.max_hw_contexts = 8;
4664                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4665                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4666                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4667                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4668                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4669                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4670                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4671                 break;
4672         case IP_VERSION(10, 1, 3):
4673         case IP_VERSION(10, 1, 4):
4674                 adev->gfx.config.max_hw_contexts = 8;
4675                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4676                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4677                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4678                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4679                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4680                 break;
4681         default:
4682                 BUG();
4683                 break;
4684         }
4685
4686         adev->gfx.config.gb_addr_config = gb_addr_config;
4687
4688         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4689                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4690                                       GB_ADDR_CONFIG, NUM_PIPES);
4691
4692         adev->gfx.config.max_tile_pipes =
4693                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4694
4695         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4696                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4697                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4698         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4699                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4700                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4701         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4702                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4703                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4704         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4705                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4706                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4707 }
4708
4709 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4710                                    int me, int pipe, int queue)
4711 {
4712         struct amdgpu_ring *ring;
4713         unsigned int irq_type;
4714
4715         ring = &adev->gfx.gfx_ring[ring_id];
4716
4717         ring->me = me;
4718         ring->pipe = pipe;
4719         ring->queue = queue;
4720
4721         ring->ring_obj = NULL;
4722         ring->use_doorbell = true;
4723
4724         if (!ring_id)
4725                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4726         else
4727                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4728         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4729
4730         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4731         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4732                              AMDGPU_RING_PRIO_DEFAULT, NULL);
4733 }
4734
4735 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4736                                        int mec, int pipe, int queue)
4737 {
4738         unsigned irq_type;
4739         struct amdgpu_ring *ring;
4740         unsigned int hw_prio;
4741
4742         ring = &adev->gfx.compute_ring[ring_id];
4743
4744         /* mec0 is me1 */
4745         ring->me = mec + 1;
4746         ring->pipe = pipe;
4747         ring->queue = queue;
4748
4749         ring->ring_obj = NULL;
4750         ring->use_doorbell = true;
4751         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4752         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4753                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4754         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4755
4756         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4757                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4758                 + ring->pipe;
4759         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4760                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4761         /* type-2 packets are deprecated on MEC, use type-3 instead */
4762         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4763                              hw_prio, NULL);
4764 }
4765
4766 static int gfx_v10_0_sw_init(void *handle)
4767 {
4768         int i, j, k, r, ring_id = 0;
4769         struct amdgpu_kiq *kiq;
4770         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4771
4772         switch (adev->ip_versions[GC_HWIP][0]) {
4773         case IP_VERSION(10, 1, 10):
4774         case IP_VERSION(10, 1, 1):
4775         case IP_VERSION(10, 1, 2):
4776         case IP_VERSION(10, 1, 3):
4777         case IP_VERSION(10, 1, 4):
4778                 adev->gfx.me.num_me = 1;
4779                 adev->gfx.me.num_pipe_per_me = 1;
4780                 adev->gfx.me.num_queue_per_pipe = 1;
4781                 adev->gfx.mec.num_mec = 2;
4782                 adev->gfx.mec.num_pipe_per_mec = 4;
4783                 adev->gfx.mec.num_queue_per_pipe = 8;
4784                 break;
4785         case IP_VERSION(10, 3, 0):
4786         case IP_VERSION(10, 3, 2):
4787         case IP_VERSION(10, 3, 1):
4788         case IP_VERSION(10, 3, 4):
4789         case IP_VERSION(10, 3, 5):
4790         case IP_VERSION(10, 3, 6):
4791         case IP_VERSION(10, 3, 3):
4792         case IP_VERSION(10, 3, 7):
4793                 adev->gfx.me.num_me = 1;
4794                 adev->gfx.me.num_pipe_per_me = 1;
4795                 adev->gfx.me.num_queue_per_pipe = 1;
4796                 adev->gfx.mec.num_mec = 2;
4797                 adev->gfx.mec.num_pipe_per_mec = 4;
4798                 adev->gfx.mec.num_queue_per_pipe = 4;
4799                 break;
4800         default:
4801                 adev->gfx.me.num_me = 1;
4802                 adev->gfx.me.num_pipe_per_me = 1;
4803                 adev->gfx.me.num_queue_per_pipe = 1;
4804                 adev->gfx.mec.num_mec = 1;
4805                 adev->gfx.mec.num_pipe_per_mec = 4;
4806                 adev->gfx.mec.num_queue_per_pipe = 8;
4807                 break;
4808         }
4809
4810         /* KIQ event */
4811         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4812                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4813                               &adev->gfx.kiq.irq);
4814         if (r)
4815                 return r;
4816
4817         /* EOP Event */
4818         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4819                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4820                               &adev->gfx.eop_irq);
4821         if (r)
4822                 return r;
4823
4824         /* Privileged reg */
4825         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4826                               &adev->gfx.priv_reg_irq);
4827         if (r)
4828                 return r;
4829
4830         /* Privileged inst */
4831         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4832                               &adev->gfx.priv_inst_irq);
4833         if (r)
4834                 return r;
4835
4836         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4837
4838         r = gfx_v10_0_me_init(adev);
4839         if (r)
4840                 return r;
4841
4842         if (adev->gfx.rlc.funcs) {
4843                 if (adev->gfx.rlc.funcs->init) {
4844                         r = adev->gfx.rlc.funcs->init(adev);
4845                         if (r) {
4846                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4847                                 return r;
4848                         }
4849                 }
4850         }
4851
4852         r = gfx_v10_0_mec_init(adev);
4853         if (r) {
4854                 DRM_ERROR("Failed to init MEC BOs!\n");
4855                 return r;
4856         }
4857
4858         /* set up the gfx ring */
4859         for (i = 0; i < adev->gfx.me.num_me; i++) {
4860                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4861                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4862                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4863                                         continue;
4864
4865                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4866                                                             i, k, j);
4867                                 if (r)
4868                                         return r;
4869                                 ring_id++;
4870                         }
4871                 }
4872         }
4873
4874         ring_id = 0;
4875         /* set up the compute queues - allocate horizontally across pipes */
4876         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4877                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4878                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4879                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4880                                                                      j))
4881                                         continue;
4882
4883                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4884                                                                 i, k, j);
4885                                 if (r)
4886                                         return r;
4887
4888                                 ring_id++;
4889                         }
4890                 }
4891         }
4892
4893         if (!adev->enable_mes_kiq) {
4894                 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4895                 if (r) {
4896                         DRM_ERROR("Failed to init KIQ BOs!\n");
4897                         return r;
4898                 }
4899
4900                 kiq = &adev->gfx.kiq;
4901                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4902                 if (r)
4903                         return r;
4904         }
4905
4906         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4907         if (r)
4908                 return r;
4909
4910         /* allocate visible FB for rlc auto-loading fw */
4911         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4912                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4913                 if (r)
4914                         return r;
4915         }
4916
4917         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4918
4919         gfx_v10_0_gpu_early_init(adev);
4920
4921         return 0;
4922 }
4923
4924 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4925 {
4926         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4927                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4928                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4929 }
4930
4931 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4932 {
4933         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4934                               &adev->gfx.ce.ce_fw_gpu_addr,
4935                               (void **)&adev->gfx.ce.ce_fw_ptr);
4936 }
4937
4938 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4939 {
4940         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4941                               &adev->gfx.me.me_fw_gpu_addr,
4942                               (void **)&adev->gfx.me.me_fw_ptr);
4943 }
4944
4945 static int gfx_v10_0_sw_fini(void *handle)
4946 {
4947         int i;
4948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4949
4950         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4951                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4952         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4953                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4954
4955         amdgpu_gfx_mqd_sw_fini(adev);
4956
4957         if (!adev->enable_mes_kiq) {
4958                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4959                 amdgpu_gfx_kiq_fini(adev);
4960         }
4961
4962         gfx_v10_0_pfp_fini(adev);
4963         gfx_v10_0_ce_fini(adev);
4964         gfx_v10_0_me_fini(adev);
4965         gfx_v10_0_rlc_fini(adev);
4966         gfx_v10_0_mec_fini(adev);
4967
4968         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4969                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4970
4971         gfx_v10_0_free_microcode(adev);
4972
4973         return 0;
4974 }
4975
4976 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4977                                    u32 sh_num, u32 instance)
4978 {
4979         u32 data;
4980
4981         if (instance == 0xffffffff)
4982                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4983                                      INSTANCE_BROADCAST_WRITES, 1);
4984         else
4985                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4986                                      instance);
4987
4988         if (se_num == 0xffffffff)
4989                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4990                                      1);
4991         else
4992                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4993
4994         if (sh_num == 0xffffffff)
4995                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4996                                      1);
4997         else
4998                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4999
5000         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5001 }
5002
5003 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5004 {
5005         u32 data, mask;
5006
5007         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5008         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5009
5010         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5011         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5012
5013         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5014                                          adev->gfx.config.max_sh_per_se);
5015
5016         return (~data) & mask;
5017 }
5018
5019 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5020 {
5021         int i, j;
5022         u32 data;
5023         u32 active_rbs = 0;
5024         u32 bitmap;
5025         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5026                                         adev->gfx.config.max_sh_per_se;
5027
5028         mutex_lock(&adev->grbm_idx_mutex);
5029         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5030                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5031                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
5032                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5033                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5034                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
5035                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5036                                 continue;
5037                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5038                         data = gfx_v10_0_get_rb_active_bitmap(adev);
5039                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5040                                                rb_bitmap_width_per_sh);
5041                 }
5042         }
5043         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5044         mutex_unlock(&adev->grbm_idx_mutex);
5045
5046         adev->gfx.config.backend_enable_mask = active_rbs;
5047         adev->gfx.config.num_rbs = hweight32(active_rbs);
5048 }
5049
5050 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5051 {
5052         uint32_t num_sc;
5053         uint32_t enabled_rb_per_sh;
5054         uint32_t active_rb_bitmap;
5055         uint32_t num_rb_per_sc;
5056         uint32_t num_packer_per_sc;
5057         uint32_t pa_sc_tile_steering_override;
5058
5059         /* for ASICs that integrates GFX v10.3
5060          * pa_sc_tile_steering_override should be set to 0 */
5061         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5062                 return 0;
5063
5064         /* init num_sc */
5065         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5066                         adev->gfx.config.num_sc_per_sh;
5067         /* init num_rb_per_sc */
5068         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5069         enabled_rb_per_sh = hweight32(active_rb_bitmap);
5070         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5071         /* init num_packer_per_sc */
5072         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5073
5074         pa_sc_tile_steering_override = 0;
5075         pa_sc_tile_steering_override |=
5076                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5077                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5078         pa_sc_tile_steering_override |=
5079                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5080                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5081         pa_sc_tile_steering_override |=
5082                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5083                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5084
5085         return pa_sc_tile_steering_override;
5086 }
5087
5088 #define DEFAULT_SH_MEM_BASES    (0x6000)
5089
5090 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5091 {
5092         int i;
5093         uint32_t sh_mem_bases;
5094
5095         /*
5096          * Configure apertures:
5097          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5098          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5099          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5100          */
5101         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5102
5103         mutex_lock(&adev->srbm_mutex);
5104         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5105                 nv_grbm_select(adev, 0, 0, 0, i);
5106                 /* CP and shaders */
5107                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5108                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5109         }
5110         nv_grbm_select(adev, 0, 0, 0, 0);
5111         mutex_unlock(&adev->srbm_mutex);
5112
5113         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5114            access. These should be enabled by FW for target VMIDs. */
5115         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5116                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5117                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5118                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5119                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5120         }
5121 }
5122
5123 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5124 {
5125         int vmid;
5126
5127         /*
5128          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5129          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5130          * the driver can enable them for graphics. VMID0 should maintain
5131          * access so that HWS firmware can save/restore entries.
5132          */
5133         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5134                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5135                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5136                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5137                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5138         }
5139 }
5140
5141
5142 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5143 {
5144         int i, j, k;
5145         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5146         u32 tmp, wgp_active_bitmap = 0;
5147         u32 gcrd_targets_disable_tcp = 0;
5148         u32 utcl_invreq_disable = 0;
5149         /*
5150          * GCRD_TARGETS_DISABLE field contains
5151          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5152          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5153          */
5154         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5155                 2 * max_wgp_per_sh + /* TCP */
5156                 max_wgp_per_sh + /* SQC */
5157                 4); /* GL1C */
5158         /*
5159          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5160          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5161          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5162          */
5163         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5164                 2 * max_wgp_per_sh + /* TCP */
5165                 2 * max_wgp_per_sh + /* SQC */
5166                 4 + /* RMI */
5167                 1); /* SQG */
5168
5169         mutex_lock(&adev->grbm_idx_mutex);
5170         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5171                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5172                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5173                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5174                         /*
5175                          * Set corresponding TCP bits for the inactive WGPs in
5176                          * GCRD_SA_TARGETS_DISABLE
5177                          */
5178                         gcrd_targets_disable_tcp = 0;
5179                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5180                         utcl_invreq_disable = 0;
5181
5182                         for (k = 0; k < max_wgp_per_sh; k++) {
5183                                 if (!(wgp_active_bitmap & (1 << k))) {
5184                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5185                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5186                                         utcl_invreq_disable |= (3 << (2 * k)) |
5187                                                 (3 << (2 * (max_wgp_per_sh + k)));
5188                                 }
5189                         }
5190
5191                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5192                         /* only override TCP & SQC bits */
5193                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5194                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5195                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5196
5197                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5198                         /* only override TCP & SQC bits */
5199                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5200                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5201                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5202                 }
5203         }
5204
5205         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5206         mutex_unlock(&adev->grbm_idx_mutex);
5207 }
5208
5209 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5210 {
5211         /* TCCs are global (not instanced). */
5212         uint32_t tcc_disable;
5213
5214         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5215                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5216                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5217         } else {
5218                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5219                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5220         }
5221
5222         adev->gfx.config.tcc_disabled_mask =
5223                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5224                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5225 }
5226
5227 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5228 {
5229         u32 tmp;
5230         int i;
5231
5232         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5233
5234         gfx_v10_0_setup_rb(adev);
5235         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5236         gfx_v10_0_get_tcc_info(adev);
5237         adev->gfx.config.pa_sc_tile_steering_override =
5238                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5239
5240         /* XXX SH_MEM regs */
5241         /* where to put LDS, scratch, GPUVM in FSA64 space */
5242         mutex_lock(&adev->srbm_mutex);
5243         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5244                 nv_grbm_select(adev, 0, 0, 0, i);
5245                 /* CP and shaders */
5246                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5247                 if (i != 0) {
5248                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5249                                 (adev->gmc.private_aperture_start >> 48));
5250                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5251                                 (adev->gmc.shared_aperture_start >> 48));
5252                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5253                 }
5254         }
5255         nv_grbm_select(adev, 0, 0, 0, 0);
5256
5257         mutex_unlock(&adev->srbm_mutex);
5258
5259         gfx_v10_0_init_compute_vmid(adev);
5260         gfx_v10_0_init_gds_vmid(adev);
5261
5262 }
5263
5264 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5265                                                bool enable)
5266 {
5267         u32 tmp;
5268
5269         if (amdgpu_sriov_vf(adev))
5270                 return;
5271
5272         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5273
5274         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5275                             enable ? 1 : 0);
5276         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5277                             enable ? 1 : 0);
5278         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5279                             enable ? 1 : 0);
5280         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5281                             enable ? 1 : 0);
5282
5283         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5284 }
5285
5286 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5287 {
5288         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5289
5290         /* csib */
5291         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5292                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5293                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5294                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5295                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5296                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5297         } else {
5298                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5299                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5300                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5301                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5302                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5303         }
5304         return 0;
5305 }
5306
5307 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5308 {
5309         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5310
5311         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5312         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5313 }
5314
5315 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5316 {
5317         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5318         udelay(50);
5319         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5320         udelay(50);
5321 }
5322
5323 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5324                                              bool enable)
5325 {
5326         uint32_t rlc_pg_cntl;
5327
5328         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5329
5330         if (!enable) {
5331                 /* RLC_PG_CNTL[23] = 0 (default)
5332                  * RLC will wait for handshake acks with SMU
5333                  * GFXOFF will be enabled
5334                  * RLC_PG_CNTL[23] = 1
5335                  * RLC will not issue any message to SMU
5336                  * hence no handshake between SMU & RLC
5337                  * GFXOFF will be disabled
5338                  */
5339                 rlc_pg_cntl |= 0x800000;
5340         } else
5341                 rlc_pg_cntl &= ~0x800000;
5342         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5343 }
5344
5345 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5346 {
5347         /* TODO: enable rlc & smu handshake until smu
5348          * and gfxoff feature works as expected */
5349         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5350                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5351
5352         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5353         udelay(50);
5354 }
5355
5356 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5357 {
5358         uint32_t tmp;
5359
5360         /* enable Save Restore Machine */
5361         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5362         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5363         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5364         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5365 }
5366
5367 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5368 {
5369         const struct rlc_firmware_header_v2_0 *hdr;
5370         const __le32 *fw_data;
5371         unsigned i, fw_size;
5372
5373         if (!adev->gfx.rlc_fw)
5374                 return -EINVAL;
5375
5376         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5377         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5378
5379         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5380                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5381         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5382
5383         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5384                      RLCG_UCODE_LOADING_START_ADDRESS);
5385
5386         for (i = 0; i < fw_size; i++)
5387                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5388                              le32_to_cpup(fw_data++));
5389
5390         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5391
5392         return 0;
5393 }
5394
5395 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5396 {
5397         int r;
5398
5399         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5400                 adev->psp.autoload_supported) {
5401
5402                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5403                 if (r)
5404                         return r;
5405
5406                 gfx_v10_0_init_csb(adev);
5407
5408                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5409                         gfx_v10_0_rlc_enable_srm(adev);
5410         } else {
5411                 if (amdgpu_sriov_vf(adev)) {
5412                         gfx_v10_0_init_csb(adev);
5413                         return 0;
5414                 }
5415
5416                 adev->gfx.rlc.funcs->stop(adev);
5417
5418                 /* disable CG */
5419                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5420
5421                 /* disable PG */
5422                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5423
5424                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5425                         /* legacy rlc firmware loading */
5426                         r = gfx_v10_0_rlc_load_microcode(adev);
5427                         if (r)
5428                                 return r;
5429                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5430                         /* rlc backdoor autoload firmware */
5431                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5432                         if (r)
5433                                 return r;
5434                 }
5435
5436                 gfx_v10_0_init_csb(adev);
5437
5438                 adev->gfx.rlc.funcs->start(adev);
5439
5440                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5441                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5442                         if (r)
5443                                 return r;
5444                 }
5445         }
5446         return 0;
5447 }
5448
5449 static struct {
5450         FIRMWARE_ID     id;
5451         unsigned int    offset;
5452         unsigned int    size;
5453 } rlc_autoload_info[FIRMWARE_ID_MAX];
5454
5455 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5456 {
5457         int ret;
5458         RLC_TABLE_OF_CONTENT *rlc_toc;
5459
5460         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5461                                         AMDGPU_GEM_DOMAIN_GTT,
5462                                         &adev->gfx.rlc.rlc_toc_bo,
5463                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5464                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5465         if (ret) {
5466                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5467                 return ret;
5468         }
5469
5470         /* Copy toc from psp sos fw to rlc toc buffer */
5471         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5472
5473         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5474         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5475                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5476                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5477                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5478                         /* Offset needs 4KB alignment */
5479                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5480                 }
5481
5482                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5483                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5484                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5485
5486                 rlc_toc++;
5487         }
5488
5489         return 0;
5490 }
5491
5492 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5493 {
5494         uint32_t total_size = 0;
5495         FIRMWARE_ID id;
5496         int ret;
5497
5498         ret = gfx_v10_0_parse_rlc_toc(adev);
5499         if (ret) {
5500                 dev_err(adev->dev, "failed to parse rlc toc\n");
5501                 return 0;
5502         }
5503
5504         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5505                 total_size += rlc_autoload_info[id].size;
5506
5507         /* In case the offset in rlc toc ucode is aligned */
5508         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5509                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5510                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5511
5512         return total_size;
5513 }
5514
5515 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5516 {
5517         int r;
5518         uint32_t total_size;
5519
5520         total_size = gfx_v10_0_calc_toc_total_size(adev);
5521
5522         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5523                                       AMDGPU_GEM_DOMAIN_GTT,
5524                                       &adev->gfx.rlc.rlc_autoload_bo,
5525                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5526                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5527         if (r) {
5528                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5529                 return r;
5530         }
5531
5532         return 0;
5533 }
5534
5535 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5536 {
5537         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5538                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5539                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5540         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5541                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5542                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5543 }
5544
5545 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5546                                                        FIRMWARE_ID id,
5547                                                        const void *fw_data,
5548                                                        uint32_t fw_size)
5549 {
5550         uint32_t toc_offset;
5551         uint32_t toc_fw_size;
5552         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5553
5554         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5555                 return;
5556
5557         toc_offset = rlc_autoload_info[id].offset;
5558         toc_fw_size = rlc_autoload_info[id].size;
5559
5560         if (fw_size == 0)
5561                 fw_size = toc_fw_size;
5562
5563         if (fw_size > toc_fw_size)
5564                 fw_size = toc_fw_size;
5565
5566         memcpy(ptr + toc_offset, fw_data, fw_size);
5567
5568         if (fw_size < toc_fw_size)
5569                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5570 }
5571
5572 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5573 {
5574         void *data;
5575         uint32_t size;
5576
5577         data = adev->gfx.rlc.rlc_toc_buf;
5578         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5579
5580         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5581                                                    FIRMWARE_ID_RLC_TOC,
5582                                                    data, size);
5583 }
5584
5585 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5586 {
5587         const __le32 *fw_data;
5588         uint32_t fw_size;
5589         const struct gfx_firmware_header_v1_0 *cp_hdr;
5590         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5591
5592         /* pfp ucode */
5593         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5594                 adev->gfx.pfp_fw->data;
5595         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5596                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5597         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5598         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5599                                                    FIRMWARE_ID_CP_PFP,
5600                                                    fw_data, fw_size);
5601
5602         /* ce ucode */
5603         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5604                 adev->gfx.ce_fw->data;
5605         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5606                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5607         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5608         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5609                                                    FIRMWARE_ID_CP_CE,
5610                                                    fw_data, fw_size);
5611
5612         /* me ucode */
5613         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5614                 adev->gfx.me_fw->data;
5615         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5616                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5617         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5618         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5619                                                    FIRMWARE_ID_CP_ME,
5620                                                    fw_data, fw_size);
5621
5622         /* rlc ucode */
5623         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5624                 adev->gfx.rlc_fw->data;
5625         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5626                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5627         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5628         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5629                                                    FIRMWARE_ID_RLC_G_UCODE,
5630                                                    fw_data, fw_size);
5631
5632         /* mec1 ucode */
5633         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5634                 adev->gfx.mec_fw->data;
5635         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5636                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5637         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5638                 cp_hdr->jt_size * 4;
5639         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5640                                                    FIRMWARE_ID_CP_MEC,
5641                                                    fw_data, fw_size);
5642         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5643 }
5644
5645 /* Temporarily put sdma part here */
5646 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5647 {
5648         const __le32 *fw_data;
5649         uint32_t fw_size;
5650         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5651         int i;
5652
5653         for (i = 0; i < adev->sdma.num_instances; i++) {
5654                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5655                         adev->sdma.instance[i].fw->data;
5656                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5657                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5658                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5659
5660                 if (i == 0) {
5661                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5662                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5663                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5664                                 FIRMWARE_ID_SDMA0_JT,
5665                                 (uint32_t *)fw_data +
5666                                 sdma_hdr->jt_offset,
5667                                 sdma_hdr->jt_size * 4);
5668                 } else if (i == 1) {
5669                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5670                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5671                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5672                                 FIRMWARE_ID_SDMA1_JT,
5673                                 (uint32_t *)fw_data +
5674                                 sdma_hdr->jt_offset,
5675                                 sdma_hdr->jt_size * 4);
5676                 }
5677         }
5678 }
5679
5680 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5681 {
5682         uint32_t rlc_g_offset, rlc_g_size, tmp;
5683         uint64_t gpu_addr;
5684
5685         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5686         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5687         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5688
5689         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5690         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5691         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5692
5693         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5694         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5695         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5696
5697         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5698         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5699                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5700                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5701                 return -EINVAL;
5702         }
5703
5704         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5705         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5706                 DRM_ERROR("RLC ROM should halt itself\n");
5707                 return -EINVAL;
5708         }
5709
5710         return 0;
5711 }
5712
5713 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5714 {
5715         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5716         uint32_t tmp;
5717         int i;
5718         uint64_t addr;
5719
5720         /* Trigger an invalidation of the L1 instruction caches */
5721         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5722         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5723         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5724
5725         /* Wait for invalidation complete */
5726         for (i = 0; i < usec_timeout; i++) {
5727                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5728                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5729                         INVALIDATE_CACHE_COMPLETE))
5730                         break;
5731                 udelay(1);
5732         }
5733
5734         if (i >= usec_timeout) {
5735                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5736                 return -EINVAL;
5737         }
5738
5739         /* Program me ucode address into intruction cache address register */
5740         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5741                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5742         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5743                         lower_32_bits(addr) & 0xFFFFF000);
5744         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5745                         upper_32_bits(addr));
5746
5747         return 0;
5748 }
5749
5750 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5751 {
5752         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5753         uint32_t tmp;
5754         int i;
5755         uint64_t addr;
5756
5757         /* Trigger an invalidation of the L1 instruction caches */
5758         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5759         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5760         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5761
5762         /* Wait for invalidation complete */
5763         for (i = 0; i < usec_timeout; i++) {
5764                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5765                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5766                         INVALIDATE_CACHE_COMPLETE))
5767                         break;
5768                 udelay(1);
5769         }
5770
5771         if (i >= usec_timeout) {
5772                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5773                 return -EINVAL;
5774         }
5775
5776         /* Program ce ucode address into intruction cache address register */
5777         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5778                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5779         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5780                         lower_32_bits(addr) & 0xFFFFF000);
5781         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5782                         upper_32_bits(addr));
5783
5784         return 0;
5785 }
5786
5787 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5788 {
5789         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5790         uint32_t tmp;
5791         int i;
5792         uint64_t addr;
5793
5794         /* Trigger an invalidation of the L1 instruction caches */
5795         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5796         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5797         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5798
5799         /* Wait for invalidation complete */
5800         for (i = 0; i < usec_timeout; i++) {
5801                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5802                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5803                         INVALIDATE_CACHE_COMPLETE))
5804                         break;
5805                 udelay(1);
5806         }
5807
5808         if (i >= usec_timeout) {
5809                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5810                 return -EINVAL;
5811         }
5812
5813         /* Program pfp ucode address into intruction cache address register */
5814         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5815                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5816         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5817                         lower_32_bits(addr) & 0xFFFFF000);
5818         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5819                         upper_32_bits(addr));
5820
5821         return 0;
5822 }
5823
5824 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5825 {
5826         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5827         uint32_t tmp;
5828         int i;
5829         uint64_t addr;
5830
5831         /* Trigger an invalidation of the L1 instruction caches */
5832         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5833         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5834         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5835
5836         /* Wait for invalidation complete */
5837         for (i = 0; i < usec_timeout; i++) {
5838                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5839                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5840                         INVALIDATE_CACHE_COMPLETE))
5841                         break;
5842                 udelay(1);
5843         }
5844
5845         if (i >= usec_timeout) {
5846                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5847                 return -EINVAL;
5848         }
5849
5850         /* Program mec1 ucode address into intruction cache address register */
5851         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5852                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5853         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5854                         lower_32_bits(addr) & 0xFFFFF000);
5855         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5856                         upper_32_bits(addr));
5857
5858         return 0;
5859 }
5860
5861 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5862 {
5863         uint32_t cp_status;
5864         uint32_t bootload_status;
5865         int i, r;
5866
5867         for (i = 0; i < adev->usec_timeout; i++) {
5868                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5869                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5870                 if ((cp_status == 0) &&
5871                     (REG_GET_FIELD(bootload_status,
5872                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5873                         break;
5874                 }
5875                 udelay(1);
5876         }
5877
5878         if (i >= adev->usec_timeout) {
5879                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5880                 return -ETIMEDOUT;
5881         }
5882
5883         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5884                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5885                 if (r)
5886                         return r;
5887
5888                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5889                 if (r)
5890                         return r;
5891
5892                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5893                 if (r)
5894                         return r;
5895
5896                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5897                 if (r)
5898                         return r;
5899         }
5900
5901         return 0;
5902 }
5903
5904 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5905 {
5906         int i;
5907         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5908
5909         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5910         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5911         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5912
5913         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5914                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5915         } else {
5916                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5917         }
5918
5919         for (i = 0; i < adev->usec_timeout; i++) {
5920                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5921                         break;
5922                 udelay(1);
5923         }
5924
5925         if (i >= adev->usec_timeout)
5926                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5927
5928         return 0;
5929 }
5930
5931 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5932 {
5933         int r;
5934         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5935         const __le32 *fw_data;
5936         unsigned i, fw_size;
5937         uint32_t tmp;
5938         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5939
5940         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5941                 adev->gfx.pfp_fw->data;
5942
5943         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5944
5945         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5946                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5947         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5948
5949         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5950                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5951                                       &adev->gfx.pfp.pfp_fw_obj,
5952                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5953                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5954         if (r) {
5955                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5956                 gfx_v10_0_pfp_fini(adev);
5957                 return r;
5958         }
5959
5960         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5961
5962         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5963         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5964
5965         /* Trigger an invalidation of the L1 instruction caches */
5966         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5967         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5968         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5969
5970         /* Wait for invalidation complete */
5971         for (i = 0; i < usec_timeout; i++) {
5972                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5973                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5974                         INVALIDATE_CACHE_COMPLETE))
5975                         break;
5976                 udelay(1);
5977         }
5978
5979         if (i >= usec_timeout) {
5980                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5981                 return -EINVAL;
5982         }
5983
5984         if (amdgpu_emu_mode == 1)
5985                 adev->hdp.funcs->flush_hdp(adev, NULL);
5986
5987         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5988         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5989         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5990         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5991         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5992         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5993         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5994                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5995         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5996                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5997
5998         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5999
6000         for (i = 0; i < pfp_hdr->jt_size; i++)
6001                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6002                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6003
6004         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6005
6006         return 0;
6007 }
6008
6009 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6010 {
6011         int r;
6012         const struct gfx_firmware_header_v1_0 *ce_hdr;
6013         const __le32 *fw_data;
6014         unsigned i, fw_size;
6015         uint32_t tmp;
6016         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6017
6018         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6019                 adev->gfx.ce_fw->data;
6020
6021         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6022
6023         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6024                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6025         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6026
6027         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6028                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6029                                       &adev->gfx.ce.ce_fw_obj,
6030                                       &adev->gfx.ce.ce_fw_gpu_addr,
6031                                       (void **)&adev->gfx.ce.ce_fw_ptr);
6032         if (r) {
6033                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6034                 gfx_v10_0_ce_fini(adev);
6035                 return r;
6036         }
6037
6038         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6039
6040         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6041         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6042
6043         /* Trigger an invalidation of the L1 instruction caches */
6044         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6045         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6046         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6047
6048         /* Wait for invalidation complete */
6049         for (i = 0; i < usec_timeout; i++) {
6050                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6051                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6052                         INVALIDATE_CACHE_COMPLETE))
6053                         break;
6054                 udelay(1);
6055         }
6056
6057         if (i >= usec_timeout) {
6058                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6059                 return -EINVAL;
6060         }
6061
6062         if (amdgpu_emu_mode == 1)
6063                 adev->hdp.funcs->flush_hdp(adev, NULL);
6064
6065         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6066         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6067         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6068         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6069         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6070         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6071                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6072         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6073                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6074
6075         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6076
6077         for (i = 0; i < ce_hdr->jt_size; i++)
6078                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6079                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6080
6081         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6082
6083         return 0;
6084 }
6085
6086 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6087 {
6088         int r;
6089         const struct gfx_firmware_header_v1_0 *me_hdr;
6090         const __le32 *fw_data;
6091         unsigned i, fw_size;
6092         uint32_t tmp;
6093         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6094
6095         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6096                 adev->gfx.me_fw->data;
6097
6098         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6099
6100         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6101                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6102         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6103
6104         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6105                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6106                                       &adev->gfx.me.me_fw_obj,
6107                                       &adev->gfx.me.me_fw_gpu_addr,
6108                                       (void **)&adev->gfx.me.me_fw_ptr);
6109         if (r) {
6110                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6111                 gfx_v10_0_me_fini(adev);
6112                 return r;
6113         }
6114
6115         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6116
6117         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6118         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6119
6120         /* Trigger an invalidation of the L1 instruction caches */
6121         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6122         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6123         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6124
6125         /* Wait for invalidation complete */
6126         for (i = 0; i < usec_timeout; i++) {
6127                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6128                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6129                         INVALIDATE_CACHE_COMPLETE))
6130                         break;
6131                 udelay(1);
6132         }
6133
6134         if (i >= usec_timeout) {
6135                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6136                 return -EINVAL;
6137         }
6138
6139         if (amdgpu_emu_mode == 1)
6140                 adev->hdp.funcs->flush_hdp(adev, NULL);
6141
6142         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6143         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6144         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6145         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6146         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6147         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6148                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6149         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6150                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6151
6152         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6153
6154         for (i = 0; i < me_hdr->jt_size; i++)
6155                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6156                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6157
6158         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6159
6160         return 0;
6161 }
6162
6163 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6164 {
6165         int r;
6166
6167         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6168                 return -EINVAL;
6169
6170         gfx_v10_0_cp_gfx_enable(adev, false);
6171
6172         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6173         if (r) {
6174                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6175                 return r;
6176         }
6177
6178         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6179         if (r) {
6180                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6181                 return r;
6182         }
6183
6184         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6185         if (r) {
6186                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6187                 return r;
6188         }
6189
6190         return 0;
6191 }
6192
6193 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6194 {
6195         struct amdgpu_ring *ring;
6196         const struct cs_section_def *sect = NULL;
6197         const struct cs_extent_def *ext = NULL;
6198         int r, i;
6199         int ctx_reg_offset;
6200
6201         /* init the CP */
6202         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6203                      adev->gfx.config.max_hw_contexts - 1);
6204         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6205
6206         gfx_v10_0_cp_gfx_enable(adev, true);
6207
6208         ring = &adev->gfx.gfx_ring[0];
6209         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6210         if (r) {
6211                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6212                 return r;
6213         }
6214
6215         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6216         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6217
6218         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6219         amdgpu_ring_write(ring, 0x80000000);
6220         amdgpu_ring_write(ring, 0x80000000);
6221
6222         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6223                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6224                         if (sect->id == SECT_CONTEXT) {
6225                                 amdgpu_ring_write(ring,
6226                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6227                                                           ext->reg_count));
6228                                 amdgpu_ring_write(ring, ext->reg_index -
6229                                                   PACKET3_SET_CONTEXT_REG_START);
6230                                 for (i = 0; i < ext->reg_count; i++)
6231                                         amdgpu_ring_write(ring, ext->extent[i]);
6232                         }
6233                 }
6234         }
6235
6236         ctx_reg_offset =
6237                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6238         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6239         amdgpu_ring_write(ring, ctx_reg_offset);
6240         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6241
6242         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6243         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6244
6245         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6246         amdgpu_ring_write(ring, 0);
6247
6248         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6249         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6250         amdgpu_ring_write(ring, 0x8000);
6251         amdgpu_ring_write(ring, 0x8000);
6252
6253         amdgpu_ring_commit(ring);
6254
6255         /* submit cs packet to copy state 0 to next available state */
6256         if (adev->gfx.num_gfx_rings > 1) {
6257                 /* maximum supported gfx ring is 2 */
6258                 ring = &adev->gfx.gfx_ring[1];
6259                 r = amdgpu_ring_alloc(ring, 2);
6260                 if (r) {
6261                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6262                         return r;
6263                 }
6264
6265                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6266                 amdgpu_ring_write(ring, 0);
6267
6268                 amdgpu_ring_commit(ring);
6269         }
6270         return 0;
6271 }
6272
6273 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6274                                          CP_PIPE_ID pipe)
6275 {
6276         u32 tmp;
6277
6278         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6279         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6280
6281         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6282 }
6283
6284 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6285                                           struct amdgpu_ring *ring)
6286 {
6287         u32 tmp;
6288
6289         if (!amdgpu_async_gfx_ring) {
6290                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6291                 if (ring->use_doorbell) {
6292                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6293                                                 DOORBELL_OFFSET, ring->doorbell_index);
6294                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6295                                                 DOORBELL_EN, 1);
6296                 } else {
6297                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6298                                                 DOORBELL_EN, 0);
6299                 }
6300                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6301         }
6302         switch (adev->ip_versions[GC_HWIP][0]) {
6303         case IP_VERSION(10, 3, 0):
6304         case IP_VERSION(10, 3, 2):
6305         case IP_VERSION(10, 3, 1):
6306         case IP_VERSION(10, 3, 4):
6307         case IP_VERSION(10, 3, 5):
6308         case IP_VERSION(10, 3, 6):
6309         case IP_VERSION(10, 3, 3):
6310         case IP_VERSION(10, 3, 7):
6311                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6312                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6313                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6314
6315                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6316                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6317                 break;
6318         default:
6319                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6320                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6321                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6322
6323                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6324                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6325                 break;
6326         }
6327 }
6328
6329 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6330 {
6331         struct amdgpu_ring *ring;
6332         u32 tmp;
6333         u32 rb_bufsz;
6334         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6335         u32 i;
6336
6337         /* Set the write pointer delay */
6338         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6339
6340         /* set the RB to use vmid 0 */
6341         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6342
6343         /* Init gfx ring 0 for pipe 0 */
6344         mutex_lock(&adev->srbm_mutex);
6345         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6346
6347         /* Set ring buffer size */
6348         ring = &adev->gfx.gfx_ring[0];
6349         rb_bufsz = order_base_2(ring->ring_size / 8);
6350         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6351         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6352 #ifdef __BIG_ENDIAN
6353         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6354 #endif
6355         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6356
6357         /* Initialize the ring buffer's write pointers */
6358         ring->wptr = 0;
6359         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6360         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6361
6362         /* set the wb address wether it's enabled or not */
6363         rptr_addr = ring->rptr_gpu_addr;
6364         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6365         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6366                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6367
6368         wptr_gpu_addr = ring->wptr_gpu_addr;
6369         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6370                      lower_32_bits(wptr_gpu_addr));
6371         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6372                      upper_32_bits(wptr_gpu_addr));
6373
6374         mdelay(1);
6375         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6376
6377         rb_addr = ring->gpu_addr >> 8;
6378         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6379         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6380
6381         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6382
6383         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6384         mutex_unlock(&adev->srbm_mutex);
6385
6386         /* Init gfx ring 1 for pipe 1 */
6387         if (adev->gfx.num_gfx_rings > 1) {
6388                 mutex_lock(&adev->srbm_mutex);
6389                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6390                 /* maximum supported gfx ring is 2 */
6391                 ring = &adev->gfx.gfx_ring[1];
6392                 rb_bufsz = order_base_2(ring->ring_size / 8);
6393                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6394                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6395                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6396                 /* Initialize the ring buffer's write pointers */
6397                 ring->wptr = 0;
6398                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6399                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6400                 /* Set the wb address wether it's enabled or not */
6401                 rptr_addr = ring->rptr_gpu_addr;
6402                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6403                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6404                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6405                 wptr_gpu_addr = ring->wptr_gpu_addr;
6406                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6407                              lower_32_bits(wptr_gpu_addr));
6408                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6409                              upper_32_bits(wptr_gpu_addr));
6410
6411                 mdelay(1);
6412                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6413
6414                 rb_addr = ring->gpu_addr >> 8;
6415                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6416                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6417                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6418
6419                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6420                 mutex_unlock(&adev->srbm_mutex);
6421         }
6422         /* Switch to pipe 0 */
6423         mutex_lock(&adev->srbm_mutex);
6424         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6425         mutex_unlock(&adev->srbm_mutex);
6426
6427         /* start the ring */
6428         gfx_v10_0_cp_gfx_start(adev);
6429
6430         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6431                 ring = &adev->gfx.gfx_ring[i];
6432                 ring->sched.ready = true;
6433         }
6434
6435         return 0;
6436 }
6437
6438 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6439 {
6440         if (enable) {
6441                 switch (adev->ip_versions[GC_HWIP][0]) {
6442                 case IP_VERSION(10, 3, 0):
6443                 case IP_VERSION(10, 3, 2):
6444                 case IP_VERSION(10, 3, 1):
6445                 case IP_VERSION(10, 3, 4):
6446                 case IP_VERSION(10, 3, 5):
6447                 case IP_VERSION(10, 3, 6):
6448                 case IP_VERSION(10, 3, 3):
6449                 case IP_VERSION(10, 3, 7):
6450                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6451                         break;
6452                 default:
6453                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6454                         break;
6455                 }
6456         } else {
6457                 switch (adev->ip_versions[GC_HWIP][0]) {
6458                 case IP_VERSION(10, 3, 0):
6459                 case IP_VERSION(10, 3, 2):
6460                 case IP_VERSION(10, 3, 1):
6461                 case IP_VERSION(10, 3, 4):
6462                 case IP_VERSION(10, 3, 5):
6463                 case IP_VERSION(10, 3, 6):
6464                 case IP_VERSION(10, 3, 3):
6465                 case IP_VERSION(10, 3, 7):
6466                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6467                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6468                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6469                         break;
6470                 default:
6471                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6472                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6473                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6474                         break;
6475                 }
6476                 adev->gfx.kiq.ring.sched.ready = false;
6477         }
6478         udelay(50);
6479 }
6480
6481 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6482 {
6483         const struct gfx_firmware_header_v1_0 *mec_hdr;
6484         const __le32 *fw_data;
6485         unsigned i;
6486         u32 tmp;
6487         u32 usec_timeout = 50000; /* Wait for 50 ms */
6488
6489         if (!adev->gfx.mec_fw)
6490                 return -EINVAL;
6491
6492         gfx_v10_0_cp_compute_enable(adev, false);
6493
6494         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6495         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6496
6497         fw_data = (const __le32 *)
6498                 (adev->gfx.mec_fw->data +
6499                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6500
6501         /* Trigger an invalidation of the L1 instruction caches */
6502         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6503         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6504         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6505
6506         /* Wait for invalidation complete */
6507         for (i = 0; i < usec_timeout; i++) {
6508                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6509                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6510                                        INVALIDATE_CACHE_COMPLETE))
6511                         break;
6512                 udelay(1);
6513         }
6514
6515         if (i >= usec_timeout) {
6516                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6517                 return -EINVAL;
6518         }
6519
6520         if (amdgpu_emu_mode == 1)
6521                 adev->hdp.funcs->flush_hdp(adev, NULL);
6522
6523         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6524         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6525         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6526         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6527         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6528
6529         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6530                      0xFFFFF000);
6531         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6532                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6533
6534         /* MEC1 */
6535         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6536
6537         for (i = 0; i < mec_hdr->jt_size; i++)
6538                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6539                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6540
6541         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6542
6543         /*
6544          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6545          * different microcode than MEC1.
6546          */
6547
6548         return 0;
6549 }
6550
6551 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6552 {
6553         uint32_t tmp;
6554         struct amdgpu_device *adev = ring->adev;
6555
6556         /* tell RLC which is KIQ queue */
6557         switch (adev->ip_versions[GC_HWIP][0]) {
6558         case IP_VERSION(10, 3, 0):
6559         case IP_VERSION(10, 3, 2):
6560         case IP_VERSION(10, 3, 1):
6561         case IP_VERSION(10, 3, 4):
6562         case IP_VERSION(10, 3, 5):
6563         case IP_VERSION(10, 3, 6):
6564         case IP_VERSION(10, 3, 3):
6565         case IP_VERSION(10, 3, 7):
6566                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6567                 tmp &= 0xffffff00;
6568                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6569                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6570                 tmp |= 0x80;
6571                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6572                 break;
6573         default:
6574                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6575                 tmp &= 0xffffff00;
6576                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6577                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6578                 tmp |= 0x80;
6579                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6580                 break;
6581         }
6582 }
6583
6584 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6585                                   struct amdgpu_mqd_prop *prop)
6586 {
6587         struct v10_gfx_mqd *mqd = m;
6588         uint64_t hqd_gpu_addr, wb_gpu_addr;
6589         uint32_t tmp;
6590         uint32_t rb_bufsz;
6591
6592         /* set up gfx hqd wptr */
6593         mqd->cp_gfx_hqd_wptr = 0;
6594         mqd->cp_gfx_hqd_wptr_hi = 0;
6595
6596         /* set the pointer to the MQD */
6597         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6598         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6599
6600         /* set up mqd control */
6601         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6602         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6603         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6604         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6605         mqd->cp_gfx_mqd_control = tmp;
6606
6607         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6608         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6609         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6610         mqd->cp_gfx_hqd_vmid = 0;
6611
6612         /* set up default queue priority level
6613          * 0x0 = low priority, 0x1 = high priority */
6614         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6615         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6616         mqd->cp_gfx_hqd_queue_priority = tmp;
6617
6618         /* set up time quantum */
6619         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6620         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6621         mqd->cp_gfx_hqd_quantum = tmp;
6622
6623         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6624         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6625         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6626         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6627
6628         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6629         wb_gpu_addr = prop->rptr_gpu_addr;
6630         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6631         mqd->cp_gfx_hqd_rptr_addr_hi =
6632                 upper_32_bits(wb_gpu_addr) & 0xffff;
6633
6634         /* set up rb_wptr_poll addr */
6635         wb_gpu_addr = prop->wptr_gpu_addr;
6636         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6637         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6638
6639         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6640         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6641         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6642         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6643         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6644 #ifdef __BIG_ENDIAN
6645         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6646 #endif
6647         mqd->cp_gfx_hqd_cntl = tmp;
6648
6649         /* set up cp_doorbell_control */
6650         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6651         if (prop->use_doorbell) {
6652                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6653                                     DOORBELL_OFFSET, prop->doorbell_index);
6654                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6655                                     DOORBELL_EN, 1);
6656         } else
6657                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6658                                     DOORBELL_EN, 0);
6659         mqd->cp_rb_doorbell_control = tmp;
6660
6661         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6662         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6663
6664         /* active the queue */
6665         mqd->cp_gfx_hqd_active = 1;
6666
6667         return 0;
6668 }
6669
6670 #ifdef BRING_UP_DEBUG
6671 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6672 {
6673         struct amdgpu_device *adev = ring->adev;
6674         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6675
6676         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6677         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6678         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6679
6680         /* set GFX_MQD_BASE */
6681         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6682         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6683
6684         /* set GFX_MQD_CONTROL */
6685         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6686
6687         /* set GFX_HQD_VMID to 0 */
6688         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6689
6690         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6691                         mqd->cp_gfx_hqd_queue_priority);
6692         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6693
6694         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6695         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6696         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6697
6698         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6699         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6700         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6701
6702         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6703         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6704
6705         /* set RB_WPTR_POLL_ADDR */
6706         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6707         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6708
6709         /* set RB_DOORBELL_CONTROL */
6710         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6711
6712         /* active the queue */
6713         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6714
6715         return 0;
6716 }
6717 #endif
6718
6719 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6720 {
6721         struct amdgpu_device *adev = ring->adev;
6722         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6723         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6724
6725         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6726                 memset((void *)mqd, 0, sizeof(*mqd));
6727                 mutex_lock(&adev->srbm_mutex);
6728                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6729                 amdgpu_ring_init_mqd(ring);
6730
6731                 /*
6732                  * if there are 2 gfx rings, set the lower doorbell
6733                  * range of the first ring, otherwise the range of
6734                  * the second ring will override the first ring
6735                  */
6736                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6737                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6738
6739 #ifdef BRING_UP_DEBUG
6740                 gfx_v10_0_gfx_queue_init_register(ring);
6741 #endif
6742                 nv_grbm_select(adev, 0, 0, 0, 0);
6743                 mutex_unlock(&adev->srbm_mutex);
6744                 if (adev->gfx.me.mqd_backup[mqd_idx])
6745                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6746         } else if (amdgpu_in_reset(adev)) {
6747                 /* reset mqd with the backup copy */
6748                 if (adev->gfx.me.mqd_backup[mqd_idx])
6749                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6750                 /* reset the ring */
6751                 ring->wptr = 0;
6752                 *ring->wptr_cpu_addr = 0;
6753                 amdgpu_ring_clear_ring(ring);
6754 #ifdef BRING_UP_DEBUG
6755                 mutex_lock(&adev->srbm_mutex);
6756                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6757                 gfx_v10_0_gfx_queue_init_register(ring);
6758                 nv_grbm_select(adev, 0, 0, 0, 0);
6759                 mutex_unlock(&adev->srbm_mutex);
6760 #endif
6761         } else {
6762                 amdgpu_ring_clear_ring(ring);
6763         }
6764
6765         return 0;
6766 }
6767
6768 #ifndef BRING_UP_DEBUG
6769 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6770 {
6771         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6772         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6773         int r, i;
6774
6775         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6776                 return -EINVAL;
6777
6778         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6779                                         adev->gfx.num_gfx_rings);
6780         if (r) {
6781                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6782                 return r;
6783         }
6784
6785         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6786                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6787
6788         return amdgpu_ring_test_helper(kiq_ring);
6789 }
6790 #endif
6791
6792 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6793 {
6794         int r, i;
6795         struct amdgpu_ring *ring;
6796
6797         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6798                 ring = &adev->gfx.gfx_ring[i];
6799
6800                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6801                 if (unlikely(r != 0))
6802                         goto done;
6803
6804                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6805                 if (!r) {
6806                         r = gfx_v10_0_gfx_init_queue(ring);
6807                         amdgpu_bo_kunmap(ring->mqd_obj);
6808                         ring->mqd_ptr = NULL;
6809                 }
6810                 amdgpu_bo_unreserve(ring->mqd_obj);
6811                 if (r)
6812                         goto done;
6813         }
6814 #ifndef BRING_UP_DEBUG
6815         r = gfx_v10_0_kiq_enable_kgq(adev);
6816         if (r)
6817                 goto done;
6818 #endif
6819         r = gfx_v10_0_cp_gfx_start(adev);
6820         if (r)
6821                 goto done;
6822
6823         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6824                 ring = &adev->gfx.gfx_ring[i];
6825                 ring->sched.ready = true;
6826         }
6827 done:
6828         return r;
6829 }
6830
6831 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6832                                       struct amdgpu_mqd_prop *prop)
6833 {
6834         struct v10_compute_mqd *mqd = m;
6835         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6836         uint32_t tmp;
6837
6838         mqd->header = 0xC0310800;
6839         mqd->compute_pipelinestat_enable = 0x00000001;
6840         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6841         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6842         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6843         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6844         mqd->compute_misc_reserved = 0x00000003;
6845
6846         eop_base_addr = prop->eop_gpu_addr >> 8;
6847         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6848         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6849
6850         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6851         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6852         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6853                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6854
6855         mqd->cp_hqd_eop_control = tmp;
6856
6857         /* enable doorbell? */
6858         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6859
6860         if (prop->use_doorbell) {
6861                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6862                                     DOORBELL_OFFSET, prop->doorbell_index);
6863                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6864                                     DOORBELL_EN, 1);
6865                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6866                                     DOORBELL_SOURCE, 0);
6867                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6868                                     DOORBELL_HIT, 0);
6869         } else {
6870                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6871                                     DOORBELL_EN, 0);
6872         }
6873
6874         mqd->cp_hqd_pq_doorbell_control = tmp;
6875
6876         /* disable the queue if it's active */
6877         mqd->cp_hqd_dequeue_request = 0;
6878         mqd->cp_hqd_pq_rptr = 0;
6879         mqd->cp_hqd_pq_wptr_lo = 0;
6880         mqd->cp_hqd_pq_wptr_hi = 0;
6881
6882         /* set the pointer to the MQD */
6883         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6884         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6885
6886         /* set MQD vmid to 0 */
6887         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6888         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6889         mqd->cp_mqd_control = tmp;
6890
6891         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6892         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6893         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6894         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6895
6896         /* set up the HQD, this is similar to CP_RB0_CNTL */
6897         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6898         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6899                             (order_base_2(prop->queue_size / 4) - 1));
6900         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6901                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6902 #ifdef __BIG_ENDIAN
6903         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6904 #endif
6905         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6906         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6907         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6908         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6909         mqd->cp_hqd_pq_control = tmp;
6910
6911         /* set the wb address whether it's enabled or not */
6912         wb_gpu_addr = prop->rptr_gpu_addr;
6913         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6914         mqd->cp_hqd_pq_rptr_report_addr_hi =
6915                 upper_32_bits(wb_gpu_addr) & 0xffff;
6916
6917         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6918         wb_gpu_addr = prop->wptr_gpu_addr;
6919         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6920         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6921
6922         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6923         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6924
6925         /* set the vmid for the queue */
6926         mqd->cp_hqd_vmid = 0;
6927
6928         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6929         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6930         mqd->cp_hqd_persistent_state = tmp;
6931
6932         /* set MIN_IB_AVAIL_SIZE */
6933         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6934         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6935         mqd->cp_hqd_ib_control = tmp;
6936
6937         /* set static priority for a compute queue/ring */
6938         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6939         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6940
6941         mqd->cp_hqd_active = prop->hqd_active;
6942
6943         return 0;
6944 }
6945
6946 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6947 {
6948         struct amdgpu_device *adev = ring->adev;
6949         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6950         int j;
6951
6952         /* inactivate the queue */
6953         if (amdgpu_sriov_vf(adev))
6954                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6955
6956         /* disable wptr polling */
6957         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6958
6959         /* disable the queue if it's active */
6960         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6961                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6962                 for (j = 0; j < adev->usec_timeout; j++) {
6963                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6964                                 break;
6965                         udelay(1);
6966                 }
6967                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6968                        mqd->cp_hqd_dequeue_request);
6969                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6970                        mqd->cp_hqd_pq_rptr);
6971                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6972                        mqd->cp_hqd_pq_wptr_lo);
6973                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6974                        mqd->cp_hqd_pq_wptr_hi);
6975         }
6976
6977         /* disable doorbells */
6978         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6979
6980         /* write the EOP addr */
6981         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6982                mqd->cp_hqd_eop_base_addr_lo);
6983         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6984                mqd->cp_hqd_eop_base_addr_hi);
6985
6986         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6987         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6988                mqd->cp_hqd_eop_control);
6989
6990         /* set the pointer to the MQD */
6991         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6992                mqd->cp_mqd_base_addr_lo);
6993         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6994                mqd->cp_mqd_base_addr_hi);
6995
6996         /* set MQD vmid to 0 */
6997         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6998                mqd->cp_mqd_control);
6999
7000         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7001         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7002                mqd->cp_hqd_pq_base_lo);
7003         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7004                mqd->cp_hqd_pq_base_hi);
7005
7006         /* set up the HQD, this is similar to CP_RB0_CNTL */
7007         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7008                mqd->cp_hqd_pq_control);
7009
7010         /* set the wb address whether it's enabled or not */
7011         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7012                 mqd->cp_hqd_pq_rptr_report_addr_lo);
7013         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7014                 mqd->cp_hqd_pq_rptr_report_addr_hi);
7015
7016         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7017         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7018                mqd->cp_hqd_pq_wptr_poll_addr_lo);
7019         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7020                mqd->cp_hqd_pq_wptr_poll_addr_hi);
7021
7022         /* enable the doorbell if requested */
7023         if (ring->use_doorbell) {
7024                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7025                         (adev->doorbell_index.kiq * 2) << 2);
7026                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7027                         (adev->doorbell_index.userqueue_end * 2) << 2);
7028         }
7029
7030         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7031                mqd->cp_hqd_pq_doorbell_control);
7032
7033         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7034         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7035                mqd->cp_hqd_pq_wptr_lo);
7036         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7037                mqd->cp_hqd_pq_wptr_hi);
7038
7039         /* set the vmid for the queue */
7040         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7041
7042         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7043                mqd->cp_hqd_persistent_state);
7044
7045         /* activate the queue */
7046         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7047                mqd->cp_hqd_active);
7048
7049         if (ring->use_doorbell)
7050                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7051
7052         return 0;
7053 }
7054
7055 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7056 {
7057         struct amdgpu_device *adev = ring->adev;
7058         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7059         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7060
7061         gfx_v10_0_kiq_setting(ring);
7062
7063         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7064                 /* reset MQD to a clean status */
7065                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7066                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7067
7068                 /* reset ring buffer */
7069                 ring->wptr = 0;
7070                 amdgpu_ring_clear_ring(ring);
7071
7072                 mutex_lock(&adev->srbm_mutex);
7073                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7074                 gfx_v10_0_kiq_init_register(ring);
7075                 nv_grbm_select(adev, 0, 0, 0, 0);
7076                 mutex_unlock(&adev->srbm_mutex);
7077         } else {
7078                 memset((void *)mqd, 0, sizeof(*mqd));
7079                 mutex_lock(&adev->srbm_mutex);
7080                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7081                 amdgpu_ring_init_mqd(ring);
7082                 gfx_v10_0_kiq_init_register(ring);
7083                 nv_grbm_select(adev, 0, 0, 0, 0);
7084                 mutex_unlock(&adev->srbm_mutex);
7085
7086                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7087                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7088         }
7089
7090         return 0;
7091 }
7092
7093 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7094 {
7095         struct amdgpu_device *adev = ring->adev;
7096         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7097         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7098
7099         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7100                 memset((void *)mqd, 0, sizeof(*mqd));
7101                 mutex_lock(&adev->srbm_mutex);
7102                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7103                 amdgpu_ring_init_mqd(ring);
7104                 nv_grbm_select(adev, 0, 0, 0, 0);
7105                 mutex_unlock(&adev->srbm_mutex);
7106
7107                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7108                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7109         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7110                 /* reset MQD to a clean status */
7111                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7112                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7113
7114                 /* reset ring buffer */
7115                 ring->wptr = 0;
7116                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7117                 amdgpu_ring_clear_ring(ring);
7118         } else {
7119                 amdgpu_ring_clear_ring(ring);
7120         }
7121
7122         return 0;
7123 }
7124
7125 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7126 {
7127         struct amdgpu_ring *ring;
7128         int r;
7129
7130         ring = &adev->gfx.kiq.ring;
7131
7132         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7133         if (unlikely(r != 0))
7134                 return r;
7135
7136         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7137         if (unlikely(r != 0))
7138                 return r;
7139
7140         gfx_v10_0_kiq_init_queue(ring);
7141         amdgpu_bo_kunmap(ring->mqd_obj);
7142         ring->mqd_ptr = NULL;
7143         amdgpu_bo_unreserve(ring->mqd_obj);
7144         ring->sched.ready = true;
7145         return 0;
7146 }
7147
7148 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7149 {
7150         struct amdgpu_ring *ring = NULL;
7151         int r = 0, i;
7152
7153         gfx_v10_0_cp_compute_enable(adev, true);
7154
7155         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7156                 ring = &adev->gfx.compute_ring[i];
7157
7158                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7159                 if (unlikely(r != 0))
7160                         goto done;
7161                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7162                 if (!r) {
7163                         r = gfx_v10_0_kcq_init_queue(ring);
7164                         amdgpu_bo_kunmap(ring->mqd_obj);
7165                         ring->mqd_ptr = NULL;
7166                 }
7167                 amdgpu_bo_unreserve(ring->mqd_obj);
7168                 if (r)
7169                         goto done;
7170         }
7171
7172         r = amdgpu_gfx_enable_kcq(adev);
7173 done:
7174         return r;
7175 }
7176
7177 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7178 {
7179         int r, i;
7180         struct amdgpu_ring *ring;
7181
7182         if (!(adev->flags & AMD_IS_APU))
7183                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7184
7185         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7186                 /* legacy firmware loading */
7187                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7188                 if (r)
7189                         return r;
7190
7191                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7192                 if (r)
7193                         return r;
7194         }
7195
7196         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7197                 r = amdgpu_mes_kiq_hw_init(adev);
7198         else
7199                 r = gfx_v10_0_kiq_resume(adev);
7200         if (r)
7201                 return r;
7202
7203         r = gfx_v10_0_kcq_resume(adev);
7204         if (r)
7205                 return r;
7206
7207         if (!amdgpu_async_gfx_ring) {
7208                 r = gfx_v10_0_cp_gfx_resume(adev);
7209                 if (r)
7210                         return r;
7211         } else {
7212                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7213                 if (r)
7214                         return r;
7215         }
7216
7217         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7218                 ring = &adev->gfx.gfx_ring[i];
7219                 r = amdgpu_ring_test_helper(ring);
7220                 if (r)
7221                         return r;
7222         }
7223
7224         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7225                 ring = &adev->gfx.compute_ring[i];
7226                 r = amdgpu_ring_test_helper(ring);
7227                 if (r)
7228                         return r;
7229         }
7230
7231         return 0;
7232 }
7233
7234 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7235 {
7236         gfx_v10_0_cp_gfx_enable(adev, enable);
7237         gfx_v10_0_cp_compute_enable(adev, enable);
7238 }
7239
7240 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7241 {
7242         uint32_t data, pattern = 0xDEADBEEF;
7243
7244         /* check if mmVGT_ESGS_RING_SIZE_UMD
7245          * has been remapped to mmVGT_ESGS_RING_SIZE */
7246         switch (adev->ip_versions[GC_HWIP][0]) {
7247         case IP_VERSION(10, 3, 0):
7248         case IP_VERSION(10, 3, 2):
7249         case IP_VERSION(10, 3, 4):
7250         case IP_VERSION(10, 3, 5):
7251                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7252                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7253                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7254
7255                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7256                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7257                         return true;
7258                 } else {
7259                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7260                         return false;
7261                 }
7262                 break;
7263         case IP_VERSION(10, 3, 1):
7264         case IP_VERSION(10, 3, 3):
7265         case IP_VERSION(10, 3, 6):
7266         case IP_VERSION(10, 3, 7):
7267                 return true;
7268         default:
7269                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7270                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7271                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7272
7273                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7274                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7275                         return true;
7276                 } else {
7277                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7278                         return false;
7279                 }
7280                 break;
7281         }
7282 }
7283
7284 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7285 {
7286         uint32_t data;
7287
7288         if (amdgpu_sriov_vf(adev))
7289                 return;
7290
7291         /* initialize cam_index to 0
7292          * index will auto-inc after each data writting */
7293         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7294
7295         switch (adev->ip_versions[GC_HWIP][0]) {
7296         case IP_VERSION(10, 3, 0):
7297         case IP_VERSION(10, 3, 2):
7298         case IP_VERSION(10, 3, 1):
7299         case IP_VERSION(10, 3, 4):
7300         case IP_VERSION(10, 3, 5):
7301         case IP_VERSION(10, 3, 6):
7302         case IP_VERSION(10, 3, 3):
7303         case IP_VERSION(10, 3, 7):
7304                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7305                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7306                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7307                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7308                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7309                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7310                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7311
7312                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7313                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7314                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7315                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7316                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7317                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7318                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7319
7320                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7321                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7322                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7323                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7324                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7325                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7326                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7327
7328                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7329                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7330                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7331                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7332                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7333                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7334                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7335
7336                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7337                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7338                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7339                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7340                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7341                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7342                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7343
7344                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7345                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7346                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7347                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7348                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7349                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7350                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7351
7352                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7353                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7354                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7355                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7356                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7357                 break;
7358         default:
7359                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7360                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7361                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7362                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7363                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7364                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7365                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7366
7367                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7368                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7369                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7370                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7371                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7372                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7373                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7374
7375                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7376                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7377                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7378                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7379                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7380                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7381                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7382
7383                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7384                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7385                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7386                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7387                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7388                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7389                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7390
7391                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7392                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7393                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7394                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7395                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7396                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7397                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7398
7399                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7400                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7401                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7402                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7403                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7404                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7405                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7406
7407                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7408                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7409                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7410                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7411                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7412                 break;
7413         }
7414
7415         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7416         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7417 }
7418
7419 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7420 {
7421         uint32_t data;
7422         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7423         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7424         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7425
7426         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7427         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7428         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7429 }
7430
7431 static int gfx_v10_0_hw_init(void *handle)
7432 {
7433         int r;
7434         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7435
7436         if (!amdgpu_emu_mode)
7437                 gfx_v10_0_init_golden_registers(adev);
7438
7439         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7440                 /**
7441                  * For gfx 10, rlc firmware loading relies on smu firmware is
7442                  * loaded firstly, so in direct type, it has to load smc ucode
7443                  * here before rlc.
7444                  */
7445                 if (!(adev->flags & AMD_IS_APU)) {
7446                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7447                         if (r)
7448                                 return r;
7449                 }
7450                 gfx_v10_0_disable_gpa_mode(adev);
7451         }
7452
7453         /* if GRBM CAM not remapped, set up the remapping */
7454         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7455                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7456
7457         gfx_v10_0_constants_init(adev);
7458
7459         r = gfx_v10_0_rlc_resume(adev);
7460         if (r)
7461                 return r;
7462
7463         /*
7464          * init golden registers and rlc resume may override some registers,
7465          * reconfig them here
7466          */
7467         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7468             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7469             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7470                 gfx_v10_0_tcp_harvest(adev);
7471
7472         r = gfx_v10_0_cp_resume(adev);
7473         if (r)
7474                 return r;
7475
7476         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7477                 gfx_v10_3_program_pbb_mode(adev);
7478
7479         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7480                 gfx_v10_3_set_power_brake_sequence(adev);
7481
7482         return r;
7483 }
7484
7485 #ifndef BRING_UP_DEBUG
7486 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7487 {
7488         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7489         struct amdgpu_ring *kiq_ring = &kiq->ring;
7490         int i;
7491
7492         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7493                 return -EINVAL;
7494
7495         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7496                                         adev->gfx.num_gfx_rings))
7497                 return -ENOMEM;
7498
7499         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7500                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7501                                            PREEMPT_QUEUES, 0, 0);
7502
7503         return amdgpu_ring_test_helper(kiq_ring);
7504 }
7505 #endif
7506
7507 static int gfx_v10_0_hw_fini(void *handle)
7508 {
7509         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7510         int r;
7511         uint32_t tmp;
7512
7513         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7514         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7515
7516         if (!adev->no_hw_access) {
7517 #ifndef BRING_UP_DEBUG
7518                 if (amdgpu_async_gfx_ring) {
7519                         r = gfx_v10_0_kiq_disable_kgq(adev);
7520                         if (r)
7521                                 DRM_ERROR("KGQ disable failed\n");
7522                 }
7523 #endif
7524                 if (amdgpu_gfx_disable_kcq(adev))
7525                         DRM_ERROR("KCQ disable failed\n");
7526         }
7527
7528         if (amdgpu_sriov_vf(adev)) {
7529                 gfx_v10_0_cp_gfx_enable(adev, false);
7530                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7531                 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7532                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7533                         tmp &= 0xffffff00;
7534                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7535                 } else {
7536                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7537                         tmp &= 0xffffff00;
7538                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7539                 }
7540
7541                 return 0;
7542         }
7543         gfx_v10_0_cp_enable(adev, false);
7544         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7545
7546         return 0;
7547 }
7548
7549 static int gfx_v10_0_suspend(void *handle)
7550 {
7551         return gfx_v10_0_hw_fini(handle);
7552 }
7553
7554 static int gfx_v10_0_resume(void *handle)
7555 {
7556         return gfx_v10_0_hw_init(handle);
7557 }
7558
7559 static bool gfx_v10_0_is_idle(void *handle)
7560 {
7561         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7562
7563         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7564                                 GRBM_STATUS, GUI_ACTIVE))
7565                 return false;
7566         else
7567                 return true;
7568 }
7569
7570 static int gfx_v10_0_wait_for_idle(void *handle)
7571 {
7572         unsigned i;
7573         u32 tmp;
7574         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7575
7576         for (i = 0; i < adev->usec_timeout; i++) {
7577                 /* read MC_STATUS */
7578                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7579                         GRBM_STATUS__GUI_ACTIVE_MASK;
7580
7581                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7582                         return 0;
7583                 udelay(1);
7584         }
7585         return -ETIMEDOUT;
7586 }
7587
7588 static int gfx_v10_0_soft_reset(void *handle)
7589 {
7590         u32 grbm_soft_reset = 0;
7591         u32 tmp;
7592         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7593
7594         /* GRBM_STATUS */
7595         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7596         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7597                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7598                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7599                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7600                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7601                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7602                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7603                                                 1);
7604                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7605                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7606                                                 1);
7607         }
7608
7609         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7610                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7611                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7612                                                 1);
7613         }
7614
7615         /* GRBM_STATUS2 */
7616         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7617         switch (adev->ip_versions[GC_HWIP][0]) {
7618         case IP_VERSION(10, 3, 0):
7619         case IP_VERSION(10, 3, 2):
7620         case IP_VERSION(10, 3, 1):
7621         case IP_VERSION(10, 3, 4):
7622         case IP_VERSION(10, 3, 5):
7623         case IP_VERSION(10, 3, 6):
7624         case IP_VERSION(10, 3, 3):
7625                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7626                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7627                                                         GRBM_SOFT_RESET,
7628                                                         SOFT_RESET_RLC,
7629                                                         1);
7630                 break;
7631         default:
7632                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7633                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7634                                                         GRBM_SOFT_RESET,
7635                                                         SOFT_RESET_RLC,
7636                                                         1);
7637                 break;
7638         }
7639
7640         if (grbm_soft_reset) {
7641                 /* stop the rlc */
7642                 gfx_v10_0_rlc_stop(adev);
7643
7644                 /* Disable GFX parsing/prefetching */
7645                 gfx_v10_0_cp_gfx_enable(adev, false);
7646
7647                 /* Disable MEC parsing/prefetching */
7648                 gfx_v10_0_cp_compute_enable(adev, false);
7649
7650                 if (grbm_soft_reset) {
7651                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7652                         tmp |= grbm_soft_reset;
7653                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7654                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7655                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7656
7657                         udelay(50);
7658
7659                         tmp &= ~grbm_soft_reset;
7660                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7661                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7662                 }
7663
7664                 /* Wait a little for things to settle down */
7665                 udelay(50);
7666         }
7667         return 0;
7668 }
7669
7670 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7671 {
7672         uint64_t clock, clock_lo, clock_hi, hi_check;
7673
7674         switch (adev->ip_versions[GC_HWIP][0]) {
7675         case IP_VERSION(10, 3, 1):
7676         case IP_VERSION(10, 3, 3):
7677         case IP_VERSION(10, 3, 7):
7678                 preempt_disable();
7679                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7680                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7681                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7682                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7683                  * roughly every 42 seconds.
7684                  */
7685                 if (hi_check != clock_hi) {
7686                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7687                         clock_hi = hi_check;
7688                 }
7689                 preempt_enable();
7690                 clock = clock_lo | (clock_hi << 32ULL);
7691                 break;
7692         case IP_VERSION(10, 3, 6):
7693                 preempt_disable();
7694                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7695                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7696                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7697                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7698                  * roughly every 42 seconds.
7699                  */
7700                 if (hi_check != clock_hi) {
7701                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7702                         clock_hi = hi_check;
7703                 }
7704                 preempt_enable();
7705                 clock = clock_lo | (clock_hi << 32ULL);
7706                 break;
7707         default:
7708                 preempt_disable();
7709                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7710                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7711                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7712                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7713                  * roughly every 42 seconds.
7714                  */
7715                 if (hi_check != clock_hi) {
7716                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7717                         clock_hi = hi_check;
7718                 }
7719                 preempt_enable();
7720                 clock = clock_lo | (clock_hi << 32ULL);
7721                 break;
7722         }
7723         return clock;
7724 }
7725
7726 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7727                                            uint32_t vmid,
7728                                            uint32_t gds_base, uint32_t gds_size,
7729                                            uint32_t gws_base, uint32_t gws_size,
7730                                            uint32_t oa_base, uint32_t oa_size)
7731 {
7732         struct amdgpu_device *adev = ring->adev;
7733
7734         /* GDS Base */
7735         gfx_v10_0_write_data_to_reg(ring, 0, false,
7736                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7737                                     gds_base);
7738
7739         /* GDS Size */
7740         gfx_v10_0_write_data_to_reg(ring, 0, false,
7741                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7742                                     gds_size);
7743
7744         /* GWS */
7745         gfx_v10_0_write_data_to_reg(ring, 0, false,
7746                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7747                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7748
7749         /* OA */
7750         gfx_v10_0_write_data_to_reg(ring, 0, false,
7751                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7752                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7753 }
7754
7755 static int gfx_v10_0_early_init(void *handle)
7756 {
7757         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7758
7759         switch (adev->ip_versions[GC_HWIP][0]) {
7760         case IP_VERSION(10, 1, 10):
7761         case IP_VERSION(10, 1, 1):
7762         case IP_VERSION(10, 1, 2):
7763         case IP_VERSION(10, 1, 3):
7764         case IP_VERSION(10, 1, 4):
7765                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7766                 break;
7767         case IP_VERSION(10, 3, 0):
7768         case IP_VERSION(10, 3, 2):
7769         case IP_VERSION(10, 3, 1):
7770         case IP_VERSION(10, 3, 4):
7771         case IP_VERSION(10, 3, 5):
7772         case IP_VERSION(10, 3, 6):
7773         case IP_VERSION(10, 3, 3):
7774         case IP_VERSION(10, 3, 7):
7775                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7776                 break;
7777         default:
7778                 break;
7779         }
7780
7781         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7782                                           AMDGPU_MAX_COMPUTE_RINGS);
7783
7784         gfx_v10_0_set_kiq_pm4_funcs(adev);
7785         gfx_v10_0_set_ring_funcs(adev);
7786         gfx_v10_0_set_irq_funcs(adev);
7787         gfx_v10_0_set_gds_init(adev);
7788         gfx_v10_0_set_rlc_funcs(adev);
7789         gfx_v10_0_set_mqd_funcs(adev);
7790
7791         /* init rlcg reg access ctrl */
7792         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7793
7794         return 0;
7795 }
7796
7797 static int gfx_v10_0_late_init(void *handle)
7798 {
7799         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7800         int r;
7801
7802         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7803         if (r)
7804                 return r;
7805
7806         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7807         if (r)
7808                 return r;
7809
7810         return 0;
7811 }
7812
7813 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7814 {
7815         uint32_t rlc_cntl;
7816
7817         /* if RLC is not enabled, do nothing */
7818         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7819         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7820 }
7821
7822 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7823 {
7824         uint32_t data;
7825         unsigned i;
7826
7827         data = RLC_SAFE_MODE__CMD_MASK;
7828         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7829
7830         switch (adev->ip_versions[GC_HWIP][0]) {
7831         case IP_VERSION(10, 3, 0):
7832         case IP_VERSION(10, 3, 2):
7833         case IP_VERSION(10, 3, 1):
7834         case IP_VERSION(10, 3, 4):
7835         case IP_VERSION(10, 3, 5):
7836         case IP_VERSION(10, 3, 6):
7837         case IP_VERSION(10, 3, 3):
7838         case IP_VERSION(10, 3, 7):
7839                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7840
7841                 /* wait for RLC_SAFE_MODE */
7842                 for (i = 0; i < adev->usec_timeout; i++) {
7843                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7844                                            RLC_SAFE_MODE, CMD))
7845                                 break;
7846                         udelay(1);
7847                 }
7848                 break;
7849         default:
7850                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7851
7852                 /* wait for RLC_SAFE_MODE */
7853                 for (i = 0; i < adev->usec_timeout; i++) {
7854                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7855                                            RLC_SAFE_MODE, CMD))
7856                                 break;
7857                         udelay(1);
7858                 }
7859                 break;
7860         }
7861 }
7862
7863 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7864 {
7865         uint32_t data;
7866
7867         data = RLC_SAFE_MODE__CMD_MASK;
7868         switch (adev->ip_versions[GC_HWIP][0]) {
7869         case IP_VERSION(10, 3, 0):
7870         case IP_VERSION(10, 3, 2):
7871         case IP_VERSION(10, 3, 1):
7872         case IP_VERSION(10, 3, 4):
7873         case IP_VERSION(10, 3, 5):
7874         case IP_VERSION(10, 3, 6):
7875         case IP_VERSION(10, 3, 3):
7876         case IP_VERSION(10, 3, 7):
7877                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7878                 break;
7879         default:
7880                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7881                 break;
7882         }
7883 }
7884
7885 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7886                                                       bool enable)
7887 {
7888         uint32_t data, def;
7889
7890         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7891                 return;
7892
7893         /* It is disabled by HW by default */
7894         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7895                 /* 0 - Disable some blocks' MGCG */
7896                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7897                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7898                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7899                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7900
7901                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7902                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7903                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7904                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7905                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7906                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7907                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7908                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7909
7910                 if (def != data)
7911                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7912
7913                 /* MGLS is a global flag to control all MGLS in GFX */
7914                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7915                         /* 2 - RLC memory Light sleep */
7916                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7917                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7918                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7919                                 if (def != data)
7920                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7921                         }
7922                         /* 3 - CP memory Light sleep */
7923                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7924                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7925                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7926                                 if (def != data)
7927                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7928                         }
7929                 }
7930         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7931                 /* 1 - MGCG_OVERRIDE */
7932                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7933                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7934                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7935                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7936                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7937                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7938                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7939                 if (def != data)
7940                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7941
7942                 /* 2 - disable MGLS in CP */
7943                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7944                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7945                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7946                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7947                 }
7948
7949                 /* 3 - disable MGLS in RLC */
7950                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7951                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7952                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7953                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7954                 }
7955
7956         }
7957 }
7958
7959 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7960                                            bool enable)
7961 {
7962         uint32_t data, def;
7963
7964         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7965                 return;
7966
7967         /* Enable 3D CGCG/CGLS */
7968         if (enable) {
7969                 /* write cmd to clear cgcg/cgls ov */
7970                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7971
7972                 /* unset CGCG override */
7973                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7974                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7975
7976                 /* update CGCG and CGLS override bits */
7977                 if (def != data)
7978                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7979
7980                 /* enable 3Dcgcg FSM(0x0000363f) */
7981                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7982                 data = 0;
7983
7984                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7985                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7986                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7987
7988                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7989                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7990                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7991
7992                 if (def != data)
7993                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7994
7995                 /* set IDLE_POLL_COUNT(0x00900100) */
7996                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7997                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7998                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7999                 if (def != data)
8000                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8001         } else {
8002                 /* Disable CGCG/CGLS */
8003                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8004
8005                 /* disable cgcg, cgls should be disabled */
8006                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8007                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8008
8009                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8010                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8011
8012                 /* disable cgcg and cgls in FSM */
8013                 if (def != data)
8014                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8015         }
8016 }
8017
8018 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8019                                                       bool enable)
8020 {
8021         uint32_t def, data;
8022
8023         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8024                 return;
8025
8026         if (enable) {
8027                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8028
8029                 /* unset CGCG override */
8030                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8031                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8032
8033                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8034                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8035
8036                 /* update CGCG and CGLS override bits */
8037                 if (def != data)
8038                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8039
8040                 /* enable cgcg FSM(0x0000363F) */
8041                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8042                 data = 0;
8043
8044                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8045                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8046                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8047
8048                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8049                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8050                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8051
8052                 if (def != data)
8053                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8054
8055                 /* set IDLE_POLL_COUNT(0x00900100) */
8056                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8057                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8058                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8059                 if (def != data)
8060                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8061         } else {
8062                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8063
8064                 /* reset CGCG/CGLS bits */
8065                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8066                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8067
8068                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8069                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8070
8071                 /* disable cgcg and cgls in FSM */
8072                 if (def != data)
8073                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8074         }
8075 }
8076
8077 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8078                                                       bool enable)
8079 {
8080         uint32_t def, data;
8081
8082         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8083                 return;
8084
8085         if (enable) {
8086                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8087                 /* unset FGCG override */
8088                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8089                 /* update FGCG override bits */
8090                 if (def != data)
8091                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8092
8093                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8094                 /* unset RLC SRAM CLK GATER override */
8095                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8096                 /* update RLC SRAM CLK GATER override bits */
8097                 if (def != data)
8098                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8099         } else {
8100                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8101                 /* reset FGCG bits */
8102                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8103                 /* disable FGCG*/
8104                 if (def != data)
8105                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8106
8107                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8108                 /* reset RLC SRAM CLK GATER bits */
8109                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8110                 /* disable RLC SRAM CLK*/
8111                 if (def != data)
8112                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8113         }
8114 }
8115
8116 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8117 {
8118         uint32_t reg_data = 0;
8119         uint32_t reg_idx = 0;
8120         uint32_t i;
8121
8122         const uint32_t tcp_ctrl_regs[] = {
8123                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8124                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8125                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8126                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8127                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8128                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8129                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8130                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8131                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8132                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8133                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8134                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8135                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8136                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8137                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8138                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8139                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8140                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8141                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8142                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8143                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8144                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8145                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8146                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8147         };
8148
8149         const uint32_t tcp_ctrl_regs_nv12[] = {
8150                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8151                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8152                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8153                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8154                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8155                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8156                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8157                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8158                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8159                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8160                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8161                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8162                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8163                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8164                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8165                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8166                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8167                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8168                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8169                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8170         };
8171
8172         const uint32_t sm_ctlr_regs[] = {
8173                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8174                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8175                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8176                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8177         };
8178
8179         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8180                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8181                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8182                                   tcp_ctrl_regs_nv12[i];
8183                         reg_data = RREG32(reg_idx);
8184                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8185                         WREG32(reg_idx, reg_data);
8186                 }
8187         } else {
8188                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8189                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8190                                   tcp_ctrl_regs[i];
8191                         reg_data = RREG32(reg_idx);
8192                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8193                         WREG32(reg_idx, reg_data);
8194                 }
8195         }
8196
8197         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8198                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8199                           sm_ctlr_regs[i];
8200                 reg_data = RREG32(reg_idx);
8201                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8202                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8203                 WREG32(reg_idx, reg_data);
8204         }
8205 }
8206
8207 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8208                                             bool enable)
8209 {
8210         amdgpu_gfx_rlc_enter_safe_mode(adev);
8211
8212         if (enable) {
8213                 /* enable FGCG firstly*/
8214                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8215                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8216                  * ===  MGCG + MGLS ===
8217                  */
8218                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8219                 /* ===  CGCG /CGLS for GFX 3D Only === */
8220                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8221                 /* ===  CGCG + CGLS === */
8222                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8223
8224                 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8225                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8226                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8227                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8228         } else {
8229                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8230                  * ===  CGCG + CGLS ===
8231                  */
8232                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8233                 /* ===  CGCG /CGLS for GFX 3D Only === */
8234                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8235                 /* ===  MGCG + MGLS === */
8236                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8237                 /* disable fgcg at last*/
8238                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8239         }
8240
8241         if (adev->cg_flags &
8242             (AMD_CG_SUPPORT_GFX_MGCG |
8243              AMD_CG_SUPPORT_GFX_CGLS |
8244              AMD_CG_SUPPORT_GFX_CGCG |
8245              AMD_CG_SUPPORT_GFX_3D_CGCG |
8246              AMD_CG_SUPPORT_GFX_3D_CGLS))
8247                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8248
8249         amdgpu_gfx_rlc_exit_safe_mode(adev);
8250
8251         return 0;
8252 }
8253
8254 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8255 {
8256         u32 reg, data;
8257
8258         amdgpu_gfx_off_ctrl(adev, false);
8259
8260         /* not for *_SOC15 */
8261         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8262         if (amdgpu_sriov_is_pp_one_vf(adev))
8263                 data = RREG32_NO_KIQ(reg);
8264         else
8265                 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8266
8267         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8268         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8269
8270         if (amdgpu_sriov_is_pp_one_vf(adev))
8271                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8272         else
8273                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8274
8275         amdgpu_gfx_off_ctrl(adev, true);
8276 }
8277
8278 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8279                                         uint32_t offset,
8280                                         struct soc15_reg_rlcg *entries, int arr_size)
8281 {
8282         int i;
8283         uint32_t reg;
8284
8285         if (!entries)
8286                 return false;
8287
8288         for (i = 0; i < arr_size; i++) {
8289                 const struct soc15_reg_rlcg *entry;
8290
8291                 entry = &entries[i];
8292                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8293                 if (offset == reg)
8294                         return true;
8295         }
8296
8297         return false;
8298 }
8299
8300 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8301 {
8302         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8303 }
8304
8305 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8306 {
8307         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8308
8309         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8310                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8311         else
8312                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8313
8314         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8315
8316         /*
8317          * CGPG enablement required and the register to program the hysteresis value
8318          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8319          * in refclk count. Note that RLC FW is modified to take 16 bits from
8320          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8321          *
8322          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8323          * of CGPG enablement starting point.
8324          * Power/performance team will optimize it and might give a new value later.
8325          */
8326         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8327                 switch (adev->ip_versions[GC_HWIP][0]) {
8328                 case IP_VERSION(10, 3, 1):
8329                 case IP_VERSION(10, 3, 3):
8330                 case IP_VERSION(10, 3, 6):
8331                 case IP_VERSION(10, 3, 7):
8332                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8333                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8334                         break;
8335                 default:
8336                         break;
8337                 }
8338         }
8339 }
8340
8341 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8342 {
8343         amdgpu_gfx_rlc_enter_safe_mode(adev);
8344
8345         gfx_v10_cntl_power_gating(adev, enable);
8346
8347         amdgpu_gfx_rlc_exit_safe_mode(adev);
8348 }
8349
8350 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8351         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8352         .set_safe_mode = gfx_v10_0_set_safe_mode,
8353         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8354         .init = gfx_v10_0_rlc_init,
8355         .get_csb_size = gfx_v10_0_get_csb_size,
8356         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8357         .resume = gfx_v10_0_rlc_resume,
8358         .stop = gfx_v10_0_rlc_stop,
8359         .reset = gfx_v10_0_rlc_reset,
8360         .start = gfx_v10_0_rlc_start,
8361         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8362 };
8363
8364 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8365         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8366         .set_safe_mode = gfx_v10_0_set_safe_mode,
8367         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8368         .init = gfx_v10_0_rlc_init,
8369         .get_csb_size = gfx_v10_0_get_csb_size,
8370         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8371         .resume = gfx_v10_0_rlc_resume,
8372         .stop = gfx_v10_0_rlc_stop,
8373         .reset = gfx_v10_0_rlc_reset,
8374         .start = gfx_v10_0_rlc_start,
8375         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8376         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8377 };
8378
8379 static int gfx_v10_0_set_powergating_state(void *handle,
8380                                           enum amd_powergating_state state)
8381 {
8382         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8383         bool enable = (state == AMD_PG_STATE_GATE);
8384
8385         if (amdgpu_sriov_vf(adev))
8386                 return 0;
8387
8388         switch (adev->ip_versions[GC_HWIP][0]) {
8389         case IP_VERSION(10, 1, 10):
8390         case IP_VERSION(10, 1, 1):
8391         case IP_VERSION(10, 1, 2):
8392         case IP_VERSION(10, 3, 0):
8393         case IP_VERSION(10, 3, 2):
8394         case IP_VERSION(10, 3, 4):
8395         case IP_VERSION(10, 3, 5):
8396                 amdgpu_gfx_off_ctrl(adev, enable);
8397                 break;
8398         case IP_VERSION(10, 3, 1):
8399         case IP_VERSION(10, 3, 3):
8400         case IP_VERSION(10, 3, 6):
8401         case IP_VERSION(10, 3, 7):
8402                 gfx_v10_cntl_pg(adev, enable);
8403                 amdgpu_gfx_off_ctrl(adev, enable);
8404                 break;
8405         default:
8406                 break;
8407         }
8408         return 0;
8409 }
8410
8411 static int gfx_v10_0_set_clockgating_state(void *handle,
8412                                           enum amd_clockgating_state state)
8413 {
8414         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8415
8416         if (amdgpu_sriov_vf(adev))
8417                 return 0;
8418
8419         switch (adev->ip_versions[GC_HWIP][0]) {
8420         case IP_VERSION(10, 1, 10):
8421         case IP_VERSION(10, 1, 1):
8422         case IP_VERSION(10, 1, 2):
8423         case IP_VERSION(10, 3, 0):
8424         case IP_VERSION(10, 3, 2):
8425         case IP_VERSION(10, 3, 1):
8426         case IP_VERSION(10, 3, 4):
8427         case IP_VERSION(10, 3, 5):
8428         case IP_VERSION(10, 3, 6):
8429         case IP_VERSION(10, 3, 3):
8430         case IP_VERSION(10, 3, 7):
8431                 gfx_v10_0_update_gfx_clock_gating(adev,
8432                                                  state == AMD_CG_STATE_GATE);
8433                 break;
8434         default:
8435                 break;
8436         }
8437         return 0;
8438 }
8439
8440 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8441 {
8442         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8443         int data;
8444
8445         /* AMD_CG_SUPPORT_GFX_FGCG */
8446         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8447         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8448                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8449
8450         /* AMD_CG_SUPPORT_GFX_MGCG */
8451         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8452         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8453                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8454
8455         /* AMD_CG_SUPPORT_GFX_CGCG */
8456         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8457         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8458                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8459
8460         /* AMD_CG_SUPPORT_GFX_CGLS */
8461         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8462                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8463
8464         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8465         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8466         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8467                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8468
8469         /* AMD_CG_SUPPORT_GFX_CP_LS */
8470         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8471         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8472                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8473
8474         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8475         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8476         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8477                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8478
8479         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8480         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8481                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8482 }
8483
8484 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8485 {
8486         /* gfx10 is 32bit rptr*/
8487         return *(uint32_t *)ring->rptr_cpu_addr;
8488 }
8489
8490 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8491 {
8492         struct amdgpu_device *adev = ring->adev;
8493         u64 wptr;
8494
8495         /* XXX check if swapping is necessary on BE */
8496         if (ring->use_doorbell) {
8497                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8498         } else {
8499                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8500                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8501         }
8502
8503         return wptr;
8504 }
8505
8506 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8507 {
8508         struct amdgpu_device *adev = ring->adev;
8509
8510         if (ring->use_doorbell) {
8511                 /* XXX check if swapping is necessary on BE */
8512                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
8513                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8514         } else {
8515                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8516                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8517         }
8518 }
8519
8520 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8521 {
8522         /* gfx10 hardware is 32bit rptr */
8523         return *(uint32_t *)ring->rptr_cpu_addr;
8524 }
8525
8526 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8527 {
8528         u64 wptr;
8529
8530         /* XXX check if swapping is necessary on BE */
8531         if (ring->use_doorbell)
8532                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8533         else
8534                 BUG();
8535         return wptr;
8536 }
8537
8538 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8539 {
8540         struct amdgpu_device *adev = ring->adev;
8541
8542         /* XXX check if swapping is necessary on BE */
8543         if (ring->use_doorbell) {
8544                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
8545                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8546         } else {
8547                 BUG(); /* only DOORBELL method supported on gfx10 now */
8548         }
8549 }
8550
8551 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8552 {
8553         struct amdgpu_device *adev = ring->adev;
8554         u32 ref_and_mask, reg_mem_engine;
8555         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8556
8557         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8558                 switch (ring->me) {
8559                 case 1:
8560                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8561                         break;
8562                 case 2:
8563                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8564                         break;
8565                 default:
8566                         return;
8567                 }
8568                 reg_mem_engine = 0;
8569         } else {
8570                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8571                 reg_mem_engine = 1; /* pfp */
8572         }
8573
8574         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8575                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8576                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8577                                ref_and_mask, ref_and_mask, 0x20);
8578 }
8579
8580 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8581                                        struct amdgpu_job *job,
8582                                        struct amdgpu_ib *ib,
8583                                        uint32_t flags)
8584 {
8585         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8586         u32 header, control = 0;
8587
8588         if (ib->flags & AMDGPU_IB_FLAG_CE)
8589                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8590         else
8591                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8592
8593         control |= ib->length_dw | (vmid << 24);
8594
8595         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8596                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8597
8598                 if (flags & AMDGPU_IB_PREEMPTED)
8599                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8600
8601                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8602                         gfx_v10_0_ring_emit_de_meta(ring,
8603                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8604         }
8605
8606         if (ring->is_mes_queue)
8607                 /* inherit vmid from mqd */
8608                 control |= 0x400000;
8609
8610         amdgpu_ring_write(ring, header);
8611         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8612         amdgpu_ring_write(ring,
8613 #ifdef __BIG_ENDIAN
8614                 (2 << 0) |
8615 #endif
8616                 lower_32_bits(ib->gpu_addr));
8617         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8618         amdgpu_ring_write(ring, control);
8619 }
8620
8621 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8622                                            struct amdgpu_job *job,
8623                                            struct amdgpu_ib *ib,
8624                                            uint32_t flags)
8625 {
8626         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8627         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8628
8629         if (ring->is_mes_queue)
8630                 /* inherit vmid from mqd */
8631                 control |= 0x40000000;
8632
8633         /* Currently, there is a high possibility to get wave ID mismatch
8634          * between ME and GDS, leading to a hw deadlock, because ME generates
8635          * different wave IDs than the GDS expects. This situation happens
8636          * randomly when at least 5 compute pipes use GDS ordered append.
8637          * The wave IDs generated by ME are also wrong after suspend/resume.
8638          * Those are probably bugs somewhere else in the kernel driver.
8639          *
8640          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8641          * GDS to 0 for this ring (me/pipe).
8642          */
8643         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8644                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8645                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8646                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8647         }
8648
8649         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8650         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8651         amdgpu_ring_write(ring,
8652 #ifdef __BIG_ENDIAN
8653                                 (2 << 0) |
8654 #endif
8655                                 lower_32_bits(ib->gpu_addr));
8656         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8657         amdgpu_ring_write(ring, control);
8658 }
8659
8660 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8661                                      u64 seq, unsigned flags)
8662 {
8663         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8664         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8665
8666         /* RELEASE_MEM - flush caches, send int */
8667         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8668         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8669                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8670                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8671                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8672                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8673                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8674                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8675         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8676                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8677
8678         /*
8679          * the address should be Qword aligned if 64bit write, Dword
8680          * aligned if only send 32bit data low (discard data high)
8681          */
8682         if (write64bit)
8683                 BUG_ON(addr & 0x7);
8684         else
8685                 BUG_ON(addr & 0x3);
8686         amdgpu_ring_write(ring, lower_32_bits(addr));
8687         amdgpu_ring_write(ring, upper_32_bits(addr));
8688         amdgpu_ring_write(ring, lower_32_bits(seq));
8689         amdgpu_ring_write(ring, upper_32_bits(seq));
8690         amdgpu_ring_write(ring, ring->is_mes_queue ?
8691                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8692 }
8693
8694 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8695 {
8696         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8697         uint32_t seq = ring->fence_drv.sync_seq;
8698         uint64_t addr = ring->fence_drv.gpu_addr;
8699
8700         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8701                                upper_32_bits(addr), seq, 0xffffffff, 4);
8702 }
8703
8704 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8705                                    uint16_t pasid, uint32_t flush_type,
8706                                    bool all_hub, uint8_t dst_sel)
8707 {
8708         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8709         amdgpu_ring_write(ring,
8710                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8711                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8712                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8713                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8714 }
8715
8716 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8717                                          unsigned vmid, uint64_t pd_addr)
8718 {
8719         if (ring->is_mes_queue)
8720                 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8721         else
8722                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8723
8724         /* compute doesn't have PFP */
8725         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8726                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8727                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8728                 amdgpu_ring_write(ring, 0x0);
8729         }
8730 }
8731
8732 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8733                                           u64 seq, unsigned int flags)
8734 {
8735         struct amdgpu_device *adev = ring->adev;
8736
8737         /* we only allocate 32bit for each seq wb address */
8738         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8739
8740         /* write fence seq to the "addr" */
8741         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8742         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8743                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8744         amdgpu_ring_write(ring, lower_32_bits(addr));
8745         amdgpu_ring_write(ring, upper_32_bits(addr));
8746         amdgpu_ring_write(ring, lower_32_bits(seq));
8747
8748         if (flags & AMDGPU_FENCE_FLAG_INT) {
8749                 /* set register to trigger INT */
8750                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8751                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8752                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8753                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8754                 amdgpu_ring_write(ring, 0);
8755                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8756         }
8757 }
8758
8759 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8760 {
8761         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8762         amdgpu_ring_write(ring, 0);
8763 }
8764
8765 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8766                                          uint32_t flags)
8767 {
8768         uint32_t dw2 = 0;
8769
8770         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8771                 gfx_v10_0_ring_emit_ce_meta(ring,
8772                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8773
8774         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8775         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8776                 /* set load_global_config & load_global_uconfig */
8777                 dw2 |= 0x8001;
8778                 /* set load_cs_sh_regs */
8779                 dw2 |= 0x01000000;
8780                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8781                 dw2 |= 0x10002;
8782
8783                 /* set load_ce_ram if preamble presented */
8784                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8785                         dw2 |= 0x10000000;
8786         } else {
8787                 /* still load_ce_ram if this is the first time preamble presented
8788                  * although there is no context switch happens.
8789                  */
8790                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8791                         dw2 |= 0x10000000;
8792         }
8793
8794         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8795         amdgpu_ring_write(ring, dw2);
8796         amdgpu_ring_write(ring, 0);
8797 }
8798
8799 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8800 {
8801         unsigned ret;
8802
8803         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8804         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8805         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8806         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8807         ret = ring->wptr & ring->buf_mask;
8808         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8809
8810         return ret;
8811 }
8812
8813 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8814 {
8815         unsigned cur;
8816         BUG_ON(offset > ring->buf_mask);
8817         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8818
8819         cur = (ring->wptr - 1) & ring->buf_mask;
8820         if (likely(cur > offset))
8821                 ring->ring[offset] = cur - offset;
8822         else
8823                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8824 }
8825
8826 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8827 {
8828         int i, r = 0;
8829         struct amdgpu_device *adev = ring->adev;
8830         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8831         struct amdgpu_ring *kiq_ring = &kiq->ring;
8832         unsigned long flags;
8833
8834         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8835                 return -EINVAL;
8836
8837         spin_lock_irqsave(&kiq->ring_lock, flags);
8838
8839         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8840                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8841                 return -ENOMEM;
8842         }
8843
8844         /* assert preemption condition */
8845         amdgpu_ring_set_preempt_cond_exec(ring, false);
8846
8847         /* assert IB preemption, emit the trailing fence */
8848         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8849                                    ring->trail_fence_gpu_addr,
8850                                    ++ring->trail_seq);
8851         amdgpu_ring_commit(kiq_ring);
8852
8853         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8854
8855         /* poll the trailing fence */
8856         for (i = 0; i < adev->usec_timeout; i++) {
8857                 if (ring->trail_seq ==
8858                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8859                         break;
8860                 udelay(1);
8861         }
8862
8863         if (i >= adev->usec_timeout) {
8864                 r = -EINVAL;
8865                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8866         }
8867
8868         /* deassert preemption condition */
8869         amdgpu_ring_set_preempt_cond_exec(ring, true);
8870         return r;
8871 }
8872
8873 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8874 {
8875         struct amdgpu_device *adev = ring->adev;
8876         struct v10_ce_ib_state ce_payload = {0};
8877         uint64_t offset, ce_payload_gpu_addr;
8878         void *ce_payload_cpu_addr;
8879         int cnt;
8880
8881         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8882
8883         if (ring->is_mes_queue) {
8884                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8885                                   gfx[0].gfx_meta_data) +
8886                         offsetof(struct v10_gfx_meta_data, ce_payload);
8887                 ce_payload_gpu_addr =
8888                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8889                 ce_payload_cpu_addr =
8890                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8891         } else {
8892                 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8893                 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8894                 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8895         }
8896
8897         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8898         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8899                                  WRITE_DATA_DST_SEL(8) |
8900                                  WR_CONFIRM) |
8901                                  WRITE_DATA_CACHE_POLICY(0));
8902         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8903         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8904
8905         if (resume)
8906                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8907                                            sizeof(ce_payload) >> 2);
8908         else
8909                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8910                                            sizeof(ce_payload) >> 2);
8911 }
8912
8913 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8914 {
8915         struct amdgpu_device *adev = ring->adev;
8916         struct v10_de_ib_state de_payload = {0};
8917         uint64_t offset, gds_addr, de_payload_gpu_addr;
8918         void *de_payload_cpu_addr;
8919         int cnt;
8920
8921         if (ring->is_mes_queue) {
8922                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8923                                   gfx[0].gfx_meta_data) +
8924                         offsetof(struct v10_gfx_meta_data, de_payload);
8925                 de_payload_gpu_addr =
8926                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8927                 de_payload_cpu_addr =
8928                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8929
8930                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8931                                   gfx[0].gds_backup) +
8932                         offsetof(struct v10_gfx_meta_data, de_payload);
8933                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8934         } else {
8935                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8936                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8937                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8938
8939                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8940                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
8941                                  PAGE_SIZE);
8942         }
8943
8944         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8945         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8946
8947         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8948         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8949         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8950                                  WRITE_DATA_DST_SEL(8) |
8951                                  WR_CONFIRM) |
8952                                  WRITE_DATA_CACHE_POLICY(0));
8953         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8954         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8955
8956         if (resume)
8957                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8958                                            sizeof(de_payload) >> 2);
8959         else
8960                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8961                                            sizeof(de_payload) >> 2);
8962 }
8963
8964 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8965                                     bool secure)
8966 {
8967         uint32_t v = secure ? FRAME_TMZ : 0;
8968
8969         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8970         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8971 }
8972
8973 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8974                                      uint32_t reg_val_offs)
8975 {
8976         struct amdgpu_device *adev = ring->adev;
8977
8978         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8979         amdgpu_ring_write(ring, 0 |     /* src: register*/
8980                                 (5 << 8) |      /* dst: memory */
8981                                 (1 << 20));     /* write confirm */
8982         amdgpu_ring_write(ring, reg);
8983         amdgpu_ring_write(ring, 0);
8984         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8985                                 reg_val_offs * 4));
8986         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8987                                 reg_val_offs * 4));
8988 }
8989
8990 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8991                                    uint32_t val)
8992 {
8993         uint32_t cmd = 0;
8994
8995         switch (ring->funcs->type) {
8996         case AMDGPU_RING_TYPE_GFX:
8997                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8998                 break;
8999         case AMDGPU_RING_TYPE_KIQ:
9000                 cmd = (1 << 16); /* no inc addr */
9001                 break;
9002         default:
9003                 cmd = WR_CONFIRM;
9004                 break;
9005         }
9006         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9007         amdgpu_ring_write(ring, cmd);
9008         amdgpu_ring_write(ring, reg);
9009         amdgpu_ring_write(ring, 0);
9010         amdgpu_ring_write(ring, val);
9011 }
9012
9013 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9014                                         uint32_t val, uint32_t mask)
9015 {
9016         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9017 }
9018
9019 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9020                                                    uint32_t reg0, uint32_t reg1,
9021                                                    uint32_t ref, uint32_t mask)
9022 {
9023         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9024         struct amdgpu_device *adev = ring->adev;
9025         bool fw_version_ok = false;
9026
9027         fw_version_ok = adev->gfx.cp_fw_write_wait;
9028
9029         if (fw_version_ok)
9030                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9031                                        ref, mask, 0x20);
9032         else
9033                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9034                                                            ref, mask);
9035 }
9036
9037 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9038                                          unsigned vmid)
9039 {
9040         struct amdgpu_device *adev = ring->adev;
9041         uint32_t value = 0;
9042
9043         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9044         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9045         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9046         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9047         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9048 }
9049
9050 static void
9051 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9052                                       uint32_t me, uint32_t pipe,
9053                                       enum amdgpu_interrupt_state state)
9054 {
9055         uint32_t cp_int_cntl, cp_int_cntl_reg;
9056
9057         if (!me) {
9058                 switch (pipe) {
9059                 case 0:
9060                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9061                         break;
9062                 case 1:
9063                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9064                         break;
9065                 default:
9066                         DRM_DEBUG("invalid pipe %d\n", pipe);
9067                         return;
9068                 }
9069         } else {
9070                 DRM_DEBUG("invalid me %d\n", me);
9071                 return;
9072         }
9073
9074         switch (state) {
9075         case AMDGPU_IRQ_STATE_DISABLE:
9076                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9077                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9078                                             TIME_STAMP_INT_ENABLE, 0);
9079                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9080                 break;
9081         case AMDGPU_IRQ_STATE_ENABLE:
9082                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9083                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9084                                             TIME_STAMP_INT_ENABLE, 1);
9085                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9086                 break;
9087         default:
9088                 break;
9089         }
9090 }
9091
9092 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9093                                                      int me, int pipe,
9094                                                      enum amdgpu_interrupt_state state)
9095 {
9096         u32 mec_int_cntl, mec_int_cntl_reg;
9097
9098         /*
9099          * amdgpu controls only the first MEC. That's why this function only
9100          * handles the setting of interrupts for this specific MEC. All other
9101          * pipes' interrupts are set by amdkfd.
9102          */
9103
9104         if (me == 1) {
9105                 switch (pipe) {
9106                 case 0:
9107                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9108                         break;
9109                 case 1:
9110                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9111                         break;
9112                 case 2:
9113                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9114                         break;
9115                 case 3:
9116                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9117                         break;
9118                 default:
9119                         DRM_DEBUG("invalid pipe %d\n", pipe);
9120                         return;
9121                 }
9122         } else {
9123                 DRM_DEBUG("invalid me %d\n", me);
9124                 return;
9125         }
9126
9127         switch (state) {
9128         case AMDGPU_IRQ_STATE_DISABLE:
9129                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9130                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9131                                              TIME_STAMP_INT_ENABLE, 0);
9132                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9133                 break;
9134         case AMDGPU_IRQ_STATE_ENABLE:
9135                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9136                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9137                                              TIME_STAMP_INT_ENABLE, 1);
9138                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9139                 break;
9140         default:
9141                 break;
9142         }
9143 }
9144
9145 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9146                                             struct amdgpu_irq_src *src,
9147                                             unsigned type,
9148                                             enum amdgpu_interrupt_state state)
9149 {
9150         switch (type) {
9151         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9152                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9153                 break;
9154         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9155                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9156                 break;
9157         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9158                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9159                 break;
9160         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9161                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9162                 break;
9163         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9164                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9165                 break;
9166         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9167                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9168                 break;
9169         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9170                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9171                 break;
9172         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9173                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9174                 break;
9175         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9176                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9177                 break;
9178         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9179                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9180                 break;
9181         default:
9182                 break;
9183         }
9184         return 0;
9185 }
9186
9187 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9188                              struct amdgpu_irq_src *source,
9189                              struct amdgpu_iv_entry *entry)
9190 {
9191         int i;
9192         u8 me_id, pipe_id, queue_id;
9193         struct amdgpu_ring *ring;
9194         uint32_t mes_queue_id = entry->src_data[0];
9195
9196         DRM_DEBUG("IH: CP EOP\n");
9197
9198         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9199                 struct amdgpu_mes_queue *queue;
9200
9201                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9202
9203                 spin_lock(&adev->mes.queue_id_lock);
9204                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9205                 if (queue) {
9206                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9207                         amdgpu_fence_process(queue->ring);
9208                 }
9209                 spin_unlock(&adev->mes.queue_id_lock);
9210         } else {
9211                 me_id = (entry->ring_id & 0x0c) >> 2;
9212                 pipe_id = (entry->ring_id & 0x03) >> 0;
9213                 queue_id = (entry->ring_id & 0x70) >> 4;
9214
9215                 switch (me_id) {
9216                 case 0:
9217                         if (pipe_id == 0)
9218                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9219                         else
9220                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9221                         break;
9222                 case 1:
9223                 case 2:
9224                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9225                                 ring = &adev->gfx.compute_ring[i];
9226                                 /* Per-queue interrupt is supported for MEC starting from VI.
9227                                  * The interrupt can only be enabled/disabled per pipe instead
9228                                  * of per queue.
9229                                  */
9230                                 if ((ring->me == me_id) &&
9231                                     (ring->pipe == pipe_id) &&
9232                                     (ring->queue == queue_id))
9233                                         amdgpu_fence_process(ring);
9234                         }
9235                         break;
9236                 }
9237         }
9238
9239         return 0;
9240 }
9241
9242 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9243                                               struct amdgpu_irq_src *source,
9244                                               unsigned type,
9245                                               enum amdgpu_interrupt_state state)
9246 {
9247         switch (state) {
9248         case AMDGPU_IRQ_STATE_DISABLE:
9249         case AMDGPU_IRQ_STATE_ENABLE:
9250                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9251                                PRIV_REG_INT_ENABLE,
9252                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9253                 break;
9254         default:
9255                 break;
9256         }
9257
9258         return 0;
9259 }
9260
9261 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9262                                                struct amdgpu_irq_src *source,
9263                                                unsigned type,
9264                                                enum amdgpu_interrupt_state state)
9265 {
9266         switch (state) {
9267         case AMDGPU_IRQ_STATE_DISABLE:
9268         case AMDGPU_IRQ_STATE_ENABLE:
9269                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9270                                PRIV_INSTR_INT_ENABLE,
9271                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9272                 break;
9273         default:
9274                 break;
9275         }
9276
9277         return 0;
9278 }
9279
9280 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9281                                         struct amdgpu_iv_entry *entry)
9282 {
9283         u8 me_id, pipe_id, queue_id;
9284         struct amdgpu_ring *ring;
9285         int i;
9286
9287         me_id = (entry->ring_id & 0x0c) >> 2;
9288         pipe_id = (entry->ring_id & 0x03) >> 0;
9289         queue_id = (entry->ring_id & 0x70) >> 4;
9290
9291         switch (me_id) {
9292         case 0:
9293                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9294                         ring = &adev->gfx.gfx_ring[i];
9295                         /* we only enabled 1 gfx queue per pipe for now */
9296                         if (ring->me == me_id && ring->pipe == pipe_id)
9297                                 drm_sched_fault(&ring->sched);
9298                 }
9299                 break;
9300         case 1:
9301         case 2:
9302                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9303                         ring = &adev->gfx.compute_ring[i];
9304                         if (ring->me == me_id && ring->pipe == pipe_id &&
9305                             ring->queue == queue_id)
9306                                 drm_sched_fault(&ring->sched);
9307                 }
9308                 break;
9309         default:
9310                 BUG();
9311         }
9312 }
9313
9314 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9315                                   struct amdgpu_irq_src *source,
9316                                   struct amdgpu_iv_entry *entry)
9317 {
9318         DRM_ERROR("Illegal register access in command stream\n");
9319         gfx_v10_0_handle_priv_fault(adev, entry);
9320         return 0;
9321 }
9322
9323 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9324                                    struct amdgpu_irq_src *source,
9325                                    struct amdgpu_iv_entry *entry)
9326 {
9327         DRM_ERROR("Illegal instruction in command stream\n");
9328         gfx_v10_0_handle_priv_fault(adev, entry);
9329         return 0;
9330 }
9331
9332 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9333                                              struct amdgpu_irq_src *src,
9334                                              unsigned int type,
9335                                              enum amdgpu_interrupt_state state)
9336 {
9337         uint32_t tmp, target;
9338         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9339
9340         if (ring->me == 1)
9341                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9342         else
9343                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9344         target += ring->pipe;
9345
9346         switch (type) {
9347         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9348                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9349                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9350                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9351                                             GENERIC2_INT_ENABLE, 0);
9352                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9353
9354                         tmp = RREG32_SOC15_IP(GC, target);
9355                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9356                                             GENERIC2_INT_ENABLE, 0);
9357                         WREG32_SOC15_IP(GC, target, tmp);
9358                 } else {
9359                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9360                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9361                                             GENERIC2_INT_ENABLE, 1);
9362                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9363
9364                         tmp = RREG32_SOC15_IP(GC, target);
9365                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9366                                             GENERIC2_INT_ENABLE, 1);
9367                         WREG32_SOC15_IP(GC, target, tmp);
9368                 }
9369                 break;
9370         default:
9371                 BUG(); /* kiq only support GENERIC2_INT now */
9372                 break;
9373         }
9374         return 0;
9375 }
9376
9377 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9378                              struct amdgpu_irq_src *source,
9379                              struct amdgpu_iv_entry *entry)
9380 {
9381         u8 me_id, pipe_id, queue_id;
9382         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9383
9384         me_id = (entry->ring_id & 0x0c) >> 2;
9385         pipe_id = (entry->ring_id & 0x03) >> 0;
9386         queue_id = (entry->ring_id & 0x70) >> 4;
9387         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9388                    me_id, pipe_id, queue_id);
9389
9390         amdgpu_fence_process(ring);
9391         return 0;
9392 }
9393
9394 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9395 {
9396         const unsigned int gcr_cntl =
9397                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9398                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9399                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9400                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9401                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9402                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9403                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9404                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9405
9406         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9407         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9408         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9409         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9410         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9411         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9412         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9413         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9414         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9415 }
9416
9417 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9418         .name = "gfx_v10_0",
9419         .early_init = gfx_v10_0_early_init,
9420         .late_init = gfx_v10_0_late_init,
9421         .sw_init = gfx_v10_0_sw_init,
9422         .sw_fini = gfx_v10_0_sw_fini,
9423         .hw_init = gfx_v10_0_hw_init,
9424         .hw_fini = gfx_v10_0_hw_fini,
9425         .suspend = gfx_v10_0_suspend,
9426         .resume = gfx_v10_0_resume,
9427         .is_idle = gfx_v10_0_is_idle,
9428         .wait_for_idle = gfx_v10_0_wait_for_idle,
9429         .soft_reset = gfx_v10_0_soft_reset,
9430         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9431         .set_powergating_state = gfx_v10_0_set_powergating_state,
9432         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9433 };
9434
9435 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9436         .type = AMDGPU_RING_TYPE_GFX,
9437         .align_mask = 0xff,
9438         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9439         .support_64bit_ptrs = true,
9440         .secure_submission_supported = true,
9441         .vmhub = AMDGPU_GFXHUB_0,
9442         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9443         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9444         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9445         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9446                 5 + /* COND_EXEC */
9447                 7 + /* PIPELINE_SYNC */
9448                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9449                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9450                 2 + /* VM_FLUSH */
9451                 8 + /* FENCE for VM_FLUSH */
9452                 20 + /* GDS switch */
9453                 4 + /* double SWITCH_BUFFER,
9454                      * the first COND_EXEC jump to the place
9455                      * just prior to this double SWITCH_BUFFER
9456                      */
9457                 5 + /* COND_EXEC */
9458                 7 + /* HDP_flush */
9459                 4 + /* VGT_flush */
9460                 14 + /* CE_META */
9461                 31 + /* DE_META */
9462                 3 + /* CNTX_CTRL */
9463                 5 + /* HDP_INVL */
9464                 8 + 8 + /* FENCE x2 */
9465                 2 + /* SWITCH_BUFFER */
9466                 8, /* gfx_v10_0_emit_mem_sync */
9467         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9468         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9469         .emit_fence = gfx_v10_0_ring_emit_fence,
9470         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9471         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9472         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9473         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9474         .test_ring = gfx_v10_0_ring_test_ring,
9475         .test_ib = gfx_v10_0_ring_test_ib,
9476         .insert_nop = amdgpu_ring_insert_nop,
9477         .pad_ib = amdgpu_ring_generic_pad_ib,
9478         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9479         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9480         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9481         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9482         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9483         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9484         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9485         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9486         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9487         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9488         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9489 };
9490
9491 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9492         .type = AMDGPU_RING_TYPE_COMPUTE,
9493         .align_mask = 0xff,
9494         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9495         .support_64bit_ptrs = true,
9496         .vmhub = AMDGPU_GFXHUB_0,
9497         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9498         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9499         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9500         .emit_frame_size =
9501                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9502                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9503                 5 + /* hdp invalidate */
9504                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9505                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9506                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9507                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9508                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9509                 8, /* gfx_v10_0_emit_mem_sync */
9510         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9511         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9512         .emit_fence = gfx_v10_0_ring_emit_fence,
9513         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9514         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9515         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9516         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9517         .test_ring = gfx_v10_0_ring_test_ring,
9518         .test_ib = gfx_v10_0_ring_test_ib,
9519         .insert_nop = amdgpu_ring_insert_nop,
9520         .pad_ib = amdgpu_ring_generic_pad_ib,
9521         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9522         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9523         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9524         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9525 };
9526
9527 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9528         .type = AMDGPU_RING_TYPE_KIQ,
9529         .align_mask = 0xff,
9530         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9531         .support_64bit_ptrs = true,
9532         .vmhub = AMDGPU_GFXHUB_0,
9533         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9534         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9535         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9536         .emit_frame_size =
9537                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9538                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9539                 5 + /*hdp invalidate */
9540                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9541                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9542                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9543                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9544                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9545         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9546         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9547         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9548         .test_ring = gfx_v10_0_ring_test_ring,
9549         .test_ib = gfx_v10_0_ring_test_ib,
9550         .insert_nop = amdgpu_ring_insert_nop,
9551         .pad_ib = amdgpu_ring_generic_pad_ib,
9552         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9553         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9554         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9555         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9556 };
9557
9558 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9559 {
9560         int i;
9561
9562         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9563
9564         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9565                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9566
9567         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9568                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9569 }
9570
9571 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9572         .set = gfx_v10_0_set_eop_interrupt_state,
9573         .process = gfx_v10_0_eop_irq,
9574 };
9575
9576 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9577         .set = gfx_v10_0_set_priv_reg_fault_state,
9578         .process = gfx_v10_0_priv_reg_irq,
9579 };
9580
9581 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9582         .set = gfx_v10_0_set_priv_inst_fault_state,
9583         .process = gfx_v10_0_priv_inst_irq,
9584 };
9585
9586 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9587         .set = gfx_v10_0_kiq_set_interrupt_state,
9588         .process = gfx_v10_0_kiq_irq,
9589 };
9590
9591 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9592 {
9593         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9594         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9595
9596         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9597         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9598
9599         adev->gfx.priv_reg_irq.num_types = 1;
9600         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9601
9602         adev->gfx.priv_inst_irq.num_types = 1;
9603         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9604 }
9605
9606 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9607 {
9608         switch (adev->ip_versions[GC_HWIP][0]) {
9609         case IP_VERSION(10, 1, 10):
9610         case IP_VERSION(10, 1, 1):
9611         case IP_VERSION(10, 1, 3):
9612         case IP_VERSION(10, 1, 4):
9613         case IP_VERSION(10, 3, 2):
9614         case IP_VERSION(10, 3, 1):
9615         case IP_VERSION(10, 3, 4):
9616         case IP_VERSION(10, 3, 5):
9617         case IP_VERSION(10, 3, 6):
9618         case IP_VERSION(10, 3, 3):
9619         case IP_VERSION(10, 3, 7):
9620                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9621                 break;
9622         case IP_VERSION(10, 1, 2):
9623         case IP_VERSION(10, 3, 0):
9624                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9625                 break;
9626         default:
9627                 break;
9628         }
9629 }
9630
9631 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9632 {
9633         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9634                             adev->gfx.config.max_sh_per_se *
9635                             adev->gfx.config.max_shader_engines;
9636
9637         adev->gds.gds_size = 0x10000;
9638         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9639         adev->gds.gws_size = 64;
9640         adev->gds.oa_size = 16;
9641 }
9642
9643 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9644 {
9645         /* set gfx eng mqd */
9646         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9647                 sizeof(struct v10_gfx_mqd);
9648         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9649                 gfx_v10_0_gfx_mqd_init;
9650         /* set compute eng mqd */
9651         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9652                 sizeof(struct v10_compute_mqd);
9653         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9654                 gfx_v10_0_compute_mqd_init;
9655 }
9656
9657 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9658                                                           u32 bitmap)
9659 {
9660         u32 data;
9661
9662         if (!bitmap)
9663                 return;
9664
9665         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9666         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9667
9668         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9669 }
9670
9671 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9672 {
9673         u32 disabled_mask =
9674                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9675         u32 efuse_setting = 0;
9676         u32 vbios_setting = 0;
9677
9678         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9679         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9680         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9681
9682         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9683         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9684         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9685
9686         disabled_mask |= efuse_setting | vbios_setting;
9687
9688         return (~disabled_mask);
9689 }
9690
9691 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9692 {
9693         u32 wgp_idx, wgp_active_bitmap;
9694         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9695
9696         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9697         cu_active_bitmap = 0;
9698
9699         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9700                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9701                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9702                 if (wgp_active_bitmap & (1 << wgp_idx))
9703                         cu_active_bitmap |= cu_bitmap_per_wgp;
9704         }
9705
9706         return cu_active_bitmap;
9707 }
9708
9709 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9710                                  struct amdgpu_cu_info *cu_info)
9711 {
9712         int i, j, k, counter, active_cu_number = 0;
9713         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9714         unsigned disable_masks[4 * 2];
9715
9716         if (!adev || !cu_info)
9717                 return -EINVAL;
9718
9719         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9720
9721         mutex_lock(&adev->grbm_idx_mutex);
9722         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9723                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9724                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9725                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9726                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9727                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9728                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9729                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9730                                 continue;
9731                         mask = 1;
9732                         ao_bitmap = 0;
9733                         counter = 0;
9734                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9735                         if (i < 4 && j < 2)
9736                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9737                                         adev, disable_masks[i * 2 + j]);
9738                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9739                         cu_info->bitmap[i][j] = bitmap;
9740
9741                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9742                                 if (bitmap & mask) {
9743                                         if (counter < adev->gfx.config.max_cu_per_sh)
9744                                                 ao_bitmap |= mask;
9745                                         counter++;
9746                                 }
9747                                 mask <<= 1;
9748                         }
9749                         active_cu_number += counter;
9750                         if (i < 2 && j < 2)
9751                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9752                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9753                 }
9754         }
9755         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9756         mutex_unlock(&adev->grbm_idx_mutex);
9757
9758         cu_info->number = active_cu_number;
9759         cu_info->ao_cu_mask = ao_cu_mask;
9760         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9761
9762         return 0;
9763 }
9764
9765 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9766 {
9767         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9768
9769         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9770         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9771         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9772
9773         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9774         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9775         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9776
9777         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9778                                                 adev->gfx.config.max_shader_engines);
9779         disabled_sa = efuse_setting | vbios_setting;
9780         disabled_sa &= max_sa_mask;
9781
9782         return disabled_sa;
9783 }
9784
9785 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9786 {
9787         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9788         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9789
9790         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9791
9792         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9793         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9794         max_shader_engines = adev->gfx.config.max_shader_engines;
9795
9796         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9797                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9798                 disabled_sa_per_se &= max_sa_per_se_mask;
9799                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9800                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9801                         break;
9802                 }
9803         }
9804 }
9805
9806 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9807 {
9808         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9809                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9810                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9811                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9812
9813         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9814         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9815                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9816                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9817                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9818                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9819
9820         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9821                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9822                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9823                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9824
9825         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9826
9827         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9828                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9829 }
9830
9831 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9832 {
9833         .type = AMD_IP_BLOCK_TYPE_GFX,
9834         .major = 10,
9835         .minor = 0,
9836         .rev = 0,
9837         .funcs = &gfx_v10_0_ip_funcs,
9838 };