2 * Procfs interface for the PCI bus.
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/proc_fs.h>
12 #include <linux/seq_file.h>
13 #include <linux/capability.h>
14 #include <linux/uaccess.h>
15 #include <asm/byteorder.h>
18 static int proc_initialized; /* = 0 */
20 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
22 struct pci_dev *dev = PDE_DATA(file_inode(file));
23 return fixed_size_llseek(file, off, whence, dev->cfg_size);
26 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
27 size_t nbytes, loff_t *ppos)
29 struct pci_dev *dev = PDE_DATA(file_inode(file));
30 unsigned int pos = *ppos;
31 unsigned int cnt, size;
34 * Normal users can read only the standardized portion of the
35 * configuration space as several chips lock up when trying to read
36 * undefined locations (think of Intel PIIX4 as a typical example).
39 if (capable(CAP_SYS_ADMIN))
41 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
50 if (pos + nbytes > size)
54 if (!access_ok(VERIFY_WRITE, buf, cnt))
57 pci_config_pm_runtime_get(dev);
59 if ((pos & 1) && cnt) {
61 pci_user_read_config_byte(dev, pos, &val);
68 if ((pos & 3) && cnt > 2) {
70 pci_user_read_config_word(dev, pos, &val);
71 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
79 pci_user_read_config_dword(dev, pos, &val);
80 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
88 pci_user_read_config_word(dev, pos, &val);
89 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
97 pci_user_read_config_byte(dev, pos, &val);
104 pci_config_pm_runtime_put(dev);
110 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
111 size_t nbytes, loff_t *ppos)
113 struct inode *ino = file_inode(file);
114 struct pci_dev *dev = PDE_DATA(ino);
116 int size = dev->cfg_size;
123 if (pos + nbytes > size)
127 if (!access_ok(VERIFY_READ, buf, cnt))
130 pci_config_pm_runtime_get(dev);
132 if ((pos & 1) && cnt) {
134 __get_user(val, buf);
135 pci_user_write_config_byte(dev, pos, val);
141 if ((pos & 3) && cnt > 2) {
143 __get_user(val, (__le16 __user *) buf);
144 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
152 __get_user(val, (__le32 __user *) buf);
153 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
161 __get_user(val, (__le16 __user *) buf);
162 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
170 __get_user(val, buf);
171 pci_user_write_config_byte(dev, pos, val);
177 pci_config_pm_runtime_put(dev);
180 i_size_write(ino, dev->cfg_size);
184 struct pci_filp_private {
185 enum pci_mmap_state mmap_state;
189 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
192 struct pci_dev *dev = PDE_DATA(file_inode(file));
194 struct pci_filp_private *fpriv = file->private_data;
195 #endif /* HAVE_PCI_MMAP */
199 case PCIIOC_CONTROLLER:
200 ret = pci_domain_nr(dev->bus);
204 case PCIIOC_MMAP_IS_IO:
205 if (!arch_can_pci_mmap_io())
207 fpriv->mmap_state = pci_mmap_io;
210 case PCIIOC_MMAP_IS_MEM:
211 fpriv->mmap_state = pci_mmap_mem;
214 case PCIIOC_WRITE_COMBINE:
215 if (arch_can_pci_mmap_wc()) {
217 fpriv->write_combine = 1;
219 fpriv->write_combine = 0;
222 /* If arch decided it can't, fall through... */
223 #endif /* HAVE_PCI_MMAP */
233 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
235 struct pci_dev *dev = PDE_DATA(file_inode(file));
236 struct pci_filp_private *fpriv = file->private_data;
237 int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
239 if (!capable(CAP_SYS_RAWIO))
242 if (fpriv->mmap_state == pci_mmap_io) {
243 if (!arch_can_pci_mmap_io())
245 res_bit = IORESOURCE_IO;
248 /* Make sure the caller is mapping a real resource for this device */
249 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
250 if (dev->resource[i].flags & res_bit &&
251 pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
255 if (i >= PCI_ROM_RESOURCE)
258 if (fpriv->mmap_state == pci_mmap_mem &&
259 fpriv->write_combine) {
260 if (dev->resource[i].flags & IORESOURCE_PREFETCH)
265 ret = pci_mmap_page_range(dev, i, vma,
266 fpriv->mmap_state, write_combine);
273 static int proc_bus_pci_open(struct inode *inode, struct file *file)
275 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
280 fpriv->mmap_state = pci_mmap_io;
281 fpriv->write_combine = 0;
283 file->private_data = fpriv;
288 static int proc_bus_pci_release(struct inode *inode, struct file *file)
290 kfree(file->private_data);
291 file->private_data = NULL;
295 #endif /* HAVE_PCI_MMAP */
297 static const struct file_operations proc_bus_pci_operations = {
298 .owner = THIS_MODULE,
299 .llseek = proc_bus_pci_lseek,
300 .read = proc_bus_pci_read,
301 .write = proc_bus_pci_write,
302 .unlocked_ioctl = proc_bus_pci_ioctl,
303 .compat_ioctl = proc_bus_pci_ioctl,
305 .open = proc_bus_pci_open,
306 .release = proc_bus_pci_release,
307 .mmap = proc_bus_pci_mmap,
308 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
309 .get_unmapped_area = get_pci_unmapped_area,
310 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
311 #endif /* HAVE_PCI_MMAP */
315 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
317 struct pci_dev *dev = NULL;
320 for_each_pci_dev(dev) {
327 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
329 struct pci_dev *dev = v;
332 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
336 static void pci_seq_stop(struct seq_file *m, void *v)
339 struct pci_dev *dev = v;
344 static int show_device(struct seq_file *m, void *v)
346 const struct pci_dev *dev = v;
347 const struct pci_driver *drv;
353 drv = pci_dev_driver(dev);
354 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
361 /* only print standard and ROM resources to preserve compatibility */
362 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
363 resource_size_t start, end;
364 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
365 seq_printf(m, "\t%16llx",
366 (unsigned long long)(start |
367 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
369 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
370 resource_size_t start, end;
371 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
372 seq_printf(m, "\t%16llx",
373 dev->resource[i].start < dev->resource[i].end ?
374 (unsigned long long)(end - start) + 1 : 0);
378 seq_printf(m, "%s", drv->name);
383 static const struct seq_operations proc_bus_pci_devices_op = {
384 .start = pci_seq_start,
385 .next = pci_seq_next,
386 .stop = pci_seq_stop,
390 static struct proc_dir_entry *proc_bus_pci_dir;
392 int pci_proc_attach_device(struct pci_dev *dev)
394 struct pci_bus *bus = dev->bus;
395 struct proc_dir_entry *e;
398 if (!proc_initialized)
402 if (pci_proc_domain(bus)) {
403 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
406 sprintf(name, "%02x", bus->number);
408 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
413 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
414 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
415 &proc_bus_pci_operations, dev);
418 proc_set_size(e, dev->cfg_size);
424 int pci_proc_detach_device(struct pci_dev *dev)
426 proc_remove(dev->procent);
431 int pci_proc_detach_bus(struct pci_bus *bus)
433 proc_remove(bus->procdir);
437 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
439 return seq_open(file, &proc_bus_pci_devices_op);
442 static const struct file_operations proc_bus_pci_dev_operations = {
443 .owner = THIS_MODULE,
444 .open = proc_bus_pci_dev_open,
447 .release = seq_release,
450 static int __init pci_proc_init(void)
452 struct pci_dev *dev = NULL;
453 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
454 proc_create("devices", 0, proc_bus_pci_dir,
455 &proc_bus_pci_dev_operations);
456 proc_initialized = 1;
457 for_each_pci_dev(dev)
458 pci_proc_attach_device(dev);
462 device_initcall(pci_proc_init);