drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu_ras_eeprom.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_ras.h"
  27 #include <linux/bits.h>
  28 #include "smu_v11_0_i2c.h"
  29
  30 #define EEPROM_I2C_TARGET_ADDR 0xA0
  31
  32 /*
  33  * The 2 macros bellow represent the actual size in bytes that
  34  * those entities occupy in the EEPROM memory.
  35  * EEPROM_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which
  36  * uses uint64 to store 6b fields such as retired_page.
  37  */
  38 #define EEPROM_TABLE_HEADER_SIZE 20
  39 #define EEPROM_TABLE_RECORD_SIZE 24
  40
  41 #define EEPROM_ADDRESS_SIZE 0x2
  42
  43 /* Table hdr is 'AMDR' */
  44 #define EEPROM_TABLE_HDR_VAL 0x414d4452
  45 #define EEPROM_TABLE_VER 0x00010000
  46
  47 /* Assume 2 Mbit size */
  48 #define EEPROM_SIZE_BYTES 256000
  49 #define EEPROM_PAGE__SIZE_BYTES 256
  50 #define EEPROM_HDR_START 0
  51 #define EEPROM_RECORD_START (EEPROM_HDR_START + EEPROM_TABLE_HEADER_SIZE)
  52 #define EEPROM_MAX_RECORD_NUM ((EEPROM_SIZE_BYTES - EEPROM_TABLE_HEADER_SIZE) / EEPROM_TABLE_RECORD_SIZE)
  53 #define EEPROM_ADDR_MSB_MASK GENMASK(17, 8)
  54
  55 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev
  56
  57 static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
  58                                           unsigned char *buff)
  59 {
  60         uint32_t *pp = (uint32_t *) buff;
  61
  62         pp[0] = cpu_to_le32(hdr->header);
  63         pp[1] = cpu_to_le32(hdr->version);
  64         pp[2] = cpu_to_le32(hdr->first_rec_offset);
  65         pp[3] = cpu_to_le32(hdr->tbl_size);
  66         pp[4] = cpu_to_le32(hdr->checksum);
  67 }
  68
  69 static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
  70                                           unsigned char *buff)
  71 {
  72         uint32_t *pp = (uint32_t *)buff;
  73
  74         hdr->header           = le32_to_cpu(pp[0]);
  75         hdr->version          = le32_to_cpu(pp[1]);
  76         hdr->first_rec_offset = le32_to_cpu(pp[2]);
  77         hdr->tbl_size         = le32_to_cpu(pp[3]);
  78         hdr->checksum         = le32_to_cpu(pp[4]);
  79 }
  80
  81 static int __update_table_header(struct amdgpu_ras_eeprom_control *control,
  82                                  unsigned char *buff)
  83 {
  84         int ret = 0;
  85         struct i2c_msg msg = {
  86                         .addr   = EEPROM_I2C_TARGET_ADDR,
  87                         .flags  = 0,
  88                         .len    = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
  89                         .buf    = buff,
  90         };
  91
  92
  93         *(uint16_t *)buff = EEPROM_HDR_START;
  94         __encode_table_header_to_buff(&control->tbl_hdr, buff + EEPROM_ADDRESS_SIZE);
  95
  96         ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
  97         if (ret < 1)
  98                 DRM_ERROR("Failed to write EEPROM table header, ret:%d", ret);
  99
 100         return ret;
 101 }
 102
 103
 104
 105 static uint32_t  __calc_hdr_byte_sum(struct amdgpu_ras_eeprom_control *control)
 106 {
 107         int i;
 108         uint32_t tbl_sum = 0;
 109
 110         /* Header checksum, skip checksum field in the calculation */
 111         for (i = 0; i < sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); i++)
 112                 tbl_sum += *(((unsigned char *)&control->tbl_hdr) + i);
 113
 114         return tbl_sum;
 115 }
 116
 117 static uint32_t  __calc_recs_byte_sum(struct eeprom_table_record *records,
 118                                       int num)
 119 {
 120         int i, j;
 121         uint32_t tbl_sum = 0;
 122
 123         /* Records checksum */
 124         for (i = 0; i < num; i++) {
 125                 struct eeprom_table_record *record = &records[i];
 126
 127                 for (j = 0; j < sizeof(*record); j++) {
 128                         tbl_sum += *(((unsigned char *)record) + j);
 129                 }
 130         }
 131
 132         return tbl_sum;
 133 }
 134
 135 static inline uint32_t  __calc_tbl_byte_sum(struct amdgpu_ras_eeprom_control *control,
 136                                   struct eeprom_table_record *records, int num)
 137 {
 138         return __calc_hdr_byte_sum(control) + __calc_recs_byte_sum(records, num);
 139 }
 140
 141 /* Checksum = 256 -((sum of all table entries) mod 256) */
 142 static void __update_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
 143                                   struct eeprom_table_record *records, int num,
 144                                   uint32_t old_hdr_byte_sum)
 145 {
 146         /*
 147          * This will update the table sum with new records.
 148          *
 149          * TODO: What happens when the EEPROM table is to be wrapped around
 150          * and old records from start will get overridden.
 151          */
 152
 153         /* need to recalculate updated header byte sum */
 154         control->tbl_byte_sum -= old_hdr_byte_sum;
 155         control->tbl_byte_sum += __calc_tbl_byte_sum(control, records, num);
 156
 157         control->tbl_hdr.checksum = 256 - (control->tbl_byte_sum % 256);
 158 }
 159
 160 /* table sum mod 256 + checksum must equals 256 */
 161 static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
 162                             struct eeprom_table_record *records, int num)
 163 {
 164         control->tbl_byte_sum = __calc_tbl_byte_sum(control, records, num);
 165
 166         if (control->tbl_hdr.checksum + (control->tbl_byte_sum % 256) != 256) {
 167                 DRM_WARN("Checksum mismatch, checksum: %u ", control->tbl_hdr.checksum);
 168                 return false;
 169         }
 170
 171         return true;
 172 }
 173
 174 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
 175 {
 176         unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
 177         struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
 178         int ret = 0;
 179
 180         mutex_lock(&control->tbl_mutex);
 181
 182         hdr->header = EEPROM_TABLE_HDR_VAL;
 183         hdr->version = EEPROM_TABLE_VER;
 184         hdr->first_rec_offset = EEPROM_RECORD_START;
 185         hdr->tbl_size = EEPROM_TABLE_HEADER_SIZE;
 186
 187         control->tbl_byte_sum = 0;
 188         __update_tbl_checksum(control, NULL, 0, 0);
 189         control->next_addr = EEPROM_RECORD_START;
 190
 191         ret = __update_table_header(control, buff);
 192
 193         mutex_unlock(&control->tbl_mutex);
 194
 195         return ret;
 196
 197 }
 198
 199 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
 200 {
 201         int ret = 0;
 202         struct amdgpu_device *adev = to_amdgpu_device(control);
 203         unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
 204         struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
 205         struct i2c_msg msg = {
 206                         .addr   = EEPROM_I2C_TARGET_ADDR,
 207                         .flags  = I2C_M_RD,
 208                         .len    = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE,
 209                         .buf    = buff,
 210         };
 211
 212         mutex_init(&control->tbl_mutex);
 213
 214         switch (adev->asic_type) {
 215         case CHIP_VEGA20:
 216                 ret = smu_v11_0_i2c_eeprom_control_init(&control->eeprom_accessor);
 217                 break;
 218
 219         case CHIP_ARCTURUS:
 220                 ret = smu_i2c_eeprom_init(&adev->smu, &control->eeprom_accessor);
 221                 break;
 222
 223         default:
 224                 return 0;
 225         }
 226
 227         if (ret) {
 228                 DRM_ERROR("Failed to init I2C controller, ret:%d", ret);
 229                 return ret;
 230         }
 231
 232         /* Read/Create table header from EEPROM address 0 */
 233         ret = i2c_transfer(&control->eeprom_accessor, &msg, 1);
 234         if (ret < 1) {
 235                 DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
 236                 return ret;
 237         }
 238
 239         __decode_table_header_from_buff(hdr, &buff[2]);
 240
 241         if (hdr->header == EEPROM_TABLE_HDR_VAL) {
 242                 control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
 243                                     EEPROM_TABLE_RECORD_SIZE;
 244                 control->tbl_byte_sum = __calc_hdr_byte_sum(control);
 245                 control->next_addr = EEPROM_RECORD_START;
 246
 247                 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records",
 248                                  control->num_recs);
 249
 250         } else {
 251                 DRM_INFO("Creating new EEPROM table");
 252
 253                 ret = amdgpu_ras_eeprom_reset_table(control);
 254         }
 255
 256         return ret == 1 ? 0 : -EIO;
 257 }
 258
 259 void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
 260 {
 261         struct amdgpu_device *adev = to_amdgpu_device(control);
 262
 263         switch (adev->asic_type) {
 264         case CHIP_VEGA20:
 265                 smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
 266                 break;
 267         case CHIP_ARCTURUS:
 268                 smu_i2c_eeprom_fini(&adev->smu, &control->eeprom_accessor);
 269                 break;
 270
 271         default:
 272                 return;
 273         }
 274 }
 275
 276 static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
 277                                           struct eeprom_table_record *record,
 278                                           unsigned char *buff)
 279 {
 280         __le64 tmp = 0;
 281         int i = 0;
 282
 283         /* Next are all record fields according to EEPROM page spec in LE foramt */
 284         buff[i++] = record->err_type;
 285
 286         buff[i++] = record->bank;
 287
 288         tmp = cpu_to_le64(record->ts);
 289         memcpy(buff + i, &tmp, 8);
 290         i += 8;
 291
 292         tmp = cpu_to_le64((record->offset & 0xffffffffffff));
 293         memcpy(buff + i, &tmp, 6);
 294         i += 6;
 295
 296         buff[i++] = record->mem_channel;
 297         buff[i++] = record->mcumc_id;
 298
 299         tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
 300         memcpy(buff + i, &tmp, 6);
 301 }
 302
 303 static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
 304                                             struct eeprom_table_record *record,
 305                                             unsigned char *buff)
 306 {
 307         __le64 tmp = 0;
 308         int i =  0;
 309
 310         /* Next are all record fields according to EEPROM page spec in LE foramt */
 311         record->err_type = buff[i++];
 312
 313         record->bank = buff[i++];
 314
 315         memcpy(&tmp, buff + i, 8);
 316         record->ts = le64_to_cpu(tmp);
 317         i += 8;
 318
 319         memcpy(&tmp, buff + i, 6);
 320         record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
 321         i += 6;
 322
 323         record->mem_channel = buff[i++];
 324         record->mcumc_id = buff[i++];
 325
 326         memcpy(&tmp, buff + i,  6);
 327         record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
 328 }
 329
 330 /*
 331  * When reaching end of EEPROM memory jump back to 0 record address
 332  * When next record access will go beyond EEPROM page boundary modify bits A17/A8
 333  * in I2C selector to go to next page
 334  */
 335 static uint32_t __correct_eeprom_dest_address(uint32_t curr_address)
 336 {
 337         uint32_t next_address = curr_address + EEPROM_TABLE_RECORD_SIZE;
 338
 339         /* When all EEPROM memory used jump back to 0 address */
 340         if (next_address > EEPROM_SIZE_BYTES) {
 341                 DRM_INFO("Reached end of EEPROM memory, jumping to 0 "
 342                          "and overriding old record");
 343                 return EEPROM_RECORD_START;
 344         }
 345
 346         /*
 347          * To check if we overflow page boundary  compare next address with
 348          * current and see if bits 17/8 of the EEPROM address will change
 349          * If they do start from the next 256b page
 350          *
 351          * https://www.st.com/resource/en/datasheet/m24m02-dr.pdf sec. 5.1.2
 352          */
 353         if ((curr_address & EEPROM_ADDR_MSB_MASK) != (next_address & EEPROM_ADDR_MSB_MASK)) {
 354                 DRM_DEBUG_DRIVER("Reached end of EEPROM memory page, jumping to next: %lx",
 355                                 (next_address & EEPROM_ADDR_MSB_MASK));
 356
 357                 return  (next_address & EEPROM_ADDR_MSB_MASK);
 358         }
 359
 360         return curr_address;
 361 }
 362
 363 int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 364                                             struct eeprom_table_record *records,
 365                                             bool write,
 366                                             int num)
 367 {
 368         int i, ret = 0;
 369         struct i2c_msg *msgs, *msg;
 370         unsigned char *buffs, *buff;
 371         struct eeprom_table_record *record;
 372         struct amdgpu_device *adev = to_amdgpu_device(control);
 373
 374         if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
 375                 return 0;
 376
 377         buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
 378                          GFP_KERNEL);
 379         if (!buffs)
 380                 return -ENOMEM;
 381
 382         mutex_lock(&control->tbl_mutex);
 383
 384         msgs = kcalloc(num, sizeof(*msgs), GFP_KERNEL);
 385         if (!msgs) {
 386                 ret = -ENOMEM;
 387                 goto free_buff;
 388         }
 389
 390         /* In case of overflow just start from beginning to not lose newest records */
 391         if (write && (control->next_addr + EEPROM_TABLE_RECORD_SIZE * num > EEPROM_SIZE_BYTES))
 392                 control->next_addr = EEPROM_RECORD_START;
 393
 394
 395         /*
 396          * TODO Currently makes EEPROM writes for each record, this creates
 397          * internal fragmentation. Optimized the code to do full page write of
 398          * 256b
 399          */
 400         for (i = 0; i < num; i++) {
 401                 buff = &buffs[i * (EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
 402                 record = &records[i];
 403                 msg = &msgs[i];
 404
 405                 control->next_addr = __correct_eeprom_dest_address(control->next_addr);
 406
 407                 /*
 408                  * Update bits 16,17 of EEPROM address in I2C address by setting them
 409                  * to bits 1,2 of Device address byte
 410                  */
 411                 msg->addr = EEPROM_I2C_TARGET_ADDR |
 412                                ((control->next_addr & EEPROM_ADDR_MSB_MASK) >> 15);
 413                 msg->flags      = write ? 0 : I2C_M_RD;
 414                 msg->len        = EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE;
 415                 msg->buf        = buff;
 416
 417                 /* Insert the EEPROM dest addess, bits 0-15 */
 418                 buff[0] = ((control->next_addr >> 8) & 0xff);
 419                 buff[1] = (control->next_addr & 0xff);
 420
 421                 /* EEPROM table content is stored in LE format */
 422                 if (write)
 423                         __encode_table_record_to_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
 424
 425                 /*
 426                  * The destination EEPROM address might need to be corrected to account
 427                  * for page or entire memory wrapping
 428                  */
 429                 control->next_addr += EEPROM_TABLE_RECORD_SIZE;
 430         }
 431
 432         ret = i2c_transfer(&control->eeprom_accessor, msgs, num);
 433         if (ret < 1) {
 434                 DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
 435
 436                 /* TODO Restore prev next EEPROM address ? */
 437                 goto free_msgs;
 438         }
 439
 440
 441         if (!write) {
 442                 for (i = 0; i < num; i++) {
 443                         buff = &buffs[i*(EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE)];
 444                         record = &records[i];
 445
 446                         __decode_table_record_from_buff(control, record, buff + EEPROM_ADDRESS_SIZE);
 447                 }
 448         }
 449
 450         if (write) {
 451                 uint32_t old_hdr_byte_sum = __calc_hdr_byte_sum(control);
 452
 453                 /*
 454                  * Update table header with size and CRC and account for table
 455                  * wrap around where the assumption is that we treat it as empty
 456                  * table
 457                  *
 458                  * TODO - Check the assumption is correct
 459                  */
 460                 control->num_recs += num;
 461                 control->num_recs %= EEPROM_MAX_RECORD_NUM;
 462                 control->tbl_hdr.tbl_size += EEPROM_TABLE_RECORD_SIZE * num;
 463                 if (control->tbl_hdr.tbl_size > EEPROM_SIZE_BYTES)
 464                         control->tbl_hdr.tbl_size = EEPROM_TABLE_HEADER_SIZE +
 465                         control->num_recs * EEPROM_TABLE_RECORD_SIZE;
 466
 467                 __update_tbl_checksum(control, records, num, old_hdr_byte_sum);
 468
 469                 __update_table_header(control, buffs);
 470         } else if (!__validate_tbl_checksum(control, records, num)) {
 471                 DRM_WARN("EEPROM Table checksum mismatch!");
 472                 /* TODO Uncomment when EEPROM read/write is relliable */
 473                 /* ret = -EIO; */
 474         }
 475
 476 free_msgs:
 477         kfree(msgs);
 478
 479 free_buff:
 480         kfree(buffs);
 481
 482         mutex_unlock(&control->tbl_mutex);
 483
 484         return ret == num ? 0 : -EIO;
 485 }
 486
 487 /* Used for testing if bugs encountered */
 488 #if 0
 489 void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control)
 490 {
 491         int i;
 492         struct eeprom_table_record *recs = kcalloc(1, sizeof(*recs), GFP_KERNEL);
 493
 494         if (!recs)
 495                 return;
 496
 497         for (i = 0; i < 1 ; i++) {
 498                 recs[i].address = 0xdeadbeef;
 499                 recs[i].retired_page = i;
 500         }
 501
 502         if (!amdgpu_ras_eeprom_process_recods(control, recs, true, 1)) {
 503
 504                 memset(recs, 0, sizeof(*recs) * 1);
 505
 506                 control->next_addr = EEPROM_RECORD_START;
 507
 508                 if (!amdgpu_ras_eeprom_process_recods(control, recs, false, 1)) {
 509                         for (i = 0; i < 1; i++)
 510                                 DRM_INFO("rec.address :0x%llx, rec.retired_page :%llu",
 511                                          recs[i].address, recs[i].retired_page);
 512                 } else
 513                         DRM_ERROR("Failed in reading from table");
 514
 515         } else
 516                 DRM_ERROR("Failed in writing to table");
 517 }
 518 #endif