2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/clk.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip.h>
25 #include <linux/module.h>
26 #include <linux/pm_runtime.h>
28 #include "atmel_hlcdc_dc.h"
30 #define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
32 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
35 .formats = &atmel_hlcdc_plane_rgb_formats,
38 .type = ATMEL_HLCDC_BASE_LAYER,
49 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
57 .conflicting_output_formats = true,
58 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
59 .layers = atmel_hlcdc_at91sam9n12_layers,
62 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
65 .formats = &atmel_hlcdc_plane_rgb_formats,
68 .type = ATMEL_HLCDC_BASE_LAYER,
81 .formats = &atmel_hlcdc_plane_rgb_formats,
84 .type = ATMEL_HLCDC_OVERLAY_LAYER,
99 .name = "high-end-overlay",
100 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
101 .regs_offset = 0x280,
103 .type = ATMEL_HLCDC_OVERLAY_LAYER,
113 .chroma_key_mask = 11,
114 .general_config = 12,
118 .clut_offset = 0x1000,
122 .formats = &atmel_hlcdc_plane_rgb_formats,
123 .regs_offset = 0x340,
125 .type = ATMEL_HLCDC_CURSOR_LAYER,
135 .chroma_key_mask = 8,
138 .clut_offset = 0x1400,
142 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
150 .conflicting_output_formats = true,
151 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
152 .layers = atmel_hlcdc_at91sam9x5_layers,
155 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
158 .formats = &atmel_hlcdc_plane_rgb_formats,
161 .type = ATMEL_HLCDC_BASE_LAYER,
170 .clut_offset = 0x600,
174 .formats = &atmel_hlcdc_plane_rgb_formats,
175 .regs_offset = 0x140,
177 .type = ATMEL_HLCDC_OVERLAY_LAYER,
186 .chroma_key_mask = 8,
189 .clut_offset = 0xa00,
193 .formats = &atmel_hlcdc_plane_rgb_formats,
194 .regs_offset = 0x240,
196 .type = ATMEL_HLCDC_OVERLAY_LAYER,
205 .chroma_key_mask = 8,
208 .clut_offset = 0xe00,
211 .name = "high-end-overlay",
212 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
213 .regs_offset = 0x340,
215 .type = ATMEL_HLCDC_OVERLAY_LAYER,
225 .chroma_key_mask = 11,
226 .general_config = 12,
234 .clut_offset = 0x1200,
238 .formats = &atmel_hlcdc_plane_rgb_formats,
239 .regs_offset = 0x440,
241 .type = ATMEL_HLCDC_CURSOR_LAYER,
252 .chroma_key_mask = 8,
256 .clut_offset = 0x1600,
260 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
268 .conflicting_output_formats = true,
269 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
270 .layers = atmel_hlcdc_sama5d3_layers,
273 static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
276 .formats = &atmel_hlcdc_plane_rgb_formats,
279 .type = ATMEL_HLCDC_BASE_LAYER,
288 .clut_offset = 0x600,
292 .formats = &atmel_hlcdc_plane_rgb_formats,
293 .regs_offset = 0x140,
295 .type = ATMEL_HLCDC_OVERLAY_LAYER,
304 .chroma_key_mask = 8,
307 .clut_offset = 0xa00,
311 .formats = &atmel_hlcdc_plane_rgb_formats,
312 .regs_offset = 0x240,
314 .type = ATMEL_HLCDC_OVERLAY_LAYER,
323 .chroma_key_mask = 8,
326 .clut_offset = 0xe00,
329 .name = "high-end-overlay",
330 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
331 .regs_offset = 0x340,
333 .type = ATMEL_HLCDC_OVERLAY_LAYER,
343 .chroma_key_mask = 11,
344 .general_config = 12,
352 .clut_offset = 0x1200,
356 static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
364 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
365 .layers = atmel_hlcdc_sama5d4_layers,
367 static const struct of_device_id atmel_hlcdc_of_match[] = {
369 .compatible = "atmel,at91sam9n12-hlcdc",
370 .data = &atmel_hlcdc_dc_at91sam9n12,
373 .compatible = "atmel,at91sam9x5-hlcdc",
374 .data = &atmel_hlcdc_dc_at91sam9x5,
377 .compatible = "atmel,sama5d2-hlcdc",
378 .data = &atmel_hlcdc_dc_sama5d4,
381 .compatible = "atmel,sama5d3-hlcdc",
382 .data = &atmel_hlcdc_dc_sama5d3,
385 .compatible = "atmel,sama5d4-hlcdc",
386 .data = &atmel_hlcdc_dc_sama5d4,
390 MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
393 atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
394 const struct drm_display_mode *mode)
396 int vfront_porch = mode->vsync_start - mode->vdisplay;
397 int vback_porch = mode->vtotal - mode->vsync_end;
398 int vsync_len = mode->vsync_end - mode->vsync_start;
399 int hfront_porch = mode->hsync_start - mode->hdisplay;
400 int hback_porch = mode->htotal - mode->hsync_end;
401 int hsync_len = mode->hsync_end - mode->hsync_start;
403 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
406 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
409 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
410 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
412 return MODE_H_ILLEGAL;
414 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
415 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
417 return MODE_V_ILLEGAL;
422 static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
427 if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||
428 layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
429 layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)
430 atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));
433 static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
435 struct drm_device *dev = data;
436 struct atmel_hlcdc_dc *dc = dev->dev_private;
437 unsigned long status;
438 unsigned int imr, isr;
441 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
442 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
447 if (status & ATMEL_HLCDC_SOF)
448 atmel_hlcdc_crtc_irq(dc->crtc);
450 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
451 if (ATMEL_HLCDC_LAYER_STATUS(i) & status)
452 atmel_hlcdc_layer_irq(dc->layers[i]);
458 static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
459 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
461 return drm_gem_fb_create(dev, file_priv, mode_cmd);
464 static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
466 struct atmel_hlcdc_dc *dc = dev->dev_private;
468 drm_fbdev_cma_hotplug_event(dc->fbdev);
471 struct atmel_hlcdc_dc_commit {
472 struct work_struct work;
473 struct drm_device *dev;
474 struct drm_atomic_state *state;
478 atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit)
480 struct drm_device *dev = commit->dev;
481 struct atmel_hlcdc_dc *dc = dev->dev_private;
482 struct drm_atomic_state *old_state = commit->state;
484 /* Apply the atomic update. */
485 drm_atomic_helper_commit_modeset_disables(dev, old_state);
486 drm_atomic_helper_commit_planes(dev, old_state, 0);
487 drm_atomic_helper_commit_modeset_enables(dev, old_state);
489 drm_atomic_helper_wait_for_vblanks(dev, old_state);
491 drm_atomic_helper_cleanup_planes(dev, old_state);
493 drm_atomic_state_put(old_state);
495 /* Complete the commit, wake up any waiter. */
496 spin_lock(&dc->commit.wait.lock);
497 dc->commit.pending = false;
498 wake_up_all_locked(&dc->commit.wait);
499 spin_unlock(&dc->commit.wait.lock);
504 static void atmel_hlcdc_dc_atomic_work(struct work_struct *work)
506 struct atmel_hlcdc_dc_commit *commit =
507 container_of(work, struct atmel_hlcdc_dc_commit, work);
509 atmel_hlcdc_dc_atomic_complete(commit);
512 static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev,
513 struct drm_atomic_state *state,
516 struct atmel_hlcdc_dc *dc = dev->dev_private;
517 struct atmel_hlcdc_dc_commit *commit;
520 ret = drm_atomic_helper_prepare_planes(dev, state);
524 /* Allocate the commit object. */
525 commit = kzalloc(sizeof(*commit), GFP_KERNEL);
531 INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work);
533 commit->state = state;
535 spin_lock(&dc->commit.wait.lock);
536 ret = wait_event_interruptible_locked(dc->commit.wait,
537 !dc->commit.pending);
539 dc->commit.pending = true;
540 spin_unlock(&dc->commit.wait.lock);
545 /* We have our own synchronization through the commit lock. */
546 BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
548 /* Swap state succeeded, this is the point of no return. */
549 drm_atomic_state_get(state);
551 queue_work(dc->wq, &commit->work);
553 atmel_hlcdc_dc_atomic_complete(commit);
560 drm_atomic_helper_cleanup_planes(dev, state);
564 static const struct drm_mode_config_funcs mode_config_funcs = {
565 .fb_create = atmel_hlcdc_fb_create,
566 .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
567 .atomic_check = drm_atomic_helper_check,
568 .atomic_commit = atmel_hlcdc_dc_atomic_commit,
571 static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
573 struct atmel_hlcdc_dc *dc = dev->dev_private;
576 drm_mode_config_init(dev);
578 ret = atmel_hlcdc_create_outputs(dev);
580 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
584 ret = atmel_hlcdc_create_planes(dev);
586 dev_err(dev->dev, "failed to create planes: %d\n", ret);
590 ret = atmel_hlcdc_crtc_create(dev);
592 dev_err(dev->dev, "failed to create crtc\n");
596 dev->mode_config.min_width = dc->desc->min_width;
597 dev->mode_config.min_height = dc->desc->min_height;
598 dev->mode_config.max_width = dc->desc->max_width;
599 dev->mode_config.max_height = dc->desc->max_height;
600 dev->mode_config.funcs = &mode_config_funcs;
605 static int atmel_hlcdc_dc_load(struct drm_device *dev)
607 struct platform_device *pdev = to_platform_device(dev->dev);
608 const struct of_device_id *match;
609 struct atmel_hlcdc_dc *dc;
612 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
614 dev_err(&pdev->dev, "invalid compatible string\n");
619 dev_err(&pdev->dev, "invalid hlcdc description\n");
623 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
627 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
631 init_waitqueue_head(&dc->commit.wait);
632 dc->desc = match->data;
633 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
634 dev->dev_private = dc;
636 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
638 dev_err(dev->dev, "failed to enable periph_clk\n");
642 pm_runtime_enable(dev->dev);
644 ret = drm_vblank_init(dev, 1);
646 dev_err(dev->dev, "failed to initialize vblank\n");
647 goto err_periph_clk_disable;
650 ret = atmel_hlcdc_dc_modeset_init(dev);
652 dev_err(dev->dev, "failed to initialize mode setting\n");
653 goto err_periph_clk_disable;
656 drm_mode_config_reset(dev);
658 pm_runtime_get_sync(dev->dev);
659 ret = drm_irq_install(dev, dc->hlcdc->irq);
660 pm_runtime_put_sync(dev->dev);
662 dev_err(dev->dev, "failed to install IRQ handler\n");
663 goto err_periph_clk_disable;
666 platform_set_drvdata(pdev, dev);
668 dc->fbdev = drm_fbdev_cma_init(dev, 24,
669 dev->mode_config.num_connector);
670 if (IS_ERR(dc->fbdev))
673 drm_kms_helper_poll_init(dev);
677 err_periph_clk_disable:
678 pm_runtime_disable(dev->dev);
679 clk_disable_unprepare(dc->hlcdc->periph_clk);
682 destroy_workqueue(dc->wq);
687 static void atmel_hlcdc_dc_unload(struct drm_device *dev)
689 struct atmel_hlcdc_dc *dc = dev->dev_private;
692 drm_fbdev_cma_fini(dc->fbdev);
693 flush_workqueue(dc->wq);
694 drm_kms_helper_poll_fini(dev);
695 drm_mode_config_cleanup(dev);
697 pm_runtime_get_sync(dev->dev);
698 drm_irq_uninstall(dev);
699 pm_runtime_put_sync(dev->dev);
701 dev->dev_private = NULL;
703 pm_runtime_disable(dev->dev);
704 clk_disable_unprepare(dc->hlcdc->periph_clk);
705 destroy_workqueue(dc->wq);
708 static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
710 struct atmel_hlcdc_dc *dc = dev->dev_private;
712 drm_fbdev_cma_restore_mode(dc->fbdev);
715 static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
717 struct atmel_hlcdc_dc *dc = dev->dev_private;
718 unsigned int cfg = 0;
721 /* Enable interrupts on activated layers */
722 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
724 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
727 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
732 static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
734 struct atmel_hlcdc_dc *dc = dev->dev_private;
737 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
738 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
741 DEFINE_DRM_GEM_CMA_FOPS(fops);
743 static struct drm_driver atmel_hlcdc_dc_driver = {
744 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
745 DRIVER_MODESET | DRIVER_PRIME |
747 .lastclose = atmel_hlcdc_dc_lastclose,
748 .irq_handler = atmel_hlcdc_dc_irq_handler,
749 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
750 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
751 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
752 .gem_free_object_unlocked = drm_gem_cma_free_object,
753 .gem_vm_ops = &drm_gem_cma_vm_ops,
754 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
755 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
756 .gem_prime_import = drm_gem_prime_import,
757 .gem_prime_export = drm_gem_prime_export,
758 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
759 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
760 .gem_prime_vmap = drm_gem_cma_prime_vmap,
761 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
762 .gem_prime_mmap = drm_gem_cma_prime_mmap,
763 .dumb_create = drm_gem_cma_dumb_create,
765 .name = "atmel-hlcdc",
766 .desc = "Atmel HLCD Controller DRM",
772 static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
774 struct drm_device *ddev;
777 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
779 return PTR_ERR(ddev);
781 ret = atmel_hlcdc_dc_load(ddev);
785 ret = drm_dev_register(ddev, 0);
792 atmel_hlcdc_dc_unload(ddev);
800 static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
802 struct drm_device *ddev = platform_get_drvdata(pdev);
804 drm_dev_unregister(ddev);
805 atmel_hlcdc_dc_unload(ddev);
811 #ifdef CONFIG_PM_SLEEP
812 static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
814 struct drm_device *drm_dev = dev_get_drvdata(dev);
815 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
816 struct regmap *regmap = dc->hlcdc->regmap;
817 struct drm_atomic_state *state;
819 state = drm_atomic_helper_suspend(drm_dev);
821 return PTR_ERR(state);
823 dc->suspend.state = state;
825 regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);
826 regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);
827 clk_disable_unprepare(dc->hlcdc->periph_clk);
832 static int atmel_hlcdc_dc_drm_resume(struct device *dev)
834 struct drm_device *drm_dev = dev_get_drvdata(dev);
835 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
837 clk_prepare_enable(dc->hlcdc->periph_clk);
838 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);
840 return drm_atomic_helper_resume(drm_dev, dc->suspend.state);
844 static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
845 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
847 static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
848 { .compatible = "atmel,hlcdc-display-controller" },
852 static struct platform_driver atmel_hlcdc_dc_platform_driver = {
853 .probe = atmel_hlcdc_dc_drm_probe,
854 .remove = atmel_hlcdc_dc_drm_remove,
856 .name = "atmel-hlcdc-display-controller",
857 .pm = &atmel_hlcdc_dc_drm_pm_ops,
858 .of_match_table = atmel_hlcdc_dc_of_match,
861 module_platform_driver(atmel_hlcdc_dc_platform_driver);
865 MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
866 MODULE_LICENSE("GPL");
867 MODULE_ALIAS("platform:atmel-hlcdc-dc");