drivers/staging/xgifb/vb_init.c

   1 #include <linux/delay.h>
   2 #include <linux/vmalloc.h>
   3
   4 #include "XGIfb.h"
   5 #include "vb_def.h"
   6 #include "vb_util.h"
   7 #include "vb_setmode.h"
   8 #include "vb_init.h"
   9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  10         { 16, 0x45},
  11         {  8, 0x35},
  12         {  4, 0x31},
  13         {  2, 0x21} };
  14
  15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  16         { 128, 0x5D},
  17         { 64, 0x59},
  18         { 64, 0x4D},
  19         { 32, 0x55},
  20         { 32, 0x49},
  21         { 32, 0x3D},
  22         { 16, 0x51},
  23         { 16, 0x45},
  24         { 16, 0x39},
  25         {  8, 0x41},
  26         {  8, 0x35},
  27         {  4, 0x31} };
  28
  29 #define XGIFB_ROM_SIZE  65536
  30
  31 static unsigned char
  32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  33                        struct vb_device_info *pVBInfo)
  34 {
  35         unsigned char data, temp;
  36
  37         if (HwDeviceExtension->jChipType < XG20) {
  38                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  39                 if (data == 0)
  40                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  41                                    0x02) >> 1;
  42                 return data;
  43         } else if (HwDeviceExtension->jChipType == XG27) {
  44                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  45                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  46                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  47                         data = 0; /* DDR */
  48                 else
  49                         data = 1; /* DDRII */
  50                 return data;
  51         } else if (HwDeviceExtension->jChipType == XG21) {
  52                 /* Independent GPIO control */
  53                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  54                 udelay(800);
  55                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  56                 /* GPIOF 0:DVI 1:DVO */
  57                 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  58                 /* HOTPLUG_SUPPORT */
  59                 /* for current XG20 & XG21, GPIOH is floating, driver will
  60                  * fix DDR temporarily */
  61                 /* DVI read GPIOH */
  62                 data &= 0x01; /* 1=DDRII, 0=DDR */
  63                 /* ~HOTPLUG_SUPPORT */
  64                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  65                 return data;
  66         } else {
  67                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  68
  69                 if (data == 1)
  70                         data++;
  71
  72                 return data;
  73         }
  74 }
  75
  76 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  77                                  struct vb_device_info *pVBInfo)
  78 {
  79         xgifb_reg_set(P3c4, 0x18, 0x01);
  80         xgifb_reg_set(P3c4, 0x19, 0x20);
  81         xgifb_reg_set(P3c4, 0x16, 0x00);
  82         xgifb_reg_set(P3c4, 0x16, 0x80);
  83
  84         mdelay(3);
  85         xgifb_reg_set(P3c4, 0x18, 0x00);
  86         xgifb_reg_set(P3c4, 0x19, 0x20);
  87         xgifb_reg_set(P3c4, 0x16, 0x00);
  88         xgifb_reg_set(P3c4, 0x16, 0x80);
  89
  90         udelay(60);
  91         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  92         xgifb_reg_set(P3c4, 0x19, 0x01);
  93         xgifb_reg_set(P3c4, 0x16, 0x03);
  94         xgifb_reg_set(P3c4, 0x16, 0x83);
  95         mdelay(1);
  96         xgifb_reg_set(P3c4, 0x1B, 0x03);
  97         udelay(500);
  98         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
  99         xgifb_reg_set(P3c4, 0x19, 0x00);
 100         xgifb_reg_set(P3c4, 0x16, 0x03);
 101         xgifb_reg_set(P3c4, 0x16, 0x83);
 102         xgifb_reg_set(P3c4, 0x1B, 0x00);
 103 }
 104
 105 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
 106 {
 107         xgifb_reg_set(pVBInfo->P3c4,
 108                       0x28,
 109                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 110         xgifb_reg_set(pVBInfo->P3c4,
 111                       0x29,
 112                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 113         xgifb_reg_set(pVBInfo->P3c4,
 114                       0x2A,
 115                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 116
 117         xgifb_reg_set(pVBInfo->P3c4,
 118                       0x2E,
 119                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 120         xgifb_reg_set(pVBInfo->P3c4,
 121                       0x2F,
 122                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 123         xgifb_reg_set(pVBInfo->P3c4,
 124                       0x30,
 125                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 126 }
 127
 128 static void XGINew_DDRII_Bootup_XG27(
 129                         struct xgi_hw_device_info *HwDeviceExtension,
 130                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 131 {
 132         unsigned long P3d4 = P3c4 + 0x10;
 133
 134         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 135         XGINew_SetMemoryClock(pVBInfo);
 136
 137         /* Set Double Frequency */
 138         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 139
 140         udelay(200);
 141
 142         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 143         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 144         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 145         udelay(15);
 146         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 147         udelay(15);
 148
 149         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 150         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 151         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 152         udelay(15);
 153         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 154         udelay(15);
 155
 156         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 157         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 158         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 159         udelay(30);
 160         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 161         udelay(15);
 162
 163         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 164         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 165         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 166         udelay(30);
 167         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 168         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 169
 170         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 171         udelay(60);
 172         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 173
 174         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 175         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 176         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 177
 178         udelay(30);
 179         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 180         udelay(15);
 181
 182         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 183         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 184         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 185         udelay(30);
 186         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 187         udelay(15);
 188
 189         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 190         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 191         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 192         udelay(30);
 193         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 194         udelay(15);
 195
 196         /* Set SR1B refresh control 000:close; 010:open */
 197         xgifb_reg_set(P3c4, 0x1B, 0x04);
 198         udelay(200);
 199
 200 }
 201
 202 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 203                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 204 {
 205         unsigned long P3d4 = P3c4 + 0x10;
 206
 207         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 208         XGINew_SetMemoryClock(pVBInfo);
 209
 210         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 211
 212         udelay(200);
 213         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 214         xgifb_reg_set(P3c4, 0x19, 0x80);
 215         xgifb_reg_set(P3c4, 0x16, 0x05);
 216         xgifb_reg_set(P3c4, 0x16, 0x85);
 217
 218         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 219         xgifb_reg_set(P3c4, 0x19, 0xC0);
 220         xgifb_reg_set(P3c4, 0x16, 0x05);
 221         xgifb_reg_set(P3c4, 0x16, 0x85);
 222
 223         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 224         xgifb_reg_set(P3c4, 0x19, 0x40);
 225         xgifb_reg_set(P3c4, 0x16, 0x05);
 226         xgifb_reg_set(P3c4, 0x16, 0x85);
 227
 228         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 229         xgifb_reg_set(P3c4, 0x19, 0x02);
 230         xgifb_reg_set(P3c4, 0x16, 0x05);
 231         xgifb_reg_set(P3c4, 0x16, 0x85);
 232
 233         udelay(15);
 234         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 235         udelay(30);
 236         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 237         udelay(100);
 238
 239         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 240         xgifb_reg_set(P3c4, 0x19, 0x00);
 241         xgifb_reg_set(P3c4, 0x16, 0x05);
 242         xgifb_reg_set(P3c4, 0x16, 0x85);
 243
 244         udelay(200);
 245 }
 246
 247 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 248                                   struct vb_device_info *pVBInfo)
 249 {
 250         xgifb_reg_set(P3c4, 0x18, 0x01);
 251         xgifb_reg_set(P3c4, 0x19, 0x40);
 252         xgifb_reg_set(P3c4, 0x16, 0x00);
 253         xgifb_reg_set(P3c4, 0x16, 0x80);
 254         udelay(60);
 255
 256         xgifb_reg_set(P3c4, 0x18, 0x00);
 257         xgifb_reg_set(P3c4, 0x19, 0x40);
 258         xgifb_reg_set(P3c4, 0x16, 0x00);
 259         xgifb_reg_set(P3c4, 0x16, 0x80);
 260         udelay(60);
 261         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 262         xgifb_reg_set(P3c4, 0x19, 0x01);
 263         xgifb_reg_set(P3c4, 0x16, 0x03);
 264         xgifb_reg_set(P3c4, 0x16, 0x83);
 265         mdelay(1);
 266         xgifb_reg_set(P3c4, 0x1B, 0x03);
 267         udelay(500);
 268         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 269         xgifb_reg_set(P3c4, 0x19, 0x00);
 270         xgifb_reg_set(P3c4, 0x16, 0x03);
 271         xgifb_reg_set(P3c4, 0x16, 0x83);
 272         xgifb_reg_set(P3c4, 0x1B, 0x00);
 273 }
 274
 275 static void XGINew_DDR1x_DefaultRegister(
 276                 struct xgi_hw_device_info *HwDeviceExtension,
 277                 unsigned long Port, struct vb_device_info *pVBInfo)
 278 {
 279         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 280
 281         if (HwDeviceExtension->jChipType >= XG20) {
 282                 XGINew_SetMemoryClock(pVBInfo);
 283                 xgifb_reg_set(P3d4,
 284                               0x82,
 285                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 286                 xgifb_reg_set(P3d4,
 287                               0x85,
 288                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 289                 xgifb_reg_set(P3d4,
 290                               0x86,
 291                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 292
 293                 xgifb_reg_set(P3d4, 0x98, 0x01);
 294                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 295
 296                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 297         } else {
 298                 XGINew_SetMemoryClock(pVBInfo);
 299
 300                 switch (HwDeviceExtension->jChipType) {
 301                 case XG42:
 302                         /* CR82 */
 303                         xgifb_reg_set(P3d4,
 304                                       0x82,
 305                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 306                         /* CR85 */
 307                         xgifb_reg_set(P3d4,
 308                                       0x85,
 309                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 310                         /* CR86 */
 311                         xgifb_reg_set(P3d4,
 312                                       0x86,
 313                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 314                         break;
 315                 default:
 316                         xgifb_reg_set(P3d4, 0x82, 0x88);
 317                         xgifb_reg_set(P3d4, 0x86, 0x00);
 318                         /* Insert read command for delay */
 319                         xgifb_reg_get(P3d4, 0x86);
 320                         xgifb_reg_set(P3d4, 0x86, 0x88);
 321                         xgifb_reg_get(P3d4, 0x86);
 322                         xgifb_reg_set(P3d4,
 323                                       0x86,
 324                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 325                         xgifb_reg_set(P3d4, 0x82, 0x77);
 326                         xgifb_reg_set(P3d4, 0x85, 0x00);
 327
 328                         /* Insert read command for delay */
 329                         xgifb_reg_get(P3d4, 0x85);
 330                         xgifb_reg_set(P3d4, 0x85, 0x88);
 331
 332                         /* Insert read command for delay */
 333                         xgifb_reg_get(P3d4, 0x85);
 334                         /* CR85 */
 335                         xgifb_reg_set(P3d4,
 336                                       0x85,
 337                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 338                         /* CR82 */
 339                         xgifb_reg_set(P3d4,
 340                                       0x82,
 341                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 342                         break;
 343                 }
 344
 345                 xgifb_reg_set(P3d4, 0x97, 0x00);
 346                 xgifb_reg_set(P3d4, 0x98, 0x01);
 347                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 348                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 349         }
 350 }
 351
 352 static void XGINew_DDR2_DefaultRegister(
 353                 struct xgi_hw_device_info *HwDeviceExtension,
 354                 unsigned long Port, struct vb_device_info *pVBInfo)
 355 {
 356         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 357
 358         /* keep following setting sequence, each setting in
 359          * the same reg insert idle */
 360         xgifb_reg_set(P3d4, 0x82, 0x77);
 361         xgifb_reg_set(P3d4, 0x86, 0x00);
 362         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 363         xgifb_reg_set(P3d4, 0x86, 0x88);
 364         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 365         /* CR86 */
 366         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 367         xgifb_reg_set(P3d4, 0x82, 0x77);
 368         xgifb_reg_set(P3d4, 0x85, 0x00);
 369         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 370         xgifb_reg_set(P3d4, 0x85, 0x88);
 371         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 372         xgifb_reg_set(P3d4,
 373                       0x85,
 374                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 375         if (HwDeviceExtension->jChipType == XG27)
 376                 /* CR82 */
 377                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 378         else
 379                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 380
 381         xgifb_reg_set(P3d4, 0x98, 0x01);
 382         xgifb_reg_set(P3d4, 0x9A, 0x02);
 383         if (HwDeviceExtension->jChipType == XG27)
 384                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 385         else
 386                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 387 }
 388
 389 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 390         u8 shift_factor, u8 mask1, u8 mask2)
 391 {
 392         u8 j;
 393
 394         for (j = 0; j < 4; j++) {
 395                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 396                 xgifb_reg_set(P3d4, reg, temp2);
 397                 xgifb_reg_get(P3d4, reg);
 398                 temp2 &= mask1;
 399                 temp2 += mask2;
 400         }
 401 }
 402
 403 static void XGINew_SetDRAMDefaultRegister340(
 404                 struct xgi_hw_device_info *HwDeviceExtension,
 405                 unsigned long Port, struct vb_device_info *pVBInfo)
 406 {
 407         unsigned char temp, temp1, temp2, temp3, j, k;
 408
 409         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 410
 411         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 412         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 413         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 414         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 415
 416         /* CR6B DQS fine tune delay */
 417         temp = 0xaa;
 418         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 419
 420         /* CR6E DQM fine tune delay */
 421         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 422
 423         temp3 = 0;
 424         for (k = 0; k < 4; k++) {
 425                 /* CR6E_D[1:0] select channel */
 426                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 427                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 428                 temp3 += 0x01;
 429         }
 430
 431         xgifb_reg_set(P3d4,
 432                       0x80,
 433                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 434         xgifb_reg_set(P3d4,
 435                       0x81,
 436                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 437
 438         temp2 = 0x80;
 439         /* CR89 terminator type select */
 440         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 441
 442         temp = 0;
 443         temp1 = temp & 0x03;
 444         temp2 |= temp1;
 445         xgifb_reg_set(P3d4, 0x89, temp2);
 446
 447         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 448         temp1 = temp & 0x0F;
 449         temp2 = (temp >> 4) & 0x07;
 450         temp3 = temp & 0x80;
 451         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 452         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 453         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 454         xgifb_reg_set(P3d4,
 455                       0x41,
 456                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 457
 458         if (HwDeviceExtension->jChipType == XG27)
 459                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 460
 461         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 462                 xgifb_reg_set(P3d4, (0x90 + j),
 463                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 464
 465         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 466                 xgifb_reg_set(P3d4, (0xC3 + j),
 467                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 468
 469         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 470                 xgifb_reg_set(P3d4, (0x8A + j),
 471                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 472
 473         if (HwDeviceExtension->jChipType == XG42)
 474                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 475
 476         xgifb_reg_set(P3d4,
 477                       0x59,
 478                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 479
 480         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 481         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 482         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 483         if (pVBInfo->ram_type) {
 484                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 485                 if (HwDeviceExtension->jChipType == XG27)
 486                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 487
 488         } else {
 489                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 490         }
 491         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 492
 493         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 494         if (temp == 0) {
 495                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 496         } else {
 497                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 498                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 499         }
 500         xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
 501 }
 502
 503
 504 static unsigned short XGINew_SetDRAMSize20Reg(
 505                 unsigned short dram_size,
 506                 struct vb_device_info *pVBInfo)
 507 {
 508         unsigned short data = 0, memsize = 0;
 509         int RankSize;
 510         unsigned char ChannelNo;
 511
 512         RankSize = dram_size * pVBInfo->ram_bus / 8;
 513         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 514         data &= 0x80;
 515
 516         if (data == 0x80)
 517                 RankSize *= 2;
 518
 519         data = 0;
 520
 521         if (pVBInfo->ram_channel == 3)
 522                 ChannelNo = 4;
 523         else
 524                 ChannelNo = pVBInfo->ram_channel;
 525
 526         if (ChannelNo * RankSize <= 256) {
 527                 while ((RankSize >>= 1) > 0)
 528                         data += 0x10;
 529
 530                 memsize = data >> 4;
 531
 532                 /* Fix DRAM Sizing Error */
 533                 xgifb_reg_set(pVBInfo->P3c4,
 534                               0x14,
 535                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 536                                 (data & 0xF0));
 537                 udelay(15);
 538         }
 539         return memsize;
 540 }
 541
 542 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 543                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 544 {
 545         int i;
 546         unsigned long Position = 0;
 547         void __iomem *fbaddr = pVBInfo->FBAddr;
 548
 549         writel(Position, fbaddr + Position);
 550
 551         for (i = StartAddr; i <= StopAddr; i++) {
 552                 Position = 1 << i;
 553                 writel(Position, fbaddr + Position);
 554         }
 555
 556         udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
 557
 558         Position = 0;
 559
 560         if (readl(fbaddr + Position) != Position)
 561                 return 0;
 562
 563         for (i = StartAddr; i <= StopAddr; i++) {
 564                 Position = 1 << i;
 565                 if (readl(fbaddr + Position) != Position)
 566                         return 0;
 567         }
 568         return 1;
 569 }
 570
 571 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 572 {
 573         unsigned char data;
 574
 575         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 576
 577         if ((data & 0x10) == 0) {
 578                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 579                 data = (data & 0x02) >> 1;
 580                 return data;
 581         } else {
 582                 return data & 0x01;
 583         }
 584 }
 585
 586 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 587                 struct vb_device_info *pVBInfo)
 588 {
 589         unsigned char data;
 590
 591         switch (HwDeviceExtension->jChipType) {
 592         case XG20:
 593         case XG21:
 594                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 595                 data = data & 0x01;
 596                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 597
 598                 if (data == 0) { /* Single_32_16 */
 599
 600                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 601                                         > 0x1000000) {
 602
 603                                 pVBInfo->ram_bus = 32; /* 32 bits */
 604                                 /* 22bit + 2 rank + 32bit */
 605                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 606                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 607                                 udelay(15);
 608
 609                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 610                                         return;
 611
 612                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 613                                     0x800000) {
 614                                         /* 22bit + 1 rank + 32bit */
 615                                         xgifb_reg_set(pVBInfo->P3c4,
 616                                                       0x13,
 617                                                       0x31);
 618                                         xgifb_reg_set(pVBInfo->P3c4,
 619                                                       0x14,
 620                                                       0x42);
 621                                         udelay(15);
 622
 623                                         if (XGINew_ReadWriteRest(23,
 624                                                                  23,
 625                                                                  pVBInfo) == 1)
 626                                                 return;
 627                                 }
 628                         }
 629
 630                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 631                             0x800000) {
 632                                 pVBInfo->ram_bus = 16; /* 16 bits */
 633                                 /* 22bit + 2 rank + 16bit */
 634                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 635                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 636                                 udelay(15);
 637
 638                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 639                                         return;
 640                                 else
 641                                         xgifb_reg_set(pVBInfo->P3c4,
 642                                                       0x13,
 643                                                       0x31);
 644                                 udelay(15);
 645                         }
 646
 647                 } else { /* Dual_16_8 */
 648                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 649                             0x800000) {
 650                                 pVBInfo->ram_bus = 16; /* 16 bits */
 651                                 /* (0x31:12x8x2) 22bit + 2 rank */
 652                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 653                                 /* 0x41:16Mx16 bit*/
 654                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 655                                 udelay(15);
 656
 657                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 658                                         return;
 659
 660                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 661                                     0x400000) {
 662                                         /* (0x31:12x8x2) 22bit + 1 rank */
 663                                         xgifb_reg_set(pVBInfo->P3c4,
 664                                                       0x13,
 665                                                       0x31);
 666                                         /* 0x31:8Mx16 bit*/
 667                                         xgifb_reg_set(pVBInfo->P3c4,
 668                                                       0x14,
 669                                                       0x31);
 670                                         udelay(15);
 671
 672                                         if (XGINew_ReadWriteRest(22,
 673                                                                  22,
 674                                                                  pVBInfo) == 1)
 675                                                 return;
 676                                 }
 677                         }
 678
 679                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 680                             0x400000) {
 681                                 pVBInfo->ram_bus = 8; /* 8 bits */
 682                                 /* (0x31:12x8x2) 22bit + 2 rank */
 683                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 684                                 /* 0x30:8Mx8 bit*/
 685                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 686                                 udelay(15);
 687
 688                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 689                                         return;
 690                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 691                                         xgifb_reg_set(pVBInfo->P3c4,
 692                                                       0x13,
 693                                                       0x31);
 694                                 udelay(15);
 695                         }
 696                 }
 697                 break;
 698
 699         case XG27:
 700                 pVBInfo->ram_bus = 16; /* 16 bits */
 701                 pVBInfo->ram_channel = 1; /* Single channel */
 702                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 703                 break;
 704         case XG42:
 705                 /*
 706                  XG42 SR14 D[3] Reserve
 707                  D[2] = 1, Dual Channel
 708                  = 0, Single Channel
 709
 710                  It's Different from Other XG40 Series.
 711                  */
 712                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 713                         pVBInfo->ram_bus = 32; /* 32 bits */
 714                         pVBInfo->ram_channel = 2; /* 2 Channel */
 715                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 716                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 717
 718                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 719                                 return;
 720
 721                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 722                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 723                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 724                                 return;
 725
 726                         pVBInfo->ram_channel = 1; /* Single Channel */
 727                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 728                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 729
 730                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 731                                 return;
 732                         else {
 733                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 734                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 735                         }
 736                 } else { /* DDR */
 737                         pVBInfo->ram_bus = 64; /* 64 bits */
 738                         pVBInfo->ram_channel = 1; /* 1 channels */
 739                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 740                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 741
 742                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 743                                 return;
 744                         else {
 745                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 746                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 747                         }
 748                 }
 749
 750                 break;
 751
 752         default: /* XG40 */
 753
 754                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 755                         pVBInfo->ram_bus = 32; /* 32 bits */
 756                         pVBInfo->ram_channel = 3;
 757                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 758                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 759
 760                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 761                                 return;
 762
 763                         pVBInfo->ram_channel = 2; /* 2 channels */
 764                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 765
 766                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 767                                 return;
 768
 769                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 770                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 771
 772                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 773                                 pVBInfo->ram_channel = 3; /* 4 channels */
 774                         } else {
 775                                 pVBInfo->ram_channel = 2; /* 2 channels */
 776                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 777                         }
 778                 } else { /* DDR */
 779                         pVBInfo->ram_bus = 64; /* 64 bits */
 780                         pVBInfo->ram_channel = 2; /* 2 channels */
 781                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 782                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 783
 784                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 785                                 return;
 786                         } else {
 787                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 788                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 789                         }
 790                 }
 791                 break;
 792         }
 793 }
 794
 795 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 796                 struct vb_device_info *pVBInfo)
 797 {
 798         u8 i, size;
 799         unsigned short memsize, start_addr;
 800         const unsigned short (*dram_table)[2];
 801
 802         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 803         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 804         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 805
 806         if (HwDeviceExtension->jChipType >= XG20) {
 807                 dram_table = XGINew_DDRDRAM_TYPE20;
 808                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 809                 start_addr = 5;
 810         } else {
 811                 dram_table = XGINew_DDRDRAM_TYPE340;
 812                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 813                 start_addr = 9;
 814         }
 815
 816         for (i = 0; i < size; i++) {
 817                 /* SetDRAMSizingType */
 818                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 819                 udelay(15); /* should delay 50 ns */
 820
 821                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 822
 823                 if (memsize == 0)
 824                         continue;
 825
 826                 memsize += (pVBInfo->ram_channel - 2) + 20;
 827                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 828                         (unsigned long) (1 << memsize))
 829                         continue;
 830
 831                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 832                         return 1;
 833         }
 834         return 0;
 835 }
 836
 837 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 838                 struct xgi_hw_device_info *HwDeviceExtension,
 839                 struct vb_device_info *pVBInfo)
 840 {
 841         unsigned short data;
 842
 843         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 844
 845         XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 846
 847         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 848         /* disable read cache */
 849         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
 850         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 851
 852         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 853         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 854         /* enable read cache */
 855         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
 856 }
 857
 858 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
 859 {
 860         void __iomem *rom_address;
 861         u8 *rom_copy;
 862
 863         rom_address = pci_map_rom(dev, rom_size);
 864         if (rom_address == NULL)
 865                 return NULL;
 866
 867         rom_copy = vzalloc(XGIFB_ROM_SIZE);
 868         if (rom_copy == NULL)
 869                 goto done;
 870
 871         *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
 872         memcpy_fromio(rom_copy, rom_address, *rom_size);
 873
 874 done:
 875         pci_unmap_rom(dev, rom_address);
 876         return rom_copy;
 877 }
 878
 879 static bool xgifb_read_vbios(struct pci_dev *pdev)
 880 {
 881         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
 882         u8 *vbios;
 883         unsigned long i;
 884         unsigned char j;
 885         struct XGI21_LVDSCapStruct *lvds;
 886         size_t vbios_size;
 887         int entry;
 888
 889         vbios = xgifb_copy_rom(pdev, &vbios_size);
 890         if (vbios == NULL) {
 891                 dev_err(&pdev->dev, "Video BIOS not available\n");
 892                 return false;
 893         }
 894         if (vbios_size <= 0x65)
 895                 goto error;
 896         /*
 897          * The user can ignore the LVDS bit in the BIOS and force the display
 898          * type.
 899          */
 900         if (!(vbios[0x65] & 0x1) &&
 901             (!xgifb_info->display2_force ||
 902              xgifb_info->display2 != XGIFB_DISP_LCD)) {
 903                 vfree(vbios);
 904                 return false;
 905         }
 906         if (vbios_size <= 0x317)
 907                 goto error;
 908         i = vbios[0x316] | (vbios[0x317] << 8);
 909         if (vbios_size <= i - 1)
 910                 goto error;
 911         j = vbios[i - 1];
 912         if (j == 0)
 913                 goto error;
 914         if (j == 0xff)
 915                 j = 1;
 916         /*
 917          * Read the LVDS table index scratch register set by the BIOS.
 918          */
 919         entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
 920         if (entry >= j)
 921                 entry = 0;
 922         i += entry * 25;
 923         lvds = &xgifb_info->lvds_data;
 924         if (vbios_size <= i + 24)
 925                 goto error;
 926         lvds->LVDS_Capability   = vbios[i]      | (vbios[i + 1] << 8);
 927         lvds->LVDSHT            = vbios[i + 2]  | (vbios[i + 3] << 8);
 928         lvds->LVDSVT            = vbios[i + 4]  | (vbios[i + 5] << 8);
 929         lvds->LVDSHDE           = vbios[i + 6]  | (vbios[i + 7] << 8);
 930         lvds->LVDSVDE           = vbios[i + 8]  | (vbios[i + 9] << 8);
 931         lvds->LVDSHFP           = vbios[i + 10] | (vbios[i + 11] << 8);
 932         lvds->LVDSVFP           = vbios[i + 12] | (vbios[i + 13] << 8);
 933         lvds->LVDSHSYNC         = vbios[i + 14] | (vbios[i + 15] << 8);
 934         lvds->LVDSVSYNC         = vbios[i + 16] | (vbios[i + 17] << 8);
 935         lvds->VCLKData1         = vbios[i + 18];
 936         lvds->VCLKData2         = vbios[i + 19];
 937         lvds->PSC_S1            = vbios[i + 20];
 938         lvds->PSC_S2            = vbios[i + 21];
 939         lvds->PSC_S3            = vbios[i + 22];
 940         lvds->PSC_S4            = vbios[i + 23];
 941         lvds->PSC_S5            = vbios[i + 24];
 942         vfree(vbios);
 943         return true;
 944 error:
 945         dev_err(&pdev->dev, "Video BIOS corrupted\n");
 946         vfree(vbios);
 947         return false;
 948 }
 949
 950 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
 951 {
 952         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 953
 954         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 955
 956         if (temp & Monitor1Sense)
 957                 tempbx |= ActiveCRT1;
 958         if (temp & LCDSense)
 959                 tempbx |= ActiveLCD;
 960         if (temp & Monitor2Sense)
 961                 tempbx |= ActiveCRT2;
 962         if (temp & TVSense) {
 963                 tempbx |= ActiveTV;
 964                 if (temp & AVIDEOSense)
 965                         tempbx |= (ActiveAVideo << 8);
 966                 if (temp & SVIDEOSense)
 967                         tempbx |= (ActiveSVideo << 8);
 968                 if (temp & SCARTSense)
 969                         tempbx |= (ActiveSCART << 8);
 970                 if (temp & HiTVSense)
 971                         tempbx |= (ActiveHiTV << 8);
 972                 if (temp & YPbPrSense)
 973                         tempbx |= (ActiveYPbPr << 8);
 974         }
 975
 976         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 977         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
 978
 979         if (tempbx & tempcx) {
 980                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
 981                 if (!(CR3CData & DisplayDeviceFromCMOS))
 982                         tempcx = 0x1FF0;
 983         } else {
 984                 tempcx = 0x1FF0;
 985         }
 986
 987         tempbx &= tempcx;
 988         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
 989         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
 990 }
 991
 992 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
 993 {
 994         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
 995
 996         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 997         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
 998         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
 999
1000         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1001                 if (temp & ActiveCRT2)
1002                         tempcl = SetCRT2ToRAMDAC;
1003         }
1004
1005         if (temp & ActiveLCD) {
1006                 tempcl |= SetCRT2ToLCD;
1007                 if (temp & DriverMode) {
1008                         if (temp & ActiveTV) {
1009                                 tempch = SetToLCDA | EnableDualEdge;
1010                                 temp ^= SetCRT2ToLCD;
1011
1012                                 if ((temp >> 8) & ActiveAVideo)
1013                                         tempcl |= SetCRT2ToAVIDEO;
1014                                 if ((temp >> 8) & ActiveSVideo)
1015                                         tempcl |= SetCRT2ToSVIDEO;
1016                                 if ((temp >> 8) & ActiveSCART)
1017                                         tempcl |= SetCRT2ToSCART;
1018
1019                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1020                                         if ((temp >> 8) & ActiveHiTV)
1021                                                 tempcl |= SetCRT2ToHiVision;
1022                                 }
1023
1024                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1025                                         if ((temp >> 8) & ActiveYPbPr)
1026                                                 tempch |= SetYPbPr;
1027                                 }
1028                         }
1029                 }
1030         } else {
1031                 if ((temp >> 8) & ActiveAVideo)
1032                         tempcl |= SetCRT2ToAVIDEO;
1033                 if ((temp >> 8) & ActiveSVideo)
1034                         tempcl |= SetCRT2ToSVIDEO;
1035                 if ((temp >> 8) & ActiveSCART)
1036                         tempcl |= SetCRT2ToSCART;
1037
1038                 if (pVBInfo->IF_DEF_HiVision == 1) {
1039                         if ((temp >> 8) & ActiveHiTV)
1040                                 tempcl |= SetCRT2ToHiVision;
1041                 }
1042
1043                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1044                         if ((temp >> 8) & ActiveYPbPr)
1045                                 tempch |= SetYPbPr;
1046                 }
1047         }
1048
1049         tempcl |= SetSimuScanMode;
1050         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1051                         || (temp & ActiveCRT2)))
1052                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1053         if ((temp & ActiveLCD) && (temp & ActiveTV))
1054                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1055         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1056
1057         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1058         CR31Data &= ~(SetNotSimuMode >> 8);
1059         if (!(temp & ActiveCRT1))
1060                 CR31Data |= (SetNotSimuMode >> 8);
1061         CR31Data &= ~(DisableCRT2Display >> 8);
1062         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1063                 CR31Data |= (DisableCRT2Display >> 8);
1064         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1065
1066         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1067         CR38Data &= ~SetYPbPr;
1068         CR38Data |= tempch;
1069         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1070
1071 }
1072
1073 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1074                                                         *HwDeviceExtension,
1075                                       struct vb_device_info *pVBInfo)
1076 {
1077         unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
1078
1079         switch (HwDeviceExtension->ulCRT2LCDType) {
1080         case LCD_640x480:
1081         case LCD_1024x600:
1082         case LCD_1152x864:
1083         case LCD_1280x960:
1084         case LCD_1152x768:
1085         case LCD_1920x1440:
1086         case LCD_2048x1536:
1087                 temp = 0; /* overwrite used ulCRT2LCDType */
1088                 break;
1089         case LCD_UNKNOWN: /* unknown lcd, do nothing */
1090                 return 0;
1091         }
1092         xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1093         return 1;
1094 }
1095
1096 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1097                 struct vb_device_info *pVBInfo)
1098 {
1099         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1100         unsigned char Temp;
1101
1102         if (xgifb_read_vbios(pdev)) { /* For XG21 LVDS */
1103                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1104                 /* LVDS on chip */
1105                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1106         } else {
1107                 /* Enable GPIOA/B read  */
1108                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1109                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1110                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1111                         XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1112                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1113                         /* Enable read GPIOF */
1114                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1115                         if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1116                                 Temp = 0xA0; /* Only DVO on chip */
1117                         else
1118                                 Temp = 0x80; /* TMDS on chip */
1119                         xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1120                         /* Disable read GPIOF */
1121                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1122                 }
1123         }
1124 }
1125
1126 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1127 {
1128         unsigned char Temp, bCR4A;
1129
1130         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1131         /* Enable GPIOA/B/C read  */
1132         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1133         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1134         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1135
1136         if (Temp <= 0x02) {
1137                 /* LVDS setting */
1138                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1139                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1140         } else {
1141                 /* TMDS/DVO setting */
1142                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1143         }
1144         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1145
1146 }
1147
1148 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1149 {
1150         unsigned char CR38, CR4A, temp;
1151
1152         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1153         /* enable GPIOE read */
1154         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1155         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1156         temp = 0;
1157         if ((CR38 & 0xE0) > 0x80) {
1158                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1159                 temp &= 0x08;
1160                 temp >>= 3;
1161         }
1162
1163         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1164
1165         return temp;
1166 }
1167
1168 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1169 {
1170         unsigned char CR4A, temp;
1171
1172         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1173         /* enable GPIOA/B/C read */
1174         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1175         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1176         if (temp > 2)
1177                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1178
1179         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1180
1181         return temp;
1182 }
1183
1184 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1185 {
1186         u8 flag;
1187
1188         flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1189         return flag == 1 || flag == 2;
1190 }
1191
1192 unsigned char XGIInitNew(struct pci_dev *pdev)
1193 {
1194         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1195         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1196         struct vb_device_info VBINF;
1197         struct vb_device_info *pVBInfo = &VBINF;
1198         unsigned char i, temp = 0, temp1;
1199
1200         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1201
1202         if (pVBInfo->FBAddr == NULL) {
1203                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1204                 return 0;
1205         }
1206
1207         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1208
1209         outb(0x67, pVBInfo->P3c2);
1210
1211         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1212
1213         /* Openkey */
1214         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1215
1216         /* GetXG21Sense (GPIO) */
1217         if (HwDeviceExtension->jChipType == XG21)
1218                 XGINew_GetXG21Sense(pdev, pVBInfo);
1219
1220         if (HwDeviceExtension->jChipType == XG27)
1221                 XGINew_GetXG27Sense(pVBInfo);
1222
1223         /* Reset Extended register */
1224
1225         for (i = 0x06; i < 0x20; i++)
1226                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1227
1228         for (i = 0x21; i <= 0x27; i++)
1229                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1230
1231         for (i = 0x31; i <= 0x3B; i++)
1232                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1233
1234         /* Auto over driver for XG42 */
1235         if (HwDeviceExtension->jChipType == XG42)
1236                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1237
1238         for (i = 0x79; i <= 0x7C; i++)
1239                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1240
1241         if (HwDeviceExtension->jChipType >= XG20)
1242                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1243
1244         /* SetDefExt1Regs begin */
1245         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1246         if (HwDeviceExtension->jChipType == XG27) {
1247                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1248                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1249         }
1250         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1251         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1252         /* Frame buffer can read/write SR20 */
1253         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1254         /* H/W request for slow corner chip */
1255         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1256         if (HwDeviceExtension->jChipType == XG27)
1257                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1258
1259         if (HwDeviceExtension->jChipType < XG20) {
1260                 u32 Temp;
1261
1262                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1263                 for (i = 0x47; i <= 0x4C; i++)
1264                         xgifb_reg_set(pVBInfo->P3d4,
1265                                       i,
1266                                       XGI340_AGPReg[i - 0x47]);
1267
1268                 for (i = 0x70; i <= 0x71; i++)
1269                         xgifb_reg_set(pVBInfo->P3d4,
1270                                       i,
1271                                       XGI340_AGPReg[6 + i - 0x70]);
1272
1273                 for (i = 0x74; i <= 0x77; i++)
1274                         xgifb_reg_set(pVBInfo->P3d4,
1275                                       i,
1276                                       XGI340_AGPReg[8 + i - 0x74]);
1277
1278                 pci_read_config_dword(pdev, 0x50, &Temp);
1279                 Temp >>= 20;
1280                 Temp &= 0xF;
1281
1282                 if (Temp == 1)
1283                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1284         } /* != XG20 */
1285
1286         /* Set PCI */
1287         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1288         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1289         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1290
1291         if (HwDeviceExtension->jChipType < XG20) {
1292                 /* Set VB */
1293                 XGI_UnLockCRT2(pVBInfo);
1294                 /* disable VideoCapture */
1295                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1296                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1297                 /* chk if BCLK>=100MHz */
1298                 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1299
1300                 xgifb_reg_set(pVBInfo->Part1Port,
1301                               0x02, XGI330_CRT2Data_1_2);
1302
1303                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1304         } /* != XG20 */
1305
1306         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1307
1308         if ((HwDeviceExtension->jChipType == XG42) &&
1309             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1310                 /* Not DDR */
1311                 xgifb_reg_set(pVBInfo->P3c4,
1312                               0x31,
1313                               (XGI330_SR31 & 0x3F) | 0x40);
1314                 xgifb_reg_set(pVBInfo->P3c4,
1315                               0x32,
1316                               (XGI330_SR32 & 0xFC) | 0x01);
1317         } else {
1318                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1319                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1320         }
1321         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1322
1323         if (HwDeviceExtension->jChipType < XG20) {
1324                 if (xgifb_bridge_is_on(pVBInfo)) {
1325                         xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1326                         xgifb_reg_set(pVBInfo->Part4Port,
1327                                       0x0D, XGI330_CRT2Data_4_D);
1328                         xgifb_reg_set(pVBInfo->Part4Port,
1329                                       0x0E, XGI330_CRT2Data_4_E);
1330                         xgifb_reg_set(pVBInfo->Part4Port,
1331                                       0x10, XGI330_CRT2Data_4_10);
1332                         xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1333                         XGI_LockCRT2(pVBInfo);
1334                 }
1335         } /* != XG20 */
1336
1337         XGI_SenseCRT1(pVBInfo);
1338
1339         if (HwDeviceExtension->jChipType == XG21) {
1340
1341                 xgifb_reg_and_or(pVBInfo->P3d4,
1342                                  0x32,
1343                                  ~Monitor1Sense,
1344                                  Monitor1Sense); /* Z9 default has CRT */
1345                 temp = GetXG21FPBits(pVBInfo);
1346                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1347
1348         }
1349         if (HwDeviceExtension->jChipType == XG27) {
1350                 xgifb_reg_and_or(pVBInfo->P3d4,
1351                                  0x32,
1352                                  ~Monitor1Sense,
1353                                  Monitor1Sense); /* Z9 default has CRT */
1354                 temp = GetXG27FPBits(pVBInfo);
1355                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1356         }
1357
1358         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1359
1360         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1361                                          pVBInfo->P3d4,
1362                                          pVBInfo);
1363
1364         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1365
1366         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1367         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1368
1369         XGINew_ChkSenseStatus(pVBInfo);
1370         XGINew_SetModeScratch(pVBInfo);
1371
1372         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1373
1374         return 1;
1375 } /* end of init */