drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25 #ifndef __AMDGPU_PSP_H__
  26 #define __AMDGPU_PSP_H__
  27
  28 #include "amdgpu.h"
  29 #include "psp_gfx_if.h"
  30 #include "ta_xgmi_if.h"
  31 #include "ta_ras_if.h"
  32
  33 #define PSP_FENCE_BUFFER_SIZE   0x1000
  34 #define PSP_CMD_BUFFER_SIZE     0x1000
  35 #define PSP_XGMI_SHARED_MEM_SIZE 0x4000
  36 #define PSP_RAS_SHARED_MEM_SIZE 0x4000
  37 #define PSP_1_MEG               0x100000
  38 #define PSP_TMR_SIZE    0x400000
  39 #define PSP_HDCP_SHARED_MEM_SIZE        0x4000
  40 #define PSP_DTM_SHARED_MEM_SIZE 0x4000
  41 #define PSP_SHARED_MEM_SIZE             0x4000
  42
  43 struct psp_context;
  44 struct psp_xgmi_node_info;
  45 struct psp_xgmi_topology_info;
  46
  47 enum psp_bootloader_cmd {
  48         PSP_BL__LOAD_SYSDRV             = 0x10000,
  49         PSP_BL__LOAD_SOSDRV             = 0x20000,
  50         PSP_BL__LOAD_KEY_DATABASE       = 0x80000,
  51         PSP_BL__DRAM_LONG_TRAIN         = 0x100000,
  52         PSP_BL__DRAM_SHORT_TRAIN        = 0x200000,
  53 };
  54
  55 enum psp_ring_type
  56 {
  57         PSP_RING_TYPE__INVALID = 0,
  58         /*
  59          * These values map to the way the PSP kernel identifies the
  60          * rings.
  61          */
  62         PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
  63         PSP_RING_TYPE__KM = 2  /* Kernel mode ring (formerly called GPCOM) */
  64 };
  65
  66 struct psp_ring
  67 {
  68         enum psp_ring_type              ring_type;
  69         struct psp_gfx_rb_frame         *ring_mem;
  70         uint64_t                        ring_mem_mc_addr;
  71         void                            *ring_mem_handle;
  72         uint32_t                        ring_size;
  73 };
  74
  75 /* More registers may will be supported */
  76 enum psp_reg_prog_id {
  77         PSP_REG_IH_RB_CNTL        = 0,  /* register IH_RB_CNTL */
  78         PSP_REG_IH_RB_CNTL_RING1  = 1,  /* register IH_RB_CNTL_RING1 */
  79         PSP_REG_IH_RB_CNTL_RING2  = 2,  /* register IH_RB_CNTL_RING2 */
  80         PSP_REG_LAST
  81 };
  82
  83 struct psp_funcs
  84 {
  85         int (*init_microcode)(struct psp_context *psp);
  86         int (*bootloader_load_kdb)(struct psp_context *psp);
  87         int (*bootloader_load_sysdrv)(struct psp_context *psp);
  88         int (*bootloader_load_sos)(struct psp_context *psp);
  89         int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
  90         int (*ring_create)(struct psp_context *psp,
  91                            enum psp_ring_type ring_type);
  92         int (*ring_stop)(struct psp_context *psp,
  93                             enum psp_ring_type ring_type);
  94         int (*ring_destroy)(struct psp_context *psp,
  95                             enum psp_ring_type ring_type);
  96         bool (*compare_sram_data)(struct psp_context *psp,
  97                                   struct amdgpu_firmware_info *ucode,
  98                                   enum AMDGPU_UCODE_ID ucode_type);
  99         bool (*smu_reload_quirk)(struct psp_context *psp);
 100         int (*mode1_reset)(struct psp_context *psp);
 101         int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
 102         int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
 103         int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
 104                                       struct psp_xgmi_topology_info *topology);
 105         int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
 106                                       struct psp_xgmi_topology_info *topology);
 107         bool (*support_vmr_ring)(struct psp_context *psp);
 108         int (*ras_trigger_error)(struct psp_context *psp,
 109                         struct ta_ras_trigger_error_input *info);
 110         int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
 111         int (*rlc_autoload_start)(struct psp_context *psp);
 112         int (*mem_training_init)(struct psp_context *psp);
 113         void (*mem_training_fini)(struct psp_context *psp);
 114         int (*mem_training)(struct psp_context *psp, uint32_t ops);
 115         uint32_t (*ring_get_wptr)(struct psp_context *psp);
 116         void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
 117 };
 118
 119 #define AMDGPU_XGMI_MAX_CONNECTED_NODES         64
 120 struct psp_xgmi_node_info {
 121         uint64_t                                node_id;
 122         uint8_t                                 num_hops;
 123         uint8_t                                 is_sharing_enabled;
 124         enum ta_xgmi_assigned_sdma_engine       sdma_engine;
 125 };
 126
 127 struct psp_xgmi_topology_info {
 128         uint32_t                        num_nodes;
 129         struct psp_xgmi_node_info       nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
 130 };
 131
 132 struct psp_asd_context {
 133         bool                    asd_initialized;
 134         uint32_t                session_id;
 135 };
 136
 137 struct psp_xgmi_context {
 138         uint8_t                         initialized;
 139         uint32_t                        session_id;
 140         struct amdgpu_bo                *xgmi_shared_bo;
 141         uint64_t                        xgmi_shared_mc_addr;
 142         void                            *xgmi_shared_buf;
 143         struct psp_xgmi_topology_info   top_info;
 144 };
 145
 146 struct psp_ras_context {
 147         /*ras fw*/
 148         bool                    ras_initialized;
 149         uint32_t                session_id;
 150         struct amdgpu_bo        *ras_shared_bo;
 151         uint64_t                ras_shared_mc_addr;
 152         void                    *ras_shared_buf;
 153         struct amdgpu_ras       *ras;
 154 };
 155
 156 struct psp_hdcp_context {
 157         bool                    hdcp_initialized;
 158         uint32_t                session_id;
 159         struct amdgpu_bo        *hdcp_shared_bo;
 160         uint64_t                hdcp_shared_mc_addr;
 161         void                    *hdcp_shared_buf;
 162 };
 163
 164 struct psp_dtm_context {
 165         bool                    dtm_initialized;
 166         uint32_t                session_id;
 167         struct amdgpu_bo        *dtm_shared_bo;
 168         uint64_t                dtm_shared_mc_addr;
 169         void                    *dtm_shared_buf;
 170 };
 171
 172 #define MEM_TRAIN_SYSTEM_SIGNATURE              0x54534942
 173 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES   0x1000
 174 #define GDDR6_MEM_TRAINING_OFFSET               0x8000
 175 /*Define the VRAM size that will be encroached by BIST training.*/
 176 #define GDDR6_MEM_TRAINING_ENCROACHED_SIZE      0x2000000
 177
 178 enum psp_memory_training_init_flag {
 179         PSP_MEM_TRAIN_NOT_SUPPORT       = 0x0,
 180         PSP_MEM_TRAIN_SUPPORT           = 0x1,
 181         PSP_MEM_TRAIN_INIT_FAILED       = 0x2,
 182         PSP_MEM_TRAIN_RESERVE_SUCCESS   = 0x4,
 183         PSP_MEM_TRAIN_INIT_SUCCESS      = 0x8,
 184 };
 185
 186 enum psp_memory_training_ops {
 187         PSP_MEM_TRAIN_SEND_LONG_MSG     = 0x1,
 188         PSP_MEM_TRAIN_SAVE              = 0x2,
 189         PSP_MEM_TRAIN_RESTORE           = 0x4,
 190         PSP_MEM_TRAIN_SEND_SHORT_MSG    = 0x8,
 191         PSP_MEM_TRAIN_COLD_BOOT         = PSP_MEM_TRAIN_SEND_LONG_MSG,
 192         PSP_MEM_TRAIN_RESUME            = PSP_MEM_TRAIN_SEND_SHORT_MSG,
 193 };
 194
 195 struct psp_memory_training_context {
 196         /*training data size*/
 197         u64 train_data_size;
 198         /*
 199          * sys_cache
 200          * cpu virtual address
 201          * system memory buffer that used to store the training data.
 202          */
 203         void *sys_cache;
 204
 205         /*vram offset of the p2c training data*/
 206         u64 p2c_train_data_offset;
 207
 208         /*vram offset of the c2p training data*/
 209         u64 c2p_train_data_offset;
 210         struct amdgpu_bo *c2p_bo;
 211
 212         enum psp_memory_training_init_flag init;
 213         u32 training_cnt;
 214 };
 215
 216 struct psp_context
 217 {
 218         struct amdgpu_device            *adev;
 219         struct psp_ring                 km_ring;
 220         struct psp_gfx_cmd_resp         *cmd;
 221
 222         const struct psp_funcs          *funcs;
 223
 224         /* firmware buffer */
 225         struct amdgpu_bo                *fw_pri_bo;
 226         uint64_t                        fw_pri_mc_addr;
 227         void                            *fw_pri_buf;
 228
 229         /* sos firmware */
 230         const struct firmware           *sos_fw;
 231         uint32_t                        sos_fw_version;
 232         uint32_t                        sos_feature_version;
 233         uint32_t                        sys_bin_size;
 234         uint32_t                        sos_bin_size;
 235         uint32_t                        toc_bin_size;
 236         uint32_t                        kdb_bin_size;
 237         uint8_t                         *sys_start_addr;
 238         uint8_t                         *sos_start_addr;
 239         uint8_t                         *toc_start_addr;
 240         uint8_t                         *kdb_start_addr;
 241
 242         /* tmr buffer */
 243         struct amdgpu_bo                *tmr_bo;
 244         uint64_t                        tmr_mc_addr;
 245
 246         /* asd firmware */
 247         const struct firmware           *asd_fw;
 248         uint32_t                        asd_fw_version;
 249         uint32_t                        asd_feature_version;
 250         uint32_t                        asd_ucode_size;
 251         uint8_t                         *asd_start_addr;
 252
 253         /* fence buffer */
 254         struct amdgpu_bo                *fence_buf_bo;
 255         uint64_t                        fence_buf_mc_addr;
 256         void                            *fence_buf;
 257
 258         /* cmd buffer */
 259         struct amdgpu_bo                *cmd_buf_bo;
 260         uint64_t                        cmd_buf_mc_addr;
 261         struct psp_gfx_cmd_resp         *cmd_buf_mem;
 262
 263         /* fence value associated with cmd buffer */
 264         atomic_t                        fence_value;
 265         /* flag to mark whether gfx fw autoload is supported or not */
 266         bool                            autoload_supported;
 267
 268         /* xgmi ta firmware and buffer */
 269         const struct firmware           *ta_fw;
 270         uint32_t                        ta_fw_version;
 271         uint32_t                        ta_xgmi_ucode_version;
 272         uint32_t                        ta_xgmi_ucode_size;
 273         uint8_t                         *ta_xgmi_start_addr;
 274         uint32_t                        ta_ras_ucode_version;
 275         uint32_t                        ta_ras_ucode_size;
 276         uint8_t                         *ta_ras_start_addr;
 277
 278         uint32_t                        ta_hdcp_ucode_version;
 279         uint32_t                        ta_hdcp_ucode_size;
 280         uint8_t                         *ta_hdcp_start_addr;
 281
 282         uint32_t                        ta_dtm_ucode_version;
 283         uint32_t                        ta_dtm_ucode_size;
 284         uint8_t                         *ta_dtm_start_addr;
 285
 286         struct psp_asd_context          asd_context;
 287         struct psp_xgmi_context         xgmi_context;
 288         struct psp_ras_context          ras;
 289         struct psp_hdcp_context         hdcp_context;
 290         struct psp_dtm_context          dtm_context;
 291         struct mutex                    mutex;
 292         struct psp_memory_training_context mem_train_ctx;
 293 };
 294
 295 struct amdgpu_psp_funcs {
 296         bool (*check_fw_loading_status)(struct amdgpu_device *adev,
 297                                         enum AMDGPU_UCODE_ID);
 298 };
 299
 300
 301 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
 302 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
 303 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
 304 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
 305 #define psp_compare_sram_data(psp, ucode, type) \
 306                 (psp)->funcs->compare_sram_data((psp), (ucode), (type))
 307 #define psp_init_microcode(psp) \
 308                 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
 309 #define psp_bootloader_load_kdb(psp) \
 310                 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
 311 #define psp_bootloader_load_sysdrv(psp) \
 312                 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
 313 #define psp_bootloader_load_sos(psp) \
 314                 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
 315 #define psp_smu_reload_quirk(psp) \
 316                 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
 317 #define psp_support_vmr_ring(psp) \
 318                 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
 319 #define psp_mode1_reset(psp) \
 320                 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
 321 #define psp_xgmi_get_node_id(psp, node_id) \
 322                 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
 323 #define psp_xgmi_get_hive_id(psp, hive_id) \
 324                 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
 325 #define psp_xgmi_get_topology_info(psp, num_device, topology) \
 326                 ((psp)->funcs->xgmi_get_topology_info ? \
 327                 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
 328 #define psp_xgmi_set_topology_info(psp, num_device, topology) \
 329                 ((psp)->funcs->xgmi_set_topology_info ?  \
 330                 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
 331 #define psp_rlc_autoload(psp) \
 332                 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
 333 #define psp_mem_training_init(psp) \
 334         ((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0)
 335 #define psp_mem_training_fini(psp) \
 336         ((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0)
 337 #define psp_mem_training(psp, ops) \
 338         ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
 339
 340 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
 341
 342 #define psp_ras_trigger_error(psp, info) \
 343         ((psp)->funcs->ras_trigger_error ? \
 344         (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL)
 345 #define psp_ras_cure_posion(psp, addr) \
 346         ((psp)->funcs->ras_cure_posion ? \
 347         (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
 348
 349 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
 350 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
 351
 352 extern const struct amd_ip_funcs psp_ip_funcs;
 353
 354 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
 355 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 356                         uint32_t field_val, uint32_t mask, bool check_changed);
 357
 358 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
 359 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
 360
 361 int psp_gpu_reset(struct amdgpu_device *adev);
 362 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
 363                         uint64_t cmd_gpu_addr, int cmd_size);
 364
 365 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 366
 367 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 368 int psp_ras_enable_features(struct psp_context *psp,
 369                 union ta_ras_cmd_input *info, bool enable);
 370 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 371 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
 372
 373 int psp_rlc_autoload_start(struct psp_context *psp);
 374
 375 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
 376 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 377                 uint32_t value);
 378 int psp_ring_cmd_submit(struct psp_context *psp,
 379                         uint64_t cmd_buf_mc_addr,
 380                         uint64_t fence_mc_addr,
 381                         int index);
 382 #endif