1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
6 #include <dt-bindings/clock/at91.h>
10 static const struct clk_master_characteristics mck_characteristics = {
11 .output = { .min = 0, .max = 133333333 },
12 .divisors = { 1, 2, 4, 3 },
15 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
17 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
19 static const struct clk_range plla_outputs[] = {
20 { .min = 745000000, .max = 800000000 },
21 { .min = 695000000, .max = 750000000 },
22 { .min = 645000000, .max = 700000000 },
23 { .min = 595000000, .max = 650000000 },
24 { .min = 545000000, .max = 600000000 },
25 { .min = 495000000, .max = 555000000 },
26 { .min = 445000000, .max = 500000000 },
27 { .min = 400000000, .max = 450000000 },
30 static const struct clk_pll_characteristics plla_characteristics = {
31 .input = { .min = 2000000, .max = 32000000 },
32 .num_output = ARRAY_SIZE(plla_outputs),
33 .output = plla_outputs,
42 } at91sam9g45_systemck[] = {
43 { .n = "ddrck", .p = "masterck", .id = 2 },
44 { .n = "uhpck", .p = "usbck", .id = 6 },
45 { .n = "pck0", .p = "prog0", .id = 8 },
46 { .n = "pck1", .p = "prog1", .id = 9 },
49 static const struct clk_pcr_layout at91sam9g45_pcr_layout = {
52 .pid_mask = GENMASK(5, 0),
53 .div_mask = GENMASK(17, 16),
61 static const struct pck at91sam9g45_periphck[] = {
62 { .n = "pioA_clk", .id = 2, },
63 { .n = "pioB_clk", .id = 3, },
64 { .n = "pioC_clk", .id = 4, },
65 { .n = "pioDE_clk", .id = 5, },
66 { .n = "trng_clk", .id = 6, },
67 { .n = "usart0_clk", .id = 7, },
68 { .n = "usart1_clk", .id = 8, },
69 { .n = "usart2_clk", .id = 9, },
70 { .n = "usart3_clk", .id = 10, },
71 { .n = "mci0_clk", .id = 11, },
72 { .n = "twi0_clk", .id = 12, },
73 { .n = "twi1_clk", .id = 13, },
74 { .n = "spi0_clk", .id = 14, },
75 { .n = "spi1_clk", .id = 15, },
76 { .n = "ssc0_clk", .id = 16, },
77 { .n = "ssc1_clk", .id = 17, },
78 { .n = "tcb0_clk", .id = 18, },
79 { .n = "pwm_clk", .id = 19, },
80 { .n = "adc_clk", .id = 20, },
81 { .n = "dma0_clk", .id = 21, },
82 { .n = "uhphs_clk", .id = 22, },
83 { .n = "lcd_clk", .id = 23, },
84 { .n = "ac97_clk", .id = 24, },
85 { .n = "macb0_clk", .id = 25, },
86 { .n = "isi_clk", .id = 26, },
87 { .n = "udphs_clk", .id = 27, },
88 { .n = "aestdessha_clk", .id = 28, },
89 { .n = "mci1_clk", .id = 29, },
90 { .n = "vdec_clk", .id = 30, },
93 static void __init at91sam9g45_pmc_setup(struct device_node *np)
95 const char *slck_name, *mainxtal_name;
96 struct pmc_data *at91sam9g45_pmc;
97 const char *parent_names[6];
98 struct regmap *regmap;
103 i = of_property_match_string(np, "clock-names", "slow_clk");
107 slck_name = of_clk_get_parent_name(np, i);
109 i = of_property_match_string(np, "clock-names", "main_xtal");
112 mainxtal_name = of_clk_get_parent_name(np, i);
114 regmap = device_node_to_regmap(np);
118 at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1,
119 nck(at91sam9g45_systemck),
120 nck(at91sam9g45_periphck), 0, 2);
121 if (!at91sam9g45_pmc)
124 bypass = of_property_read_bool(np, "atmel,osc-bypass");
126 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
131 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
135 at91sam9g45_pmc->chws[PMC_MAIN] = hw;
137 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
138 &at91rm9200_pll_layout, &plla_characteristics);
142 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
146 at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
148 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
152 at91sam9g45_pmc->chws[PMC_UTMI] = hw;
154 parent_names[0] = slck_name;
155 parent_names[1] = "mainck";
156 parent_names[2] = "plladivck";
157 parent_names[3] = "utmick";
158 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
159 &at91rm9200_master_layout,
160 &mck_characteristics);
164 at91sam9g45_pmc->chws[PMC_MCK] = hw;
166 parent_names[0] = "plladivck";
167 parent_names[1] = "utmick";
168 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
172 parent_names[0] = slck_name;
173 parent_names[1] = "mainck";
174 parent_names[2] = "plladivck";
175 parent_names[3] = "utmick";
176 parent_names[4] = "masterck";
177 for (i = 0; i < 2; i++) {
180 snprintf(name, sizeof(name), "prog%d", i);
182 hw = at91_clk_register_programmable(regmap, name,
184 &at91sam9g45_programmable_layout,
189 at91sam9g45_pmc->pchws[i] = hw;
192 for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
193 hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
194 at91sam9g45_systemck[i].p,
195 at91sam9g45_systemck[i].id);
199 at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw;
202 for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
203 hw = at91_clk_register_peripheral(regmap,
204 at91sam9g45_periphck[i].n,
206 at91sam9g45_periphck[i].id);
210 at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw;
213 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc);
218 kfree(at91sam9g45_pmc);
221 * The TCB is used as the clocksource so its clock is needed early. This means
222 * this can't be a platform driver.
224 CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
225 at91sam9g45_pmc_setup);