drivers/pwm/pwm-mtk-disp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * MediaTek display pulse-width-modulation controller driver.
   4  * Copyright (c) 2015 MediaTek Inc.
   5  * Author: YH Huang <[email protected]>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pwm.h>
  16 #include <linux/slab.h>
  17
  18 #define DISP_PWM_EN             0x00
  19
  20 #define PWM_CLKDIV_SHIFT        16
  21 #define PWM_CLKDIV_MAX          0x3ff
  22 #define PWM_CLKDIV_MASK         (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
  23
  24 #define PWM_PERIOD_BIT_WIDTH    12
  25 #define PWM_PERIOD_MASK         ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
  26
  27 #define PWM_HIGH_WIDTH_SHIFT    16
  28 #define PWM_HIGH_WIDTH_MASK     (0x1fff << PWM_HIGH_WIDTH_SHIFT)
  29
  30 struct mtk_pwm_data {
  31         u32 enable_mask;
  32         unsigned int con0;
  33         u32 con0_sel;
  34         unsigned int con1;
  35
  36         bool has_commit;
  37         unsigned int commit;
  38         unsigned int commit_mask;
  39
  40         unsigned int bls_debug;
  41         u32 bls_debug_mask;
  42 };
  43
  44 struct mtk_disp_pwm {
  45         struct pwm_chip chip;
  46         const struct mtk_pwm_data *data;
  47         struct clk *clk_main;
  48         struct clk *clk_mm;
  49         void __iomem *base;
  50         bool enabled;
  51 };
  52
  53 static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
  54 {
  55         return container_of(chip, struct mtk_disp_pwm, chip);
  56 }
  57
  58 static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
  59                                      u32 mask, u32 data)
  60 {
  61         void __iomem *address = mdp->base + offset;
  62         u32 value;
  63
  64         value = readl(address);
  65         value &= ~mask;
  66         value |= data;
  67         writel(value, address);
  68 }
  69
  70 static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
  71                               const struct pwm_state *state)
  72 {
  73         struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
  74         u32 clk_div, period, high_width, value;
  75         u64 div, rate;
  76         int err;
  77
  78         if (state->polarity != PWM_POLARITY_NORMAL)
  79                 return -EINVAL;
  80
  81         if (!state->enabled) {
  82                 mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
  83                                          0x0);
  84
  85                 if (mdp->enabled) {
  86                         clk_disable_unprepare(mdp->clk_mm);
  87                         clk_disable_unprepare(mdp->clk_main);
  88                 }
  89
  90                 mdp->enabled = false;
  91                 return 0;
  92         }
  93
  94         if (!mdp->enabled) {
  95                 err = clk_prepare_enable(mdp->clk_main);
  96                 if (err < 0) {
  97                         dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n",
  98                                 ERR_PTR(err));
  99                         return err;
 100                 }
 101
 102                 err = clk_prepare_enable(mdp->clk_mm);
 103                 if (err < 0) {
 104                         dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n",
 105                                 ERR_PTR(err));
 106                         clk_disable_unprepare(mdp->clk_main);
 107                         return err;
 108                 }
 109         }
 110
 111         /*
 112          * Find period, high_width and clk_div to suit duty_ns and period_ns.
 113          * Calculate proper div value to keep period value in the bound.
 114          *
 115          * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
 116          * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
 117          *
 118          * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
 119          * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
 120          */
 121         rate = clk_get_rate(mdp->clk_main);
 122         clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >>
 123                           PWM_PERIOD_BIT_WIDTH;
 124         if (clk_div > PWM_CLKDIV_MAX) {
 125                 if (!mdp->enabled) {
 126                         clk_disable_unprepare(mdp->clk_mm);
 127                         clk_disable_unprepare(mdp->clk_main);
 128                 }
 129                 return -EINVAL;
 130         }
 131
 132         div = NSEC_PER_SEC * (clk_div + 1);
 133         period = div64_u64(rate * state->period, div);
 134         if (period > 0)
 135                 period--;
 136
 137         high_width = div64_u64(rate * state->duty_cycle, div);
 138         value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
 139
 140         mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 141                                  PWM_CLKDIV_MASK,
 142                                  clk_div << PWM_CLKDIV_SHIFT);
 143         mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
 144                                  PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
 145                                  value);
 146
 147         if (mdp->data->has_commit) {
 148                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 149                                          mdp->data->commit_mask,
 150                                          mdp->data->commit_mask);
 151                 mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
 152                                          mdp->data->commit_mask,
 153                                          0x0);
 154         } else {
 155                 /*
 156                  * For MT2701, disable double buffer before writing register
 157                  * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
 158                  */
 159                 mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
 160                                          mdp->data->bls_debug_mask,
 161                                          mdp->data->bls_debug_mask);
 162                 mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
 163                                          mdp->data->con0_sel,
 164                                          mdp->data->con0_sel);
 165         }
 166
 167         mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
 168                                  mdp->data->enable_mask);
 169         mdp->enabled = true;
 170
 171         return 0;
 172 }
 173
 174 static const struct pwm_ops mtk_disp_pwm_ops = {
 175         .apply = mtk_disp_pwm_apply,
 176         .owner = THIS_MODULE,
 177 };
 178
 179 static int mtk_disp_pwm_probe(struct platform_device *pdev)
 180 {
 181         struct mtk_disp_pwm *mdp;
 182         int ret;
 183
 184         mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
 185         if (!mdp)
 186                 return -ENOMEM;
 187
 188         mdp->data = of_device_get_match_data(&pdev->dev);
 189
 190         mdp->base = devm_platform_ioremap_resource(pdev, 0);
 191         if (IS_ERR(mdp->base))
 192                 return PTR_ERR(mdp->base);
 193
 194         mdp->clk_main = devm_clk_get(&pdev->dev, "main");
 195         if (IS_ERR(mdp->clk_main))
 196                 return PTR_ERR(mdp->clk_main);
 197
 198         mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
 199         if (IS_ERR(mdp->clk_mm))
 200                 return PTR_ERR(mdp->clk_mm);
 201
 202         mdp->chip.dev = &pdev->dev;
 203         mdp->chip.ops = &mtk_disp_pwm_ops;
 204         mdp->chip.npwm = 1;
 205
 206         ret = pwmchip_add(&mdp->chip);
 207         if (ret < 0) {
 208                 dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
 209                 return ret;
 210         }
 211
 212         platform_set_drvdata(pdev, mdp);
 213
 214         return 0;
 215 }
 216
 217 static int mtk_disp_pwm_remove(struct platform_device *pdev)
 218 {
 219         struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
 220
 221         pwmchip_remove(&mdp->chip);
 222
 223         return 0;
 224 }
 225
 226 static const struct mtk_pwm_data mt2701_pwm_data = {
 227         .enable_mask = BIT(16),
 228         .con0 = 0xa8,
 229         .con0_sel = 0x2,
 230         .con1 = 0xac,
 231         .has_commit = false,
 232         .bls_debug = 0xb0,
 233         .bls_debug_mask = 0x3,
 234 };
 235
 236 static const struct mtk_pwm_data mt8173_pwm_data = {
 237         .enable_mask = BIT(0),
 238         .con0 = 0x10,
 239         .con0_sel = 0x0,
 240         .con1 = 0x14,
 241         .has_commit = true,
 242         .commit = 0x8,
 243         .commit_mask = 0x1,
 244 };
 245
 246 static const struct mtk_pwm_data mt8183_pwm_data = {
 247         .enable_mask = BIT(0),
 248         .con0 = 0x18,
 249         .con0_sel = 0x0,
 250         .con1 = 0x1c,
 251         .has_commit = false,
 252         .bls_debug = 0x80,
 253         .bls_debug_mask = 0x3,
 254 };
 255
 256 static const struct of_device_id mtk_disp_pwm_of_match[] = {
 257         { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
 258         { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
 259         { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
 260         { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
 261         { }
 262 };
 263 MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
 264
 265 static struct platform_driver mtk_disp_pwm_driver = {
 266         .driver = {
 267                 .name = "mediatek-disp-pwm",
 268                 .of_match_table = mtk_disp_pwm_of_match,
 269         },
 270         .probe = mtk_disp_pwm_probe,
 271         .remove = mtk_disp_pwm_remove,
 272 };
 273 module_platform_driver(mtk_disp_pwm_driver);
 274
 275 MODULE_AUTHOR("YH Huang <[email protected]>");
 276 MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
 277 MODULE_LICENSE("GPL v2");