drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <[email protected]>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21
  22 #include <drm/drm_of.h>
  23 #include <drm/drmP.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_edid.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/bridge/dw_hdmi.h>
  28
  29 #include "dw_hdmi.h"
  30
  31 #define HDMI_EDID_LEN           512
  32
  33 #define RGB                     0
  34 #define YCBCR444                1
  35 #define YCBCR422_16BITS         2
  36 #define YCBCR422_8BITS          3
  37 #define XVYCC444                4
  38
  39 enum hdmi_datamap {
  40         RGB444_8B = 0x01,
  41         RGB444_10B = 0x03,
  42         RGB444_12B = 0x05,
  43         RGB444_16B = 0x07,
  44         YCbCr444_8B = 0x09,
  45         YCbCr444_10B = 0x0B,
  46         YCbCr444_12B = 0x0D,
  47         YCbCr444_16B = 0x0F,
  48         YCbCr422_8B = 0x16,
  49         YCbCr422_10B = 0x14,
  50         YCbCr422_12B = 0x12,
  51 };
  52
  53 static const u16 csc_coeff_default[3][4] = {
  54         { 0x2000, 0x0000, 0x0000, 0x0000 },
  55         { 0x0000, 0x2000, 0x0000, 0x0000 },
  56         { 0x0000, 0x0000, 0x2000, 0x0000 }
  57 };
  58
  59 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  60         { 0x2000, 0x6926, 0x74fd, 0x010e },
  61         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  62         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  63 };
  64
  65 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  66         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  67         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  68         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  69 };
  70
  71 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  72         { 0x2591, 0x1322, 0x074b, 0x0000 },
  73         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  74         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  75 };
  76
  77 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  78         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  79         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  80         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  81 };
  82
  83 struct hdmi_vmode {
  84         bool mdvi;
  85         bool mhsyncpolarity;
  86         bool mvsyncpolarity;
  87         bool minterlaced;
  88         bool mdataenablepolarity;
  89
  90         unsigned int mpixelclock;
  91         unsigned int mpixelrepetitioninput;
  92         unsigned int mpixelrepetitionoutput;
  93 };
  94
  95 struct hdmi_data_info {
  96         unsigned int enc_in_format;
  97         unsigned int enc_out_format;
  98         unsigned int enc_color_depth;
  99         unsigned int colorimetry;
 100         unsigned int pix_repet_factor;
 101         unsigned int hdcp_enable;
 102         struct hdmi_vmode video_mode;
 103 };
 104
 105 struct dw_hdmi {
 106         struct drm_connector connector;
 107         struct drm_encoder *encoder;
 108         struct drm_bridge *bridge;
 109
 110         enum dw_hdmi_devtype dev_type;
 111         struct device *dev;
 112         struct clk *isfr_clk;
 113         struct clk *iahb_clk;
 114
 115         struct hdmi_data_info hdmi_data;
 116         const struct dw_hdmi_plat_data *plat_data;
 117
 118         int vic;
 119
 120         u8 edid[HDMI_EDID_LEN];
 121         bool cable_plugin;
 122
 123         bool phy_enabled;
 124         struct drm_display_mode previous_mode;
 125
 126         struct regmap *regmap;
 127         struct i2c_adapter *ddc;
 128         void __iomem *regs;
 129
 130         struct mutex audio_mutex;
 131         unsigned int sample_rate;
 132         int ratio;
 133
 134         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 135         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 136 };
 137
 138 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 139 {
 140         writel(val, hdmi->regs + (offset << 2));
 141 }
 142
 143 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 144 {
 145         return readl(hdmi->regs + (offset << 2));
 146 }
 147
 148 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 149 {
 150         writeb(val, hdmi->regs + offset);
 151 }
 152
 153 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 154 {
 155         return readb(hdmi->regs + offset);
 156 }
 157
 158 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 159 {
 160         hdmi->write(hdmi, val, offset);
 161 }
 162
 163 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 164 {
 165         return hdmi->read(hdmi, offset);
 166 }
 167
 168 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 169 {
 170         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 171
 172         val |= data & mask;
 173         hdmi_writeb(hdmi, val, reg);
 174 }
 175
 176 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 177                              u8 shift, u8 mask)
 178 {
 179         hdmi_modb(hdmi, data << shift, mask, reg);
 180 }
 181
 182 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 183                            unsigned int n)
 184 {
 185         /* Must be set/cleared first */
 186         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 187
 188         /* nshift factor = 0 */
 189         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 190
 191         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 192                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 193         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 194         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 195
 196         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 197         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 198         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 199 }
 200
 201 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 202                                    unsigned int ratio)
 203 {
 204         unsigned int n = (128 * freq) / 1000;
 205
 206         switch (freq) {
 207         case 32000:
 208                 if (pixel_clk == 25170000)
 209                         n = (ratio == 150) ? 9152 : 4576;
 210                 else if (pixel_clk == 27020000)
 211                         n = (ratio == 150) ? 8192 : 4096;
 212                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 213                         n = 11648;
 214                 else
 215                         n = 4096;
 216                 break;
 217
 218         case 44100:
 219                 if (pixel_clk == 25170000)
 220                         n = 7007;
 221                 else if (pixel_clk == 74170000)
 222                         n = 17836;
 223                 else if (pixel_clk == 148350000)
 224                         n = (ratio == 150) ? 17836 : 8918;
 225                 else
 226                         n = 6272;
 227                 break;
 228
 229         case 48000:
 230                 if (pixel_clk == 25170000)
 231                         n = (ratio == 150) ? 9152 : 6864;
 232                 else if (pixel_clk == 27020000)
 233                         n = (ratio == 150) ? 8192 : 6144;
 234                 else if (pixel_clk == 74170000)
 235                         n = 11648;
 236                 else if (pixel_clk == 148350000)
 237                         n = (ratio == 150) ? 11648 : 5824;
 238                 else
 239                         n = 6144;
 240                 break;
 241
 242         case 88200:
 243                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 244                 break;
 245
 246         case 96000:
 247                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 248                 break;
 249
 250         case 176400:
 251                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 252                 break;
 253
 254         case 192000:
 255                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 256                 break;
 257
 258         default:
 259                 break;
 260         }
 261
 262         return n;
 263 }
 264
 265 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 266                                      unsigned int ratio)
 267 {
 268         unsigned int cts = 0;
 269
 270         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 271                  pixel_clk, ratio);
 272
 273         switch (freq) {
 274         case 32000:
 275                 if (pixel_clk == 297000000) {
 276                         cts = 222750;
 277                         break;
 278                 }
 279         case 48000:
 280         case 96000:
 281         case 192000:
 282                 switch (pixel_clk) {
 283                 case 25200000:
 284                 case 27000000:
 285                 case 54000000:
 286                 case 74250000:
 287                 case 148500000:
 288                         cts = pixel_clk / 1000;
 289                         break;
 290                 case 297000000:
 291                         cts = 247500;
 292                         break;
 293                 /*
 294                  * All other TMDS clocks are not supported by
 295                  * DWC_hdmi_tx. The TMDS clocks divided or
 296                  * multiplied by 1,001 coefficients are not
 297                  * supported.
 298                  */
 299                 default:
 300                         break;
 301                 }
 302                 break;
 303         case 44100:
 304         case 88200:
 305         case 176400:
 306                 switch (pixel_clk) {
 307                 case 25200000:
 308                         cts = 28000;
 309                         break;
 310                 case 27000000:
 311                         cts = 30000;
 312                         break;
 313                 case 54000000:
 314                         cts = 60000;
 315                         break;
 316                 case 74250000:
 317                         cts = 82500;
 318                         break;
 319                 case 148500000:
 320                         cts = 165000;
 321                         break;
 322                 case 297000000:
 323                         cts = 247500;
 324                         break;
 325                 default:
 326                         break;
 327                 }
 328                 break;
 329         default:
 330                 break;
 331         }
 332         if (ratio == 100)
 333                 return cts;
 334         return (cts * ratio) / 100;
 335 }
 336
 337 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 338                                      unsigned long pixel_clk)
 339 {
 340         unsigned int clk_n, clk_cts;
 341
 342         clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
 343                                hdmi->ratio);
 344         clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
 345                                    hdmi->ratio);
 346
 347         if (!clk_cts) {
 348                 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
 349                         __func__, pixel_clk);
 350                 return;
 351         }
 352
 353         dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
 354                 __func__, hdmi->sample_rate, hdmi->ratio,
 355                 pixel_clk, clk_n, clk_cts);
 356
 357         hdmi_set_cts_n(hdmi, clk_cts, clk_n);
 358 }
 359
 360 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 361 {
 362         mutex_lock(&hdmi->audio_mutex);
 363         hdmi_set_clk_regenerator(hdmi, 74250000);
 364         mutex_unlock(&hdmi->audio_mutex);
 365 }
 366
 367 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 368 {
 369         mutex_lock(&hdmi->audio_mutex);
 370         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
 371         mutex_unlock(&hdmi->audio_mutex);
 372 }
 373
 374 /*
 375  * this submodule is responsible for the video data synchronization.
 376  * for example, for RGB 4:4:4 input, the data map is defined as
 377  *                      pin{47~40} <==> R[7:0]
 378  *                      pin{31~24} <==> G[7:0]
 379  *                      pin{15~8}  <==> B[7:0]
 380  */
 381 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 382 {
 383         int color_format = 0;
 384         u8 val;
 385
 386         if (hdmi->hdmi_data.enc_in_format == RGB) {
 387                 if (hdmi->hdmi_data.enc_color_depth == 8)
 388                         color_format = 0x01;
 389                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 390                         color_format = 0x03;
 391                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 392                         color_format = 0x05;
 393                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 394                         color_format = 0x07;
 395                 else
 396                         return;
 397         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 398                 if (hdmi->hdmi_data.enc_color_depth == 8)
 399                         color_format = 0x09;
 400                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 401                         color_format = 0x0B;
 402                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 403                         color_format = 0x0D;
 404                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 405                         color_format = 0x0F;
 406                 else
 407                         return;
 408         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 409                 if (hdmi->hdmi_data.enc_color_depth == 8)
 410                         color_format = 0x16;
 411                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 412                         color_format = 0x14;
 413                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 414                         color_format = 0x12;
 415                 else
 416                         return;
 417         }
 418
 419         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 420                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 421                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 422         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 423
 424         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 425         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 426                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 427                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 428         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 429         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 430         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 431         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 432         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 433         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 434         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 435 }
 436
 437 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 438 {
 439         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 440 }
 441
 442 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 443 {
 444         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 445                 return 0;
 446         if (hdmi->hdmi_data.enc_in_format == RGB ||
 447             hdmi->hdmi_data.enc_in_format == YCBCR444)
 448                 return 1;
 449         return 0;
 450 }
 451
 452 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 453 {
 454         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 455                 return 0;
 456         if (hdmi->hdmi_data.enc_out_format == RGB ||
 457             hdmi->hdmi_data.enc_out_format == YCBCR444)
 458                 return 1;
 459         return 0;
 460 }
 461
 462 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 463 {
 464         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 465         unsigned i;
 466         u32 csc_scale = 1;
 467
 468         if (is_color_space_conversion(hdmi)) {
 469                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 470                         if (hdmi->hdmi_data.colorimetry ==
 471                                         HDMI_COLORIMETRY_ITU_601)
 472                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 473                         else
 474                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 475                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 476                         if (hdmi->hdmi_data.colorimetry ==
 477                                         HDMI_COLORIMETRY_ITU_601)
 478                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 479                         else
 480                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 481                         csc_scale = 0;
 482                 }
 483         }
 484
 485         /* The CSC registers are sequential, alternating MSB then LSB */
 486         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 487                 u16 coeff_a = (*csc_coeff)[0][i];
 488                 u16 coeff_b = (*csc_coeff)[1][i];
 489                 u16 coeff_c = (*csc_coeff)[2][i];
 490
 491                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 492                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 493                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 494                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 495                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 496                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 497         }
 498
 499         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 500                   HDMI_CSC_SCALE);
 501 }
 502
 503 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 504 {
 505         int color_depth = 0;
 506         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 507         int decimation = 0;
 508
 509         /* YCC422 interpolation to 444 mode */
 510         if (is_color_space_interpolation(hdmi))
 511                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 512         else if (is_color_space_decimation(hdmi))
 513                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 514
 515         if (hdmi->hdmi_data.enc_color_depth == 8)
 516                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 517         else if (hdmi->hdmi_data.enc_color_depth == 10)
 518                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 519         else if (hdmi->hdmi_data.enc_color_depth == 12)
 520                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 521         else if (hdmi->hdmi_data.enc_color_depth == 16)
 522                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 523         else
 524                 return;
 525
 526         /* Configure the CSC registers */
 527         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 528         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 529                   HDMI_CSC_SCALE);
 530
 531         dw_hdmi_update_csc_coeffs(hdmi);
 532 }
 533
 534 /*
 535  * HDMI video packetizer is used to packetize the data.
 536  * for example, if input is YCC422 mode or repeater is used,
 537  * data should be repacked this module can be bypassed.
 538  */
 539 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 540 {
 541         unsigned int color_depth = 0;
 542         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 543         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 544         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 545         u8 val, vp_conf;
 546
 547         if (hdmi_data->enc_out_format == RGB ||
 548             hdmi_data->enc_out_format == YCBCR444) {
 549                 if (!hdmi_data->enc_color_depth) {
 550                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 551                 } else if (hdmi_data->enc_color_depth == 8) {
 552                         color_depth = 4;
 553                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 554                 } else if (hdmi_data->enc_color_depth == 10) {
 555                         color_depth = 5;
 556                 } else if (hdmi_data->enc_color_depth == 12) {
 557                         color_depth = 6;
 558                 } else if (hdmi_data->enc_color_depth == 16) {
 559                         color_depth = 7;
 560                 } else {
 561                         return;
 562                 }
 563         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 564                 if (!hdmi_data->enc_color_depth ||
 565                     hdmi_data->enc_color_depth == 8)
 566                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 567                 else if (hdmi_data->enc_color_depth == 10)
 568                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 569                 else if (hdmi_data->enc_color_depth == 12)
 570                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 571                 else
 572                         return;
 573                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 574         } else {
 575                 return;
 576         }
 577
 578         /* set the packetizer registers */
 579         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 580                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 581                 ((hdmi_data->pix_repet_factor <<
 582                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 583                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 584         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 585
 586         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 587                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 588
 589         /* Data from pixel repeater block */
 590         if (hdmi_data->pix_repet_factor > 1) {
 591                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 592                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 593         } else { /* data from packetizer block */
 594                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 595                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 596         }
 597
 598         hdmi_modb(hdmi, vp_conf,
 599                   HDMI_VP_CONF_PR_EN_MASK |
 600                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 601
 602         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 603                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 604
 605         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 606
 607         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 608                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 609                           HDMI_VP_CONF_PP_EN_ENABLE |
 610                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 611         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 612                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 613                           HDMI_VP_CONF_PP_EN_DISABLE |
 614                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 615         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 616                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 617                           HDMI_VP_CONF_PP_EN_DISABLE |
 618                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 619         } else {
 620                 return;
 621         }
 622
 623         hdmi_modb(hdmi, vp_conf,
 624                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 625                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 626
 627         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 628                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 629                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 630                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 631
 632         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 633                   HDMI_VP_CONF);
 634 }
 635
 636 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 637                                        unsigned char bit)
 638 {
 639         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 640                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 641 }
 642
 643 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 644                                         unsigned char bit)
 645 {
 646         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 647                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 648 }
 649
 650 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 651                                        unsigned char bit)
 652 {
 653         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 654                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 655 }
 656
 657 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 658                                      unsigned char bit)
 659 {
 660         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 661 }
 662
 663 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 664                                       unsigned char bit)
 665 {
 666         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 667 }
 668
 669 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 670 {
 671         u32 val;
 672
 673         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 674                 if (msec-- == 0)
 675                         return false;
 676                 udelay(1000);
 677         }
 678         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 679
 680         return true;
 681 }
 682
 683 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 684                                  unsigned char addr)
 685 {
 686         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 687         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 688         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 689                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 690         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 691                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 692         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 693                     HDMI_PHY_I2CM_OPERATION_ADDR);
 694         hdmi_phy_wait_i2c_done(hdmi, 1000);
 695 }
 696
 697 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 698                               unsigned char addr)
 699 {
 700         __hdmi_phy_i2c_write(hdmi, data, addr);
 701         return 0;
 702 }
 703
 704 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
 705 {
 706         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 707                          HDMI_PHY_CONF0_PDZ_OFFSET,
 708                          HDMI_PHY_CONF0_PDZ_MASK);
 709 }
 710
 711 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 712 {
 713         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 714                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 715                          HDMI_PHY_CONF0_ENTMDS_MASK);
 716 }
 717
 718 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 719 {
 720         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 721                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 722                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 723 }
 724
 725 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 726 {
 727         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 728                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 729                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 730 }
 731
 732 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 733 {
 734         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 735                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 736                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 737 }
 738
 739 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 740 {
 741         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 742                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 743                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 744 }
 745
 746 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 747 {
 748         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 749                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 750                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 751 }
 752
 753 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 754                               unsigned char res, int cscon)
 755 {
 756         unsigned res_idx, i;
 757         u8 val, msec;
 758         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 759         const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg;
 760         const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr;
 761         const struct dw_hdmi_phy_config *phy_config = plat_data->phy_config;
 762
 763         if (prep)
 764                 return -EINVAL;
 765
 766         switch (res) {
 767         case 0: /* color resolution 0 is 8 bit colour depth */
 768         case 8:
 769                 res_idx = DW_HDMI_RES_8;
 770                 break;
 771         case 10:
 772                 res_idx = DW_HDMI_RES_10;
 773                 break;
 774         case 12:
 775                 res_idx = DW_HDMI_RES_12;
 776                 break;
 777         default:
 778                 return -EINVAL;
 779         }
 780
 781         /* Enable csc path */
 782         if (cscon)
 783                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 784         else
 785                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 786
 787         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 788
 789         /* gen2 tx power off */
 790         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 791
 792         /* gen2 pddq */
 793         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 794
 795         /* PHY reset */
 796         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 797         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 798
 799         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 800
 801         hdmi_phy_test_clear(hdmi, 1);
 802         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 803                     HDMI_PHY_I2CM_SLAVE_ADDR);
 804         hdmi_phy_test_clear(hdmi, 0);
 805
 806         /* PLL/MPLL Cfg - always match on final entry */
 807         for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
 808                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 809                     mpll_config[i].mpixelclock)
 810                         break;
 811
 812         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
 813         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
 814
 815         for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
 816                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 817                     curr_ctrl[i].mpixelclock)
 818                         break;
 819
 820         if (curr_ctrl[i].mpixelclock == (~0UL)) {
 821                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 822                         hdmi->hdmi_data.video_mode.mpixelclock);
 823                 return -EINVAL;
 824         }
 825
 826         /* CURRCTRL */
 827         hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
 828
 829         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 830         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 831
 832         for (i = 0; phy_config[i].mpixelclock != (~0UL); i++)
 833                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 834                     phy_config[i].mpixelclock)
 835                         break;
 836
 837         /* RESISTANCE TERM 133Ohm Cfg */
 838         hdmi_phy_i2c_write(hdmi, phy_config[i].term, 0x19);  /* TXTERM */
 839         /* PREEMP Cgf 0.00 */
 840         hdmi_phy_i2c_write(hdmi, phy_config[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
 841         /* TX/CK LVL 10 */
 842         hdmi_phy_i2c_write(hdmi, phy_config[i].vlev_ctr, 0x0E); /* VLEVCTRL */
 843
 844         /* REMOVE CLK TERM */
 845         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 846
 847         dw_hdmi_phy_enable_power(hdmi, 1);
 848
 849         /* toggle TMDS enable */
 850         dw_hdmi_phy_enable_tmds(hdmi, 0);
 851         dw_hdmi_phy_enable_tmds(hdmi, 1);
 852
 853         /* gen2 tx power on */
 854         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 855         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 856
 857         if (hdmi->dev_type == RK3288_HDMI)
 858                 dw_hdmi_phy_enable_spare(hdmi, 1);
 859
 860         /*Wait for PHY PLL lock */
 861         msec = 5;
 862         do {
 863                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 864                 if (!val)
 865                         break;
 866
 867                 if (msec == 0) {
 868                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 869                         return -ETIMEDOUT;
 870                 }
 871
 872                 udelay(1000);
 873                 msec--;
 874         } while (1);
 875
 876         return 0;
 877 }
 878
 879 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 880 {
 881         int i, ret;
 882         bool cscon = false;
 883
 884         /*check csc whether needed activated in HDMI mode */
 885         cscon = (is_color_space_conversion(hdmi) &&
 886                         !hdmi->hdmi_data.video_mode.mdvi);
 887
 888         /* HDMI Phy spec says to do the phy initialization sequence twice */
 889         for (i = 0; i < 2; i++) {
 890                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 891                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 892                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 893                 dw_hdmi_phy_enable_power(hdmi, 0);
 894
 895                 /* Enable CSC */
 896                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 897                 if (ret)
 898                         return ret;
 899         }
 900
 901         hdmi->phy_enabled = true;
 902         return 0;
 903 }
 904
 905 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 906 {
 907         u8 de;
 908
 909         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 910                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 911         else
 912                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 913
 914         /* disable rx detect */
 915         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 916                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 917
 918         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 919
 920         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 921                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 922 }
 923
 924 static void hdmi_config_AVI(struct dw_hdmi *hdmi)
 925 {
 926         u8 val, pix_fmt, under_scan;
 927         u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
 928         bool aspect_16_9;
 929
 930         aspect_16_9 = false; /* FIXME */
 931
 932         /* AVI Data Byte 1 */
 933         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 934                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
 935         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 936                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
 937         else
 938                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
 939
 940                 under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
 941
 942         /*
 943          * Active format identification data is present in the AVI InfoFrame.
 944          * Under scan info, no bar data
 945          */
 946         val = pix_fmt | under_scan |
 947                 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
 948                 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
 949
 950         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 951
 952         /* AVI Data Byte 2 -Set the Aspect Ratio */
 953         if (aspect_16_9) {
 954                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
 955                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
 956         } else {
 957                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
 958                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
 959         }
 960
 961         /* Set up colorimetry */
 962         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 963                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
 964                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 965                         ext_colorimetry =
 966                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 967                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 968                         ext_colorimetry =
 969                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
 970         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 971                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 972                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
 973                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 974                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
 975                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 976         } else { /* Carries no data */
 977                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
 978                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 979         }
 980
 981         val = colorimetry | coded_ratio | act_ratio;
 982         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
 983
 984         /* AVI Data Byte 3 */
 985         val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
 986                 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
 987                 HDMI_FC_AVICONF2_SCALING_NONE;
 988         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
 989
 990         /* AVI Data Byte 4 */
 991         hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
 992
 993         /* AVI Data Byte 5- set up input and output pixel repetition */
 994         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
 995                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
 996                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
 997                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
 998                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
 999                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1000         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1001
1002         /* IT Content and quantization range = don't care */
1003         val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1004                 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1005         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1006
1007         /* AVI Data Bytes 6-13 */
1008         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1009         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1010         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1011         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1012         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1013         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1014         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1015         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1016 }
1017
1018 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1019                              const struct drm_display_mode *mode)
1020 {
1021         u8 inv_val;
1022         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1023         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1024
1025         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1026         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1027         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1028         vmode->mpixelclock = mode->clock * 1000;
1029
1030         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1031
1032         /* Set up HDMI_FC_INVIDCONF */
1033         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1034                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1035                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1036
1037         inv_val |= (vmode->mvsyncpolarity ?
1038                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1039                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1040
1041         inv_val |= (vmode->mhsyncpolarity ?
1042                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1043                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1044
1045         inv_val |= (vmode->mdataenablepolarity ?
1046                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1047                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1048
1049         if (hdmi->vic == 39)
1050                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1051         else
1052                 inv_val |= (vmode->minterlaced ?
1053                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1054                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1055
1056         inv_val |= (vmode->minterlaced ?
1057                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1058                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1059
1060         inv_val |= (vmode->mdvi ?
1061                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1062                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1063
1064         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1065
1066         /* Set up horizontal active pixel width */
1067         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1068         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1069
1070         /* Set up vertical active lines */
1071         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1072         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1073
1074         /* Set up horizontal blanking pixel region width */
1075         hblank = mode->htotal - mode->hdisplay;
1076         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1077         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1078
1079         /* Set up vertical blanking pixel region width */
1080         vblank = mode->vtotal - mode->vdisplay;
1081         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1082
1083         /* Set up HSYNC active edge delay width (in pixel clks) */
1084         h_de_hs = mode->hsync_start - mode->hdisplay;
1085         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1086         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1087
1088         /* Set up VSYNC active edge delay (in lines) */
1089         v_de_vs = mode->vsync_start - mode->vdisplay;
1090         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1091
1092         /* Set up HSYNC active pulse width (in pixel clks) */
1093         hsync_len = mode->hsync_end - mode->hsync_start;
1094         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1095         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1096
1097         /* Set up VSYNC active edge delay (in lines) */
1098         vsync_len = mode->vsync_end - mode->vsync_start;
1099         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1100 }
1101
1102 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1103 {
1104         if (!hdmi->phy_enabled)
1105                 return;
1106
1107         dw_hdmi_phy_enable_tmds(hdmi, 0);
1108         dw_hdmi_phy_enable_power(hdmi, 0);
1109
1110         hdmi->phy_enabled = false;
1111 }
1112
1113 /* HDMI Initialization Step B.4 */
1114 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1115 {
1116         u8 clkdis;
1117
1118         /* control period minimum duration */
1119         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1120         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1121         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1122
1123         /* Set to fill TMDS data channels */
1124         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1125         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1126         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1127
1128         /* Enable pixel clock and tmds data path */
1129         clkdis = 0x7F;
1130         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1131         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1132
1133         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1134         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1135
1136         /* Enable csc path */
1137         if (is_color_space_conversion(hdmi)) {
1138                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1139                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1140         }
1141 }
1142
1143 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1144 {
1145         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1146 }
1147
1148 /* Workaround to clear the overflow condition */
1149 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1150 {
1151         int count;
1152         u8 val;
1153
1154         /* TMDS software reset */
1155         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1156
1157         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1158         if (hdmi->dev_type == IMX6DL_HDMI) {
1159                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1160                 return;
1161         }
1162
1163         for (count = 0; count < 4; count++)
1164                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1165 }
1166
1167 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1168 {
1169         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1170         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1171 }
1172
1173 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1174 {
1175         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1176                     HDMI_IH_MUTE_FC_STAT2);
1177 }
1178
1179 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1180 {
1181         int ret;
1182
1183         hdmi_disable_overflow_interrupts(hdmi);
1184
1185         hdmi->vic = drm_match_cea_mode(mode);
1186
1187         if (!hdmi->vic) {
1188                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1189                 hdmi->hdmi_data.video_mode.mdvi = true;
1190         } else {
1191                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1192                 hdmi->hdmi_data.video_mode.mdvi = false;
1193         }
1194
1195         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1196             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1197             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1198             (hdmi->vic == 17) || (hdmi->vic == 18))
1199                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1200         else
1201                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1202
1203         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1204             (hdmi->vic == 12) || (hdmi->vic == 13) ||
1205             (hdmi->vic == 14) || (hdmi->vic == 15) ||
1206             (hdmi->vic == 25) || (hdmi->vic == 26) ||
1207             (hdmi->vic == 27) || (hdmi->vic == 28) ||
1208             (hdmi->vic == 29) || (hdmi->vic == 30) ||
1209             (hdmi->vic == 35) || (hdmi->vic == 36) ||
1210             (hdmi->vic == 37) || (hdmi->vic == 38))
1211                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1212         else
1213                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1214
1215         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1216
1217         /* TODO: Get input format from IPU (via FB driver interface) */
1218         hdmi->hdmi_data.enc_in_format = RGB;
1219
1220         hdmi->hdmi_data.enc_out_format = RGB;
1221
1222         hdmi->hdmi_data.enc_color_depth = 8;
1223         hdmi->hdmi_data.pix_repet_factor = 0;
1224         hdmi->hdmi_data.hdcp_enable = 0;
1225         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1226
1227         /* HDMI Initialization Step B.1 */
1228         hdmi_av_composer(hdmi, mode);
1229
1230         /* HDMI Initializateion Step B.2 */
1231         ret = dw_hdmi_phy_init(hdmi);
1232         if (ret)
1233                 return ret;
1234
1235         /* HDMI Initialization Step B.3 */
1236         dw_hdmi_enable_video_path(hdmi);
1237
1238         /* not for DVI mode */
1239         if (hdmi->hdmi_data.video_mode.mdvi) {
1240                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1241         } else {
1242                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1243
1244                 /* HDMI Initialization Step E - Configure audio */
1245                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1246                 hdmi_enable_audio_clk(hdmi);
1247
1248                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1249                 hdmi_config_AVI(hdmi);
1250         }
1251
1252         hdmi_video_packetize(hdmi);
1253         hdmi_video_csc(hdmi);
1254         hdmi_video_sample(hdmi);
1255         hdmi_tx_hdcp_config(hdmi);
1256
1257         dw_hdmi_clear_overflow(hdmi);
1258         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1259                 hdmi_enable_overflow_interrupts(hdmi);
1260
1261         return 0;
1262 }
1263
1264 /* Wait until we are registered to enable interrupts */
1265 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1266 {
1267         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1268                     HDMI_PHY_I2CM_INT_ADDR);
1269
1270         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1271                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1272                     HDMI_PHY_I2CM_CTLINT_ADDR);
1273
1274         /* enable cable hot plug irq */
1275         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1276
1277         /* Clear Hotplug interrupts */
1278         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1279
1280         return 0;
1281 }
1282
1283 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1284 {
1285         u8 ih_mute;
1286
1287         /*
1288          * Boot up defaults are:
1289          * HDMI_IH_MUTE   = 0x03 (disabled)
1290          * HDMI_IH_MUTE_* = 0x00 (enabled)
1291          *
1292          * Disable top level interrupt bits in HDMI block
1293          */
1294         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1295                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1296                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1297
1298         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1299
1300         /* by default mask all interrupts */
1301         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1302         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1303         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1304         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1305         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1306         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1307         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1308         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1309         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1310         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1311         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1312         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1313         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1314         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1315         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1316
1317         /* Disable interrupts in the IH_MUTE_* registers */
1318         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1319         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1320         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1321         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1322         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1323         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1324         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1325         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1326         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1327         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1328
1329         /* Enable top level interrupt bits in HDMI block */
1330         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1331                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1332         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1333 }
1334
1335 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1336 {
1337         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1338 }
1339
1340 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1341 {
1342         dw_hdmi_phy_disable(hdmi);
1343 }
1344
1345 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1346                                     struct drm_display_mode *orig_mode,
1347                                     struct drm_display_mode *mode)
1348 {
1349         struct dw_hdmi *hdmi = bridge->driver_private;
1350
1351         dw_hdmi_setup(hdmi, mode);
1352
1353         /* Store the display mode for plugin/DKMS poweron events */
1354         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1355 }
1356
1357 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1358                                       const struct drm_display_mode *mode,
1359                                       struct drm_display_mode *adjusted_mode)
1360 {
1361         return true;
1362 }
1363
1364 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1365 {
1366         struct dw_hdmi *hdmi = bridge->driver_private;
1367
1368         dw_hdmi_poweroff(hdmi);
1369 }
1370
1371 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1372 {
1373         struct dw_hdmi *hdmi = bridge->driver_private;
1374
1375         dw_hdmi_poweron(hdmi);
1376 }
1377
1378 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1379 {
1380         /* do nothing */
1381 }
1382
1383 static enum drm_connector_status
1384 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1385 {
1386         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1387                                              connector);
1388
1389         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1390                 connector_status_connected : connector_status_disconnected;
1391 }
1392
1393 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1394 {
1395         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1396                                              connector);
1397         struct edid *edid;
1398         int ret = 0;
1399
1400         if (!hdmi->ddc)
1401                 return 0;
1402
1403         edid = drm_get_edid(connector, hdmi->ddc);
1404         if (edid) {
1405                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1406                         edid->width_cm, edid->height_cm);
1407
1408                 drm_mode_connector_update_edid_property(connector, edid);
1409                 ret = drm_add_edid_modes(connector, edid);
1410                 kfree(edid);
1411         } else {
1412                 dev_dbg(hdmi->dev, "failed to get edid\n");
1413         }
1414
1415         return ret;
1416 }
1417
1418 static enum drm_mode_status
1419 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1420                              struct drm_display_mode *mode)
1421 {
1422         struct dw_hdmi *hdmi = container_of(connector,
1423                                            struct dw_hdmi, connector);
1424         enum drm_mode_status mode_status = MODE_OK;
1425
1426         if (hdmi->plat_data->mode_valid)
1427                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1428
1429         return mode_status;
1430 }
1431
1432 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1433                                                            *connector)
1434 {
1435         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1436                                              connector);
1437
1438         return hdmi->encoder;
1439 }
1440
1441 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1442 {
1443         drm_connector_unregister(connector);
1444         drm_connector_cleanup(connector);
1445 }
1446
1447 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1448         .dpms = drm_helper_connector_dpms,
1449         .fill_modes = drm_helper_probe_single_connector_modes,
1450         .detect = dw_hdmi_connector_detect,
1451         .destroy = dw_hdmi_connector_destroy,
1452 };
1453
1454 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1455         .get_modes = dw_hdmi_connector_get_modes,
1456         .mode_valid = dw_hdmi_connector_mode_valid,
1457         .best_encoder = dw_hdmi_connector_best_encoder,
1458 };
1459
1460 static struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1461         .enable = dw_hdmi_bridge_enable,
1462         .disable = dw_hdmi_bridge_disable,
1463         .pre_enable = dw_hdmi_bridge_nop,
1464         .post_disable = dw_hdmi_bridge_nop,
1465         .mode_set = dw_hdmi_bridge_mode_set,
1466         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1467 };
1468
1469 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1470 {
1471         struct dw_hdmi *hdmi = dev_id;
1472         u8 intr_stat;
1473
1474         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1475         if (intr_stat)
1476                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1477
1478         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1479 }
1480
1481 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1482 {
1483         struct dw_hdmi *hdmi = dev_id;
1484         u8 intr_stat;
1485         u8 phy_int_pol;
1486
1487         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1488
1489         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1490
1491         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1492                 if (phy_int_pol & HDMI_PHY_HPD) {
1493                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1494
1495                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1496
1497                         dw_hdmi_poweron(hdmi);
1498                 } else {
1499                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1500
1501                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1502                                   HDMI_PHY_POL0);
1503
1504                         dw_hdmi_poweroff(hdmi);
1505                 }
1506                 drm_helper_hpd_irq_event(hdmi->connector.dev);
1507         }
1508
1509         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1510         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1511
1512         return IRQ_HANDLED;
1513 }
1514
1515 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1516 {
1517         struct drm_encoder *encoder = hdmi->encoder;
1518         struct drm_bridge *bridge;
1519         int ret;
1520
1521         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1522         if (!bridge) {
1523                 DRM_ERROR("Failed to allocate drm bridge\n");
1524                 return -ENOMEM;
1525         }
1526
1527         hdmi->bridge = bridge;
1528         bridge->driver_private = hdmi;
1529         bridge->funcs = &dw_hdmi_bridge_funcs;
1530         ret = drm_bridge_attach(drm, bridge);
1531         if (ret) {
1532                 DRM_ERROR("Failed to initialize bridge with drm\n");
1533                 return -EINVAL;
1534         }
1535
1536         encoder->bridge = bridge;
1537         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1538
1539         drm_connector_helper_add(&hdmi->connector,
1540                                  &dw_hdmi_connector_helper_funcs);
1541         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1542                            DRM_MODE_CONNECTOR_HDMIA);
1543
1544         hdmi->connector.encoder = encoder;
1545
1546         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1547
1548         return 0;
1549 }
1550
1551 int dw_hdmi_bind(struct device *dev, struct device *master,
1552                  void *data, struct drm_encoder *encoder,
1553                  struct resource *iores, int irq,
1554                  const struct dw_hdmi_plat_data *plat_data)
1555 {
1556         struct drm_device *drm = data;
1557         struct device_node *np = dev->of_node;
1558         struct device_node *ddc_node;
1559         struct dw_hdmi *hdmi;
1560         int ret;
1561         u32 val = 1;
1562
1563         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1564         if (!hdmi)
1565                 return -ENOMEM;
1566
1567         hdmi->plat_data = plat_data;
1568         hdmi->dev = dev;
1569         hdmi->dev_type = plat_data->dev_type;
1570         hdmi->sample_rate = 48000;
1571         hdmi->ratio = 100;
1572         hdmi->encoder = encoder;
1573
1574         mutex_init(&hdmi->audio_mutex);
1575
1576         of_property_read_u32(np, "reg-io-width", &val);
1577
1578         switch (val) {
1579         case 4:
1580                 hdmi->write = dw_hdmi_writel;
1581                 hdmi->read = dw_hdmi_readl;
1582                 break;
1583         case 1:
1584                 hdmi->write = dw_hdmi_writeb;
1585                 hdmi->read = dw_hdmi_readb;
1586                 break;
1587         default:
1588                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1589                 return -EINVAL;
1590         }
1591
1592         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1593         if (ddc_node) {
1594                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1595                 of_node_put(ddc_node);
1596                 if (!hdmi->ddc) {
1597                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1598                         return -EPROBE_DEFER;
1599                 }
1600
1601         } else {
1602                 dev_dbg(hdmi->dev, "no ddc property found\n");
1603         }
1604
1605         hdmi->regs = devm_ioremap_resource(dev, iores);
1606         if (IS_ERR(hdmi->regs))
1607                 return PTR_ERR(hdmi->regs);
1608
1609         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1610         if (IS_ERR(hdmi->isfr_clk)) {
1611                 ret = PTR_ERR(hdmi->isfr_clk);
1612                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1613                 return ret;
1614         }
1615
1616         ret = clk_prepare_enable(hdmi->isfr_clk);
1617         if (ret) {
1618                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1619                 return ret;
1620         }
1621
1622         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1623         if (IS_ERR(hdmi->iahb_clk)) {
1624                 ret = PTR_ERR(hdmi->iahb_clk);
1625                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1626                 goto err_isfr;
1627         }
1628
1629         ret = clk_prepare_enable(hdmi->iahb_clk);
1630         if (ret) {
1631                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1632                 goto err_isfr;
1633         }
1634
1635         /* Product and revision IDs */
1636         dev_info(dev,
1637                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1638                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1639                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1640                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1641                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1642
1643         initialize_hdmi_ih_mutes(hdmi);
1644
1645         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1646                                         dw_hdmi_irq, IRQF_SHARED,
1647                                         dev_name(dev), hdmi);
1648         if (ret)
1649                 goto err_iahb;
1650
1651         /*
1652          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1653          * N and cts values before enabling phy
1654          */
1655         hdmi_init_clk_regenerator(hdmi);
1656
1657         /*
1658          * Configure registers related to HDMI interrupt
1659          * generation before registering IRQ.
1660          */
1661         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1662
1663         /* Clear Hotplug interrupts */
1664         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1665
1666         ret = dw_hdmi_fb_registered(hdmi);
1667         if (ret)
1668                 goto err_iahb;
1669
1670         ret = dw_hdmi_register(drm, hdmi);
1671         if (ret)
1672                 goto err_iahb;
1673
1674         /* Unmute interrupts */
1675         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1676
1677         dev_set_drvdata(dev, hdmi);
1678
1679         return 0;
1680
1681 err_iahb:
1682         clk_disable_unprepare(hdmi->iahb_clk);
1683 err_isfr:
1684         clk_disable_unprepare(hdmi->isfr_clk);
1685
1686         return ret;
1687 }
1688 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1689
1690 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1691 {
1692         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1693
1694         /* Disable all interrupts */
1695         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1696
1697         hdmi->connector.funcs->destroy(&hdmi->connector);
1698         hdmi->encoder->funcs->destroy(hdmi->encoder);
1699
1700         clk_disable_unprepare(hdmi->iahb_clk);
1701         clk_disable_unprepare(hdmi->isfr_clk);
1702         i2c_put_adapter(hdmi->ddc);
1703 }
1704 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1705
1706 MODULE_AUTHOR("Sascha Hauer <[email protected]>");
1707 MODULE_AUTHOR("Andy Yan <[email protected]>");
1708 MODULE_AUTHOR("Yakir Yang <[email protected]>");
1709 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1710 MODULE_LICENSE("GPL");
1711 MODULE_ALIAS("platform:dw-hdmi");