drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include <drm/drm_syncobj.h>
  31 #include "amdgpu.h"
  32 #include "amdgpu_trace.h"
  33
  34 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  35                                       struct drm_amdgpu_cs_chunk_fence *data,
  36                                       uint32_t *offset)
  37 {
  38         struct drm_gem_object *gobj;
  39         unsigned long size;
  40
  41         gobj = drm_gem_object_lookup(p->filp, data->handle);
  42         if (gobj == NULL)
  43                 return -EINVAL;
  44
  45         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  46         p->uf_entry.priority = 0;
  47         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
  48         p->uf_entry.tv.shared = true;
  49         p->uf_entry.user_pages = NULL;
  50
  51         size = amdgpu_bo_size(p->uf_entry.robj);
  52         if (size != PAGE_SIZE || (data->offset + 8) > size)
  53                 return -EINVAL;
  54
  55         *offset = data->offset;
  56
  57         drm_gem_object_put_unlocked(gobj);
  58
  59         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
  60                 amdgpu_bo_unref(&p->uf_entry.robj);
  61                 return -EINVAL;
  62         }
  63
  64         return 0;
  65 }
  66
  67 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
  68 {
  69         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
  70         struct amdgpu_vm *vm = &fpriv->vm;
  71         union drm_amdgpu_cs *cs = data;
  72         uint64_t *chunk_array_user;
  73         uint64_t *chunk_array;
  74         unsigned size, num_ibs = 0;
  75         uint32_t uf_offset = 0;
  76         int i;
  77         int ret;
  78
  79         if (cs->in.num_chunks == 0)
  80                 return 0;
  81
  82         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
  83         if (!chunk_array)
  84                 return -ENOMEM;
  85
  86         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
  87         if (!p->ctx) {
  88                 ret = -EINVAL;
  89                 goto free_chunk;
  90         }
  91
  92         /* get chunks */
  93         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
  94         if (copy_from_user(chunk_array, chunk_array_user,
  95                            sizeof(uint64_t)*cs->in.num_chunks)) {
  96                 ret = -EFAULT;
  97                 goto put_ctx;
  98         }
  99
 100         p->nchunks = cs->in.num_chunks;
 101         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 102                             GFP_KERNEL);
 103         if (!p->chunks) {
 104                 ret = -ENOMEM;
 105                 goto put_ctx;
 106         }
 107
 108         for (i = 0; i < p->nchunks; i++) {
 109                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 110                 struct drm_amdgpu_cs_chunk user_chunk;
 111                 uint32_t __user *cdata;
 112
 113                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 114                 if (copy_from_user(&user_chunk, chunk_ptr,
 115                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 116                         ret = -EFAULT;
 117                         i--;
 118                         goto free_partial_kdata;
 119                 }
 120                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 121                 p->chunks[i].length_dw = user_chunk.length_dw;
 122
 123                 size = p->chunks[i].length_dw;
 124                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 125
 126                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 127                 if (p->chunks[i].kdata == NULL) {
 128                         ret = -ENOMEM;
 129                         i--;
 130                         goto free_partial_kdata;
 131                 }
 132                 size *= sizeof(uint32_t);
 133                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 134                         ret = -EFAULT;
 135                         goto free_partial_kdata;
 136                 }
 137
 138                 switch (p->chunks[i].chunk_id) {
 139                 case AMDGPU_CHUNK_ID_IB:
 140                         ++num_ibs;
 141                         break;
 142
 143                 case AMDGPU_CHUNK_ID_FENCE:
 144                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 145                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 146                                 ret = -EINVAL;
 147                                 goto free_partial_kdata;
 148                         }
 149
 150                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 151                                                          &uf_offset);
 152                         if (ret)
 153                                 goto free_partial_kdata;
 154
 155                         break;
 156
 157                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 158                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 159                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 160                         break;
 161
 162                 default:
 163                         ret = -EINVAL;
 164                         goto free_partial_kdata;
 165                 }
 166         }
 167
 168         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 169         if (ret)
 170                 goto free_all_kdata;
 171
 172         if (p->uf_entry.robj)
 173                 p->job->uf_addr = uf_offset;
 174         kfree(chunk_array);
 175         return 0;
 176
 177 free_all_kdata:
 178         i = p->nchunks - 1;
 179 free_partial_kdata:
 180         for (; i >= 0; i--)
 181                 kvfree(p->chunks[i].kdata);
 182         kfree(p->chunks);
 183         p->chunks = NULL;
 184         p->nchunks = 0;
 185 put_ctx:
 186         amdgpu_ctx_put(p->ctx);
 187 free_chunk:
 188         kfree(chunk_array);
 189
 190         return ret;
 191 }
 192
 193 /* Convert microseconds to bytes. */
 194 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 195 {
 196         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 197                 return 0;
 198
 199         /* Since accum_us is incremented by a million per second, just
 200          * multiply it by the number of MB/s to get the number of bytes.
 201          */
 202         return us << adev->mm_stats.log2_max_MBps;
 203 }
 204
 205 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 206 {
 207         if (!adev->mm_stats.log2_max_MBps)
 208                 return 0;
 209
 210         return bytes >> adev->mm_stats.log2_max_MBps;
 211 }
 212
 213 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 214  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 215  * which means it can go over the threshold once. If that happens, the driver
 216  * will be in debt and no other buffer migrations can be done until that debt
 217  * is repaid.
 218  *
 219  * This approach allows moving a buffer of any size (it's important to allow
 220  * that).
 221  *
 222  * The currency is simply time in microseconds and it increases as the clock
 223  * ticks. The accumulated microseconds (us) are converted to bytes and
 224  * returned.
 225  */
 226 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 227                                               u64 *max_bytes,
 228                                               u64 *max_vis_bytes)
 229 {
 230         s64 time_us, increment_us;
 231         u64 free_vram, total_vram, used_vram;
 232
 233         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 234          * throttling.
 235          *
 236          * It means that in order to get full max MBps, at least 5 IBs per
 237          * second must be submitted and not more than 200ms apart from each
 238          * other.
 239          */
 240         const s64 us_upper_bound = 200000;
 241
 242         if (!adev->mm_stats.log2_max_MBps) {
 243                 *max_bytes = 0;
 244                 *max_vis_bytes = 0;
 245                 return;
 246         }
 247
 248         total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
 249         used_vram = atomic64_read(&adev->vram_usage);
 250         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 251
 252         spin_lock(&adev->mm_stats.lock);
 253
 254         /* Increase the amount of accumulated us. */
 255         time_us = ktime_to_us(ktime_get());
 256         increment_us = time_us - adev->mm_stats.last_update_us;
 257         adev->mm_stats.last_update_us = time_us;
 258         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 259                                       us_upper_bound);
 260
 261         /* This prevents the short period of low performance when the VRAM
 262          * usage is low and the driver is in debt or doesn't have enough
 263          * accumulated us to fill VRAM quickly.
 264          *
 265          * The situation can occur in these cases:
 266          * - a lot of VRAM is freed by userspace
 267          * - the presence of a big buffer causes a lot of evictions
 268          *   (solution: split buffers into smaller ones)
 269          *
 270          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 271          * accum_us to a positive number.
 272          */
 273         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 274                 s64 min_us;
 275
 276                 /* Be more aggresive on dGPUs. Try to fill a portion of free
 277                  * VRAM now.
 278                  */
 279                 if (!(adev->flags & AMD_IS_APU))
 280                         min_us = bytes_to_us(adev, free_vram / 4);
 281                 else
 282                         min_us = 0; /* Reset accum_us on APUs. */
 283
 284                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 285         }
 286
 287         /* This is set to 0 if the driver is in debt to disallow (optional)
 288          * buffer moves.
 289          */
 290         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 291
 292         /* Do the same for visible VRAM if half of it is free */
 293         if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 294                 u64 total_vis_vram = adev->mc.visible_vram_size;
 295                 u64 used_vis_vram = atomic64_read(&adev->vram_vis_usage);
 296
 297                 if (used_vis_vram < total_vis_vram) {
 298                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 299                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 300                                                           increment_us, us_upper_bound);
 301
 302                         if (free_vis_vram >= total_vis_vram / 2)
 303                                 adev->mm_stats.accum_us_vis =
 304                                         max(bytes_to_us(adev, free_vis_vram / 2),
 305                                             adev->mm_stats.accum_us_vis);
 306                 }
 307
 308                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 309         } else {
 310                 *max_vis_bytes = 0;
 311         }
 312
 313         spin_unlock(&adev->mm_stats.lock);
 314 }
 315
 316 /* Report how many bytes have really been moved for the last command
 317  * submission. This can result in a debt that can stop buffer migrations
 318  * temporarily.
 319  */
 320 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 321                                   u64 num_vis_bytes)
 322 {
 323         spin_lock(&adev->mm_stats.lock);
 324         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 325         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 326         spin_unlock(&adev->mm_stats.lock);
 327 }
 328
 329 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 330                                  struct amdgpu_bo *bo)
 331 {
 332         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 333         u64 initial_bytes_moved, bytes_moved;
 334         uint32_t domain;
 335         int r;
 336
 337         if (bo->pin_count)
 338                 return 0;
 339
 340         /* Don't move this buffer if we have depleted our allowance
 341          * to move it. Don't move anything if the threshold is zero.
 342          */
 343         if (p->bytes_moved < p->bytes_moved_threshold) {
 344                 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 345                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 346                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 347                          * visible VRAM if we've depleted our allowance to do
 348                          * that.
 349                          */
 350                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 351                                 domain = bo->preferred_domains;
 352                         else
 353                                 domain = bo->allowed_domains;
 354                 } else {
 355                         domain = bo->preferred_domains;
 356                 }
 357         } else {
 358                 domain = bo->allowed_domains;
 359         }
 360
 361 retry:
 362         amdgpu_ttm_placement_from_domain(bo, domain);
 363         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 364         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 365         bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 366                       initial_bytes_moved;
 367         p->bytes_moved += bytes_moved;
 368         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 369             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 370             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 371                 p->bytes_moved_vis += bytes_moved;
 372
 373         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 374                 domain = bo->allowed_domains;
 375                 goto retry;
 376         }
 377
 378         return r;
 379 }
 380
 381 /* Last resort, try to evict something from the current working set */
 382 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 383                                 struct amdgpu_bo *validated)
 384 {
 385         uint32_t domain = validated->allowed_domains;
 386         int r;
 387
 388         if (!p->evictable)
 389                 return false;
 390
 391         for (;&p->evictable->tv.head != &p->validated;
 392              p->evictable = list_prev_entry(p->evictable, tv.head)) {
 393
 394                 struct amdgpu_bo_list_entry *candidate = p->evictable;
 395                 struct amdgpu_bo *bo = candidate->robj;
 396                 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 397                 u64 initial_bytes_moved, bytes_moved;
 398                 bool update_bytes_moved_vis;
 399                 uint32_t other;
 400
 401                 /* If we reached our current BO we can forget it */
 402                 if (candidate->robj == validated)
 403                         break;
 404
 405                 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 406
 407                 /* Check if this BO is in one of the domains we need space for */
 408                 if (!(other & domain))
 409                         continue;
 410
 411                 /* Check if we can move this BO somewhere else */
 412                 other = bo->allowed_domains & ~domain;
 413                 if (!other)
 414                         continue;
 415
 416                 /* Good we can try to move this BO somewhere else */
 417                 amdgpu_ttm_placement_from_domain(bo, other);
 418                 update_bytes_moved_vis =
 419                         adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 420                         bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 421                         bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;
 422                 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 423                 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 424                 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
 425                         initial_bytes_moved;
 426                 p->bytes_moved += bytes_moved;
 427                 if (update_bytes_moved_vis)
 428                         p->bytes_moved_vis += bytes_moved;
 429
 430                 if (unlikely(r))
 431                         break;
 432
 433                 p->evictable = list_prev_entry(p->evictable, tv.head);
 434                 list_move(&candidate->tv.head, &p->validated);
 435
 436                 return true;
 437         }
 438
 439         return false;
 440 }
 441
 442 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
 443 {
 444         struct amdgpu_cs_parser *p = param;
 445         int r;
 446
 447         do {
 448                 r = amdgpu_cs_bo_validate(p, bo);
 449         } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
 450         if (r)
 451                 return r;
 452
 453         if (bo->shadow)
 454                 r = amdgpu_cs_bo_validate(p, bo->shadow);
 455
 456         return r;
 457 }
 458
 459 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 460                             struct list_head *validated)
 461 {
 462         struct amdgpu_bo_list_entry *lobj;
 463         int r;
 464
 465         list_for_each_entry(lobj, validated, tv.head) {
 466                 struct amdgpu_bo *bo = lobj->robj;
 467                 bool binding_userptr = false;
 468                 struct mm_struct *usermm;
 469
 470                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 471                 if (usermm && usermm != current->mm)
 472                         return -EPERM;
 473
 474                 /* Check if we have user pages and nobody bound the BO already */
 475                 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
 476                         size_t size = sizeof(struct page *);
 477
 478                         size *= bo->tbo.ttm->num_pages;
 479                         memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
 480                         binding_userptr = true;
 481                 }
 482
 483                 if (p->evictable == lobj)
 484                         p->evictable = NULL;
 485
 486                 r = amdgpu_cs_validate(p, bo);
 487                 if (r)
 488                         return r;
 489
 490                 if (binding_userptr) {
 491                         kvfree(lobj->user_pages);
 492                         lobj->user_pages = NULL;
 493                 }
 494         }
 495         return 0;
 496 }
 497
 498 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 499                                 union drm_amdgpu_cs *cs)
 500 {
 501         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 502         struct amdgpu_bo_list_entry *e;
 503         struct list_head duplicates;
 504         bool need_mmap_lock = false;
 505         unsigned i, tries = 10;
 506         int r;
 507
 508         INIT_LIST_HEAD(&p->validated);
 509
 510         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 511         if (p->bo_list) {
 512                 need_mmap_lock = p->bo_list->first_userptr !=
 513                         p->bo_list->num_entries;
 514                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 515         }
 516
 517         INIT_LIST_HEAD(&duplicates);
 518         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 519
 520         if (p->uf_entry.robj)
 521                 list_add(&p->uf_entry.tv.head, &p->validated);
 522
 523         if (need_mmap_lock)
 524                 down_read(&current->mm->mmap_sem);
 525
 526         while (1) {
 527                 struct list_head need_pages;
 528                 unsigned i;
 529
 530                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 531                                            &duplicates);
 532                 if (unlikely(r != 0)) {
 533                         if (r != -ERESTARTSYS)
 534                                 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 535                         goto error_free_pages;
 536                 }
 537
 538                 /* Without a BO list we don't have userptr BOs */
 539                 if (!p->bo_list)
 540                         break;
 541
 542                 INIT_LIST_HEAD(&need_pages);
 543                 for (i = p->bo_list->first_userptr;
 544                      i < p->bo_list->num_entries; ++i) {
 545
 546                         e = &p->bo_list->array[i];
 547
 548                         if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
 549                                  &e->user_invalidated) && e->user_pages) {
 550
 551                                 /* We acquired a page array, but somebody
 552                                  * invalidated it. Free it and try again
 553                                  */
 554                                 release_pages(e->user_pages,
 555                                               e->robj->tbo.ttm->num_pages,
 556                                               false);
 557                                 kvfree(e->user_pages);
 558                                 e->user_pages = NULL;
 559                         }
 560
 561                         if (e->robj->tbo.ttm->state != tt_bound &&
 562                             !e->user_pages) {
 563                                 list_del(&e->tv.head);
 564                                 list_add(&e->tv.head, &need_pages);
 565
 566                                 amdgpu_bo_unreserve(e->robj);
 567                         }
 568                 }
 569
 570                 if (list_empty(&need_pages))
 571                         break;
 572
 573                 /* Unreserve everything again. */
 574                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 575
 576                 /* We tried too many times, just abort */
 577                 if (!--tries) {
 578                         r = -EDEADLK;
 579                         DRM_ERROR("deadlock in %s\n", __func__);
 580                         goto error_free_pages;
 581                 }
 582
 583                 /* Fill the page arrays for all userptrs. */
 584                 list_for_each_entry(e, &need_pages, tv.head) {
 585                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 586
 587                         e->user_pages = kvmalloc_array(ttm->num_pages,
 588                                                          sizeof(struct page*),
 589                                                          GFP_KERNEL | __GFP_ZERO);
 590                         if (!e->user_pages) {
 591                                 r = -ENOMEM;
 592                                 DRM_ERROR("calloc failure in %s\n", __func__);
 593                                 goto error_free_pages;
 594                         }
 595
 596                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 597                         if (r) {
 598                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 599                                 kvfree(e->user_pages);
 600                                 e->user_pages = NULL;
 601                                 goto error_free_pages;
 602                         }
 603                 }
 604
 605                 /* And try again. */
 606                 list_splice(&need_pages, &p->validated);
 607         }
 608
 609         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 610                                           &p->bytes_moved_vis_threshold);
 611         p->bytes_moved = 0;
 612         p->bytes_moved_vis = 0;
 613         p->evictable = list_last_entry(&p->validated,
 614                                        struct amdgpu_bo_list_entry,
 615                                        tv.head);
 616
 617         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 618                                       amdgpu_cs_validate, p);
 619         if (r) {
 620                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 621                 goto error_validate;
 622         }
 623
 624         r = amdgpu_cs_list_validate(p, &duplicates);
 625         if (r) {
 626                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 627                 goto error_validate;
 628         }
 629
 630         r = amdgpu_cs_list_validate(p, &p->validated);
 631         if (r) {
 632                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 633                 goto error_validate;
 634         }
 635
 636         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 637                                      p->bytes_moved_vis);
 638         fpriv->vm.last_eviction_counter =
 639                 atomic64_read(&p->adev->num_evictions);
 640
 641         if (p->bo_list) {
 642                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 643                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 644                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 645                 struct amdgpu_vm *vm = &fpriv->vm;
 646                 unsigned i;
 647
 648                 for (i = 0; i < p->bo_list->num_entries; i++) {
 649                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 650
 651                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 652                 }
 653
 654                 if (gds) {
 655                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 656                         p->job->gds_size = amdgpu_bo_size(gds);
 657                 }
 658                 if (gws) {
 659                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 660                         p->job->gws_size = amdgpu_bo_size(gws);
 661                 }
 662                 if (oa) {
 663                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 664                         p->job->oa_size = amdgpu_bo_size(oa);
 665                 }
 666         }
 667
 668         if (!r && p->uf_entry.robj) {
 669                 struct amdgpu_bo *uf = p->uf_entry.robj;
 670
 671                 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
 672                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 673         }
 674
 675 error_validate:
 676         if (r) {
 677                 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
 678                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 679         }
 680
 681 error_free_pages:
 682
 683         if (need_mmap_lock)
 684                 up_read(&current->mm->mmap_sem);
 685
 686         if (p->bo_list) {
 687                 for (i = p->bo_list->first_userptr;
 688                      i < p->bo_list->num_entries; ++i) {
 689                         e = &p->bo_list->array[i];
 690
 691                         if (!e->user_pages)
 692                                 continue;
 693
 694                         release_pages(e->user_pages,
 695                                       e->robj->tbo.ttm->num_pages,
 696                                       false);
 697                         kvfree(e->user_pages);
 698                 }
 699         }
 700
 701         return r;
 702 }
 703
 704 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 705 {
 706         struct amdgpu_bo_list_entry *e;
 707         int r;
 708
 709         list_for_each_entry(e, &p->validated, tv.head) {
 710                 struct reservation_object *resv = e->robj->tbo.resv;
 711                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
 712
 713                 if (r)
 714                         return r;
 715         }
 716         return 0;
 717 }
 718
 719 /**
 720  * cs_parser_fini() - clean parser states
 721  * @parser:     parser structure holding parsing context.
 722  * @error:      error number
 723  *
 724  * If error is set than unvalidate buffer, otherwise just free memory
 725  * used by parsing context.
 726  **/
 727 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 728 {
 729         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 730         unsigned i;
 731
 732         if (!error) {
 733                 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
 734
 735                 ttm_eu_fence_buffer_objects(&parser->ticket,
 736                                             &parser->validated,
 737                                             parser->fence);
 738         } else if (backoff) {
 739                 ttm_eu_backoff_reservation(&parser->ticket,
 740                                            &parser->validated);
 741         }
 742
 743         for (i = 0; i < parser->num_post_dep_syncobjs; i++)
 744                 drm_syncobj_put(parser->post_dep_syncobjs[i]);
 745         kfree(parser->post_dep_syncobjs);
 746
 747         dma_fence_put(parser->fence);
 748
 749         if (parser->ctx)
 750                 amdgpu_ctx_put(parser->ctx);
 751         if (parser->bo_list)
 752                 amdgpu_bo_list_put(parser->bo_list);
 753
 754         for (i = 0; i < parser->nchunks; i++)
 755                 kvfree(parser->chunks[i].kdata);
 756         kfree(parser->chunks);
 757         if (parser->job)
 758                 amdgpu_job_free(parser->job);
 759         amdgpu_bo_unref(&parser->uf_entry.robj);
 760 }
 761
 762 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 763 {
 764         struct amdgpu_device *adev = p->adev;
 765         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 766         struct amdgpu_vm *vm = &fpriv->vm;
 767         struct amdgpu_bo_va *bo_va;
 768         struct amdgpu_bo *bo;
 769         int i, r;
 770
 771         r = amdgpu_vm_update_directories(adev, vm);
 772         if (r)
 773                 return r;
 774
 775         r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
 776         if (r)
 777                 return r;
 778
 779         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 780         if (r)
 781                 return r;
 782
 783         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 784         if (r)
 785                 return r;
 786
 787         r = amdgpu_sync_fence(adev, &p->job->sync,
 788                               fpriv->prt_va->last_pt_update);
 789         if (r)
 790                 return r;
 791
 792         if (amdgpu_sriov_vf(adev)) {
 793                 struct dma_fence *f;
 794                 bo_va = vm->csa_bo_va;
 795                 BUG_ON(!bo_va);
 796                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 797                 if (r)
 798                         return r;
 799
 800                 f = bo_va->last_pt_update;
 801                 r = amdgpu_sync_fence(adev, &p->job->sync, f);
 802                 if (r)
 803                         return r;
 804         }
 805
 806         if (p->bo_list) {
 807                 for (i = 0; i < p->bo_list->num_entries; i++) {
 808                         struct dma_fence *f;
 809
 810                         /* ignore duplicates */
 811                         bo = p->bo_list->array[i].robj;
 812                         if (!bo)
 813                                 continue;
 814
 815                         bo_va = p->bo_list->array[i].bo_va;
 816                         if (bo_va == NULL)
 817                                 continue;
 818
 819                         r = amdgpu_vm_bo_update(adev, bo_va, false);
 820                         if (r)
 821                                 return r;
 822
 823                         f = bo_va->last_pt_update;
 824                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 825                         if (r)
 826                                 return r;
 827                 }
 828
 829         }
 830
 831         r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
 832
 833         if (amdgpu_vm_debug && p->bo_list) {
 834                 /* Invalidate all BOs to test for userspace bugs */
 835                 for (i = 0; i < p->bo_list->num_entries; i++) {
 836                         /* ignore duplicates */
 837                         bo = p->bo_list->array[i].robj;
 838                         if (!bo)
 839                                 continue;
 840
 841                         amdgpu_vm_bo_invalidate(adev, bo);
 842                 }
 843         }
 844
 845         return r;
 846 }
 847
 848 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 849                                  struct amdgpu_cs_parser *p)
 850 {
 851         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 852         struct amdgpu_vm *vm = &fpriv->vm;
 853         struct amdgpu_ring *ring = p->job->ring;
 854         int i, r;
 855
 856         /* Only for UVD/VCE VM emulation */
 857         if (ring->funcs->parse_cs) {
 858                 for (i = 0; i < p->job->num_ibs; i++) {
 859                         r = amdgpu_ring_parse_cs(ring, p, i);
 860                         if (r)
 861                                 return r;
 862                 }
 863         }
 864
 865         if (p->job->vm) {
 866                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.bo);
 867
 868                 r = amdgpu_bo_vm_update_pte(p);
 869                 if (r)
 870                         return r;
 871         }
 872
 873         return amdgpu_cs_sync_rings(p);
 874 }
 875
 876 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 877                              struct amdgpu_cs_parser *parser)
 878 {
 879         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 880         struct amdgpu_vm *vm = &fpriv->vm;
 881         int i, j;
 882         int r, ce_preempt = 0, de_preempt = 0;
 883
 884         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 885                 struct amdgpu_cs_chunk *chunk;
 886                 struct amdgpu_ib *ib;
 887                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 888                 struct amdgpu_ring *ring;
 889
 890                 chunk = &parser->chunks[i];
 891                 ib = &parser->job->ibs[j];
 892                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 893
 894                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 895                         continue;
 896
 897                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
 898                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 899                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 900                                         ce_preempt++;
 901                                 else
 902                                         de_preempt++;
 903                         }
 904
 905                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 906                         if (ce_preempt > 1 || de_preempt > 1)
 907                                 return -EINVAL;
 908                 }
 909
 910                 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
 911                                          chunk_ib->ip_instance, chunk_ib->ring, &ring);
 912                 if (r)
 913                         return r;
 914
 915                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
 916                         parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
 917                         if (!parser->ctx->preamble_presented) {
 918                                 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
 919                                 parser->ctx->preamble_presented = true;
 920                         }
 921                 }
 922
 923                 if (parser->job->ring && parser->job->ring != ring)
 924                         return -EINVAL;
 925
 926                 parser->job->ring = ring;
 927
 928                 if (ring->funcs->parse_cs) {
 929                         struct amdgpu_bo_va_mapping *m;
 930                         struct amdgpu_bo *aobj = NULL;
 931                         uint64_t offset;
 932                         uint8_t *kptr;
 933
 934                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 935                                                    &aobj);
 936                         if (!aobj) {
 937                                 DRM_ERROR("IB va_start is invalid\n");
 938                                 return -EINVAL;
 939                         }
 940
 941                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 942                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 943                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 944                                 return -EINVAL;
 945                         }
 946
 947                         /* the IB should be reserved at this point */
 948                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 949                         if (r) {
 950                                 return r;
 951                         }
 952
 953                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 954                         kptr += chunk_ib->va_start - offset;
 955
 956                         r =  amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
 957                         if (r) {
 958                                 DRM_ERROR("Failed to get ib !\n");
 959                                 return r;
 960                         }
 961
 962                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 963                         amdgpu_bo_kunmap(aobj);
 964                 } else {
 965                         r =  amdgpu_ib_get(adev, vm, 0, ib);
 966                         if (r) {
 967                                 DRM_ERROR("Failed to get ib !\n");
 968                                 return r;
 969                         }
 970
 971                 }
 972
 973                 ib->gpu_addr = chunk_ib->va_start;
 974                 ib->length_dw = chunk_ib->ib_bytes / 4;
 975                 ib->flags = chunk_ib->flags;
 976                 j++;
 977         }
 978
 979         /* UVD & VCE fw doesn't support user fences */
 980         if (parser->job->uf_addr && (
 981             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
 982             parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
 983                 return -EINVAL;
 984
 985         return 0;
 986 }
 987
 988 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 989                                        struct amdgpu_cs_chunk *chunk)
 990 {
 991         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 992         unsigned num_deps;
 993         int i, r;
 994         struct drm_amdgpu_cs_chunk_dep *deps;
 995
 996         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 997         num_deps = chunk->length_dw * 4 /
 998                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 999
1000         for (i = 0; i < num_deps; ++i) {
1001                 struct amdgpu_ring *ring;
1002                 struct amdgpu_ctx *ctx;
1003                 struct dma_fence *fence;
1004
1005                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1006                 if (ctx == NULL)
1007                         return -EINVAL;
1008
1009                 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1010                                          deps[i].ip_type,
1011                                          deps[i].ip_instance,
1012                                          deps[i].ring, &ring);
1013                 if (r) {
1014                         amdgpu_ctx_put(ctx);
1015                         return r;
1016                 }
1017
1018                 fence = amdgpu_ctx_get_fence(ctx, ring,
1019                                              deps[i].handle);
1020                 if (IS_ERR(fence)) {
1021                         r = PTR_ERR(fence);
1022                         amdgpu_ctx_put(ctx);
1023                         return r;
1024                 } else if (fence) {
1025                         r = amdgpu_sync_fence(p->adev, &p->job->sync,
1026                                               fence);
1027                         dma_fence_put(fence);
1028                         amdgpu_ctx_put(ctx);
1029                         if (r)
1030                                 return r;
1031                 }
1032         }
1033         return 0;
1034 }
1035
1036 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1037                                                  uint32_t handle)
1038 {
1039         int r;
1040         struct dma_fence *fence;
1041         r = drm_syncobj_fence_get(p->filp, handle, &fence);
1042         if (r)
1043                 return r;
1044
1045         r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
1046         dma_fence_put(fence);
1047
1048         return r;
1049 }
1050
1051 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1052                                             struct amdgpu_cs_chunk *chunk)
1053 {
1054         unsigned num_deps;
1055         int i, r;
1056         struct drm_amdgpu_cs_chunk_sem *deps;
1057
1058         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1059         num_deps = chunk->length_dw * 4 /
1060                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1061
1062         for (i = 0; i < num_deps; ++i) {
1063                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1064                 if (r)
1065                         return r;
1066         }
1067         return 0;
1068 }
1069
1070 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1071                                              struct amdgpu_cs_chunk *chunk)
1072 {
1073         unsigned num_deps;
1074         int i;
1075         struct drm_amdgpu_cs_chunk_sem *deps;
1076         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1077         num_deps = chunk->length_dw * 4 /
1078                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1079
1080         p->post_dep_syncobjs = kmalloc_array(num_deps,
1081                                              sizeof(struct drm_syncobj *),
1082                                              GFP_KERNEL);
1083         p->num_post_dep_syncobjs = 0;
1084
1085         for (i = 0; i < num_deps; ++i) {
1086                 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1087                 if (!p->post_dep_syncobjs[i])
1088                         return -EINVAL;
1089                 p->num_post_dep_syncobjs++;
1090         }
1091         return 0;
1092 }
1093
1094 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1095                                   struct amdgpu_cs_parser *p)
1096 {
1097         int i, r;
1098
1099         for (i = 0; i < p->nchunks; ++i) {
1100                 struct amdgpu_cs_chunk *chunk;
1101
1102                 chunk = &p->chunks[i];
1103
1104                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1105                         r = amdgpu_cs_process_fence_dep(p, chunk);
1106                         if (r)
1107                                 return r;
1108                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1109                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1110                         if (r)
1111                                 return r;
1112                 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1113                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1114                         if (r)
1115                                 return r;
1116                 }
1117         }
1118
1119         return 0;
1120 }
1121
1122 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1123 {
1124         int i;
1125
1126         for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1127                 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1128 }
1129
1130 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1131                             union drm_amdgpu_cs *cs)
1132 {
1133         struct amdgpu_ring *ring = p->job->ring;
1134         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1135         struct amdgpu_job *job;
1136         int r;
1137
1138         job = p->job;
1139         p->job = NULL;
1140
1141         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1142         if (r) {
1143                 amdgpu_job_free(job);
1144                 return r;
1145         }
1146
1147         job->owner = p->filp;
1148         job->fence_ctx = entity->fence_context;
1149         p->fence = dma_fence_get(&job->base.s_fence->finished);
1150
1151         amdgpu_cs_post_dependencies(p);
1152
1153         cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1154         job->uf_sequence = cs->out.handle;
1155         amdgpu_job_free_resources(job);
1156         amdgpu_cs_parser_fini(p, 0, true);
1157
1158         trace_amdgpu_cs_ioctl(job);
1159         amd_sched_entity_push_job(&job->base);
1160         return 0;
1161 }
1162
1163 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1164 {
1165         struct amdgpu_device *adev = dev->dev_private;
1166         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1167         union drm_amdgpu_cs *cs = data;
1168         struct amdgpu_cs_parser parser = {};
1169         bool reserved_buffers = false;
1170         int i, r;
1171
1172         if (!adev->accel_working)
1173                 return -EBUSY;
1174         if (amdgpu_kms_vram_lost(adev, fpriv))
1175                 return -ENODEV;
1176
1177         parser.adev = adev;
1178         parser.filp = filp;
1179
1180         r = amdgpu_cs_parser_init(&parser, data);
1181         if (r) {
1182                 DRM_ERROR("Failed to initialize parser !\n");
1183                 goto out;
1184         }
1185
1186         r = amdgpu_cs_parser_bos(&parser, data);
1187         if (r) {
1188                 if (r == -ENOMEM)
1189                         DRM_ERROR("Not enough memory for command submission!\n");
1190                 else if (r != -ERESTARTSYS)
1191                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1192                 goto out;
1193         }
1194
1195         reserved_buffers = true;
1196         r = amdgpu_cs_ib_fill(adev, &parser);
1197         if (r)
1198                 goto out;
1199
1200         r = amdgpu_cs_dependencies(adev, &parser);
1201         if (r) {
1202                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1203                 goto out;
1204         }
1205
1206         for (i = 0; i < parser.job->num_ibs; i++)
1207                 trace_amdgpu_cs(&parser, i);
1208
1209         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1210         if (r)
1211                 goto out;
1212
1213         r = amdgpu_cs_submit(&parser, cs);
1214         if (r)
1215                 goto out;
1216
1217         return 0;
1218 out:
1219         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1220         return r;
1221 }
1222
1223 /**
1224  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1225  *
1226  * @dev: drm device
1227  * @data: data from userspace
1228  * @filp: file private
1229  *
1230  * Wait for the command submission identified by handle to finish.
1231  */
1232 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1233                          struct drm_file *filp)
1234 {
1235         union drm_amdgpu_wait_cs *wait = data;
1236         struct amdgpu_device *adev = dev->dev_private;
1237         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1238         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1239         struct amdgpu_ring *ring = NULL;
1240         struct amdgpu_ctx *ctx;
1241         struct dma_fence *fence;
1242         long r;
1243
1244         if (amdgpu_kms_vram_lost(adev, fpriv))
1245                 return -ENODEV;
1246
1247         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1248         if (ctx == NULL)
1249                 return -EINVAL;
1250
1251         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1252                                  wait->in.ip_type, wait->in.ip_instance,
1253                                  wait->in.ring, &ring);
1254         if (r) {
1255                 amdgpu_ctx_put(ctx);
1256                 return r;
1257         }
1258
1259         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1260         if (IS_ERR(fence))
1261                 r = PTR_ERR(fence);
1262         else if (fence) {
1263                 r = dma_fence_wait_timeout(fence, true, timeout);
1264                 dma_fence_put(fence);
1265         } else
1266                 r = 1;
1267
1268         amdgpu_ctx_put(ctx);
1269         if (r < 0)
1270                 return r;
1271
1272         memset(wait, 0, sizeof(*wait));
1273         wait->out.status = (r == 0);
1274
1275         return 0;
1276 }
1277
1278 /**
1279  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1280  *
1281  * @adev: amdgpu device
1282  * @filp: file private
1283  * @user: drm_amdgpu_fence copied from user space
1284  */
1285 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1286                                              struct drm_file *filp,
1287                                              struct drm_amdgpu_fence *user)
1288 {
1289         struct amdgpu_ring *ring;
1290         struct amdgpu_ctx *ctx;
1291         struct dma_fence *fence;
1292         int r;
1293
1294         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1295         if (ctx == NULL)
1296                 return ERR_PTR(-EINVAL);
1297
1298         r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1299                                  user->ip_instance, user->ring, &ring);
1300         if (r) {
1301                 amdgpu_ctx_put(ctx);
1302                 return ERR_PTR(r);
1303         }
1304
1305         fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1306         amdgpu_ctx_put(ctx);
1307
1308         return fence;
1309 }
1310
1311 /**
1312  * amdgpu_cs_wait_all_fence - wait on all fences to signal
1313  *
1314  * @adev: amdgpu device
1315  * @filp: file private
1316  * @wait: wait parameters
1317  * @fences: array of drm_amdgpu_fence
1318  */
1319 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1320                                      struct drm_file *filp,
1321                                      union drm_amdgpu_wait_fences *wait,
1322                                      struct drm_amdgpu_fence *fences)
1323 {
1324         uint32_t fence_count = wait->in.fence_count;
1325         unsigned int i;
1326         long r = 1;
1327
1328         for (i = 0; i < fence_count; i++) {
1329                 struct dma_fence *fence;
1330                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1331
1332                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1333                 if (IS_ERR(fence))
1334                         return PTR_ERR(fence);
1335                 else if (!fence)
1336                         continue;
1337
1338                 r = dma_fence_wait_timeout(fence, true, timeout);
1339                 dma_fence_put(fence);
1340                 if (r < 0)
1341                         return r;
1342
1343                 if (r == 0)
1344                         break;
1345         }
1346
1347         memset(wait, 0, sizeof(*wait));
1348         wait->out.status = (r > 0);
1349
1350         return 0;
1351 }
1352
1353 /**
1354  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1355  *
1356  * @adev: amdgpu device
1357  * @filp: file private
1358  * @wait: wait parameters
1359  * @fences: array of drm_amdgpu_fence
1360  */
1361 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1362                                     struct drm_file *filp,
1363                                     union drm_amdgpu_wait_fences *wait,
1364                                     struct drm_amdgpu_fence *fences)
1365 {
1366         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1367         uint32_t fence_count = wait->in.fence_count;
1368         uint32_t first = ~0;
1369         struct dma_fence **array;
1370         unsigned int i;
1371         long r;
1372
1373         /* Prepare the fence array */
1374         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1375
1376         if (array == NULL)
1377                 return -ENOMEM;
1378
1379         for (i = 0; i < fence_count; i++) {
1380                 struct dma_fence *fence;
1381
1382                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1383                 if (IS_ERR(fence)) {
1384                         r = PTR_ERR(fence);
1385                         goto err_free_fence_array;
1386                 } else if (fence) {
1387                         array[i] = fence;
1388                 } else { /* NULL, the fence has been already signaled */
1389                         r = 1;
1390                         goto out;
1391                 }
1392         }
1393
1394         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1395                                        &first);
1396         if (r < 0)
1397                 goto err_free_fence_array;
1398
1399 out:
1400         memset(wait, 0, sizeof(*wait));
1401         wait->out.status = (r > 0);
1402         wait->out.first_signaled = first;
1403         /* set return value 0 to indicate success */
1404         r = 0;
1405
1406 err_free_fence_array:
1407         for (i = 0; i < fence_count; i++)
1408                 dma_fence_put(array[i]);
1409         kfree(array);
1410
1411         return r;
1412 }
1413
1414 /**
1415  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1416  *
1417  * @dev: drm device
1418  * @data: data from userspace
1419  * @filp: file private
1420  */
1421 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1422                                 struct drm_file *filp)
1423 {
1424         struct amdgpu_device *adev = dev->dev_private;
1425         struct amdgpu_fpriv *fpriv = filp->driver_priv;
1426         union drm_amdgpu_wait_fences *wait = data;
1427         uint32_t fence_count = wait->in.fence_count;
1428         struct drm_amdgpu_fence *fences_user;
1429         struct drm_amdgpu_fence *fences;
1430         int r;
1431
1432         if (amdgpu_kms_vram_lost(adev, fpriv))
1433                 return -ENODEV;
1434         /* Get the fences from userspace */
1435         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1436                         GFP_KERNEL);
1437         if (fences == NULL)
1438                 return -ENOMEM;
1439
1440         fences_user = u64_to_user_ptr(wait->in.fences);
1441         if (copy_from_user(fences, fences_user,
1442                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1443                 r = -EFAULT;
1444                 goto err_free_fences;
1445         }
1446
1447         if (wait->in.wait_all)
1448                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1449         else
1450                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1451
1452 err_free_fences:
1453         kfree(fences);
1454
1455         return r;
1456 }
1457
1458 /**
1459  * amdgpu_cs_find_bo_va - find bo_va for VM address
1460  *
1461  * @parser: command submission parser context
1462  * @addr: VM address
1463  * @bo: resulting BO of the mapping found
1464  *
1465  * Search the buffer objects in the command submission context for a certain
1466  * virtual memory address. Returns allocation structure when found, NULL
1467  * otherwise.
1468  */
1469 struct amdgpu_bo_va_mapping *
1470 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1471                        uint64_t addr, struct amdgpu_bo **bo)
1472 {
1473         struct amdgpu_bo_va_mapping *mapping;
1474         unsigned i;
1475
1476         if (!parser->bo_list)
1477                 return NULL;
1478
1479         addr /= AMDGPU_GPU_PAGE_SIZE;
1480
1481         for (i = 0; i < parser->bo_list->num_entries; i++) {
1482                 struct amdgpu_bo_list_entry *lobj;
1483
1484                 lobj = &parser->bo_list->array[i];
1485                 if (!lobj->bo_va)
1486                         continue;
1487
1488                 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1489                         if (mapping->start > addr ||
1490                             addr > mapping->last)
1491                                 continue;
1492
1493                         *bo = lobj->bo_va->bo;
1494                         return mapping;
1495                 }
1496
1497                 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1498                         if (mapping->start > addr ||
1499                             addr > mapping->last)
1500                                 continue;
1501
1502                         *bo = lobj->bo_va->bo;
1503                         return mapping;
1504                 }
1505         }
1506
1507         return NULL;
1508 }
1509
1510 /**
1511  * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1512  *
1513  * @parser: command submission parser context
1514  *
1515  * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1516  */
1517 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
1518 {
1519         unsigned i;
1520         int r;
1521
1522         if (!parser->bo_list)
1523                 return 0;
1524
1525         for (i = 0; i < parser->bo_list->num_entries; i++) {
1526                 struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
1527
1528                 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1529                 if (unlikely(r))
1530                         return r;
1531
1532                 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
1533                         continue;
1534
1535                 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1536                 amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
1537                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
1538                 if (unlikely(r))
1539                         return r;
1540         }
1541
1542         return 0;
1543 }