drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <drm/amdgpu_drm.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_i2c.h"
  30 #include "atom.h"
  31 #include "amdgpu_connectors.h"
  32 #include "amdgpu_display.h"
  33 #include <asm/div64.h>
  34
  35 #include <linux/pci.h>
  36 #include <linux/pm_runtime.h>
  37 #include <drm/drm_crtc_helper.h>
  38 #include <drm/drm_edid.h>
  39 #include <drm/drm_gem_framebuffer_helper.h>
  40 #include <drm/drm_fb_helper.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_vblank.h>
  43
  44 static void amdgpu_display_flip_callback(struct dma_fence *f,
  45                                          struct dma_fence_cb *cb)
  46 {
  47         struct amdgpu_flip_work *work =
  48                 container_of(cb, struct amdgpu_flip_work, cb);
  49
  50         dma_fence_put(f);
  51         schedule_work(&work->flip_work.work);
  52 }
  53
  54 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work,
  55                                              struct dma_fence **f)
  56 {
  57         struct dma_fence *fence= *f;
  58
  59         if (fence == NULL)
  60                 return false;
  61
  62         *f = NULL;
  63
  64         if (!dma_fence_add_callback(fence, &work->cb,
  65                                     amdgpu_display_flip_callback))
  66                 return true;
  67
  68         dma_fence_put(fence);
  69         return false;
  70 }
  71
  72 static void amdgpu_display_flip_work_func(struct work_struct *__work)
  73 {
  74         struct delayed_work *delayed_work =
  75                 container_of(__work, struct delayed_work, work);
  76         struct amdgpu_flip_work *work =
  77                 container_of(delayed_work, struct amdgpu_flip_work, flip_work);
  78         struct amdgpu_device *adev = work->adev;
  79         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id];
  80
  81         struct drm_crtc *crtc = &amdgpu_crtc->base;
  82         unsigned long flags;
  83         unsigned i;
  84         int vpos, hpos;
  85
  86         if (amdgpu_display_flip_handle_fence(work, &work->excl))
  87                 return;
  88
  89         for (i = 0; i < work->shared_count; ++i)
  90                 if (amdgpu_display_flip_handle_fence(work, &work->shared[i]))
  91                         return;
  92
  93         /* Wait until we're out of the vertical blank period before the one
  94          * targeted by the flip
  95          */
  96         if (amdgpu_crtc->enabled &&
  97             (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0,
  98                                                 &vpos, &hpos, NULL, NULL,
  99                                                 &crtc->hwmode)
 100              & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
 101             (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
 102             (int)(work->target_vblank -
 103                   amdgpu_get_vblank_counter_kms(crtc)) > 0) {
 104                 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000));
 105                 return;
 106         }
 107
 108         /* We borrow the event spin lock for protecting flip_status */
 109         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 110
 111         /* Do the flip (mmio) */
 112         adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async);
 113
 114         /* Set the flip status */
 115         amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 116         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 117
 118
 119         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n",
 120                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 121
 122 }
 123
 124 /*
 125  * Handle unpin events outside the interrupt handler proper.
 126  */
 127 static void amdgpu_display_unpin_work_func(struct work_struct *__work)
 128 {
 129         struct amdgpu_flip_work *work =
 130                 container_of(__work, struct amdgpu_flip_work, unpin_work);
 131         int r;
 132
 133         /* unpin of the old buffer */
 134         r = amdgpu_bo_reserve(work->old_abo, true);
 135         if (likely(r == 0)) {
 136                 r = amdgpu_bo_unpin(work->old_abo);
 137                 if (unlikely(r != 0)) {
 138                         DRM_ERROR("failed to unpin buffer after flip\n");
 139                 }
 140                 amdgpu_bo_unreserve(work->old_abo);
 141         } else
 142                 DRM_ERROR("failed to reserve buffer after flip\n");
 143
 144         amdgpu_bo_unref(&work->old_abo);
 145         kfree(work->shared);
 146         kfree(work);
 147 }
 148
 149 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
 150                                 struct drm_framebuffer *fb,
 151                                 struct drm_pending_vblank_event *event,
 152                                 uint32_t page_flip_flags, uint32_t target,
 153                                 struct drm_modeset_acquire_ctx *ctx)
 154 {
 155         struct drm_device *dev = crtc->dev;
 156         struct amdgpu_device *adev = drm_to_adev(dev);
 157         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 158         struct drm_gem_object *obj;
 159         struct amdgpu_flip_work *work;
 160         struct amdgpu_bo *new_abo;
 161         unsigned long flags;
 162         u64 tiling_flags;
 163         int i, r;
 164
 165         work = kzalloc(sizeof *work, GFP_KERNEL);
 166         if (work == NULL)
 167                 return -ENOMEM;
 168
 169         INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func);
 170         INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func);
 171
 172         work->event = event;
 173         work->adev = adev;
 174         work->crtc_id = amdgpu_crtc->crtc_id;
 175         work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
 176
 177         /* schedule unpin of the old buffer */
 178         obj = crtc->primary->fb->obj[0];
 179
 180         /* take a reference to the old object */
 181         work->old_abo = gem_to_amdgpu_bo(obj);
 182         amdgpu_bo_ref(work->old_abo);
 183
 184         obj = fb->obj[0];
 185         new_abo = gem_to_amdgpu_bo(obj);
 186
 187         /* pin the new buffer */
 188         r = amdgpu_bo_reserve(new_abo, false);
 189         if (unlikely(r != 0)) {
 190                 DRM_ERROR("failed to reserve new abo buffer before flip\n");
 191                 goto cleanup;
 192         }
 193
 194         if (!adev->enable_virtual_display) {
 195                 r = amdgpu_bo_pin(new_abo,
 196                                   amdgpu_display_supported_domains(adev, new_abo->flags));
 197                 if (unlikely(r != 0)) {
 198                         DRM_ERROR("failed to pin new abo buffer before flip\n");
 199                         goto unreserve;
 200                 }
 201         }
 202
 203         r = amdgpu_ttm_alloc_gart(&new_abo->tbo);
 204         if (unlikely(r != 0)) {
 205                 DRM_ERROR("%p bind failed\n", new_abo);
 206                 goto unpin;
 207         }
 208
 209         r = dma_resv_get_fences_rcu(new_abo->tbo.base.resv, &work->excl,
 210                                               &work->shared_count,
 211                                               &work->shared);
 212         if (unlikely(r != 0)) {
 213                 DRM_ERROR("failed to get fences for buffer\n");
 214                 goto unpin;
 215         }
 216
 217         amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
 218         amdgpu_bo_unreserve(new_abo);
 219
 220         if (!adev->enable_virtual_display)
 221                 work->base = amdgpu_bo_gpu_offset(new_abo);
 222         work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
 223                 amdgpu_get_vblank_counter_kms(crtc);
 224
 225         /* we borrow the event spin lock for protecting flip_wrok */
 226         spin_lock_irqsave(&crtc->dev->event_lock, flags);
 227         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
 228                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 229                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 230                 r = -EBUSY;
 231                 goto pflip_cleanup;
 232         }
 233
 234         amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
 235         amdgpu_crtc->pflip_works = work;
 236
 237
 238         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n",
 239                                          amdgpu_crtc->crtc_id, amdgpu_crtc, work);
 240         /* update crtc fb */
 241         crtc->primary->fb = fb;
 242         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 243         amdgpu_display_flip_work_func(&work->flip_work.work);
 244         return 0;
 245
 246 pflip_cleanup:
 247         if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) {
 248                 DRM_ERROR("failed to reserve new abo in error path\n");
 249                 goto cleanup;
 250         }
 251 unpin:
 252         if (!adev->enable_virtual_display)
 253                 if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
 254                         DRM_ERROR("failed to unpin new abo in error path\n");
 255
 256 unreserve:
 257         amdgpu_bo_unreserve(new_abo);
 258
 259 cleanup:
 260         amdgpu_bo_unref(&work->old_abo);
 261         dma_fence_put(work->excl);
 262         for (i = 0; i < work->shared_count; ++i)
 263                 dma_fence_put(work->shared[i]);
 264         kfree(work->shared);
 265         kfree(work);
 266
 267         return r;
 268 }
 269
 270 int amdgpu_display_crtc_set_config(struct drm_mode_set *set,
 271                                    struct drm_modeset_acquire_ctx *ctx)
 272 {
 273         struct drm_device *dev;
 274         struct amdgpu_device *adev;
 275         struct drm_crtc *crtc;
 276         bool active = false;
 277         int ret;
 278
 279         if (!set || !set->crtc)
 280                 return -EINVAL;
 281
 282         dev = set->crtc->dev;
 283
 284         ret = pm_runtime_get_sync(dev->dev);
 285         if (ret < 0)
 286                 goto out;
 287
 288         ret = drm_crtc_helper_set_config(set, ctx);
 289
 290         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 291                 if (crtc->enabled)
 292                         active = true;
 293
 294         pm_runtime_mark_last_busy(dev->dev);
 295
 296         adev = drm_to_adev(dev);
 297         /* if we have active crtcs and we don't have a power ref,
 298            take the current one */
 299         if (active && !adev->have_disp_power_ref) {
 300                 adev->have_disp_power_ref = true;
 301                 return ret;
 302         }
 303         /* if we have no active crtcs, then drop the power ref
 304            we got before */
 305         if (!active && adev->have_disp_power_ref) {
 306                 pm_runtime_put_autosuspend(dev->dev);
 307                 adev->have_disp_power_ref = false;
 308         }
 309
 310 out:
 311         /* drop the power reference we got coming in here */
 312         pm_runtime_put_autosuspend(dev->dev);
 313         return ret;
 314 }
 315
 316 static const char *encoder_names[41] = {
 317         "NONE",
 318         "INTERNAL_LVDS",
 319         "INTERNAL_TMDS1",
 320         "INTERNAL_TMDS2",
 321         "INTERNAL_DAC1",
 322         "INTERNAL_DAC2",
 323         "INTERNAL_SDVOA",
 324         "INTERNAL_SDVOB",
 325         "SI170B",
 326         "CH7303",
 327         "CH7301",
 328         "INTERNAL_DVO1",
 329         "EXTERNAL_SDVOA",
 330         "EXTERNAL_SDVOB",
 331         "TITFP513",
 332         "INTERNAL_LVTM1",
 333         "VT1623",
 334         "HDMI_SI1930",
 335         "HDMI_INTERNAL",
 336         "INTERNAL_KLDSCP_TMDS1",
 337         "INTERNAL_KLDSCP_DVO1",
 338         "INTERNAL_KLDSCP_DAC1",
 339         "INTERNAL_KLDSCP_DAC2",
 340         "SI178",
 341         "MVPU_FPGA",
 342         "INTERNAL_DDI",
 343         "VT1625",
 344         "HDMI_SI1932",
 345         "DP_AN9801",
 346         "DP_DP501",
 347         "INTERNAL_UNIPHY",
 348         "INTERNAL_KLDSCP_LVTMA",
 349         "INTERNAL_UNIPHY1",
 350         "INTERNAL_UNIPHY2",
 351         "NUTMEG",
 352         "TRAVIS",
 353         "INTERNAL_VCE",
 354         "INTERNAL_UNIPHY3",
 355         "HDMI_ANX9805",
 356         "INTERNAL_AMCLK",
 357         "VIRTUAL",
 358 };
 359
 360 static const char *hpd_names[6] = {
 361         "HPD1",
 362         "HPD2",
 363         "HPD3",
 364         "HPD4",
 365         "HPD5",
 366         "HPD6",
 367 };
 368
 369 void amdgpu_display_print_display_setup(struct drm_device *dev)
 370 {
 371         struct drm_connector *connector;
 372         struct amdgpu_connector *amdgpu_connector;
 373         struct drm_encoder *encoder;
 374         struct amdgpu_encoder *amdgpu_encoder;
 375         struct drm_connector_list_iter iter;
 376         uint32_t devices;
 377         int i = 0;
 378
 379         drm_connector_list_iter_begin(dev, &iter);
 380         DRM_INFO("AMDGPU Display Connectors\n");
 381         drm_for_each_connector_iter(connector, &iter) {
 382                 amdgpu_connector = to_amdgpu_connector(connector);
 383                 DRM_INFO("Connector %d:\n", i);
 384                 DRM_INFO("  %s\n", connector->name);
 385                 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
 386                         DRM_INFO("  %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
 387                 if (amdgpu_connector->ddc_bus) {
 388                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 389                                  amdgpu_connector->ddc_bus->rec.mask_clk_reg,
 390                                  amdgpu_connector->ddc_bus->rec.mask_data_reg,
 391                                  amdgpu_connector->ddc_bus->rec.a_clk_reg,
 392                                  amdgpu_connector->ddc_bus->rec.a_data_reg,
 393                                  amdgpu_connector->ddc_bus->rec.en_clk_reg,
 394                                  amdgpu_connector->ddc_bus->rec.en_data_reg,
 395                                  amdgpu_connector->ddc_bus->rec.y_clk_reg,
 396                                  amdgpu_connector->ddc_bus->rec.y_data_reg);
 397                         if (amdgpu_connector->router.ddc_valid)
 398                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 399                                          amdgpu_connector->router.ddc_mux_control_pin,
 400                                          amdgpu_connector->router.ddc_mux_state);
 401                         if (amdgpu_connector->router.cd_valid)
 402                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 403                                          amdgpu_connector->router.cd_mux_control_pin,
 404                                          amdgpu_connector->router.cd_mux_state);
 405                 } else {
 406                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 407                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 408                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 409                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 410                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 411                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 412                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n");
 413                 }
 414                 DRM_INFO("  Encoders:\n");
 415                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 416                         amdgpu_encoder = to_amdgpu_encoder(encoder);
 417                         devices = amdgpu_encoder->devices & amdgpu_connector->devices;
 418                         if (devices) {
 419                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 420                                         DRM_INFO("    CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 421                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 422                                         DRM_INFO("    CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 423                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 424                                         DRM_INFO("    LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 425                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 426                                         DRM_INFO("    DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 427                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 428                                         DRM_INFO("    DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 429                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 430                                         DRM_INFO("    DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 431                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 432                                         DRM_INFO("    DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 433                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 434                                         DRM_INFO("    DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 435                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 436                                         DRM_INFO("    DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 437                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 438                                         DRM_INFO("    TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 439                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 440                                         DRM_INFO("    CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
 441                         }
 442                 }
 443                 i++;
 444         }
 445         drm_connector_list_iter_end(&iter);
 446 }
 447
 448 /**
 449  * amdgpu_display_ddc_probe
 450  *
 451  */
 452 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
 453                               bool use_aux)
 454 {
 455         u8 out = 0x0;
 456         u8 buf[8];
 457         int ret;
 458         struct i2c_msg msgs[] = {
 459                 {
 460                         .addr = DDC_ADDR,
 461                         .flags = 0,
 462                         .len = 1,
 463                         .buf = &out,
 464                 },
 465                 {
 466                         .addr = DDC_ADDR,
 467                         .flags = I2C_M_RD,
 468                         .len = 8,
 469                         .buf = buf,
 470                 }
 471         };
 472
 473         /* on hw with routers, select right port */
 474         if (amdgpu_connector->router.ddc_valid)
 475                 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 476
 477         if (use_aux) {
 478                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
 479         } else {
 480                 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
 481         }
 482
 483         if (ret != 2)
 484                 /* Couldn't find an accessible DDC on this connector */
 485                 return false;
 486         /* Probe also for valid EDID header
 487          * EDID header starts with:
 488          * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
 489          * Only the first 6 bytes must be valid as
 490          * drm_edid_block_valid() can fix the last 2 bytes */
 491         if (drm_edid_header_is_valid(buf) < 6) {
 492                 /* Couldn't find an accessible EDID on this
 493                  * connector */
 494                 return false;
 495         }
 496         return true;
 497 }
 498
 499 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
 500         .destroy = drm_gem_fb_destroy,
 501         .create_handle = drm_gem_fb_create_handle,
 502 };
 503
 504 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
 505                                           uint64_t bo_flags)
 506 {
 507         uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 508
 509 #if defined(CONFIG_DRM_AMD_DC)
 510         /*
 511          * if amdgpu_bo_support_uswc returns false it means that USWC mappings
 512          * is not supported for this board. But this mapping is required
 513          * to avoid hang caused by placement of scanout BO in GTT on certain
 514          * APUs. So force the BO placement to VRAM in case this architecture
 515          * will not allow USWC mappings.
 516          * Also, don't allow GTT domain if the BO doens't have USWC falg set.
 517          */
 518         if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
 519             amdgpu_bo_support_uswc(bo_flags) &&
 520             amdgpu_device_asic_has_dc_support(adev->asic_type)) {
 521                 switch (adev->asic_type) {
 522                 case CHIP_CARRIZO:
 523                 case CHIP_STONEY:
 524                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 525                         break;
 526                 case CHIP_RAVEN:
 527                         /* enable S/G on PCO and RV2 */
 528                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
 529                             (adev->apu_flags & AMD_APU_IS_PICASSO))
 530                                 domain |= AMDGPU_GEM_DOMAIN_GTT;
 531                         break;
 532                 case CHIP_RENOIR:
 533                         domain |= AMDGPU_GEM_DOMAIN_GTT;
 534                         break;
 535
 536                 default:
 537                         break;
 538                 }
 539         }
 540 #endif
 541
 542         return domain;
 543 }
 544
 545 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
 546 {
 547         struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
 548         uint64_t modifier = 0;
 549
 550         if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
 551                 modifier = DRM_FORMAT_MOD_LINEAR;
 552         } else {
 553                 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
 554                 bool has_xor = swizzle >= 16;
 555                 int block_size_bits;
 556                 int version;
 557                 int pipe_xor_bits = 0;
 558                 int bank_xor_bits = 0;
 559                 int packers = 0;
 560                 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
 561
 562                 switch (swizzle >> 2) {
 563                 case 0: /* 256B */
 564                         block_size_bits = 8;
 565                         break;
 566                 case 1: /* 4KiB */
 567                 case 5: /* 4KiB _X */
 568                         block_size_bits = 12;
 569                         break;
 570                 case 2: /* 64KiB */
 571                 case 4: /* 64 KiB _T */
 572                 case 6: /* 64 KiB _X */
 573                         block_size_bits = 16;
 574                         break;
 575                 default:
 576                         /* RESERVED or VAR */
 577                         return -EINVAL;
 578                 }
 579
 580                 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 581                         version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 582                 else if (adev->family == AMDGPU_FAMILY_NV)
 583                         version = AMD_FMT_MOD_TILE_VER_GFX10;
 584                 else
 585                         version = AMD_FMT_MOD_TILE_VER_GFX9;
 586
 587                 switch (swizzle & 3) {
 588                 case 0: /* Z microtiling */
 589                         return -EINVAL;
 590                 case 1: /* S microtiling */
 591                         if (!has_xor)
 592                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 593                         break;
 594                 case 2:
 595                         if (!has_xor && afb->base.format->cpp[0] != 4)
 596                                 version = AMD_FMT_MOD_TILE_VER_GFX9;
 597                         break;
 598                 case 3:
 599                         break;
 600                 }
 601
 602                 if (has_xor) {
 603                         switch (version) {
 604                         case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS:
 605                                 pipe_xor_bits = min(block_size_bits - 8,
 606                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes));
 607                                 packers = min(block_size_bits - 8 - pipe_xor_bits,
 608                                               ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs));
 609                                 break;
 610                         case AMD_FMT_MOD_TILE_VER_GFX10:
 611                                 pipe_xor_bits = min(block_size_bits - 8,
 612                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes));
 613                                 break;
 614                         case AMD_FMT_MOD_TILE_VER_GFX9:
 615                                 pipe_xor_bits = min(block_size_bits - 8,
 616                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes) +
 617                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_se));
 618                                 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits,
 619                                                     ilog2(adev->gfx.config.gb_addr_config_fields.num_banks));
 620                                 break;
 621                         }
 622                 }
 623
 624                 modifier = AMD_FMT_MOD |
 625                            AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
 626                            AMD_FMT_MOD_SET(TILE_VERSION, version) |
 627                            AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
 628                            AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) |
 629                            AMD_FMT_MOD_SET(PACKERS, packers);
 630
 631                 if (dcc_offset != 0) {
 632                         bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
 633                         bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
 634
 635                         /* Enable constant encode on RAVEN2 and later. */
 636                         bool dcc_constant_encode = adev->asic_type > CHIP_RAVEN ||
 637                                                    (adev->asic_type == CHIP_RAVEN &&
 638                                                     adev->external_rev_id >= 0x81);
 639
 640                         int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :
 641                                               dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B :
 642                                               AMD_FMT_MOD_DCC_BLOCK_256B;
 643
 644                         modifier |= AMD_FMT_MOD_SET(DCC, 1) |
 645                                     AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) |
 646                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) |
 647                                     AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) |
 648                                     AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size);
 649
 650                         afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
 651                         afb->base.pitches[1] = AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
 652                 }
 653         }
 654
 655         afb->base.modifier = modifier;
 656         afb->base.flags |= DRM_MODE_FB_MODIFIERS;
 657         return 0;
 658 }
 659
 660 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
 661                                       uint64_t *tiling_flags, bool *tmz_surface)
 662 {
 663         struct amdgpu_bo *rbo;
 664         int r;
 665
 666         if (!amdgpu_fb) {
 667                 *tiling_flags = 0;
 668                 *tmz_surface = false;
 669                 return 0;
 670         }
 671
 672         rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
 673         r = amdgpu_bo_reserve(rbo, false);
 674
 675         if (unlikely(r)) {
 676                 /* Don't show error message when returning -ERESTARTSYS */
 677                 if (r != -ERESTARTSYS)
 678                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
 679                 return r;
 680         }
 681
 682         if (tiling_flags)
 683                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
 684
 685         if (tmz_surface)
 686                 *tmz_surface = amdgpu_bo_encrypted(rbo);
 687
 688         amdgpu_bo_unreserve(rbo);
 689
 690         return r;
 691 }
 692
 693 int amdgpu_display_framebuffer_init(struct drm_device *dev,
 694                                     struct amdgpu_framebuffer *rfb,
 695                                     const struct drm_mode_fb_cmd2 *mode_cmd,
 696                                     struct drm_gem_object *obj)
 697 {
 698         int ret;
 699         rfb->base.obj[0] = obj;
 700         drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd);
 701         ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
 702         if (ret)
 703                 goto fail;
 704
 705         ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
 706         if (ret)
 707                 goto fail;
 708
 709         if (dev->mode_config.allow_fb_modifiers &&
 710             !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
 711                 ret = convert_tiling_flags_to_modifier(rfb);
 712                 if (ret)
 713                         goto fail;
 714         }
 715
 716         return 0;
 717
 718 fail:
 719         rfb->base.obj[0] = NULL;
 720         return ret;
 721 }
 722
 723 struct drm_framebuffer *
 724 amdgpu_display_user_framebuffer_create(struct drm_device *dev,
 725                                        struct drm_file *file_priv,
 726                                        const struct drm_mode_fb_cmd2 *mode_cmd)
 727 {
 728         struct drm_gem_object *obj;
 729         struct amdgpu_framebuffer *amdgpu_fb;
 730         int ret;
 731
 732         obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
 733         if (obj ==  NULL) {
 734                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 735                         "can't create framebuffer\n", mode_cmd->handles[0]);
 736                 return ERR_PTR(-ENOENT);
 737         }
 738
 739         /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */
 740         if (obj->import_attach) {
 741                 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n");
 742                 return ERR_PTR(-EINVAL);
 743         }
 744
 745         amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
 746         if (amdgpu_fb == NULL) {
 747                 drm_gem_object_put(obj);
 748                 return ERR_PTR(-ENOMEM);
 749         }
 750
 751         ret = amdgpu_display_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
 752         if (ret) {
 753                 kfree(amdgpu_fb);
 754                 drm_gem_object_put(obj);
 755                 return ERR_PTR(ret);
 756         }
 757
 758         return &amdgpu_fb->base;
 759 }
 760
 761 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
 762         .fb_create = amdgpu_display_user_framebuffer_create,
 763         .output_poll_changed = drm_fb_helper_output_poll_changed,
 764 };
 765
 766 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
 767 {       { UNDERSCAN_OFF, "off" },
 768         { UNDERSCAN_ON, "on" },
 769         { UNDERSCAN_AUTO, "auto" },
 770 };
 771
 772 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] =
 773 {       { AMDGPU_AUDIO_DISABLE, "off" },
 774         { AMDGPU_AUDIO_ENABLE, "on" },
 775         { AMDGPU_AUDIO_AUTO, "auto" },
 776 };
 777
 778 /* XXX support different dither options? spatial, temporal, both, etc. */
 779 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] =
 780 {       { AMDGPU_FMT_DITHER_DISABLE, "off" },
 781         { AMDGPU_FMT_DITHER_ENABLE, "on" },
 782 };
 783
 784 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)
 785 {
 786         int sz;
 787
 788         adev->mode_info.coherent_mode_property =
 789                 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1);
 790         if (!adev->mode_info.coherent_mode_property)
 791                 return -ENOMEM;
 792
 793         adev->mode_info.load_detect_property =
 794                 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1);
 795         if (!adev->mode_info.load_detect_property)
 796                 return -ENOMEM;
 797
 798         drm_mode_create_scaling_mode_property(adev_to_drm(adev));
 799
 800         sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
 801         adev->mode_info.underscan_property =
 802                 drm_property_create_enum(adev_to_drm(adev), 0,
 803                                          "underscan",
 804                                          amdgpu_underscan_enum_list, sz);
 805
 806         adev->mode_info.underscan_hborder_property =
 807                 drm_property_create_range(adev_to_drm(adev), 0,
 808                                           "underscan hborder", 0, 128);
 809         if (!adev->mode_info.underscan_hborder_property)
 810                 return -ENOMEM;
 811
 812         adev->mode_info.underscan_vborder_property =
 813                 drm_property_create_range(adev_to_drm(adev), 0,
 814                                           "underscan vborder", 0, 128);
 815         if (!adev->mode_info.underscan_vborder_property)
 816                 return -ENOMEM;
 817
 818         sz = ARRAY_SIZE(amdgpu_audio_enum_list);
 819         adev->mode_info.audio_property =
 820                 drm_property_create_enum(adev_to_drm(adev), 0,
 821                                          "audio",
 822                                          amdgpu_audio_enum_list, sz);
 823
 824         sz = ARRAY_SIZE(amdgpu_dither_enum_list);
 825         adev->mode_info.dither_property =
 826                 drm_property_create_enum(adev_to_drm(adev), 0,
 827                                          "dither",
 828                                          amdgpu_dither_enum_list, sz);
 829
 830         if (amdgpu_device_has_dc_support(adev)) {
 831                 adev->mode_info.abm_level_property =
 832                         drm_property_create_range(adev_to_drm(adev), 0,
 833                                                   "abm level", 0, 4);
 834                 if (!adev->mode_info.abm_level_property)
 835                         return -ENOMEM;
 836         }
 837
 838         return 0;
 839 }
 840
 841 void amdgpu_display_update_priority(struct amdgpu_device *adev)
 842 {
 843         /* adjustment options for the display watermarks */
 844         if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
 845                 adev->mode_info.disp_priority = 0;
 846         else
 847                 adev->mode_info.disp_priority = amdgpu_disp_priority;
 848
 849 }
 850
 851 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode)
 852 {
 853         /* try and guess if this is a tv or a monitor */
 854         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
 855             (mode->vdisplay == 576) || /* 576p */
 856             (mode->vdisplay == 720) || /* 720p */
 857             (mode->vdisplay == 1080)) /* 1080p */
 858                 return true;
 859         else
 860                 return false;
 861 }
 862
 863 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
 864                                         const struct drm_display_mode *mode,
 865                                         struct drm_display_mode *adjusted_mode)
 866 {
 867         struct drm_device *dev = crtc->dev;
 868         struct drm_encoder *encoder;
 869         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 870         struct amdgpu_encoder *amdgpu_encoder;
 871         struct drm_connector *connector;
 872         u32 src_v = 1, dst_v = 1;
 873         u32 src_h = 1, dst_h = 1;
 874
 875         amdgpu_crtc->h_border = 0;
 876         amdgpu_crtc->v_border = 0;
 877
 878         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 879                 if (encoder->crtc != crtc)
 880                         continue;
 881                 amdgpu_encoder = to_amdgpu_encoder(encoder);
 882                 connector = amdgpu_get_connector_for_encoder(encoder);
 883
 884                 /* set scaling */
 885                 if (amdgpu_encoder->rmx_type == RMX_OFF)
 886                         amdgpu_crtc->rmx_type = RMX_OFF;
 887                 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
 888                          mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
 889                         amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
 890                 else
 891                         amdgpu_crtc->rmx_type = RMX_OFF;
 892                 /* copy native mode */
 893                 memcpy(&amdgpu_crtc->native_mode,
 894                        &amdgpu_encoder->native_mode,
 895                        sizeof(struct drm_display_mode));
 896                 src_v = crtc->mode.vdisplay;
 897                 dst_v = amdgpu_crtc->native_mode.vdisplay;
 898                 src_h = crtc->mode.hdisplay;
 899                 dst_h = amdgpu_crtc->native_mode.hdisplay;
 900
 901                 /* fix up for overscan on hdmi */
 902                 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
 903                     ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
 904                      ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
 905                       drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
 906                       amdgpu_display_is_hdtv_mode(mode)))) {
 907                         if (amdgpu_encoder->underscan_hborder != 0)
 908                                 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
 909                         else
 910                                 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
 911                         if (amdgpu_encoder->underscan_vborder != 0)
 912                                 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
 913                         else
 914                                 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
 915                         amdgpu_crtc->rmx_type = RMX_FULL;
 916                         src_v = crtc->mode.vdisplay;
 917                         dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
 918                         src_h = crtc->mode.hdisplay;
 919                         dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
 920                 }
 921         }
 922         if (amdgpu_crtc->rmx_type != RMX_OFF) {
 923                 fixed20_12 a, b;
 924                 a.full = dfixed_const(src_v);
 925                 b.full = dfixed_const(dst_v);
 926                 amdgpu_crtc->vsc.full = dfixed_div(a, b);
 927                 a.full = dfixed_const(src_h);
 928                 b.full = dfixed_const(dst_h);
 929                 amdgpu_crtc->hsc.full = dfixed_div(a, b);
 930         } else {
 931                 amdgpu_crtc->vsc.full = dfixed_const(1);
 932                 amdgpu_crtc->hsc.full = dfixed_const(1);
 933         }
 934         return true;
 935 }
 936
 937 /*
 938  * Retrieve current video scanout position of crtc on a given gpu, and
 939  * an optional accurate timestamp of when query happened.
 940  *
 941  * \param dev Device to query.
 942  * \param pipe Crtc to query.
 943  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
 944  *              For driver internal use only also supports these flags:
 945  *
 946  *              USE_REAL_VBLANKSTART to use the real start of vblank instead
 947  *              of a fudged earlier start of vblank.
 948  *
 949  *              GET_DISTANCE_TO_VBLANKSTART to return distance to the
 950  *              fudged earlier start of vblank in *vpos and the distance
 951  *              to true start of vblank in *hpos.
 952  *
 953  * \param *vpos Location where vertical scanout position should be stored.
 954  * \param *hpos Location where horizontal scanout position should go.
 955  * \param *stime Target location for timestamp taken immediately before
 956  *               scanout position query. Can be NULL to skip timestamp.
 957  * \param *etime Target location for timestamp taken immediately after
 958  *               scanout position query. Can be NULL to skip timestamp.
 959  *
 960  * Returns vpos as a positive number while in active scanout area.
 961  * Returns vpos as a negative number inside vblank, counting the number
 962  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
 963  * until start of active scanout / end of vblank."
 964  *
 965  * \return Flags, or'ed together as follows:
 966  *
 967  * DRM_SCANOUTPOS_VALID = Query successful.
 968  * DRM_SCANOUTPOS_INVBL = Inside vblank.
 969  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
 970  * this flag means that returned position may be offset by a constant but
 971  * unknown small number of scanlines wrt. real scanout position.
 972  *
 973  */
 974 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,
 975                         unsigned int pipe, unsigned int flags, int *vpos,
 976                         int *hpos, ktime_t *stime, ktime_t *etime,
 977                         const struct drm_display_mode *mode)
 978 {
 979         u32 vbl = 0, position = 0;
 980         int vbl_start, vbl_end, vtotal, ret = 0;
 981         bool in_vbl = true;
 982
 983         struct amdgpu_device *adev = drm_to_adev(dev);
 984
 985         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 986
 987         /* Get optional system timestamp before query. */
 988         if (stime)
 989                 *stime = ktime_get();
 990
 991         if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
 992                 ret |= DRM_SCANOUTPOS_VALID;
 993
 994         /* Get optional system timestamp after query. */
 995         if (etime)
 996                 *etime = ktime_get();
 997
 998         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 999
1000         /* Decode into vertical and horizontal scanout position. */
1001         *vpos = position & 0x1fff;
1002         *hpos = (position >> 16) & 0x1fff;
1003
1004         /* Valid vblank area boundaries from gpu retrieved? */
1005         if (vbl > 0) {
1006                 /* Yes: Decode. */
1007                 ret |= DRM_SCANOUTPOS_ACCURATE;
1008                 vbl_start = vbl & 0x1fff;
1009                 vbl_end = (vbl >> 16) & 0x1fff;
1010         }
1011         else {
1012                 /* No: Fake something reasonable which gives at least ok results. */
1013                 vbl_start = mode->crtc_vdisplay;
1014                 vbl_end = 0;
1015         }
1016
1017         /* Called from driver internal vblank counter query code? */
1018         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1019             /* Caller wants distance from real vbl_start in *hpos */
1020             *hpos = *vpos - vbl_start;
1021         }
1022
1023         /* Fudge vblank to start a few scanlines earlier to handle the
1024          * problem that vblank irqs fire a few scanlines before start
1025          * of vblank. Some driver internal callers need the true vblank
1026          * start to be used and signal this via the USE_REAL_VBLANKSTART flag.
1027          *
1028          * The cause of the "early" vblank irq is that the irq is triggered
1029          * by the line buffer logic when the line buffer read position enters
1030          * the vblank, whereas our crtc scanout position naturally lags the
1031          * line buffer read position.
1032          */
1033         if (!(flags & USE_REAL_VBLANKSTART))
1034                 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines;
1035
1036         /* Test scanout position against vblank region. */
1037         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1038                 in_vbl = false;
1039
1040         /* In vblank? */
1041         if (in_vbl)
1042             ret |= DRM_SCANOUTPOS_IN_VBLANK;
1043
1044         /* Called from driver internal vblank counter query code? */
1045         if (flags & GET_DISTANCE_TO_VBLANKSTART) {
1046                 /* Caller wants distance from fudged earlier vbl_start */
1047                 *vpos -= vbl_start;
1048                 return ret;
1049         }
1050
1051         /* Check if inside vblank area and apply corrective offsets:
1052          * vpos will then be >=0 in video scanout area, but negative
1053          * within vblank area, counting down the number of lines until
1054          * start of scanout.
1055          */
1056
1057         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1058         if (in_vbl && (*vpos >= vbl_start)) {
1059                 vtotal = mode->crtc_vtotal;
1060
1061                 /* With variable refresh rate displays the vpos can exceed
1062                  * the vtotal value. Clamp to 0 to return -vbl_end instead
1063                  * of guessing the remaining number of lines until scanout.
1064                  */
1065                 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0;
1066         }
1067
1068         /* Correct for shifted end of vbl at vbl_end. */
1069         *vpos = *vpos - vbl_end;
1070
1071         return ret;
1072 }
1073
1074 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
1075 {
1076         if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
1077                 return AMDGPU_CRTC_IRQ_NONE;
1078
1079         switch (crtc) {
1080         case 0:
1081                 return AMDGPU_CRTC_IRQ_VBLANK1;
1082         case 1:
1083                 return AMDGPU_CRTC_IRQ_VBLANK2;
1084         case 2:
1085                 return AMDGPU_CRTC_IRQ_VBLANK3;
1086         case 3:
1087                 return AMDGPU_CRTC_IRQ_VBLANK4;
1088         case 4:
1089                 return AMDGPU_CRTC_IRQ_VBLANK5;
1090         case 5:
1091                 return AMDGPU_CRTC_IRQ_VBLANK6;
1092         default:
1093                 return AMDGPU_CRTC_IRQ_NONE;
1094         }
1095 }
1096
1097 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc,
1098                         bool in_vblank_irq, int *vpos,
1099                         int *hpos, ktime_t *stime, ktime_t *etime,
1100                         const struct drm_display_mode *mode)
1101 {
1102         struct drm_device *dev = crtc->dev;
1103         unsigned int pipe = crtc->index;
1104
1105         return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1106                                                   stime, etime, mode);
1107 }