1 // SPDX-License-Identifier: GPL-2.0-only
3 * Confidential Computing Platform Capability checks
5 * Copyright (C) 2021 Advanced Micro Devices, Inc.
10 #include <linux/export.h>
11 #include <linux/cc_platform.h>
14 #include <asm/processor.h>
16 enum cc_vendor cc_vendor __ro_after_init;
17 static u64 cc_mask __ro_after_init;
19 static bool intel_cc_platform_has(enum cc_attr attr)
22 case CC_ATTR_GUEST_UNROLL_STRING_IO:
23 case CC_ATTR_HOTPLUG_DISABLED:
24 case CC_ATTR_GUEST_MEM_ENCRYPT:
25 case CC_ATTR_MEM_ENCRYPT:
33 * Handle the SEV-SNP vTOM case where sme_me_mask is zero, and
34 * the other levels of SME/SEV functionality, including C-bit
35 * based SEV-SNP, are not enabled.
37 static __maybe_unused bool amd_cc_platform_vtom(enum cc_attr attr)
40 case CC_ATTR_GUEST_MEM_ENCRYPT:
41 case CC_ATTR_MEM_ENCRYPT:
49 * SME and SEV are very similar but they are not the same, so there are
50 * times that the kernel will need to distinguish between SME and SEV. The
51 * cc_platform_has() function is used for this. When a distinction isn't
52 * needed, the CC_ATTR_MEM_ENCRYPT attribute can be used.
54 * The trampoline code is a good example for this requirement. Before
55 * paging is activated, SME will access all memory as decrypted, but SEV
56 * will access all memory as encrypted. So, when APs are being brought
57 * up under SME the trampoline area cannot be encrypted, whereas under SEV
58 * the trampoline area must be encrypted.
61 static bool amd_cc_platform_has(enum cc_attr attr)
63 #ifdef CONFIG_AMD_MEM_ENCRYPT
65 if (sev_status & MSR_AMD64_SNP_VTOM)
66 return amd_cc_platform_vtom(attr);
69 case CC_ATTR_MEM_ENCRYPT:
72 case CC_ATTR_HOST_MEM_ENCRYPT:
73 return sme_me_mask && !(sev_status & MSR_AMD64_SEV_ENABLED);
75 case CC_ATTR_GUEST_MEM_ENCRYPT:
76 return sev_status & MSR_AMD64_SEV_ENABLED;
78 case CC_ATTR_GUEST_STATE_ENCRYPT:
79 return sev_status & MSR_AMD64_SEV_ES_ENABLED;
82 * With SEV, the rep string I/O instructions need to be unrolled
83 * but SEV-ES supports them through the #VC handler.
85 case CC_ATTR_GUEST_UNROLL_STRING_IO:
86 return (sev_status & MSR_AMD64_SEV_ENABLED) &&
87 !(sev_status & MSR_AMD64_SEV_ES_ENABLED);
89 case CC_ATTR_GUEST_SEV_SNP:
90 return sev_status & MSR_AMD64_SEV_SNP_ENABLED;
100 bool cc_platform_has(enum cc_attr attr)
104 return amd_cc_platform_has(attr);
105 case CC_VENDOR_INTEL:
106 return intel_cc_platform_has(attr);
111 EXPORT_SYMBOL_GPL(cc_platform_has);
113 u64 cc_mkenc(u64 val)
116 * Both AMD and Intel use a bit in the page table to indicate
117 * encryption status of the page.
119 * - for AMD, bit *set* means the page is encrypted
120 * - for AMD with vTOM and for Intel, *clear* means encrypted
124 if (sev_status & MSR_AMD64_SNP_VTOM)
125 return val & ~cc_mask;
127 return val | cc_mask;
128 case CC_VENDOR_INTEL:
129 return val & ~cc_mask;
135 u64 cc_mkdec(u64 val)
137 /* See comment in cc_mkenc() */
140 if (sev_status & MSR_AMD64_SNP_VTOM)
141 return val | cc_mask;
143 return val & ~cc_mask;
144 case CC_VENDOR_INTEL:
145 return val | cc_mask;
150 EXPORT_SYMBOL_GPL(cc_mkdec);
152 __init void cc_set_mask(u64 mask)