drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/delay.h>
  24 #include <linux/kernel.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_smu.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "imu_v11_0.h"
  34 #include "soc21.h"
  35 #include "nvd.h"
  36
  37 #include "gc/gc_11_0_0_offset.h"
  38 #include "gc/gc_11_0_0_sh_mask.h"
  39 #include "smuio/smuio_13_0_6_offset.h"
  40 #include "smuio/smuio_13_0_6_sh_mask.h"
  41 #include "navi10_enum.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "clearstate_gfx11.h"
  47 #include "v11_structs.h"
  48 #include "gfx_v11_0.h"
  49 #include "gfx_v11_0_3.h"
  50 #include "nbio_v4_3.h"
  51 #include "mes_v11_0.h"
  52
  53 #define GFX11_NUM_GFX_RINGS             1
  54 #define GFX11_MEC_HPD_SIZE      2048
  55
  56 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1        0x1388
  58
  59 #define regCGTT_WD_CLK_CTRL             0x5086
  60 #define regCGTT_WD_CLK_CTRL_BASE_IDX    1
  61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1   0x4e7e
  62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX  1
  63 #define regPC_CONFIG_CNTL_1             0x194d
  64 #define regPC_CONFIG_CNTL_1_BASE_IDX    1
  65
  66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
  67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
  68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
  69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
  70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
  71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
  72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
  73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
  74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
  75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
  76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
  77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
  78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
  79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
  80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
  81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
  82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
  83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
  84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
  85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
  86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
  87 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin");
  88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
  89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
  90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
  91
  92 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
  93 {
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
 103 };
 104
 105 static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x8000b007),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f)
 120 };
 121
 122 #define DEFAULT_SH_MEM_CONFIG \
 123         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 124          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 125          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 126
 127 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
 128 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
 129 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
 130 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
 131 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
 132 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
 133 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
 134 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
 135                                  struct amdgpu_cu_info *cu_info);
 136 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 137 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 138                                    u32 sh_num, u32 instance, int xcc_id);
 139 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 140
 141 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 142 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 143 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 144                                      uint32_t val);
 145 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 146 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 147                                            uint16_t pasid, uint32_t flush_type,
 148                                            bool all_hub, uint8_t dst_sel);
 149 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
 150 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
 151 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
 152                                       bool enable);
 153
 154 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 155 {
 156         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 157         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 158                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 159         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 160         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 161         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 162         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 163         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 164         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 165 }
 166
 167 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 168                                  struct amdgpu_ring *ring)
 169 {
 170         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 171         uint64_t wptr_addr = ring->wptr_gpu_addr;
 172         uint32_t me = 0, eng_sel = 0;
 173
 174         switch (ring->funcs->type) {
 175         case AMDGPU_RING_TYPE_COMPUTE:
 176                 me = 1;
 177                 eng_sel = 0;
 178                 break;
 179         case AMDGPU_RING_TYPE_GFX:
 180                 me = 0;
 181                 eng_sel = 4;
 182                 break;
 183         case AMDGPU_RING_TYPE_MES:
 184                 me = 2;
 185                 eng_sel = 5;
 186                 break;
 187         default:
 188                 WARN_ON(1);
 189         }
 190
 191         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 192         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 193         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 194                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 195                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 196                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 197                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 198                           PACKET3_MAP_QUEUES_ME((me)) |
 199                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 200                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 201                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 202                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 203         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 204         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 205         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 206         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 207         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 208 }
 209
 210 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 211                                    struct amdgpu_ring *ring,
 212                                    enum amdgpu_unmap_queues_action action,
 213                                    u64 gpu_addr, u64 seq)
 214 {
 215         struct amdgpu_device *adev = kiq_ring->adev;
 216         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 217
 218         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
 219                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
 220                 return;
 221         }
 222
 223         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 224         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 225                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 226                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 227                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 228                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 229         amdgpu_ring_write(kiq_ring,
 230                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 231
 232         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 233                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 234                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 235                 amdgpu_ring_write(kiq_ring, seq);
 236         } else {
 237                 amdgpu_ring_write(kiq_ring, 0);
 238                 amdgpu_ring_write(kiq_ring, 0);
 239                 amdgpu_ring_write(kiq_ring, 0);
 240         }
 241 }
 242
 243 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
 244                                    struct amdgpu_ring *ring,
 245                                    u64 addr,
 246                                    u64 seq)
 247 {
 248         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 249
 250         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 251         amdgpu_ring_write(kiq_ring,
 252                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 253                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 254                           PACKET3_QUERY_STATUS_COMMAND(2));
 255         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 256                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 257                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 258         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 259         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 260         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 261         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 262 }
 263
 264 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 265                                 uint16_t pasid, uint32_t flush_type,
 266                                 bool all_hub)
 267 {
 268         gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 269 }
 270
 271 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
 272         .kiq_set_resources = gfx11_kiq_set_resources,
 273         .kiq_map_queues = gfx11_kiq_map_queues,
 274         .kiq_unmap_queues = gfx11_kiq_unmap_queues,
 275         .kiq_query_status = gfx11_kiq_query_status,
 276         .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
 277         .set_resources_size = 8,
 278         .map_queues_size = 7,
 279         .unmap_queues_size = 6,
 280         .query_status_size = 7,
 281         .invalidate_tlbs_size = 2,
 282 };
 283
 284 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 285 {
 286         adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;
 287 }
 288
 289 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 290 {
 291         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 292         case IP_VERSION(11, 0, 1):
 293         case IP_VERSION(11, 0, 4):
 294                 soc15_program_register_sequence(adev,
 295                                                 golden_settings_gc_11_0_1,
 296                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
 297                 break;
 298         case IP_VERSION(11, 5, 0):
 299                 soc15_program_register_sequence(adev,
 300                                                 golden_settings_gc_11_5_0,
 301                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0));
 302                 break;
 303         default:
 304                 break;
 305         }
 306 }
 307
 308 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 309                                        bool wc, uint32_t reg, uint32_t val)
 310 {
 311         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 312         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 313                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 314         amdgpu_ring_write(ring, reg);
 315         amdgpu_ring_write(ring, 0);
 316         amdgpu_ring_write(ring, val);
 317 }
 318
 319 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 320                                   int mem_space, int opt, uint32_t addr0,
 321                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 322                                   uint32_t inv)
 323 {
 324         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 325         amdgpu_ring_write(ring,
 326                           /* memory (1) or register (0) */
 327                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 328                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 329                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 330                            WAIT_REG_MEM_ENGINE(eng_sel)));
 331
 332         if (mem_space)
 333                 BUG_ON(addr0 & 0x3); /* Dword align */
 334         amdgpu_ring_write(ring, addr0);
 335         amdgpu_ring_write(ring, addr1);
 336         amdgpu_ring_write(ring, ref);
 337         amdgpu_ring_write(ring, mask);
 338         amdgpu_ring_write(ring, inv); /* poll interval */
 339 }
 340
 341 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 342 {
 343         struct amdgpu_device *adev = ring->adev;
 344         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 345         uint32_t tmp = 0;
 346         unsigned i;
 347         int r;
 348
 349         WREG32(scratch, 0xCAFEDEAD);
 350         r = amdgpu_ring_alloc(ring, 5);
 351         if (r) {
 352                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 353                           ring->idx, r);
 354                 return r;
 355         }
 356
 357         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
 358                 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
 359         } else {
 360                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 361                 amdgpu_ring_write(ring, scratch -
 362                                   PACKET3_SET_UCONFIG_REG_START);
 363                 amdgpu_ring_write(ring, 0xDEADBEEF);
 364         }
 365         amdgpu_ring_commit(ring);
 366
 367         for (i = 0; i < adev->usec_timeout; i++) {
 368                 tmp = RREG32(scratch);
 369                 if (tmp == 0xDEADBEEF)
 370                         break;
 371                 if (amdgpu_emu_mode == 1)
 372                         msleep(1);
 373                 else
 374                         udelay(1);
 375         }
 376
 377         if (i >= adev->usec_timeout)
 378                 r = -ETIMEDOUT;
 379         return r;
 380 }
 381
 382 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 383 {
 384         struct amdgpu_device *adev = ring->adev;
 385         struct amdgpu_ib ib;
 386         struct dma_fence *f = NULL;
 387         unsigned index;
 388         uint64_t gpu_addr;
 389         volatile uint32_t *cpu_ptr;
 390         long r;
 391
 392         /* MES KIQ fw hasn't indirect buffer support for now */
 393         if (adev->enable_mes_kiq &&
 394             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 395                 return 0;
 396
 397         memset(&ib, 0, sizeof(ib));
 398
 399         if (ring->is_mes_queue) {
 400                 uint32_t padding, offset;
 401
 402                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 403                 padding = amdgpu_mes_ctx_get_offs(ring,
 404                                                   AMDGPU_MES_CTX_PADDING_OFFS);
 405
 406                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 407                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 408
 409                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
 410                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
 411                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
 412         } else {
 413                 r = amdgpu_device_wb_get(adev, &index);
 414                 if (r)
 415                         return r;
 416
 417                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 418                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 419                 cpu_ptr = &adev->wb.wb[index];
 420
 421                 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
 422                 if (r) {
 423                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 424                         goto err1;
 425                 }
 426         }
 427
 428         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 429         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 430         ib.ptr[2] = lower_32_bits(gpu_addr);
 431         ib.ptr[3] = upper_32_bits(gpu_addr);
 432         ib.ptr[4] = 0xDEADBEEF;
 433         ib.length_dw = 5;
 434
 435         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 436         if (r)
 437                 goto err2;
 438
 439         r = dma_fence_wait_timeout(f, false, timeout);
 440         if (r == 0) {
 441                 r = -ETIMEDOUT;
 442                 goto err2;
 443         } else if (r < 0) {
 444                 goto err2;
 445         }
 446
 447         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 448                 r = 0;
 449         else
 450                 r = -EINVAL;
 451 err2:
 452         if (!ring->is_mes_queue)
 453                 amdgpu_ib_free(adev, &ib, NULL);
 454         dma_fence_put(f);
 455 err1:
 456         if (!ring->is_mes_queue)
 457                 amdgpu_device_wb_free(adev, index);
 458         return r;
 459 }
 460
 461 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
 462 {
 463         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 464         amdgpu_ucode_release(&adev->gfx.me_fw);
 465         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 466         amdgpu_ucode_release(&adev->gfx.mec_fw);
 467
 468         kfree(adev->gfx.rlc.register_list_format);
 469 }
 470
 471 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
 472 {
 473         const struct psp_firmware_header_v1_0 *toc_hdr;
 474         int err = 0;
 475         char fw_name[40];
 476
 477         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);
 478         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
 479         if (err)
 480                 goto out;
 481
 482         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 483         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
 484         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 485         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 486         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
 487                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
 488         return 0;
 489 out:
 490         amdgpu_ucode_release(&adev->psp.toc_fw);
 491         return err;
 492 }
 493
 494 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev)
 495 {
 496         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 497         case IP_VERSION(11, 0, 0):
 498         case IP_VERSION(11, 0, 2):
 499         case IP_VERSION(11, 0, 3):
 500                 if ((adev->gfx.me_fw_version >= 1505) &&
 501                     (adev->gfx.pfp_fw_version >= 1600) &&
 502                     (adev->gfx.mec_fw_version >= 512)) {
 503                         if (amdgpu_sriov_vf(adev))
 504                                 adev->gfx.cp_gfx_shadow = true;
 505                         else
 506                                 adev->gfx.cp_gfx_shadow = false;
 507                 }
 508                 break;
 509         default:
 510                 adev->gfx.cp_gfx_shadow = false;
 511                 break;
 512         }
 513 }
 514
 515 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 516 {
 517         char fw_name[40];
 518         char ucode_prefix[30];
 519         int err;
 520         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 521         uint16_t version_major;
 522         uint16_t version_minor;
 523
 524         DRM_DEBUG("\n");
 525
 526         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 527
 528         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);
 529         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
 530         if (err)
 531                 goto out;
 532         /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
 533         adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
 534                                 (union amdgpu_firmware_header *)
 535                                 adev->gfx.pfp_fw->data, 2, 0);
 536         if (adev->gfx.rs64_enable) {
 537                 dev_info(adev->dev, "CP RS64 enable\n");
 538                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
 539                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 540                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
 541         } else {
 542                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 543         }
 544
 545         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
 546         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
 547         if (err)
 548                 goto out;
 549         if (adev->gfx.rs64_enable) {
 550                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
 551                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
 552                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
 553         } else {
 554                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 555         }
 556
 557         if (!amdgpu_sriov_vf(adev)) {
 558                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
 559                 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 560                 if (err)
 561                         goto out;
 562                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 563                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 564                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 565                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 566                 if (err)
 567                         goto out;
 568         }
 569
 570         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
 571         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 572         if (err)
 573                 goto out;
 574         if (adev->gfx.rs64_enable) {
 575                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
 576                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
 577                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
 578                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
 579                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
 580         } else {
 581                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 582                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 583         }
 584
 585         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
 586                 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix);
 587
 588         /* only one MEC for gfx 11.0.0. */
 589         adev->gfx.mec2_fw = NULL;
 590
 591         gfx_v11_0_check_fw_cp_gfx_shadow(adev);
 592
 593         if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) {
 594                 err = adev->gfx.imu.funcs->init_microcode(adev);
 595                 if (err)
 596                         DRM_ERROR("Failed to init imu firmware!\n");
 597                 return err;
 598         }
 599
 600 out:
 601         if (err) {
 602                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
 603                 amdgpu_ucode_release(&adev->gfx.me_fw);
 604                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 605                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 606         }
 607
 608         return err;
 609 }
 610
 611 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
 612 {
 613         u32 count = 0;
 614         const struct cs_section_def *sect = NULL;
 615         const struct cs_extent_def *ext = NULL;
 616
 617         /* begin clear state */
 618         count += 2;
 619         /* context control state */
 620         count += 3;
 621
 622         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
 623                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 624                         if (sect->id == SECT_CONTEXT)
 625                                 count += 2 + ext->reg_count;
 626                         else
 627                                 return 0;
 628                 }
 629         }
 630
 631         /* set PA_SC_TILE_STEERING_OVERRIDE */
 632         count += 3;
 633         /* end clear state */
 634         count += 2;
 635         /* clear state */
 636         count += 2;
 637
 638         return count;
 639 }
 640
 641 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
 642                                     volatile u32 *buffer)
 643 {
 644         u32 count = 0, i;
 645         const struct cs_section_def *sect = NULL;
 646         const struct cs_extent_def *ext = NULL;
 647         int ctx_reg_offset;
 648
 649         if (adev->gfx.rlc.cs_data == NULL)
 650                 return;
 651         if (buffer == NULL)
 652                 return;
 653
 654         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 655         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 656
 657         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 658         buffer[count++] = cpu_to_le32(0x80000000);
 659         buffer[count++] = cpu_to_le32(0x80000000);
 660
 661         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 662                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 663                         if (sect->id == SECT_CONTEXT) {
 664                                 buffer[count++] =
 665                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 666                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 667                                                 PACKET3_SET_CONTEXT_REG_START);
 668                                 for (i = 0; i < ext->reg_count; i++)
 669                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 670                         } else {
 671                                 return;
 672                         }
 673                 }
 674         }
 675
 676         ctx_reg_offset =
 677                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 678         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 679         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 680         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 681
 682         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 683         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 684
 685         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 686         buffer[count++] = cpu_to_le32(0);
 687 }
 688
 689 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
 690 {
 691         /* clear state block */
 692         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 693                         &adev->gfx.rlc.clear_state_gpu_addr,
 694                         (void **)&adev->gfx.rlc.cs_ptr);
 695
 696         /* jump table block */
 697         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 698                         &adev->gfx.rlc.cp_table_gpu_addr,
 699                         (void **)&adev->gfx.rlc.cp_table_ptr);
 700 }
 701
 702 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 703 {
 704         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 705
 706         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
 707         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 708         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
 709         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
 710         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
 711         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
 712         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
 713         reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
 714         adev->gfx.rlc.rlcg_reg_access_supported = true;
 715 }
 716
 717 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 718 {
 719         const struct cs_section_def *cs_data;
 720         int r;
 721
 722         adev->gfx.rlc.cs_data = gfx11_cs_data;
 723
 724         cs_data = adev->gfx.rlc.cs_data;
 725
 726         if (cs_data) {
 727                 /* init clear state block */
 728                 r = amdgpu_gfx_rlc_init_csb(adev);
 729                 if (r)
 730                         return r;
 731         }
 732
 733         /* init spm vmid with 0xf */
 734         if (adev->gfx.rlc.funcs->update_spm_vmid)
 735                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
 736
 737         return 0;
 738 }
 739
 740 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
 741 {
 742         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 743         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 744         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
 745 }
 746
 747 static void gfx_v11_0_me_init(struct amdgpu_device *adev)
 748 {
 749         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 750
 751         amdgpu_gfx_graphics_queue_acquire(adev);
 752 }
 753
 754 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
 755 {
 756         int r;
 757         u32 *hpd;
 758         size_t mec_hpd_size;
 759
 760         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 761
 762         /* take ownership of the relevant compute queues */
 763         amdgpu_gfx_compute_queue_acquire(adev);
 764         mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
 765
 766         if (mec_hpd_size) {
 767                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 768                                               AMDGPU_GEM_DOMAIN_GTT,
 769                                               &adev->gfx.mec.hpd_eop_obj,
 770                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 771                                               (void **)&hpd);
 772                 if (r) {
 773                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 774                         gfx_v11_0_mec_fini(adev);
 775                         return r;
 776                 }
 777
 778                 memset(hpd, 0, mec_hpd_size);
 779
 780                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 781                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 782         }
 783
 784         return 0;
 785 }
 786
 787 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 788 {
 789         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 790                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 791                 (address << SQ_IND_INDEX__INDEX__SHIFT));
 792         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 793 }
 794
 795 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 796                            uint32_t thread, uint32_t regno,
 797                            uint32_t num, uint32_t *out)
 798 {
 799         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 800                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 801                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 802                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 803                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 804         while (num--)
 805                 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 806 }
 807
 808 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 809 {
 810         /* in gfx11 the SIMD_ID is specified as part of the INSTANCE
 811          * field when performing a select_se_sh so it should be
 812          * zero here */
 813         WARN_ON(simd != 0);
 814
 815         /* type 3 wave data */
 816         dst[(*no_fields)++] = 3;
 817         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 818         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 819         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 820         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 821         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 822         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 823         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 824         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 825         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 826         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
 827         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
 828         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 829         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 830         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
 831         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 832 }
 833
 834 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 835                                      uint32_t wave, uint32_t start,
 836                                      uint32_t size, uint32_t *dst)
 837 {
 838         WARN_ON(simd != 0);
 839
 840         wave_read_regs(
 841                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
 842                 dst);
 843 }
 844
 845 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 846                                       uint32_t wave, uint32_t thread,
 847                                       uint32_t start, uint32_t size,
 848                                       uint32_t *dst)
 849 {
 850         wave_read_regs(
 851                 adev, wave, thread,
 852                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 853 }
 854
 855 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
 856                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 857 {
 858         soc21_grbm_select(adev, me, pipe, q, vm);
 859 }
 860
 861 /* all sizes are in bytes */
 862 #define MQD_SHADOW_BASE_SIZE      73728
 863 #define MQD_SHADOW_BASE_ALIGNMENT 256
 864 #define MQD_FWWORKAREA_SIZE       484
 865 #define MQD_FWWORKAREA_ALIGNMENT  256
 866
 867 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
 868                                          struct amdgpu_gfx_shadow_info *shadow_info)
 869 {
 870         if (adev->gfx.cp_gfx_shadow) {
 871                 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
 872                 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
 873                 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
 874                 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
 875                 return 0;
 876         } else {
 877                 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
 878                 return -ENOTSUPP;
 879         }
 880 }
 881
 882 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
 883         .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
 884         .select_se_sh = &gfx_v11_0_select_se_sh,
 885         .read_wave_data = &gfx_v11_0_read_wave_data,
 886         .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
 887         .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
 888         .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
 889         .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
 890         .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info,
 891 };
 892
 893 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
 894 {
 895         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 896         case IP_VERSION(11, 0, 0):
 897         case IP_VERSION(11, 0, 2):
 898                 adev->gfx.config.max_hw_contexts = 8;
 899                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 900                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 901                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 902                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 903                 break;
 904         case IP_VERSION(11, 0, 3):
 905                 adev->gfx.ras = &gfx_v11_0_3_ras;
 906                 adev->gfx.config.max_hw_contexts = 8;
 907                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 908                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 909                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 910                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 911                 break;
 912         case IP_VERSION(11, 0, 1):
 913         case IP_VERSION(11, 0, 4):
 914         case IP_VERSION(11, 5, 0):
 915                 adev->gfx.config.max_hw_contexts = 8;
 916                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 917                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 918                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
 919                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
 920                 break;
 921         default:
 922                 BUG();
 923                 break;
 924         }
 925
 926         return 0;
 927 }
 928
 929 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 930                                    int me, int pipe, int queue)
 931 {
 932         int r;
 933         struct amdgpu_ring *ring;
 934         unsigned int irq_type;
 935
 936         ring = &adev->gfx.gfx_ring[ring_id];
 937
 938         ring->me = me;
 939         ring->pipe = pipe;
 940         ring->queue = queue;
 941
 942         ring->ring_obj = NULL;
 943         ring->use_doorbell = true;
 944
 945         if (!ring_id)
 946                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
 947         else
 948                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
 949         ring->vm_hub = AMDGPU_GFXHUB(0);
 950         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 951
 952         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
 953         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 954                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 955         if (r)
 956                 return r;
 957         return 0;
 958 }
 959
 960 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 961                                        int mec, int pipe, int queue)
 962 {
 963         int r;
 964         unsigned irq_type;
 965         struct amdgpu_ring *ring;
 966         unsigned int hw_prio;
 967
 968         ring = &adev->gfx.compute_ring[ring_id];
 969
 970         /* mec0 is me1 */
 971         ring->me = mec + 1;
 972         ring->pipe = pipe;
 973         ring->queue = queue;
 974
 975         ring->ring_obj = NULL;
 976         ring->use_doorbell = true;
 977         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
 978         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
 979                                 + (ring_id * GFX11_MEC_HPD_SIZE);
 980         ring->vm_hub = AMDGPU_GFXHUB(0);
 981         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 982
 983         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 984                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 985                 + ring->pipe;
 986         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 987                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 988         /* type-2 packets are deprecated on MEC, use type-3 instead */
 989         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 990                              hw_prio, NULL);
 991         if (r)
 992                 return r;
 993
 994         return 0;
 995 }
 996
 997 static struct {
 998         SOC21_FIRMWARE_ID       id;
 999         unsigned int            offset;
1000         unsigned int            size;
1001 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
1002
1003 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1004 {
1005         RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
1006
1007         while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
1008                         (ucode->id < SOC21_FIRMWARE_ID_MAX)) {
1009                 rlc_autoload_info[ucode->id].id = ucode->id;
1010                 rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
1011                 rlc_autoload_info[ucode->id].size = ucode->size * 4;
1012
1013                 ucode++;
1014         }
1015 }
1016
1017 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
1018 {
1019         uint32_t total_size = 0;
1020         SOC21_FIRMWARE_ID id;
1021
1022         gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1023
1024         for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
1025                 total_size += rlc_autoload_info[id].size;
1026
1027         /* In case the offset in rlc toc ucode is aligned */
1028         if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
1029                 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
1030                         rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
1031
1032         return total_size;
1033 }
1034
1035 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1036 {
1037         int r;
1038         uint32_t total_size;
1039
1040         total_size = gfx_v11_0_calc_toc_total_size(adev);
1041
1042         r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1043                                       AMDGPU_GEM_DOMAIN_VRAM |
1044                                       AMDGPU_GEM_DOMAIN_GTT,
1045                                       &adev->gfx.rlc.rlc_autoload_bo,
1046                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1047                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1048
1049         if (r) {
1050                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1051                 return r;
1052         }
1053
1054         return 0;
1055 }
1056
1057 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1058                                               SOC21_FIRMWARE_ID id,
1059                                               const void *fw_data,
1060                                               uint32_t fw_size,
1061                                               uint32_t *fw_autoload_mask)
1062 {
1063         uint32_t toc_offset;
1064         uint32_t toc_fw_size;
1065         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1066
1067         if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
1068                 return;
1069
1070         toc_offset = rlc_autoload_info[id].offset;
1071         toc_fw_size = rlc_autoload_info[id].size;
1072
1073         if (fw_size == 0)
1074                 fw_size = toc_fw_size;
1075
1076         if (fw_size > toc_fw_size)
1077                 fw_size = toc_fw_size;
1078
1079         memcpy(ptr + toc_offset, fw_data, fw_size);
1080
1081         if (fw_size < toc_fw_size)
1082                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1083
1084         if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1085                 *(uint64_t *)fw_autoload_mask |= 1ULL << id;
1086 }
1087
1088 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1089                                                         uint32_t *fw_autoload_mask)
1090 {
1091         void *data;
1092         uint32_t size;
1093         uint64_t *toc_ptr;
1094
1095         *(uint64_t *)fw_autoload_mask |= 0x1;
1096
1097         DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1098
1099         data = adev->psp.toc.start_addr;
1100         size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1101
1102         toc_ptr = (uint64_t *)data + size / 8 - 1;
1103         *toc_ptr = *(uint64_t *)fw_autoload_mask;
1104
1105         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1106                                         data, size, fw_autoload_mask);
1107 }
1108
1109 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1110                                                         uint32_t *fw_autoload_mask)
1111 {
1112         const __le32 *fw_data;
1113         uint32_t fw_size;
1114         const struct gfx_firmware_header_v1_0 *cp_hdr;
1115         const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1116         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1117         const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1118         uint16_t version_major, version_minor;
1119
1120         if (adev->gfx.rs64_enable) {
1121                 /* pfp ucode */
1122                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1123                         adev->gfx.pfp_fw->data;
1124                 /* instruction */
1125                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1126                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1127                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1128                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1129                                                 fw_data, fw_size, fw_autoload_mask);
1130                 /* data */
1131                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1132                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1133                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1134                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1135                                                 fw_data, fw_size, fw_autoload_mask);
1136                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1137                                                 fw_data, fw_size, fw_autoload_mask);
1138                 /* me ucode */
1139                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1140                         adev->gfx.me_fw->data;
1141                 /* instruction */
1142                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1143                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1144                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1145                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1146                                                 fw_data, fw_size, fw_autoload_mask);
1147                 /* data */
1148                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1149                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1150                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1151                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1152                                                 fw_data, fw_size, fw_autoload_mask);
1153                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1154                                                 fw_data, fw_size, fw_autoload_mask);
1155                 /* mec ucode */
1156                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1157                         adev->gfx.mec_fw->data;
1158                 /* instruction */
1159                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1160                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1161                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1162                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1163                                                 fw_data, fw_size, fw_autoload_mask);
1164                 /* data */
1165                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1166                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1167                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1168                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1169                                                 fw_data, fw_size, fw_autoload_mask);
1170                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1171                                                 fw_data, fw_size, fw_autoload_mask);
1172                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1173                                                 fw_data, fw_size, fw_autoload_mask);
1174                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1175                                                 fw_data, fw_size, fw_autoload_mask);
1176         } else {
1177                 /* pfp ucode */
1178                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1179                         adev->gfx.pfp_fw->data;
1180                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1181                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1182                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1183                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1184                                                 fw_data, fw_size, fw_autoload_mask);
1185
1186                 /* me ucode */
1187                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1188                         adev->gfx.me_fw->data;
1189                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1190                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1191                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1192                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1193                                                 fw_data, fw_size, fw_autoload_mask);
1194
1195                 /* mec ucode */
1196                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1197                         adev->gfx.mec_fw->data;
1198                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1199                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1200                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1201                         cp_hdr->jt_size * 4;
1202                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1203                                                 fw_data, fw_size, fw_autoload_mask);
1204         }
1205
1206         /* rlc ucode */
1207         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1208                 adev->gfx.rlc_fw->data;
1209         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1210                         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1211         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1212         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1213                                         fw_data, fw_size, fw_autoload_mask);
1214
1215         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1216         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1217         if (version_major == 2) {
1218                 if (version_minor >= 2) {
1219                         rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1220
1221                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1222                                         le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1223                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1224                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1225                                         fw_data, fw_size, fw_autoload_mask);
1226
1227                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1228                                         le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1229                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1230                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1231                                         fw_data, fw_size, fw_autoload_mask);
1232                 }
1233         }
1234 }
1235
1236 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1237                                                         uint32_t *fw_autoload_mask)
1238 {
1239         const __le32 *fw_data;
1240         uint32_t fw_size;
1241         const struct sdma_firmware_header_v2_0 *sdma_hdr;
1242
1243         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1244                 adev->sdma.instance[0].fw->data;
1245         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1246                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1247         fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1248
1249         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1250                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1251
1252         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1253                         le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1254         fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1255
1256         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1257                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1258 }
1259
1260 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1261                                                         uint32_t *fw_autoload_mask)
1262 {
1263         const __le32 *fw_data;
1264         unsigned fw_size;
1265         const struct mes_firmware_header_v1_0 *mes_hdr;
1266         int pipe, ucode_id, data_id;
1267
1268         for (pipe = 0; pipe < 2; pipe++) {
1269                 if (pipe==0) {
1270                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1271                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1272                 } else {
1273                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1274                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1275                 }
1276
1277                 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1278                         adev->mes.fw[pipe]->data;
1279
1280                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1281                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1282                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1283
1284                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1285                                 ucode_id, fw_data, fw_size, fw_autoload_mask);
1286
1287                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1288                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1289                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1290
1291                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1292                                 data_id, fw_data, fw_size, fw_autoload_mask);
1293         }
1294 }
1295
1296 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1297 {
1298         uint32_t rlc_g_offset, rlc_g_size;
1299         uint64_t gpu_addr;
1300         uint32_t autoload_fw_id[2];
1301
1302         memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1303
1304         /* RLC autoload sequence 2: copy ucode */
1305         gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1306         gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1307         gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1308         gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1309
1310         rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1311         rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1312         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1313
1314         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1315         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1316
1317         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1318
1319         /* RLC autoload sequence 3: load IMU fw */
1320         if (adev->gfx.imu.funcs->load_microcode)
1321                 adev->gfx.imu.funcs->load_microcode(adev);
1322         /* RLC autoload sequence 4 init IMU fw */
1323         if (adev->gfx.imu.funcs->setup_imu)
1324                 adev->gfx.imu.funcs->setup_imu(adev);
1325         if (adev->gfx.imu.funcs->start_imu)
1326                 adev->gfx.imu.funcs->start_imu(adev);
1327
1328         /* RLC autoload sequence 5 disable gpa mode */
1329         gfx_v11_0_disable_gpa_mode(adev);
1330
1331         return 0;
1332 }
1333
1334 static int gfx_v11_0_sw_init(void *handle)
1335 {
1336         int i, j, k, r, ring_id = 0;
1337         struct amdgpu_kiq *kiq;
1338         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1339
1340         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1341         case IP_VERSION(11, 0, 0):
1342         case IP_VERSION(11, 0, 2):
1343         case IP_VERSION(11, 0, 3):
1344                 adev->gfx.me.num_me = 1;
1345                 adev->gfx.me.num_pipe_per_me = 1;
1346                 adev->gfx.me.num_queue_per_pipe = 1;
1347                 adev->gfx.mec.num_mec = 2;
1348                 adev->gfx.mec.num_pipe_per_mec = 4;
1349                 adev->gfx.mec.num_queue_per_pipe = 4;
1350                 break;
1351         case IP_VERSION(11, 0, 1):
1352         case IP_VERSION(11, 0, 4):
1353         case IP_VERSION(11, 5, 0):
1354                 adev->gfx.me.num_me = 1;
1355                 adev->gfx.me.num_pipe_per_me = 1;
1356                 adev->gfx.me.num_queue_per_pipe = 1;
1357                 adev->gfx.mec.num_mec = 1;
1358                 adev->gfx.mec.num_pipe_per_mec = 4;
1359                 adev->gfx.mec.num_queue_per_pipe = 4;
1360                 break;
1361         default:
1362                 adev->gfx.me.num_me = 1;
1363                 adev->gfx.me.num_pipe_per_me = 1;
1364                 adev->gfx.me.num_queue_per_pipe = 1;
1365                 adev->gfx.mec.num_mec = 1;
1366                 adev->gfx.mec.num_pipe_per_mec = 4;
1367                 adev->gfx.mec.num_queue_per_pipe = 8;
1368                 break;
1369         }
1370
1371         /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */
1372         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &&
1373             amdgpu_sriov_is_pp_one_vf(adev))
1374                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG;
1375
1376         /* EOP Event */
1377         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1378                               GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1379                               &adev->gfx.eop_irq);
1380         if (r)
1381                 return r;
1382
1383         /* Privileged reg */
1384         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1385                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1386                               &adev->gfx.priv_reg_irq);
1387         if (r)
1388                 return r;
1389
1390         /* Privileged inst */
1391         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1392                               GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1393                               &adev->gfx.priv_inst_irq);
1394         if (r)
1395                 return r;
1396
1397         /* FED error */
1398         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1399                                   GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
1400                                   &adev->gfx.rlc_gc_fed_irq);
1401         if (r)
1402                 return r;
1403
1404         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1405
1406         gfx_v11_0_me_init(adev);
1407
1408         r = gfx_v11_0_rlc_init(adev);
1409         if (r) {
1410                 DRM_ERROR("Failed to init rlc BOs!\n");
1411                 return r;
1412         }
1413
1414         r = gfx_v11_0_mec_init(adev);
1415         if (r) {
1416                 DRM_ERROR("Failed to init MEC BOs!\n");
1417                 return r;
1418         }
1419
1420         /* set up the gfx ring */
1421         for (i = 0; i < adev->gfx.me.num_me; i++) {
1422                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1423                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1424                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1425                                         continue;
1426
1427                                 r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1428                                                             i, k, j);
1429                                 if (r)
1430                                         return r;
1431                                 ring_id++;
1432                         }
1433                 }
1434         }
1435
1436         ring_id = 0;
1437         /* set up the compute queues - allocate horizontally across pipes */
1438         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1439                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1440                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1441                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
1442                                                                      k, j))
1443                                         continue;
1444
1445                                 r = gfx_v11_0_compute_ring_init(adev, ring_id,
1446                                                                 i, k, j);
1447                                 if (r)
1448                                         return r;
1449
1450                                 ring_id++;
1451                         }
1452                 }
1453         }
1454
1455         if (!adev->enable_mes_kiq) {
1456                 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);
1457                 if (r) {
1458                         DRM_ERROR("Failed to init KIQ BOs!\n");
1459                         return r;
1460                 }
1461
1462                 kiq = &adev->gfx.kiq[0];
1463                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
1464                 if (r)
1465                         return r;
1466         }
1467
1468         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0);
1469         if (r)
1470                 return r;
1471
1472         /* allocate visible FB for rlc auto-loading fw */
1473         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1474                 r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1475                 if (r)
1476                         return r;
1477         }
1478
1479         r = gfx_v11_0_gpu_early_init(adev);
1480         if (r)
1481                 return r;
1482
1483         if (amdgpu_gfx_ras_sw_init(adev)) {
1484                 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
1485                 return -EINVAL;
1486         }
1487
1488         return 0;
1489 }
1490
1491 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1492 {
1493         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1494                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1495                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1496
1497         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1498                               &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1499                               (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1500 }
1501
1502 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1503 {
1504         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1505                               &adev->gfx.me.me_fw_gpu_addr,
1506                               (void **)&adev->gfx.me.me_fw_ptr);
1507
1508         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1509                                &adev->gfx.me.me_fw_data_gpu_addr,
1510                                (void **)&adev->gfx.me.me_fw_data_ptr);
1511 }
1512
1513 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1514 {
1515         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1516                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
1517                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1518 }
1519
1520 static int gfx_v11_0_sw_fini(void *handle)
1521 {
1522         int i;
1523         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1524
1525         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1526                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1527         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1528                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1529
1530         amdgpu_gfx_mqd_sw_fini(adev, 0);
1531
1532         if (!adev->enable_mes_kiq) {
1533                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1534                 amdgpu_gfx_kiq_fini(adev, 0);
1535         }
1536
1537         gfx_v11_0_pfp_fini(adev);
1538         gfx_v11_0_me_fini(adev);
1539         gfx_v11_0_rlc_fini(adev);
1540         gfx_v11_0_mec_fini(adev);
1541
1542         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1543                 gfx_v11_0_rlc_autoload_buffer_fini(adev);
1544
1545         gfx_v11_0_free_microcode(adev);
1546
1547         return 0;
1548 }
1549
1550 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1551                                    u32 sh_num, u32 instance, int xcc_id)
1552 {
1553         u32 data;
1554
1555         if (instance == 0xffffffff)
1556                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1557                                      INSTANCE_BROADCAST_WRITES, 1);
1558         else
1559                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1560                                      instance);
1561
1562         if (se_num == 0xffffffff)
1563                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1564                                      1);
1565         else
1566                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1567
1568         if (sh_num == 0xffffffff)
1569                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1570                                      1);
1571         else
1572                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1573
1574         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1575 }
1576
1577 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1578 {
1579         u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1580
1581         gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);
1582         gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1583                                            CC_GC_SA_UNIT_DISABLE,
1584                                            SA_DISABLE);
1585         gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);
1586         gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1587                                                  GC_USER_SA_UNIT_DISABLE,
1588                                                  SA_DISABLE);
1589         sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1590                                             adev->gfx.config.max_shader_engines);
1591
1592         return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1593 }
1594
1595 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1596 {
1597         u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1598         u32 rb_mask;
1599
1600         gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1601         gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1602                                             CC_RB_BACKEND_DISABLE,
1603                                             BACKEND_DISABLE);
1604         gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1605         gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1606                                                  GC_USER_RB_BACKEND_DISABLE,
1607                                                  BACKEND_DISABLE);
1608         rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1609                                             adev->gfx.config.max_shader_engines);
1610
1611         return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1612 }
1613
1614 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1615 {
1616         u32 rb_bitmap_width_per_sa;
1617         u32 max_sa;
1618         u32 active_sa_bitmap;
1619         u32 global_active_rb_bitmap;
1620         u32 active_rb_bitmap = 0;
1621         u32 i;
1622
1623         /* query sa bitmap from SA_UNIT_DISABLE registers */
1624         active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev);
1625         /* query rb bitmap from RB_BACKEND_DISABLE registers */
1626         global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev);
1627
1628         /* generate active rb bitmap according to active sa bitmap */
1629         max_sa = adev->gfx.config.max_shader_engines *
1630                  adev->gfx.config.max_sh_per_se;
1631         rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1632                                  adev->gfx.config.max_sh_per_se;
1633         for (i = 0; i < max_sa; i++) {
1634                 if (active_sa_bitmap & (1 << i))
1635                         active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));
1636         }
1637
1638         active_rb_bitmap |= global_active_rb_bitmap;
1639         adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1640         adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1641 }
1642
1643 #define DEFAULT_SH_MEM_BASES    (0x6000)
1644 #define LDS_APP_BASE           0x1
1645 #define SCRATCH_APP_BASE       0x2
1646
1647 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1648 {
1649         int i;
1650         uint32_t sh_mem_bases;
1651         uint32_t data;
1652
1653         /*
1654          * Configure apertures:
1655          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1656          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1657          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1658          */
1659         sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1660                         SCRATCH_APP_BASE;
1661
1662         mutex_lock(&adev->srbm_mutex);
1663         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1664                 soc21_grbm_select(adev, 0, 0, 0, i);
1665                 /* CP and shaders */
1666                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1667                 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1668
1669                 /* Enable trap for each kfd vmid. */
1670                 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1671                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1672                 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1673         }
1674         soc21_grbm_select(adev, 0, 0, 0, 0);
1675         mutex_unlock(&adev->srbm_mutex);
1676
1677         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1678            acccess. These should be enabled by FW for target VMIDs. */
1679         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1680                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1681                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1682                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1683                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1684         }
1685 }
1686
1687 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1688 {
1689         int vmid;
1690
1691         /*
1692          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1693          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1694          * the driver can enable them for graphics. VMID0 should maintain
1695          * access so that HWS firmware can save/restore entries.
1696          */
1697         for (vmid = 1; vmid < 16; vmid++) {
1698                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1699                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1700                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1701                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1702         }
1703 }
1704
1705 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1706 {
1707         /* TODO: harvest feature to be added later. */
1708 }
1709
1710 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1711 {
1712         /* TCCs are global (not instanced). */
1713         uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1714                                RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1715
1716         adev->gfx.config.tcc_disabled_mask =
1717                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1718                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1719 }
1720
1721 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
1722 {
1723         u32 tmp;
1724         int i;
1725
1726         if (!amdgpu_sriov_vf(adev))
1727                 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1728
1729         gfx_v11_0_setup_rb(adev);
1730         gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1731         gfx_v11_0_get_tcc_info(adev);
1732         adev->gfx.config.pa_sc_tile_steering_override = 0;
1733
1734         /* Set whether texture coordinate truncation is conformant. */
1735         tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
1736         adev->gfx.config.ta_cntl2_truncate_coord_mode =
1737                 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
1738
1739         /* XXX SH_MEM regs */
1740         /* where to put LDS, scratch, GPUVM in FSA64 space */
1741         mutex_lock(&adev->srbm_mutex);
1742         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1743                 soc21_grbm_select(adev, 0, 0, 0, i);
1744                 /* CP and shaders */
1745                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1746                 if (i != 0) {
1747                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1748                                 (adev->gmc.private_aperture_start >> 48));
1749                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1750                                 (adev->gmc.shared_aperture_start >> 48));
1751                         WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1752                 }
1753         }
1754         soc21_grbm_select(adev, 0, 0, 0, 0);
1755
1756         mutex_unlock(&adev->srbm_mutex);
1757
1758         gfx_v11_0_init_compute_vmid(adev);
1759         gfx_v11_0_init_gds_vmid(adev);
1760 }
1761
1762 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1763                                                bool enable)
1764 {
1765         u32 tmp;
1766
1767         if (amdgpu_sriov_vf(adev))
1768                 return;
1769
1770         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
1771
1772         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1773                             enable ? 1 : 0);
1774         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1775                             enable ? 1 : 0);
1776         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1777                             enable ? 1 : 0);
1778         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1779                             enable ? 1 : 0);
1780
1781         WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1782 }
1783
1784 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
1785 {
1786         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1787
1788         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1789                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1790         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1791                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1792         WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1793
1794         return 0;
1795 }
1796
1797 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
1798 {
1799         u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1800
1801         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1802         WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1803 }
1804
1805 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
1806 {
1807         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1808         udelay(50);
1809         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1810         udelay(50);
1811 }
1812
1813 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1814                                              bool enable)
1815 {
1816         uint32_t rlc_pg_cntl;
1817
1818         rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1819
1820         if (!enable) {
1821                 /* RLC_PG_CNTL[23] = 0 (default)
1822                  * RLC will wait for handshake acks with SMU
1823                  * GFXOFF will be enabled
1824                  * RLC_PG_CNTL[23] = 1
1825                  * RLC will not issue any message to SMU
1826                  * hence no handshake between SMU & RLC
1827                  * GFXOFF will be disabled
1828                  */
1829                 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1830         } else
1831                 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1832         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1833 }
1834
1835 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
1836 {
1837         /* TODO: enable rlc & smu handshake until smu
1838          * and gfxoff feature works as expected */
1839         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1840                 gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
1841
1842         WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1843         udelay(50);
1844 }
1845
1846 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
1847 {
1848         uint32_t tmp;
1849
1850         /* enable Save Restore Machine */
1851         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1852         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1853         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1854         WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1855 }
1856
1857 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
1858 {
1859         const struct rlc_firmware_header_v2_0 *hdr;
1860         const __le32 *fw_data;
1861         unsigned i, fw_size;
1862
1863         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1864         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1865                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1866         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1867
1868         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1869                      RLCG_UCODE_LOADING_START_ADDRESS);
1870
1871         for (i = 0; i < fw_size; i++)
1872                 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1873                              le32_to_cpup(fw_data++));
1874
1875         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1876 }
1877
1878 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1879 {
1880         const struct rlc_firmware_header_v2_2 *hdr;
1881         const __le32 *fw_data;
1882         unsigned i, fw_size;
1883         u32 tmp;
1884
1885         hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1886
1887         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1888                         le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1889         fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1890
1891         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1892
1893         for (i = 0; i < fw_size; i++) {
1894                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1895                         msleep(1);
1896                 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1897                                 le32_to_cpup(fw_data++));
1898         }
1899
1900         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1901
1902         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1903                         le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1904         fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1905
1906         WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1907         for (i = 0; i < fw_size; i++) {
1908                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1909                         msleep(1);
1910                 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1911                                 le32_to_cpup(fw_data++));
1912         }
1913
1914         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1915
1916         tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1917         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1918         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1919         WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1920 }
1921
1922 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
1923 {
1924         const struct rlc_firmware_header_v2_3 *hdr;
1925         const __le32 *fw_data;
1926         unsigned i, fw_size;
1927         u32 tmp;
1928
1929         hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1930
1931         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1932                         le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
1933         fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
1934
1935         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
1936
1937         for (i = 0; i < fw_size; i++) {
1938                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1939                         msleep(1);
1940                 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
1941                                 le32_to_cpup(fw_data++));
1942         }
1943
1944         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1945
1946         tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1947         tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1948         WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
1949
1950         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1951                         le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
1952         fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
1953
1954         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
1955
1956         for (i = 0; i < fw_size; i++) {
1957                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1958                         msleep(1);
1959                 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
1960                                 le32_to_cpup(fw_data++));
1961         }
1962
1963         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1964
1965         tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
1966         tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
1967         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
1968 }
1969
1970 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
1971 {
1972         const struct rlc_firmware_header_v2_0 *hdr;
1973         uint16_t version_major;
1974         uint16_t version_minor;
1975
1976         if (!adev->gfx.rlc_fw)
1977                 return -EINVAL;
1978
1979         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1980         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1981
1982         version_major = le16_to_cpu(hdr->header.header_version_major);
1983         version_minor = le16_to_cpu(hdr->header.header_version_minor);
1984
1985         if (version_major == 2) {
1986                 gfx_v11_0_load_rlcg_microcode(adev);
1987                 if (amdgpu_dpm == 1) {
1988                         if (version_minor >= 2)
1989                                 gfx_v11_0_load_rlc_iram_dram_microcode(adev);
1990                         if (version_minor == 3)
1991                                 gfx_v11_0_load_rlcp_rlcv_microcode(adev);
1992                 }
1993
1994                 return 0;
1995         }
1996
1997         return -EINVAL;
1998 }
1999
2000 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
2001 {
2002         int r;
2003
2004         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2005                 gfx_v11_0_init_csb(adev);
2006
2007                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2008                         gfx_v11_0_rlc_enable_srm(adev);
2009         } else {
2010                 if (amdgpu_sriov_vf(adev)) {
2011                         gfx_v11_0_init_csb(adev);
2012                         return 0;
2013                 }
2014
2015                 adev->gfx.rlc.funcs->stop(adev);
2016
2017                 /* disable CG */
2018                 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2019
2020                 /* disable PG */
2021                 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2022
2023                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2024                         /* legacy rlc firmware loading */
2025                         r = gfx_v11_0_rlc_load_microcode(adev);
2026                         if (r)
2027                                 return r;
2028                 }
2029
2030                 gfx_v11_0_init_csb(adev);
2031
2032                 adev->gfx.rlc.funcs->start(adev);
2033         }
2034         return 0;
2035 }
2036
2037 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
2038 {
2039         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2040         uint32_t tmp;
2041         int i;
2042
2043         /* Trigger an invalidation of the L1 instruction caches */
2044         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2045         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2046         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2047
2048         /* Wait for invalidation complete */
2049         for (i = 0; i < usec_timeout; i++) {
2050                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2051                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2052                                         INVALIDATE_CACHE_COMPLETE))
2053                         break;
2054                 udelay(1);
2055         }
2056
2057         if (i >= usec_timeout) {
2058                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2059                 return -EINVAL;
2060         }
2061
2062         if (amdgpu_emu_mode == 1)
2063                 adev->hdp.funcs->flush_hdp(adev, NULL);
2064
2065         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2066         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2067         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2068         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2069         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2070         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2071
2072         /* Program me ucode address into intruction cache address register */
2073         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2074                         lower_32_bits(addr) & 0xFFFFF000);
2075         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2076                         upper_32_bits(addr));
2077
2078         return 0;
2079 }
2080
2081 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
2082 {
2083         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2084         uint32_t tmp;
2085         int i;
2086
2087         /* Trigger an invalidation of the L1 instruction caches */
2088         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2089         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2090         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2091
2092         /* Wait for invalidation complete */
2093         for (i = 0; i < usec_timeout; i++) {
2094                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2095                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2096                                         INVALIDATE_CACHE_COMPLETE))
2097                         break;
2098                 udelay(1);
2099         }
2100
2101         if (i >= usec_timeout) {
2102                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2103                 return -EINVAL;
2104         }
2105
2106         if (amdgpu_emu_mode == 1)
2107                 adev->hdp.funcs->flush_hdp(adev, NULL);
2108
2109         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2110         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2111         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2112         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2113         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2114         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2115
2116         /* Program pfp ucode address into intruction cache address register */
2117         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2118                         lower_32_bits(addr) & 0xFFFFF000);
2119         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2120                         upper_32_bits(addr));
2121
2122         return 0;
2123 }
2124
2125 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2126 {
2127         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2128         uint32_t tmp;
2129         int i;
2130
2131         /* Trigger an invalidation of the L1 instruction caches */
2132         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2133         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2134
2135         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2136
2137         /* Wait for invalidation complete */
2138         for (i = 0; i < usec_timeout; i++) {
2139                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2140                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2141                                         INVALIDATE_CACHE_COMPLETE))
2142                         break;
2143                 udelay(1);
2144         }
2145
2146         if (i >= usec_timeout) {
2147                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2148                 return -EINVAL;
2149         }
2150
2151         if (amdgpu_emu_mode == 1)
2152                 adev->hdp.funcs->flush_hdp(adev, NULL);
2153
2154         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2155         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2156         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2157         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2158         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2159
2160         /* Program mec1 ucode address into intruction cache address register */
2161         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2162                         lower_32_bits(addr) & 0xFFFFF000);
2163         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2164                         upper_32_bits(addr));
2165
2166         return 0;
2167 }
2168
2169 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2170 {
2171         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2172         uint32_t tmp;
2173         unsigned i, pipe_id;
2174         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2175
2176         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2177                 adev->gfx.pfp_fw->data;
2178
2179         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2180                 lower_32_bits(addr));
2181         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2182                 upper_32_bits(addr));
2183
2184         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2185         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2186         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2187         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2188         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2189
2190         /*
2191          * Programming any of the CP_PFP_IC_BASE registers
2192          * forces invalidation of the ME L1 I$. Wait for the
2193          * invalidation complete
2194          */
2195         for (i = 0; i < usec_timeout; i++) {
2196                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2197                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2198                         INVALIDATE_CACHE_COMPLETE))
2199                         break;
2200                 udelay(1);
2201         }
2202
2203         if (i >= usec_timeout) {
2204                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2205                 return -EINVAL;
2206         }
2207
2208         /* Prime the L1 instruction caches */
2209         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2210         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2211         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2212         /* Waiting for cache primed*/
2213         for (i = 0; i < usec_timeout; i++) {
2214                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2215                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2216                         ICACHE_PRIMED))
2217                         break;
2218                 udelay(1);
2219         }
2220
2221         if (i >= usec_timeout) {
2222                 dev_err(adev->dev, "failed to prime instruction cache\n");
2223                 return -EINVAL;
2224         }
2225
2226         mutex_lock(&adev->srbm_mutex);
2227         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2228                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2229                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2230                         (pfp_hdr->ucode_start_addr_hi << 30) |
2231                         (pfp_hdr->ucode_start_addr_lo >> 2));
2232                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2233                         pfp_hdr->ucode_start_addr_hi >> 2);
2234
2235                 /*
2236                  * Program CP_ME_CNTL to reset given PIPE to take
2237                  * effect of CP_PFP_PRGRM_CNTR_START.
2238                  */
2239                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2240                 if (pipe_id == 0)
2241                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2242                                         PFP_PIPE0_RESET, 1);
2243                 else
2244                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2245                                         PFP_PIPE1_RESET, 1);
2246                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2247
2248                 /* Clear pfp pipe0 reset bit. */
2249                 if (pipe_id == 0)
2250                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2251                                         PFP_PIPE0_RESET, 0);
2252                 else
2253                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2254                                         PFP_PIPE1_RESET, 0);
2255                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2256
2257                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2258                         lower_32_bits(addr2));
2259                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2260                         upper_32_bits(addr2));
2261         }
2262         soc21_grbm_select(adev, 0, 0, 0, 0);
2263         mutex_unlock(&adev->srbm_mutex);
2264
2265         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2266         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2267         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2268         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2269
2270         /* Invalidate the data caches */
2271         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2272         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2273         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2274
2275         for (i = 0; i < usec_timeout; i++) {
2276                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2277                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2278                         INVALIDATE_DCACHE_COMPLETE))
2279                         break;
2280                 udelay(1);
2281         }
2282
2283         if (i >= usec_timeout) {
2284                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2285                 return -EINVAL;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2292 {
2293         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2294         uint32_t tmp;
2295         unsigned i, pipe_id;
2296         const struct gfx_firmware_header_v2_0 *me_hdr;
2297
2298         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2299                 adev->gfx.me_fw->data;
2300
2301         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2302                 lower_32_bits(addr));
2303         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2304                 upper_32_bits(addr));
2305
2306         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2307         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2308         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2309         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2310         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2311
2312         /*
2313          * Programming any of the CP_ME_IC_BASE registers
2314          * forces invalidation of the ME L1 I$. Wait for the
2315          * invalidation complete
2316          */
2317         for (i = 0; i < usec_timeout; i++) {
2318                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2319                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2320                         INVALIDATE_CACHE_COMPLETE))
2321                         break;
2322                 udelay(1);
2323         }
2324
2325         if (i >= usec_timeout) {
2326                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2327                 return -EINVAL;
2328         }
2329
2330         /* Prime the instruction caches */
2331         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2332         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2333         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2334
2335         /* Waiting for instruction cache primed*/
2336         for (i = 0; i < usec_timeout; i++) {
2337                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2338                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2339                         ICACHE_PRIMED))
2340                         break;
2341                 udelay(1);
2342         }
2343
2344         if (i >= usec_timeout) {
2345                 dev_err(adev->dev, "failed to prime instruction cache\n");
2346                 return -EINVAL;
2347         }
2348
2349         mutex_lock(&adev->srbm_mutex);
2350         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2351                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2352                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2353                         (me_hdr->ucode_start_addr_hi << 30) |
2354                         (me_hdr->ucode_start_addr_lo >> 2) );
2355                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2356                         me_hdr->ucode_start_addr_hi>>2);
2357
2358                 /*
2359                  * Program CP_ME_CNTL to reset given PIPE to take
2360                  * effect of CP_PFP_PRGRM_CNTR_START.
2361                  */
2362                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2363                 if (pipe_id == 0)
2364                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2365                                         ME_PIPE0_RESET, 1);
2366                 else
2367                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2368                                         ME_PIPE1_RESET, 1);
2369                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2370
2371                 /* Clear pfp pipe0 reset bit. */
2372                 if (pipe_id == 0)
2373                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2374                                         ME_PIPE0_RESET, 0);
2375                 else
2376                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2377                                         ME_PIPE1_RESET, 0);
2378                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2379
2380                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2381                         lower_32_bits(addr2));
2382                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2383                         upper_32_bits(addr2));
2384         }
2385         soc21_grbm_select(adev, 0, 0, 0, 0);
2386         mutex_unlock(&adev->srbm_mutex);
2387
2388         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2389         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2390         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2391         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2392
2393         /* Invalidate the data caches */
2394         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2395         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2396         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2397
2398         for (i = 0; i < usec_timeout; i++) {
2399                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2400                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2401                         INVALIDATE_DCACHE_COMPLETE))
2402                         break;
2403                 udelay(1);
2404         }
2405
2406         if (i >= usec_timeout) {
2407                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2408                 return -EINVAL;
2409         }
2410
2411         return 0;
2412 }
2413
2414 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2415 {
2416         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2417         uint32_t tmp;
2418         unsigned i;
2419         const struct gfx_firmware_header_v2_0 *mec_hdr;
2420
2421         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2422                 adev->gfx.mec_fw->data;
2423
2424         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2425         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2426         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2427         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2428         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2429
2430         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2431         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2432         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2433         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2434
2435         mutex_lock(&adev->srbm_mutex);
2436         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2437                 soc21_grbm_select(adev, 1, i, 0, 0);
2438
2439                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2440                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2441                      upper_32_bits(addr2));
2442
2443                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2444                                         mec_hdr->ucode_start_addr_lo >> 2 |
2445                                         mec_hdr->ucode_start_addr_hi << 30);
2446                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2447                                         mec_hdr->ucode_start_addr_hi >> 2);
2448
2449                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2450                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2451                      upper_32_bits(addr));
2452         }
2453         mutex_unlock(&adev->srbm_mutex);
2454         soc21_grbm_select(adev, 0, 0, 0, 0);
2455
2456         /* Trigger an invalidation of the L1 instruction caches */
2457         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2458         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2459         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2460
2461         /* Wait for invalidation complete */
2462         for (i = 0; i < usec_timeout; i++) {
2463                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2464                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2465                                        INVALIDATE_DCACHE_COMPLETE))
2466                         break;
2467                 udelay(1);
2468         }
2469
2470         if (i >= usec_timeout) {
2471                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2472                 return -EINVAL;
2473         }
2474
2475         /* Trigger an invalidation of the L1 instruction caches */
2476         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2477         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2478         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2479
2480         /* Wait for invalidation complete */
2481         for (i = 0; i < usec_timeout; i++) {
2482                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2483                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2484                                        INVALIDATE_CACHE_COMPLETE))
2485                         break;
2486                 udelay(1);
2487         }
2488
2489         if (i >= usec_timeout) {
2490                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2491                 return -EINVAL;
2492         }
2493
2494         return 0;
2495 }
2496
2497 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2498 {
2499         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2500         const struct gfx_firmware_header_v2_0 *me_hdr;
2501         const struct gfx_firmware_header_v2_0 *mec_hdr;
2502         uint32_t pipe_id, tmp;
2503
2504         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2505                 adev->gfx.mec_fw->data;
2506         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2507                 adev->gfx.me_fw->data;
2508         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2509                 adev->gfx.pfp_fw->data;
2510
2511         /* config pfp program start addr */
2512         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2513                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2514                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2515                         (pfp_hdr->ucode_start_addr_hi << 30) |
2516                         (pfp_hdr->ucode_start_addr_lo >> 2));
2517                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2518                         pfp_hdr->ucode_start_addr_hi >> 2);
2519         }
2520         soc21_grbm_select(adev, 0, 0, 0, 0);
2521
2522         /* reset pfp pipe */
2523         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2524         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2525         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2526         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2527
2528         /* clear pfp pipe reset */
2529         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2530         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2531         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2532
2533         /* config me program start addr */
2534         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2535                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2536                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2537                         (me_hdr->ucode_start_addr_hi << 30) |
2538                         (me_hdr->ucode_start_addr_lo >> 2) );
2539                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2540                         me_hdr->ucode_start_addr_hi>>2);
2541         }
2542         soc21_grbm_select(adev, 0, 0, 0, 0);
2543
2544         /* reset me pipe */
2545         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2546         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2547         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2548         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2549
2550         /* clear me pipe reset */
2551         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2552         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2553         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2554
2555         /* config mec program start addr */
2556         for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2557                 soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2558                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2559                                         mec_hdr->ucode_start_addr_lo >> 2 |
2560                                         mec_hdr->ucode_start_addr_hi << 30);
2561                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2562                                         mec_hdr->ucode_start_addr_hi >> 2);
2563         }
2564         soc21_grbm_select(adev, 0, 0, 0, 0);
2565
2566         /* reset mec pipe */
2567         tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2568         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2569         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2570         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2571         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2572         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2573
2574         /* clear mec pipe reset */
2575         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2576         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2577         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2578         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2579         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2580 }
2581
2582 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2583 {
2584         uint32_t cp_status;
2585         uint32_t bootload_status;
2586         int i, r;
2587         uint64_t addr, addr2;
2588
2589         for (i = 0; i < adev->usec_timeout; i++) {
2590                 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2591
2592                 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
2593                             IP_VERSION(11, 0, 1) ||
2594                     amdgpu_ip_version(adev, GC_HWIP, 0) ==
2595                             IP_VERSION(11, 0, 4) ||
2596                     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0))
2597                         bootload_status = RREG32_SOC15(GC, 0,
2598                                         regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2599                 else
2600                         bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2601
2602                 if ((cp_status == 0) &&
2603                     (REG_GET_FIELD(bootload_status,
2604                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2605                         break;
2606                 }
2607                 udelay(1);
2608         }
2609
2610         if (i >= adev->usec_timeout) {
2611                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2612                 return -ETIMEDOUT;
2613         }
2614
2615         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2616                 if (adev->gfx.rs64_enable) {
2617                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2618                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2619                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2620                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2621                         r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2622                         if (r)
2623                                 return r;
2624                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2625                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2626                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2627                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2628                         r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2629                         if (r)
2630                                 return r;
2631                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2632                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2633                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2634                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2635                         r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2636                         if (r)
2637                                 return r;
2638                 } else {
2639                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2640                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2641                         r = gfx_v11_0_config_me_cache(adev, addr);
2642                         if (r)
2643                                 return r;
2644                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2645                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2646                         r = gfx_v11_0_config_pfp_cache(adev, addr);
2647                         if (r)
2648                                 return r;
2649                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2650                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2651                         r = gfx_v11_0_config_mec_cache(adev, addr);
2652                         if (r)
2653                                 return r;
2654                 }
2655         }
2656
2657         return 0;
2658 }
2659
2660 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2661 {
2662         int i;
2663         u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2664
2665         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2666         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2667         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2668
2669         for (i = 0; i < adev->usec_timeout; i++) {
2670                 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2671                         break;
2672                 udelay(1);
2673         }
2674
2675         if (i >= adev->usec_timeout)
2676                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2677
2678         return 0;
2679 }
2680
2681 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2682 {
2683         int r;
2684         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2685         const __le32 *fw_data;
2686         unsigned i, fw_size;
2687
2688         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2689                 adev->gfx.pfp_fw->data;
2690
2691         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2692
2693         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2694                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2695         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2696
2697         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2698                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2699                                       &adev->gfx.pfp.pfp_fw_obj,
2700                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2701                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2702         if (r) {
2703                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2704                 gfx_v11_0_pfp_fini(adev);
2705                 return r;
2706         }
2707
2708         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2709
2710         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2711         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2712
2713         gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2714
2715         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
2716
2717         for (i = 0; i < pfp_hdr->jt_size; i++)
2718                 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
2719                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
2720
2721         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2722
2723         return 0;
2724 }
2725
2726 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2727 {
2728         int r;
2729         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2730         const __le32 *fw_ucode, *fw_data;
2731         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2732         uint32_t tmp;
2733         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2734
2735         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2736                 adev->gfx.pfp_fw->data;
2737
2738         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2739
2740         /* instruction */
2741         fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2742                 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2743         fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2744         /* data */
2745         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2746                 le32_to_cpu(pfp_hdr->data_offset_bytes));
2747         fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2748
2749         /* 64kb align */
2750         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2751                                       64 * 1024,
2752                                       AMDGPU_GEM_DOMAIN_VRAM |
2753                                       AMDGPU_GEM_DOMAIN_GTT,
2754                                       &adev->gfx.pfp.pfp_fw_obj,
2755                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2756                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2757         if (r) {
2758                 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2759                 gfx_v11_0_pfp_fini(adev);
2760                 return r;
2761         }
2762
2763         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2764                                       64 * 1024,
2765                                       AMDGPU_GEM_DOMAIN_VRAM |
2766                                       AMDGPU_GEM_DOMAIN_GTT,
2767                                       &adev->gfx.pfp.pfp_fw_data_obj,
2768                                       &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2769                                       (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2770         if (r) {
2771                 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2772                 gfx_v11_0_pfp_fini(adev);
2773                 return r;
2774         }
2775
2776         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2777         memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2778
2779         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2780         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2781         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2782         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2783
2784         if (amdgpu_emu_mode == 1)
2785                 adev->hdp.funcs->flush_hdp(adev, NULL);
2786
2787         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2788                 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2789         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2790                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2791
2792         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2793         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2794         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2795         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2796         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2797
2798         /*
2799          * Programming any of the CP_PFP_IC_BASE registers
2800          * forces invalidation of the ME L1 I$. Wait for the
2801          * invalidation complete
2802          */
2803         for (i = 0; i < usec_timeout; i++) {
2804                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2805                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2806                         INVALIDATE_CACHE_COMPLETE))
2807                         break;
2808                 udelay(1);
2809         }
2810
2811         if (i >= usec_timeout) {
2812                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2813                 return -EINVAL;
2814         }
2815
2816         /* Prime the L1 instruction caches */
2817         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2818         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2819         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2820         /* Waiting for cache primed*/
2821         for (i = 0; i < usec_timeout; i++) {
2822                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2823                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2824                         ICACHE_PRIMED))
2825                         break;
2826                 udelay(1);
2827         }
2828
2829         if (i >= usec_timeout) {
2830                 dev_err(adev->dev, "failed to prime instruction cache\n");
2831                 return -EINVAL;
2832         }
2833
2834         mutex_lock(&adev->srbm_mutex);
2835         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2836                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2837                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2838                         (pfp_hdr->ucode_start_addr_hi << 30) |
2839                         (pfp_hdr->ucode_start_addr_lo >> 2) );
2840                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2841                         pfp_hdr->ucode_start_addr_hi>>2);
2842
2843                 /*
2844                  * Program CP_ME_CNTL to reset given PIPE to take
2845                  * effect of CP_PFP_PRGRM_CNTR_START.
2846                  */
2847                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2848                 if (pipe_id == 0)
2849                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2850                                         PFP_PIPE0_RESET, 1);
2851                 else
2852                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2853                                         PFP_PIPE1_RESET, 1);
2854                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2855
2856                 /* Clear pfp pipe0 reset bit. */
2857                 if (pipe_id == 0)
2858                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2859                                         PFP_PIPE0_RESET, 0);
2860                 else
2861                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2862                                         PFP_PIPE1_RESET, 0);
2863                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2864
2865                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2866                         lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2867                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2868                         upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2869         }
2870         soc21_grbm_select(adev, 0, 0, 0, 0);
2871         mutex_unlock(&adev->srbm_mutex);
2872
2873         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2874         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2875         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2876         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2877
2878         /* Invalidate the data caches */
2879         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2880         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2881         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2882
2883         for (i = 0; i < usec_timeout; i++) {
2884                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2885                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2886                         INVALIDATE_DCACHE_COMPLETE))
2887                         break;
2888                 udelay(1);
2889         }
2890
2891         if (i >= usec_timeout) {
2892                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2893                 return -EINVAL;
2894         }
2895
2896         return 0;
2897 }
2898
2899 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2900 {
2901         int r;
2902         const struct gfx_firmware_header_v1_0 *me_hdr;
2903         const __le32 *fw_data;
2904         unsigned i, fw_size;
2905
2906         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2907                 adev->gfx.me_fw->data;
2908
2909         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2910
2911         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2912                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2913         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2914
2915         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2916                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2917                                       &adev->gfx.me.me_fw_obj,
2918                                       &adev->gfx.me.me_fw_gpu_addr,
2919                                       (void **)&adev->gfx.me.me_fw_ptr);
2920         if (r) {
2921                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2922                 gfx_v11_0_me_fini(adev);
2923                 return r;
2924         }
2925
2926         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2927
2928         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2929         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2930
2931         gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2932
2933         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
2934
2935         for (i = 0; i < me_hdr->jt_size; i++)
2936                 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
2937                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
2938
2939         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2940
2941         return 0;
2942 }
2943
2944 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2945 {
2946         int r;
2947         const struct gfx_firmware_header_v2_0 *me_hdr;
2948         const __le32 *fw_ucode, *fw_data;
2949         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2950         uint32_t tmp;
2951         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2952
2953         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2954                 adev->gfx.me_fw->data;
2955
2956         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2957
2958         /* instruction */
2959         fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2960                 le32_to_cpu(me_hdr->ucode_offset_bytes));
2961         fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2962         /* data */
2963         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2964                 le32_to_cpu(me_hdr->data_offset_bytes));
2965         fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2966
2967         /* 64kb align*/
2968         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2969                                       64 * 1024,
2970                                       AMDGPU_GEM_DOMAIN_VRAM |
2971                                       AMDGPU_GEM_DOMAIN_GTT,
2972                                       &adev->gfx.me.me_fw_obj,
2973                                       &adev->gfx.me.me_fw_gpu_addr,
2974                                       (void **)&adev->gfx.me.me_fw_ptr);
2975         if (r) {
2976                 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2977                 gfx_v11_0_me_fini(adev);
2978                 return r;
2979         }
2980
2981         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2982                                       64 * 1024,
2983                                       AMDGPU_GEM_DOMAIN_VRAM |
2984                                       AMDGPU_GEM_DOMAIN_GTT,
2985                                       &adev->gfx.me.me_fw_data_obj,
2986                                       &adev->gfx.me.me_fw_data_gpu_addr,
2987                                       (void **)&adev->gfx.me.me_fw_data_ptr);
2988         if (r) {
2989                 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2990                 gfx_v11_0_pfp_fini(adev);
2991                 return r;
2992         }
2993
2994         memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2995         memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2996
2997         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2998         amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2999         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
3000         amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
3001
3002         if (amdgpu_emu_mode == 1)
3003                 adev->hdp.funcs->flush_hdp(adev, NULL);
3004
3005         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
3006                 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
3007         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
3008                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
3009
3010         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
3011         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
3012         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
3013         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
3014         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
3015
3016         /*
3017          * Programming any of the CP_ME_IC_BASE registers
3018          * forces invalidation of the ME L1 I$. Wait for the
3019          * invalidation complete
3020          */
3021         for (i = 0; i < usec_timeout; i++) {
3022                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3023                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3024                         INVALIDATE_CACHE_COMPLETE))
3025                         break;
3026                 udelay(1);
3027         }
3028
3029         if (i >= usec_timeout) {
3030                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3031                 return -EINVAL;
3032         }
3033
3034         /* Prime the instruction caches */
3035         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3036         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
3037         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
3038
3039         /* Waiting for instruction cache primed*/
3040         for (i = 0; i < usec_timeout; i++) {
3041                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3042                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3043                         ICACHE_PRIMED))
3044                         break;
3045                 udelay(1);
3046         }
3047
3048         if (i >= usec_timeout) {
3049                 dev_err(adev->dev, "failed to prime instruction cache\n");
3050                 return -EINVAL;
3051         }
3052
3053         mutex_lock(&adev->srbm_mutex);
3054         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
3055                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
3056                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
3057                         (me_hdr->ucode_start_addr_hi << 30) |
3058                         (me_hdr->ucode_start_addr_lo >> 2) );
3059                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
3060                         me_hdr->ucode_start_addr_hi>>2);
3061
3062                 /*
3063                  * Program CP_ME_CNTL to reset given PIPE to take
3064                  * effect of CP_PFP_PRGRM_CNTR_START.
3065                  */
3066                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
3067                 if (pipe_id == 0)
3068                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3069                                         ME_PIPE0_RESET, 1);
3070                 else
3071                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3072                                         ME_PIPE1_RESET, 1);
3073                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3074
3075                 /* Clear pfp pipe0 reset bit. */
3076                 if (pipe_id == 0)
3077                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3078                                         ME_PIPE0_RESET, 0);
3079                 else
3080                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3081                                         ME_PIPE1_RESET, 0);
3082                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3083
3084                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
3085                         lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3086                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
3087                         upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3088         }
3089         soc21_grbm_select(adev, 0, 0, 0, 0);
3090         mutex_unlock(&adev->srbm_mutex);
3091
3092         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
3093         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
3094         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
3095         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
3096
3097         /* Invalidate the data caches */
3098         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3099         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3100         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
3101
3102         for (i = 0; i < usec_timeout; i++) {
3103                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3104                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
3105                         INVALIDATE_DCACHE_COMPLETE))
3106                         break;
3107                 udelay(1);
3108         }
3109
3110         if (i >= usec_timeout) {
3111                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3112                 return -EINVAL;
3113         }
3114
3115         return 0;
3116 }
3117
3118 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3119 {
3120         int r;
3121
3122         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3123                 return -EINVAL;
3124
3125         gfx_v11_0_cp_gfx_enable(adev, false);
3126
3127         if (adev->gfx.rs64_enable)
3128                 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3129         else
3130                 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3131         if (r) {
3132                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3133                 return r;
3134         }
3135
3136         if (adev->gfx.rs64_enable)
3137                 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3138         else
3139                 r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3140         if (r) {
3141                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3142                 return r;
3143         }
3144
3145         return 0;
3146 }
3147
3148 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3149 {
3150         struct amdgpu_ring *ring;
3151         const struct cs_section_def *sect = NULL;
3152         const struct cs_extent_def *ext = NULL;
3153         int r, i;
3154         int ctx_reg_offset;
3155
3156         /* init the CP */
3157         WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3158                      adev->gfx.config.max_hw_contexts - 1);
3159         WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3160
3161         if (!amdgpu_async_gfx_ring)
3162                 gfx_v11_0_cp_gfx_enable(adev, true);
3163
3164         ring = &adev->gfx.gfx_ring[0];
3165         r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3166         if (r) {
3167                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3168                 return r;
3169         }
3170
3171         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3172         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3173
3174         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3175         amdgpu_ring_write(ring, 0x80000000);
3176         amdgpu_ring_write(ring, 0x80000000);
3177
3178         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3179                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3180                         if (sect->id == SECT_CONTEXT) {
3181                                 amdgpu_ring_write(ring,
3182                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
3183                                                           ext->reg_count));
3184                                 amdgpu_ring_write(ring, ext->reg_index -
3185                                                   PACKET3_SET_CONTEXT_REG_START);
3186                                 for (i = 0; i < ext->reg_count; i++)
3187                                         amdgpu_ring_write(ring, ext->extent[i]);
3188                         }
3189                 }
3190         }
3191
3192         ctx_reg_offset =
3193                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3194         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3195         amdgpu_ring_write(ring, ctx_reg_offset);
3196         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3197
3198         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3199         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3200
3201         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3202         amdgpu_ring_write(ring, 0);
3203
3204         amdgpu_ring_commit(ring);
3205
3206         /* submit cs packet to copy state 0 to next available state */
3207         if (adev->gfx.num_gfx_rings > 1) {
3208                 /* maximum supported gfx ring is 2 */
3209                 ring = &adev->gfx.gfx_ring[1];
3210                 r = amdgpu_ring_alloc(ring, 2);
3211                 if (r) {
3212                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3213                         return r;
3214                 }
3215
3216                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3217                 amdgpu_ring_write(ring, 0);
3218
3219                 amdgpu_ring_commit(ring);
3220         }
3221         return 0;
3222 }
3223
3224 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3225                                          CP_PIPE_ID pipe)
3226 {
3227         u32 tmp;
3228
3229         tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3230         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3231
3232         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3233 }
3234
3235 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3236                                           struct amdgpu_ring *ring)
3237 {
3238         u32 tmp;
3239
3240         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3241         if (ring->use_doorbell) {
3242                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3243                                     DOORBELL_OFFSET, ring->doorbell_index);
3244                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3245                                     DOORBELL_EN, 1);
3246         } else {
3247                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3248                                     DOORBELL_EN, 0);
3249         }
3250         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3251
3252         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3253                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
3254         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3255
3256         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3257                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3258 }
3259
3260 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3261 {
3262         struct amdgpu_ring *ring;
3263         u32 tmp;
3264         u32 rb_bufsz;
3265         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3266
3267         /* Set the write pointer delay */
3268         WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3269
3270         /* set the RB to use vmid 0 */
3271         WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3272
3273         /* Init gfx ring 0 for pipe 0 */
3274         mutex_lock(&adev->srbm_mutex);
3275         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3276
3277         /* Set ring buffer size */
3278         ring = &adev->gfx.gfx_ring[0];
3279         rb_bufsz = order_base_2(ring->ring_size / 8);
3280         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3281         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3282         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3283
3284         /* Initialize the ring buffer's write pointers */
3285         ring->wptr = 0;
3286         WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3287         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3288
3289         /* set the wb address wether it's enabled or not */
3290         rptr_addr = ring->rptr_gpu_addr;
3291         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3292         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3293                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3294
3295         wptr_gpu_addr = ring->wptr_gpu_addr;
3296         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3297                      lower_32_bits(wptr_gpu_addr));
3298         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3299                      upper_32_bits(wptr_gpu_addr));
3300
3301         mdelay(1);
3302         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3303
3304         rb_addr = ring->gpu_addr >> 8;
3305         WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3306         WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3307
3308         WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3309
3310         gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3311         mutex_unlock(&adev->srbm_mutex);
3312
3313         /* Init gfx ring 1 for pipe 1 */
3314         if (adev->gfx.num_gfx_rings > 1) {
3315                 mutex_lock(&adev->srbm_mutex);
3316                 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3317                 /* maximum supported gfx ring is 2 */
3318                 ring = &adev->gfx.gfx_ring[1];
3319                 rb_bufsz = order_base_2(ring->ring_size / 8);
3320                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3321                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3322                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3323                 /* Initialize the ring buffer's write pointers */
3324                 ring->wptr = 0;
3325                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3326                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3327                 /* Set the wb address wether it's enabled or not */
3328                 rptr_addr = ring->rptr_gpu_addr;
3329                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3330                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3331                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3332                 wptr_gpu_addr = ring->wptr_gpu_addr;
3333                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3334                              lower_32_bits(wptr_gpu_addr));
3335                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3336                              upper_32_bits(wptr_gpu_addr));
3337
3338                 mdelay(1);
3339                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3340
3341                 rb_addr = ring->gpu_addr >> 8;
3342                 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3343                 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3344                 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3345
3346                 gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3347                 mutex_unlock(&adev->srbm_mutex);
3348         }
3349         /* Switch to pipe 0 */
3350         mutex_lock(&adev->srbm_mutex);
3351         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3352         mutex_unlock(&adev->srbm_mutex);
3353
3354         /* start the ring */
3355         gfx_v11_0_cp_gfx_start(adev);
3356
3357         return 0;
3358 }
3359
3360 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3361 {
3362         u32 data;
3363
3364         if (adev->gfx.rs64_enable) {
3365                 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3366                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3367                                                          enable ? 0 : 1);
3368                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3369                                                          enable ? 0 : 1);
3370                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3371                                                          enable ? 0 : 1);
3372                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3373                                                          enable ? 0 : 1);
3374                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3375                                                          enable ? 0 : 1);
3376                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3377                                                          enable ? 1 : 0);
3378                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3379                                                          enable ? 1 : 0);
3380                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3381                                                          enable ? 1 : 0);
3382                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3383                                                          enable ? 1 : 0);
3384                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3385                                                          enable ? 0 : 1);
3386                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3387         } else {
3388                 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3389
3390                 if (enable) {
3391                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3392                         if (!adev->enable_mes_kiq)
3393                                 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3394                                                      MEC_ME2_HALT, 0);
3395                 } else {
3396                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3397                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3398                 }
3399                 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3400         }
3401
3402         udelay(50);
3403 }
3404
3405 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3406 {
3407         const struct gfx_firmware_header_v1_0 *mec_hdr;
3408         const __le32 *fw_data;
3409         unsigned i, fw_size;
3410         u32 *fw = NULL;
3411         int r;
3412
3413         if (!adev->gfx.mec_fw)
3414                 return -EINVAL;
3415
3416         gfx_v11_0_cp_compute_enable(adev, false);
3417
3418         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3419         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3420
3421         fw_data = (const __le32 *)
3422                 (adev->gfx.mec_fw->data +
3423                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3424         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3425
3426         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3427                                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3428                                           &adev->gfx.mec.mec_fw_obj,
3429                                           &adev->gfx.mec.mec_fw_gpu_addr,
3430                                           (void **)&fw);
3431         if (r) {
3432                 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3433                 gfx_v11_0_mec_fini(adev);
3434                 return r;
3435         }
3436
3437         memcpy(fw, fw_data, fw_size);
3438
3439         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3440         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3441
3442         gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3443
3444         /* MEC1 */
3445         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3446
3447         for (i = 0; i < mec_hdr->jt_size; i++)
3448                 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3449                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3450
3451         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3452
3453         return 0;
3454 }
3455
3456 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3457 {
3458         const struct gfx_firmware_header_v2_0 *mec_hdr;
3459         const __le32 *fw_ucode, *fw_data;
3460         u32 tmp, fw_ucode_size, fw_data_size;
3461         u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3462         u32 *fw_ucode_ptr, *fw_data_ptr;
3463         int r;
3464
3465         if (!adev->gfx.mec_fw)
3466                 return -EINVAL;
3467
3468         gfx_v11_0_cp_compute_enable(adev, false);
3469
3470         mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3471         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3472
3473         fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3474                                 le32_to_cpu(mec_hdr->ucode_offset_bytes));
3475         fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3476
3477         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3478                                 le32_to_cpu(mec_hdr->data_offset_bytes));
3479         fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3480
3481         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3482                                       64 * 1024,
3483                                       AMDGPU_GEM_DOMAIN_VRAM |
3484                                       AMDGPU_GEM_DOMAIN_GTT,
3485                                       &adev->gfx.mec.mec_fw_obj,
3486                                       &adev->gfx.mec.mec_fw_gpu_addr,
3487                                       (void **)&fw_ucode_ptr);
3488         if (r) {
3489                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3490                 gfx_v11_0_mec_fini(adev);
3491                 return r;
3492         }
3493
3494         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3495                                       64 * 1024,
3496                                       AMDGPU_GEM_DOMAIN_VRAM |
3497                                       AMDGPU_GEM_DOMAIN_GTT,
3498                                       &adev->gfx.mec.mec_fw_data_obj,
3499                                       &adev->gfx.mec.mec_fw_data_gpu_addr,
3500                                       (void **)&fw_data_ptr);
3501         if (r) {
3502                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3503                 gfx_v11_0_mec_fini(adev);
3504                 return r;
3505         }
3506
3507         memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3508         memcpy(fw_data_ptr, fw_data, fw_data_size);
3509
3510         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3511         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3512         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3513         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3514
3515         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3516         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3517         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3518         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3519         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3520
3521         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3522         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3523         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3524         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3525
3526         mutex_lock(&adev->srbm_mutex);
3527         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3528                 soc21_grbm_select(adev, 1, i, 0, 0);
3529
3530                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3531                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3532                      upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3533
3534                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3535                                         mec_hdr->ucode_start_addr_lo >> 2 |
3536                                         mec_hdr->ucode_start_addr_hi << 30);
3537                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3538                                         mec_hdr->ucode_start_addr_hi >> 2);
3539
3540                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3541                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3542                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3543         }
3544         mutex_unlock(&adev->srbm_mutex);
3545         soc21_grbm_select(adev, 0, 0, 0, 0);
3546
3547         /* Trigger an invalidation of the L1 instruction caches */
3548         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3549         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3550         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3551
3552         /* Wait for invalidation complete */
3553         for (i = 0; i < usec_timeout; i++) {
3554                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3555                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3556                                        INVALIDATE_DCACHE_COMPLETE))
3557                         break;
3558                 udelay(1);
3559         }
3560
3561         if (i >= usec_timeout) {
3562                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3563                 return -EINVAL;
3564         }
3565
3566         /* Trigger an invalidation of the L1 instruction caches */
3567         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3568         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3569         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3570
3571         /* Wait for invalidation complete */
3572         for (i = 0; i < usec_timeout; i++) {
3573                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3574                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3575                                        INVALIDATE_CACHE_COMPLETE))
3576                         break;
3577                 udelay(1);
3578         }
3579
3580         if (i >= usec_timeout) {
3581                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3582                 return -EINVAL;
3583         }
3584
3585         return 0;
3586 }
3587
3588 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3589 {
3590         uint32_t tmp;
3591         struct amdgpu_device *adev = ring->adev;
3592
3593         /* tell RLC which is KIQ queue */
3594         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3595         tmp &= 0xffffff00;
3596         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3597         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3598         tmp |= 0x80;
3599         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3600 }
3601
3602 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3603 {
3604         /* set graphics engine doorbell range */
3605         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3606                      (adev->doorbell_index.gfx_ring0 * 2) << 2);
3607         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3608                      (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3609
3610         /* set compute engine doorbell range */
3611         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3612                      (adev->doorbell_index.kiq * 2) << 2);
3613         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3614                      (adev->doorbell_index.userqueue_end * 2) << 2);
3615 }
3616
3617 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3618                                   struct amdgpu_mqd_prop *prop)
3619 {
3620         struct v11_gfx_mqd *mqd = m;
3621         uint64_t hqd_gpu_addr, wb_gpu_addr;
3622         uint32_t tmp;
3623         uint32_t rb_bufsz;
3624
3625         /* set up gfx hqd wptr */
3626         mqd->cp_gfx_hqd_wptr = 0;
3627         mqd->cp_gfx_hqd_wptr_hi = 0;
3628
3629         /* set the pointer to the MQD */
3630         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3631         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3632
3633         /* set up mqd control */
3634         tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3635         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3636         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3637         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3638         mqd->cp_gfx_mqd_control = tmp;
3639
3640         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3641         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3642         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3643         mqd->cp_gfx_hqd_vmid = 0;
3644
3645         /* set up default queue priority level
3646          * 0x0 = low priority, 0x1 = high priority */
3647         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3648         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3649         mqd->cp_gfx_hqd_queue_priority = tmp;
3650
3651         /* set up time quantum */
3652         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3653         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3654         mqd->cp_gfx_hqd_quantum = tmp;
3655
3656         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3657         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3658         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3659         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3660
3661         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3662         wb_gpu_addr = prop->rptr_gpu_addr;
3663         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3664         mqd->cp_gfx_hqd_rptr_addr_hi =
3665                 upper_32_bits(wb_gpu_addr) & 0xffff;
3666
3667         /* set up rb_wptr_poll addr */
3668         wb_gpu_addr = prop->wptr_gpu_addr;
3669         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3670         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3671
3672         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3673         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3674         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
3675         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3676         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3677 #ifdef __BIG_ENDIAN
3678         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3679 #endif
3680         mqd->cp_gfx_hqd_cntl = tmp;
3681
3682         /* set up cp_doorbell_control */
3683         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3684         if (prop->use_doorbell) {
3685                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3686                                     DOORBELL_OFFSET, prop->doorbell_index);
3687                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3688                                     DOORBELL_EN, 1);
3689         } else
3690                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3691                                     DOORBELL_EN, 0);
3692         mqd->cp_rb_doorbell_control = tmp;
3693
3694         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3695         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
3696
3697         /* active the queue */
3698         mqd->cp_gfx_hqd_active = 1;
3699
3700         return 0;
3701 }
3702
3703 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
3704 {
3705         struct amdgpu_device *adev = ring->adev;
3706         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3707         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3708
3709         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3710                 memset((void *)mqd, 0, sizeof(*mqd));
3711                 mutex_lock(&adev->srbm_mutex);
3712                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3713                 amdgpu_ring_init_mqd(ring);
3714                 soc21_grbm_select(adev, 0, 0, 0, 0);
3715                 mutex_unlock(&adev->srbm_mutex);
3716                 if (adev->gfx.me.mqd_backup[mqd_idx])
3717                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3718         } else {
3719                 /* restore mqd with the backup copy */
3720                 if (adev->gfx.me.mqd_backup[mqd_idx])
3721                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3722                 /* reset the ring */
3723                 ring->wptr = 0;
3724                 *ring->wptr_cpu_addr = 0;
3725                 amdgpu_ring_clear_ring(ring);
3726         }
3727
3728         return 0;
3729 }
3730
3731 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3732 {
3733         int r, i;
3734         struct amdgpu_ring *ring;
3735
3736         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3737                 ring = &adev->gfx.gfx_ring[i];
3738
3739                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3740                 if (unlikely(r != 0))
3741                         return r;
3742
3743                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3744                 if (!r) {
3745                         r = gfx_v11_0_gfx_init_queue(ring);
3746                         amdgpu_bo_kunmap(ring->mqd_obj);
3747                         ring->mqd_ptr = NULL;
3748                 }
3749                 amdgpu_bo_unreserve(ring->mqd_obj);
3750                 if (r)
3751                         return r;
3752         }
3753
3754         r = amdgpu_gfx_enable_kgq(adev, 0);
3755         if (r)
3756                 return r;
3757
3758         return gfx_v11_0_cp_gfx_start(adev);
3759 }
3760
3761 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3762                                       struct amdgpu_mqd_prop *prop)
3763 {
3764         struct v11_compute_mqd *mqd = m;
3765         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3766         uint32_t tmp;
3767
3768         mqd->header = 0xC0310800;
3769         mqd->compute_pipelinestat_enable = 0x00000001;
3770         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3771         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3772         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3773         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3774         mqd->compute_misc_reserved = 0x00000007;
3775
3776         eop_base_addr = prop->eop_gpu_addr >> 8;
3777         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3778         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3779
3780         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3781         tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3782         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3783                         (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
3784
3785         mqd->cp_hqd_eop_control = tmp;
3786
3787         /* enable doorbell? */
3788         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3789
3790         if (prop->use_doorbell) {
3791                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3792                                     DOORBELL_OFFSET, prop->doorbell_index);
3793                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3794                                     DOORBELL_EN, 1);
3795                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3796                                     DOORBELL_SOURCE, 0);
3797                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3798                                     DOORBELL_HIT, 0);
3799         } else {
3800                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3801                                     DOORBELL_EN, 0);
3802         }
3803
3804         mqd->cp_hqd_pq_doorbell_control = tmp;
3805
3806         /* disable the queue if it's active */
3807         mqd->cp_hqd_dequeue_request = 0;
3808         mqd->cp_hqd_pq_rptr = 0;
3809         mqd->cp_hqd_pq_wptr_lo = 0;
3810         mqd->cp_hqd_pq_wptr_hi = 0;
3811
3812         /* set the pointer to the MQD */
3813         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3814         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3815
3816         /* set MQD vmid to 0 */
3817         tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3818         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3819         mqd->cp_mqd_control = tmp;
3820
3821         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3822         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3823         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3824         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3825
3826         /* set up the HQD, this is similar to CP_RB0_CNTL */
3827         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3828         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3829                             (order_base_2(prop->queue_size / 4) - 1));
3830         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3831                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3832         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3833         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3834         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3835         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3836         mqd->cp_hqd_pq_control = tmp;
3837
3838         /* set the wb address whether it's enabled or not */
3839         wb_gpu_addr = prop->rptr_gpu_addr;
3840         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3841         mqd->cp_hqd_pq_rptr_report_addr_hi =
3842                 upper_32_bits(wb_gpu_addr) & 0xffff;
3843
3844         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3845         wb_gpu_addr = prop->wptr_gpu_addr;
3846         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3847         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3848
3849         tmp = 0;
3850         /* enable the doorbell if requested */
3851         if (prop->use_doorbell) {
3852                 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3853                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3854                                 DOORBELL_OFFSET, prop->doorbell_index);
3855
3856                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3857                                     DOORBELL_EN, 1);
3858                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3859                                     DOORBELL_SOURCE, 0);
3860                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3861                                     DOORBELL_HIT, 0);
3862         }
3863
3864         mqd->cp_hqd_pq_doorbell_control = tmp;
3865
3866         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3867         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3868
3869         /* set the vmid for the queue */
3870         mqd->cp_hqd_vmid = 0;
3871
3872         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3873         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3874         mqd->cp_hqd_persistent_state = tmp;
3875
3876         /* set MIN_IB_AVAIL_SIZE */
3877         tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3878         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3879         mqd->cp_hqd_ib_control = tmp;
3880
3881         /* set static priority for a compute queue/ring */
3882         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3883         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3884
3885         mqd->cp_hqd_active = prop->hqd_active;
3886
3887         return 0;
3888 }
3889
3890 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
3891 {
3892         struct amdgpu_device *adev = ring->adev;
3893         struct v11_compute_mqd *mqd = ring->mqd_ptr;
3894         int j;
3895
3896         /* inactivate the queue */
3897         if (amdgpu_sriov_vf(adev))
3898                 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3899
3900         /* disable wptr polling */
3901         WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3902
3903         /* write the EOP addr */
3904         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3905                mqd->cp_hqd_eop_base_addr_lo);
3906         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3907                mqd->cp_hqd_eop_base_addr_hi);
3908
3909         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3910         WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3911                mqd->cp_hqd_eop_control);
3912
3913         /* enable doorbell? */
3914         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3915                mqd->cp_hqd_pq_doorbell_control);
3916
3917         /* disable the queue if it's active */
3918         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3919                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3920                 for (j = 0; j < adev->usec_timeout; j++) {
3921                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3922                                 break;
3923                         udelay(1);
3924                 }
3925                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3926                        mqd->cp_hqd_dequeue_request);
3927                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3928                        mqd->cp_hqd_pq_rptr);
3929                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3930                        mqd->cp_hqd_pq_wptr_lo);
3931                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3932                        mqd->cp_hqd_pq_wptr_hi);
3933         }
3934
3935         /* set the pointer to the MQD */
3936         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3937                mqd->cp_mqd_base_addr_lo);
3938         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3939                mqd->cp_mqd_base_addr_hi);
3940
3941         /* set MQD vmid to 0 */
3942         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3943                mqd->cp_mqd_control);
3944
3945         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3946         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3947                mqd->cp_hqd_pq_base_lo);
3948         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3949                mqd->cp_hqd_pq_base_hi);
3950
3951         /* set up the HQD, this is similar to CP_RB0_CNTL */
3952         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3953                mqd->cp_hqd_pq_control);
3954
3955         /* set the wb address whether it's enabled or not */
3956         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3957                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3958         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3959                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3960
3961         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3962         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3963                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3964         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3965                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3966
3967         /* enable the doorbell if requested */
3968         if (ring->use_doorbell) {
3969                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3970                         (adev->doorbell_index.kiq * 2) << 2);
3971                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3972                         (adev->doorbell_index.userqueue_end * 2) << 2);
3973         }
3974
3975         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3976                mqd->cp_hqd_pq_doorbell_control);
3977
3978         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3979         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3980                mqd->cp_hqd_pq_wptr_lo);
3981         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3982                mqd->cp_hqd_pq_wptr_hi);
3983
3984         /* set the vmid for the queue */
3985         WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3986
3987         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3988                mqd->cp_hqd_persistent_state);
3989
3990         /* activate the queue */
3991         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3992                mqd->cp_hqd_active);
3993
3994         if (ring->use_doorbell)
3995                 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3996
3997         return 0;
3998 }
3999
4000 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
4001 {
4002         struct amdgpu_device *adev = ring->adev;
4003         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4004
4005         gfx_v11_0_kiq_setting(ring);
4006
4007         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4008                 /* reset MQD to a clean status */
4009                 if (adev->gfx.kiq[0].mqd_backup)
4010                         memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
4011
4012                 /* reset ring buffer */
4013                 ring->wptr = 0;
4014                 amdgpu_ring_clear_ring(ring);
4015
4016                 mutex_lock(&adev->srbm_mutex);
4017                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4018                 gfx_v11_0_kiq_init_register(ring);
4019                 soc21_grbm_select(adev, 0, 0, 0, 0);
4020                 mutex_unlock(&adev->srbm_mutex);
4021         } else {
4022                 memset((void *)mqd, 0, sizeof(*mqd));
4023                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4024                         amdgpu_ring_clear_ring(ring);
4025                 mutex_lock(&adev->srbm_mutex);
4026                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4027                 amdgpu_ring_init_mqd(ring);
4028                 gfx_v11_0_kiq_init_register(ring);
4029                 soc21_grbm_select(adev, 0, 0, 0, 0);
4030                 mutex_unlock(&adev->srbm_mutex);
4031
4032                 if (adev->gfx.kiq[0].mqd_backup)
4033                         memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
4034         }
4035
4036         return 0;
4037 }
4038
4039 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
4040 {
4041         struct amdgpu_device *adev = ring->adev;
4042         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4043         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4044
4045         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4046                 memset((void *)mqd, 0, sizeof(*mqd));
4047                 mutex_lock(&adev->srbm_mutex);
4048                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4049                 amdgpu_ring_init_mqd(ring);
4050                 soc21_grbm_select(adev, 0, 0, 0, 0);
4051                 mutex_unlock(&adev->srbm_mutex);
4052
4053                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4054                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4055         } else {
4056                 /* restore MQD to a clean status */
4057                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4058                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4059                 /* reset ring buffer */
4060                 ring->wptr = 0;
4061                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4062                 amdgpu_ring_clear_ring(ring);
4063         }
4064
4065         return 0;
4066 }
4067
4068 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4069 {
4070         struct amdgpu_ring *ring;
4071         int r;
4072
4073         ring = &adev->gfx.kiq[0].ring;
4074
4075         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4076         if (unlikely(r != 0))
4077                 return r;
4078
4079         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4080         if (unlikely(r != 0)) {
4081                 amdgpu_bo_unreserve(ring->mqd_obj);
4082                 return r;
4083         }
4084
4085         gfx_v11_0_kiq_init_queue(ring);
4086         amdgpu_bo_kunmap(ring->mqd_obj);
4087         ring->mqd_ptr = NULL;
4088         amdgpu_bo_unreserve(ring->mqd_obj);
4089         ring->sched.ready = true;
4090         return 0;
4091 }
4092
4093 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4094 {
4095         struct amdgpu_ring *ring = NULL;
4096         int r = 0, i;
4097
4098         if (!amdgpu_async_gfx_ring)
4099                 gfx_v11_0_cp_compute_enable(adev, true);
4100
4101         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4102                 ring = &adev->gfx.compute_ring[i];
4103
4104                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4105                 if (unlikely(r != 0))
4106                         goto done;
4107                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4108                 if (!r) {
4109                         r = gfx_v11_0_kcq_init_queue(ring);
4110                         amdgpu_bo_kunmap(ring->mqd_obj);
4111                         ring->mqd_ptr = NULL;
4112                 }
4113                 amdgpu_bo_unreserve(ring->mqd_obj);
4114                 if (r)
4115                         goto done;
4116         }
4117
4118         r = amdgpu_gfx_enable_kcq(adev, 0);
4119 done:
4120         return r;
4121 }
4122
4123 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4124 {
4125         int r, i;
4126         struct amdgpu_ring *ring;
4127
4128         if (!(adev->flags & AMD_IS_APU))
4129                 gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4130
4131         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4132                 /* legacy firmware loading */
4133                 r = gfx_v11_0_cp_gfx_load_microcode(adev);
4134                 if (r)
4135                         return r;
4136
4137                 if (adev->gfx.rs64_enable)
4138                         r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4139                 else
4140                         r = gfx_v11_0_cp_compute_load_microcode(adev);
4141                 if (r)
4142                         return r;
4143         }
4144
4145         gfx_v11_0_cp_set_doorbell_range(adev);
4146
4147         if (amdgpu_async_gfx_ring) {
4148                 gfx_v11_0_cp_compute_enable(adev, true);
4149                 gfx_v11_0_cp_gfx_enable(adev, true);
4150         }
4151
4152         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4153                 r = amdgpu_mes_kiq_hw_init(adev);
4154         else
4155                 r = gfx_v11_0_kiq_resume(adev);
4156         if (r)
4157                 return r;
4158
4159         r = gfx_v11_0_kcq_resume(adev);
4160         if (r)
4161                 return r;
4162
4163         if (!amdgpu_async_gfx_ring) {
4164                 r = gfx_v11_0_cp_gfx_resume(adev);
4165                 if (r)
4166                         return r;
4167         } else {
4168                 r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4169                 if (r)
4170                         return r;
4171         }
4172
4173         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4174                 ring = &adev->gfx.gfx_ring[i];
4175                 r = amdgpu_ring_test_helper(ring);
4176                 if (r)
4177                         return r;
4178         }
4179
4180         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4181                 ring = &adev->gfx.compute_ring[i];
4182                 r = amdgpu_ring_test_helper(ring);
4183                 if (r)
4184                         return r;
4185         }
4186
4187         return 0;
4188 }
4189
4190 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4191 {
4192         gfx_v11_0_cp_gfx_enable(adev, enable);
4193         gfx_v11_0_cp_compute_enable(adev, enable);
4194 }
4195
4196 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4197 {
4198         int r;
4199         bool value;
4200
4201         r = adev->gfxhub.funcs->gart_enable(adev);
4202         if (r)
4203                 return r;
4204
4205         adev->hdp.funcs->flush_hdp(adev, NULL);
4206
4207         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4208                 false : true;
4209
4210         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4211         amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
4212
4213         return 0;
4214 }
4215
4216 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4217 {
4218         u32 tmp;
4219
4220         /* select RS64 */
4221         if (adev->gfx.rs64_enable) {
4222                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4223                 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4224                 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4225
4226                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4227                 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4228                 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4229         }
4230
4231         if (amdgpu_emu_mode == 1)
4232                 msleep(100);
4233 }
4234
4235 static int get_gb_addr_config(struct amdgpu_device * adev)
4236 {
4237         u32 gb_addr_config;
4238
4239         gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4240         if (gb_addr_config == 0)
4241                 return -EINVAL;
4242
4243         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4244                 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4245
4246         adev->gfx.config.gb_addr_config = gb_addr_config;
4247
4248         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4249                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4250                                       GB_ADDR_CONFIG, NUM_PIPES);
4251
4252         adev->gfx.config.max_tile_pipes =
4253                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4254
4255         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4256                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4257                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4258         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4259                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4260                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4261         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4262                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4263                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4264         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4265                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4266                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4267
4268         return 0;
4269 }
4270
4271 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4272 {
4273         uint32_t data;
4274
4275         data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4276         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4277         WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4278
4279         data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4280         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4281         WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4282 }
4283
4284 static int gfx_v11_0_hw_init(void *handle)
4285 {
4286         int r;
4287         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4288
4289         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4290                 if (adev->gfx.imu.funcs) {
4291                         /* RLC autoload sequence 1: Program rlc ram */
4292                         if (adev->gfx.imu.funcs->program_rlc_ram)
4293                                 adev->gfx.imu.funcs->program_rlc_ram(adev);
4294                 }
4295                 /* rlc autoload firmware */
4296                 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4297                 if (r)
4298                         return r;
4299         } else {
4300                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4301                         if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4302                                 if (adev->gfx.imu.funcs->load_microcode)
4303                                         adev->gfx.imu.funcs->load_microcode(adev);
4304                                 if (adev->gfx.imu.funcs->setup_imu)
4305                                         adev->gfx.imu.funcs->setup_imu(adev);
4306                                 if (adev->gfx.imu.funcs->start_imu)
4307                                         adev->gfx.imu.funcs->start_imu(adev);
4308                         }
4309
4310                         /* disable gpa mode in backdoor loading */
4311                         gfx_v11_0_disable_gpa_mode(adev);
4312                 }
4313         }
4314
4315         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4316             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4317                 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4318                 if (r) {
4319                         dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4320                         return r;
4321                 }
4322         }
4323
4324         adev->gfx.is_poweron = true;
4325
4326         if(get_gb_addr_config(adev))
4327                 DRM_WARN("Invalid gb_addr_config !\n");
4328
4329         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4330             adev->gfx.rs64_enable)
4331                 gfx_v11_0_config_gfx_rs64(adev);
4332
4333         r = gfx_v11_0_gfxhub_enable(adev);
4334         if (r)
4335                 return r;
4336
4337         if (!amdgpu_emu_mode)
4338                 gfx_v11_0_init_golden_registers(adev);
4339
4340         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4341             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4342                 /**
4343                  * For gfx 11, rlc firmware loading relies on smu firmware is
4344                  * loaded firstly, so in direct type, it has to load smc ucode
4345                  * here before rlc.
4346                  */
4347                 if (!(adev->flags & AMD_IS_APU)) {
4348                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
4349                         if (r)
4350                                 return r;
4351                 }
4352         }
4353
4354         gfx_v11_0_constants_init(adev);
4355
4356         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4357                 gfx_v11_0_select_cp_fw_arch(adev);
4358
4359         if (adev->nbio.funcs->gc_doorbell_init)
4360                 adev->nbio.funcs->gc_doorbell_init(adev);
4361
4362         r = gfx_v11_0_rlc_resume(adev);
4363         if (r)
4364                 return r;
4365
4366         /*
4367          * init golden registers and rlc resume may override some registers,
4368          * reconfig them here
4369          */
4370         gfx_v11_0_tcp_harvest(adev);
4371
4372         r = gfx_v11_0_cp_resume(adev);
4373         if (r)
4374                 return r;
4375
4376         /* get IMU version from HW if it's not set */
4377         if (!adev->gfx.imu_fw_version)
4378                 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);
4379
4380         return r;
4381 }
4382
4383 static int gfx_v11_0_hw_fini(void *handle)
4384 {
4385         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4386
4387         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4388         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4389
4390         if (!adev->no_hw_access) {
4391                 if (amdgpu_async_gfx_ring) {
4392                         if (amdgpu_gfx_disable_kgq(adev, 0))
4393                                 DRM_ERROR("KGQ disable failed\n");
4394                 }
4395
4396                 if (amdgpu_gfx_disable_kcq(adev, 0))
4397                         DRM_ERROR("KCQ disable failed\n");
4398
4399                 amdgpu_mes_kiq_hw_fini(adev);
4400         }
4401
4402         if (amdgpu_sriov_vf(adev))
4403                 /* Remove the steps disabling CPG and clearing KIQ position,
4404                  * so that CP could perform IDLE-SAVE during switch. Those
4405                  * steps are necessary to avoid a DMAR error in gfx9 but it is
4406                  * not reproduced on gfx11.
4407                  */
4408                 return 0;
4409
4410         gfx_v11_0_cp_enable(adev, false);
4411         gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4412
4413         adev->gfxhub.funcs->gart_disable(adev);
4414
4415         adev->gfx.is_poweron = false;
4416
4417         return 0;
4418 }
4419
4420 static int gfx_v11_0_suspend(void *handle)
4421 {
4422         return gfx_v11_0_hw_fini(handle);
4423 }
4424
4425 static int gfx_v11_0_resume(void *handle)
4426 {
4427         return gfx_v11_0_hw_init(handle);
4428 }
4429
4430 static bool gfx_v11_0_is_idle(void *handle)
4431 {
4432         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4433
4434         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4435                                 GRBM_STATUS, GUI_ACTIVE))
4436                 return false;
4437         else
4438                 return true;
4439 }
4440
4441 static int gfx_v11_0_wait_for_idle(void *handle)
4442 {
4443         unsigned i;
4444         u32 tmp;
4445         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4446
4447         for (i = 0; i < adev->usec_timeout; i++) {
4448                 /* read MC_STATUS */
4449                 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4450                         GRBM_STATUS__GUI_ACTIVE_MASK;
4451
4452                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4453                         return 0;
4454                 udelay(1);
4455         }
4456         return -ETIMEDOUT;
4457 }
4458
4459 static int gfx_v11_0_soft_reset(void *handle)
4460 {
4461         u32 grbm_soft_reset = 0;
4462         u32 tmp;
4463         int i, j, k;
4464         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4465
4466         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4467         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4468         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4469         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4470         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4471         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4472
4473         gfx_v11_0_set_safe_mode(adev, 0);
4474
4475         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4476                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4477                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4478                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4479                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4480                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4481                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4482                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4483
4484                                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4485                                 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4486                         }
4487                 }
4488         }
4489         for (i = 0; i < adev->gfx.me.num_me; ++i) {
4490                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4491                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4492                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4493                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4494                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4495                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4496                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4497
4498                                 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4499                         }
4500                 }
4501         }
4502
4503         WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4504
4505         // Read CP_VMID_RESET register three times.
4506         // to get sufficient time for GFX_HQD_ACTIVE reach 0
4507         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4508         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4509         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4510
4511         for (i = 0; i < adev->usec_timeout; i++) {
4512                 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4513                     !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4514                         break;
4515                 udelay(1);
4516         }
4517         if (i >= adev->usec_timeout) {
4518                 printk("Failed to wait all pipes clean\n");
4519                 return -EINVAL;
4520         }
4521
4522         /**********  trigger soft reset  ***********/
4523         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4524         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4525                                         SOFT_RESET_CP, 1);
4526         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4527                                         SOFT_RESET_GFX, 1);
4528         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4529                                         SOFT_RESET_CPF, 1);
4530         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4531                                         SOFT_RESET_CPC, 1);
4532         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4533                                         SOFT_RESET_CPG, 1);
4534         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4535         /**********  exit soft reset  ***********/
4536         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4537         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4538                                         SOFT_RESET_CP, 0);
4539         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4540                                         SOFT_RESET_GFX, 0);
4541         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4542                                         SOFT_RESET_CPF, 0);
4543         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4544                                         SOFT_RESET_CPC, 0);
4545         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4546                                         SOFT_RESET_CPG, 0);
4547         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4548
4549         tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4550         tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4551         WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4552
4553         WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4554         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4555
4556         for (i = 0; i < adev->usec_timeout; i++) {
4557                 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4558                         break;
4559                 udelay(1);
4560         }
4561         if (i >= adev->usec_timeout) {
4562                 printk("Failed to wait CP_VMID_RESET to 0\n");
4563                 return -EINVAL;
4564         }
4565
4566         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4567         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4568         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4569         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4570         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4571         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4572
4573         gfx_v11_0_unset_safe_mode(adev, 0);
4574
4575         return gfx_v11_0_cp_resume(adev);
4576 }
4577
4578 static bool gfx_v11_0_check_soft_reset(void *handle)
4579 {
4580         int i, r;
4581         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4582         struct amdgpu_ring *ring;
4583         long tmo = msecs_to_jiffies(1000);
4584
4585         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4586                 ring = &adev->gfx.gfx_ring[i];
4587                 r = amdgpu_ring_test_ib(ring, tmo);
4588                 if (r)
4589                         return true;
4590         }
4591
4592         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4593                 ring = &adev->gfx.compute_ring[i];
4594                 r = amdgpu_ring_test_ib(ring, tmo);
4595                 if (r)
4596                         return true;
4597         }
4598
4599         return false;
4600 }
4601
4602 static int gfx_v11_0_post_soft_reset(void *handle)
4603 {
4604         /**
4605          * GFX soft reset will impact MES, need resume MES when do GFX soft reset
4606          */
4607         return amdgpu_mes_resume((struct amdgpu_device *)handle);
4608 }
4609
4610 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4611 {
4612         uint64_t clock;
4613         uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
4614
4615         if (amdgpu_sriov_vf(adev)) {
4616                 amdgpu_gfx_off_ctrl(adev, false);
4617                 mutex_lock(&adev->gfx.gpu_clock_mutex);
4618                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
4619                 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
4620                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
4621                 if (clock_counter_hi_pre != clock_counter_hi_after)
4622                         clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
4623                 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4624                 amdgpu_gfx_off_ctrl(adev, true);
4625         } else {
4626                 preempt_disable();
4627                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
4628                 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
4629                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
4630                 if (clock_counter_hi_pre != clock_counter_hi_after)
4631                         clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
4632                 preempt_enable();
4633         }
4634         clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
4635
4636         return clock;
4637 }
4638
4639 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4640                                            uint32_t vmid,
4641                                            uint32_t gds_base, uint32_t gds_size,
4642                                            uint32_t gws_base, uint32_t gws_size,
4643                                            uint32_t oa_base, uint32_t oa_size)
4644 {
4645         struct amdgpu_device *adev = ring->adev;
4646
4647         /* GDS Base */
4648         gfx_v11_0_write_data_to_reg(ring, 0, false,
4649                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
4650                                     gds_base);
4651
4652         /* GDS Size */
4653         gfx_v11_0_write_data_to_reg(ring, 0, false,
4654                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
4655                                     gds_size);
4656
4657         /* GWS */
4658         gfx_v11_0_write_data_to_reg(ring, 0, false,
4659                                     SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
4660                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4661
4662         /* OA */
4663         gfx_v11_0_write_data_to_reg(ring, 0, false,
4664                                     SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
4665                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
4666 }
4667
4668 static int gfx_v11_0_early_init(void *handle)
4669 {
4670         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4671
4672         adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
4673
4674         adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4675         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4676                                           AMDGPU_MAX_COMPUTE_RINGS);
4677
4678         gfx_v11_0_set_kiq_pm4_funcs(adev);
4679         gfx_v11_0_set_ring_funcs(adev);
4680         gfx_v11_0_set_irq_funcs(adev);
4681         gfx_v11_0_set_gds_init(adev);
4682         gfx_v11_0_set_rlc_funcs(adev);
4683         gfx_v11_0_set_mqd_funcs(adev);
4684         gfx_v11_0_set_imu_funcs(adev);
4685
4686         gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
4687
4688         return gfx_v11_0_init_microcode(adev);
4689 }
4690
4691 static int gfx_v11_0_late_init(void *handle)
4692 {
4693         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4694         int r;
4695
4696         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4697         if (r)
4698                 return r;
4699
4700         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4701         if (r)
4702                 return r;
4703
4704         return 0;
4705 }
4706
4707 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
4708 {
4709         uint32_t rlc_cntl;
4710
4711         /* if RLC is not enabled, do nothing */
4712         rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
4713         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4714 }
4715
4716 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
4717 {
4718         uint32_t data;
4719         unsigned i;
4720
4721         data = RLC_SAFE_MODE__CMD_MASK;
4722         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4723
4724         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
4725
4726         /* wait for RLC_SAFE_MODE */
4727         for (i = 0; i < adev->usec_timeout; i++) {
4728                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
4729                                    RLC_SAFE_MODE, CMD))
4730                         break;
4731                 udelay(1);
4732         }
4733 }
4734
4735 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
4736 {
4737         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
4738 }
4739
4740 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
4741                                       bool enable)
4742 {
4743         uint32_t def, data;
4744
4745         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
4746                 return;
4747
4748         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4749
4750         if (enable)
4751                 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4752         else
4753                 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4754
4755         if (def != data)
4756                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4757 }
4758
4759 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
4760                                        bool enable)
4761 {
4762         uint32_t def, data;
4763
4764         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4765                 return;
4766
4767         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4768
4769         if (enable)
4770                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4771         else
4772                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4773
4774         if (def != data)
4775                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4776 }
4777
4778 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
4779                                            bool enable)
4780 {
4781         uint32_t def, data;
4782
4783         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4784                 return;
4785
4786         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4787
4788         if (enable)
4789                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4790         else
4791                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4792
4793         if (def != data)
4794                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4795 }
4796
4797 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4798                                                        bool enable)
4799 {
4800         uint32_t data, def;
4801
4802         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4803                 return;
4804
4805         /* It is disabled by HW by default */
4806         if (enable) {
4807                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4808                         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4809                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4810
4811                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4812                                   RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4813                                   RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4814
4815                         if (def != data)
4816                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4817                 }
4818         } else {
4819                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4820                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4821
4822                         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4823                                  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4824                                  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4825
4826                         if (def != data)
4827                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4828                 }
4829         }
4830 }
4831
4832 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4833                                                        bool enable)
4834 {
4835         uint32_t def, data;
4836
4837         if (!(adev->cg_flags &
4838               (AMD_CG_SUPPORT_GFX_CGCG |
4839               AMD_CG_SUPPORT_GFX_CGLS |
4840               AMD_CG_SUPPORT_GFX_3D_CGCG |
4841               AMD_CG_SUPPORT_GFX_3D_CGLS)))
4842                 return;
4843
4844         if (enable) {
4845                 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4846
4847                 /* unset CGCG override */
4848                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4849                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4850                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4851                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4852                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4853                     adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4854                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4855
4856                 /* update CGCG override bits */
4857                 if (def != data)
4858                         WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4859
4860                 /* enable cgcg FSM(0x0000363F) */
4861                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4862
4863                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4864                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4865                         data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4866                                  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4867                 }
4868
4869                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4870                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4871                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4872                                  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4873                 }
4874
4875                 if (def != data)
4876                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4877
4878                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4879                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4880
4881                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4882                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4883                         data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4884                                  RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4885                 }
4886
4887                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4888                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4889                         data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4890                                  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4891                 }
4892
4893                 if (def != data)
4894                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4895
4896                 /* set IDLE_POLL_COUNT(0x00900100) */
4897                 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4898
4899                 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4900                 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4901                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4902
4903                 if (def != data)
4904                         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4905
4906                 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4907                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4908                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4909                 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4910                 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4911                 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4912
4913                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4914                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4915                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4916
4917                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4918                 if (adev->sdma.num_instances > 1) {
4919                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4920                         data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4921                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4922                 }
4923         } else {
4924                 /* Program RLC_CGCG_CGLS_CTRL */
4925                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4926
4927                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4928                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4929
4930                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4931                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4932
4933                 if (def != data)
4934                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4935
4936                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4937                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4938
4939                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4940                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4941                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4942                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4943
4944                 if (def != data)
4945                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4946
4947                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4948                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4949                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4950
4951                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4952                 if (adev->sdma.num_instances > 1) {
4953                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4954                         data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4955                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4956                 }
4957         }
4958 }
4959
4960 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4961                                             bool enable)
4962 {
4963         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4964
4965         gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
4966
4967         gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
4968
4969         gfx_v11_0_update_repeater_fgcg(adev, enable);
4970
4971         gfx_v11_0_update_sram_fgcg(adev, enable);
4972
4973         gfx_v11_0_update_perf_clk(adev, enable);
4974
4975         if (adev->cg_flags &
4976             (AMD_CG_SUPPORT_GFX_MGCG |
4977              AMD_CG_SUPPORT_GFX_CGLS |
4978              AMD_CG_SUPPORT_GFX_CGCG |
4979              AMD_CG_SUPPORT_GFX_3D_CGCG |
4980              AMD_CG_SUPPORT_GFX_3D_CGLS))
4981                 gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
4982
4983         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
4984
4985         return 0;
4986 }
4987
4988 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
4989 {
4990         u32 data;
4991
4992         amdgpu_gfx_off_ctrl(adev, false);
4993
4994         data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);
4995
4996         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4997         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4998
4999         WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
5000
5001         amdgpu_gfx_off_ctrl(adev, true);
5002 }
5003
5004 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
5005         .is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
5006         .set_safe_mode = gfx_v11_0_set_safe_mode,
5007         .unset_safe_mode = gfx_v11_0_unset_safe_mode,
5008         .init = gfx_v11_0_rlc_init,
5009         .get_csb_size = gfx_v11_0_get_csb_size,
5010         .get_csb_buffer = gfx_v11_0_get_csb_buffer,
5011         .resume = gfx_v11_0_rlc_resume,
5012         .stop = gfx_v11_0_rlc_stop,
5013         .reset = gfx_v11_0_rlc_reset,
5014         .start = gfx_v11_0_rlc_start,
5015         .update_spm_vmid = gfx_v11_0_update_spm_vmid,
5016 };
5017
5018 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5019 {
5020         u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5021
5022         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5023                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5024         else
5025                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5026
5027         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5028
5029         // Program RLC_PG_DELAY3 for CGPG hysteresis
5030         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5031                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5032                 case IP_VERSION(11, 0, 1):
5033                 case IP_VERSION(11, 0, 4):
5034                 case IP_VERSION(11, 5, 0):
5035                         WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5036                         break;
5037                 default:
5038                         break;
5039                 }
5040         }
5041 }
5042
5043 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5044 {
5045         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5046
5047         gfx_v11_cntl_power_gating(adev, enable);
5048
5049         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5050 }
5051
5052 static int gfx_v11_0_set_powergating_state(void *handle,
5053                                            enum amd_powergating_state state)
5054 {
5055         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5056         bool enable = (state == AMD_PG_STATE_GATE);
5057
5058         if (amdgpu_sriov_vf(adev))
5059                 return 0;
5060
5061         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5062         case IP_VERSION(11, 0, 0):
5063         case IP_VERSION(11, 0, 2):
5064         case IP_VERSION(11, 0, 3):
5065                 amdgpu_gfx_off_ctrl(adev, enable);
5066                 break;
5067         case IP_VERSION(11, 0, 1):
5068         case IP_VERSION(11, 0, 4):
5069         case IP_VERSION(11, 5, 0):
5070                 if (!enable)
5071                         amdgpu_gfx_off_ctrl(adev, false);
5072
5073                 gfx_v11_cntl_pg(adev, enable);
5074
5075                 if (enable)
5076                         amdgpu_gfx_off_ctrl(adev, true);
5077
5078                 break;
5079         default:
5080                 break;
5081         }
5082
5083         return 0;
5084 }
5085
5086 static int gfx_v11_0_set_clockgating_state(void *handle,
5087                                           enum amd_clockgating_state state)
5088 {
5089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5090
5091         if (amdgpu_sriov_vf(adev))
5092                 return 0;
5093
5094         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5095         case IP_VERSION(11, 0, 0):
5096         case IP_VERSION(11, 0, 1):
5097         case IP_VERSION(11, 0, 2):
5098         case IP_VERSION(11, 0, 3):
5099         case IP_VERSION(11, 0, 4):
5100         case IP_VERSION(11, 5, 0):
5101                 gfx_v11_0_update_gfx_clock_gating(adev,
5102                                 state ==  AMD_CG_STATE_GATE);
5103                 break;
5104         default:
5105                 break;
5106         }
5107
5108         return 0;
5109 }
5110
5111 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5112 {
5113         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5114         int data;
5115
5116         /* AMD_CG_SUPPORT_GFX_MGCG */
5117         data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5118         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5119                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5120
5121         /* AMD_CG_SUPPORT_REPEATER_FGCG */
5122         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5123                 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5124
5125         /* AMD_CG_SUPPORT_GFX_FGCG */
5126         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5127                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
5128
5129         /* AMD_CG_SUPPORT_GFX_PERF_CLK */
5130         if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5131                 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5132
5133         /* AMD_CG_SUPPORT_GFX_CGCG */
5134         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5135         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5136                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5137
5138         /* AMD_CG_SUPPORT_GFX_CGLS */
5139         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5140                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5141
5142         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5143         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5144         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5145                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5146
5147         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5148         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5149                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5150 }
5151
5152 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5153 {
5154         /* gfx11 is 32bit rptr*/
5155         return *(uint32_t *)ring->rptr_cpu_addr;
5156 }
5157
5158 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5159 {
5160         struct amdgpu_device *adev = ring->adev;
5161         u64 wptr;
5162
5163         /* XXX check if swapping is necessary on BE */
5164         if (ring->use_doorbell) {
5165                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5166         } else {
5167                 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5168                 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5169         }
5170
5171         return wptr;
5172 }
5173
5174 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5175 {
5176         struct amdgpu_device *adev = ring->adev;
5177
5178         if (ring->use_doorbell) {
5179                 /* XXX check if swapping is necessary on BE */
5180                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5181                              ring->wptr);
5182                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5183         } else {
5184                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5185                              lower_32_bits(ring->wptr));
5186                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5187                              upper_32_bits(ring->wptr));
5188         }
5189 }
5190
5191 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5192 {
5193         /* gfx11 hardware is 32bit rptr */
5194         return *(uint32_t *)ring->rptr_cpu_addr;
5195 }
5196
5197 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5198 {
5199         u64 wptr;
5200
5201         /* XXX check if swapping is necessary on BE */
5202         if (ring->use_doorbell)
5203                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5204         else
5205                 BUG();
5206         return wptr;
5207 }
5208
5209 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5210 {
5211         struct amdgpu_device *adev = ring->adev;
5212
5213         /* XXX check if swapping is necessary on BE */
5214         if (ring->use_doorbell) {
5215                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5216                              ring->wptr);
5217                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5218         } else {
5219                 BUG(); /* only DOORBELL method supported on gfx11 now */
5220         }
5221 }
5222
5223 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5224 {
5225         struct amdgpu_device *adev = ring->adev;
5226         u32 ref_and_mask, reg_mem_engine;
5227         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5228
5229         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5230                 switch (ring->me) {
5231                 case 1:
5232                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5233                         break;
5234                 case 2:
5235                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5236                         break;
5237                 default:
5238                         return;
5239                 }
5240                 reg_mem_engine = 0;
5241         } else {
5242                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5243                 reg_mem_engine = 1; /* pfp */
5244         }
5245
5246         gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5247                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5248                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5249                                ref_and_mask, ref_and_mask, 0x20);
5250 }
5251
5252 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5253                                        struct amdgpu_job *job,
5254                                        struct amdgpu_ib *ib,
5255                                        uint32_t flags)
5256 {
5257         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5258         u32 header, control = 0;
5259
5260         BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5261
5262         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5263
5264         control |= ib->length_dw | (vmid << 24);
5265
5266         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5267                 control |= INDIRECT_BUFFER_PRE_ENB(1);
5268
5269                 if (flags & AMDGPU_IB_PREEMPTED)
5270                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
5271
5272                 if (vmid)
5273                         gfx_v11_0_ring_emit_de_meta(ring,
5274                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5275         }
5276
5277         if (ring->is_mes_queue)
5278                 /* inherit vmid from mqd */
5279                 control |= 0x400000;
5280
5281         amdgpu_ring_write(ring, header);
5282         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5283         amdgpu_ring_write(ring,
5284 #ifdef __BIG_ENDIAN
5285                 (2 << 0) |
5286 #endif
5287                 lower_32_bits(ib->gpu_addr));
5288         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5289         amdgpu_ring_write(ring, control);
5290 }
5291
5292 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5293                                            struct amdgpu_job *job,
5294                                            struct amdgpu_ib *ib,
5295                                            uint32_t flags)
5296 {
5297         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5298         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5299
5300         if (ring->is_mes_queue)
5301                 /* inherit vmid from mqd */
5302                 control |= 0x40000000;
5303
5304         /* Currently, there is a high possibility to get wave ID mismatch
5305          * between ME and GDS, leading to a hw deadlock, because ME generates
5306          * different wave IDs than the GDS expects. This situation happens
5307          * randomly when at least 5 compute pipes use GDS ordered append.
5308          * The wave IDs generated by ME are also wrong after suspend/resume.
5309          * Those are probably bugs somewhere else in the kernel driver.
5310          *
5311          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5312          * GDS to 0 for this ring (me/pipe).
5313          */
5314         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5315                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5316                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5317                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5318         }
5319
5320         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5321         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5322         amdgpu_ring_write(ring,
5323 #ifdef __BIG_ENDIAN
5324                                 (2 << 0) |
5325 #endif
5326                                 lower_32_bits(ib->gpu_addr));
5327         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5328         amdgpu_ring_write(ring, control);
5329 }
5330
5331 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5332                                      u64 seq, unsigned flags)
5333 {
5334         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5335         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5336
5337         /* RELEASE_MEM - flush caches, send int */
5338         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5339         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5340                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
5341                                  PACKET3_RELEASE_MEM_GCR_GL2_INV |
5342                                  PACKET3_RELEASE_MEM_GCR_GL2_US |
5343                                  PACKET3_RELEASE_MEM_GCR_GL1_INV |
5344                                  PACKET3_RELEASE_MEM_GCR_GLV_INV |
5345                                  PACKET3_RELEASE_MEM_GCR_GLM_INV |
5346                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
5347                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5348                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5349                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5350         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5351                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5352
5353         /*
5354          * the address should be Qword aligned if 64bit write, Dword
5355          * aligned if only send 32bit data low (discard data high)
5356          */
5357         if (write64bit)
5358                 BUG_ON(addr & 0x7);
5359         else
5360                 BUG_ON(addr & 0x3);
5361         amdgpu_ring_write(ring, lower_32_bits(addr));
5362         amdgpu_ring_write(ring, upper_32_bits(addr));
5363         amdgpu_ring_write(ring, lower_32_bits(seq));
5364         amdgpu_ring_write(ring, upper_32_bits(seq));
5365         amdgpu_ring_write(ring, ring->is_mes_queue ?
5366                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5367 }
5368
5369 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5370 {
5371         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5372         uint32_t seq = ring->fence_drv.sync_seq;
5373         uint64_t addr = ring->fence_drv.gpu_addr;
5374
5375         gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5376                                upper_32_bits(addr), seq, 0xffffffff, 4);
5377 }
5378
5379 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5380                                    uint16_t pasid, uint32_t flush_type,
5381                                    bool all_hub, uint8_t dst_sel)
5382 {
5383         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5384         amdgpu_ring_write(ring,
5385                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5386                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5387                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5388                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5389 }
5390
5391 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5392                                          unsigned vmid, uint64_t pd_addr)
5393 {
5394         if (ring->is_mes_queue)
5395                 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5396         else
5397                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5398
5399         /* compute doesn't have PFP */
5400         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5401                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5402                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5403                 amdgpu_ring_write(ring, 0x0);
5404         }
5405 }
5406
5407 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5408                                           u64 seq, unsigned int flags)
5409 {
5410         struct amdgpu_device *adev = ring->adev;
5411
5412         /* we only allocate 32bit for each seq wb address */
5413         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5414
5415         /* write fence seq to the "addr" */
5416         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5417         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5418                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5419         amdgpu_ring_write(ring, lower_32_bits(addr));
5420         amdgpu_ring_write(ring, upper_32_bits(addr));
5421         amdgpu_ring_write(ring, lower_32_bits(seq));
5422
5423         if (flags & AMDGPU_FENCE_FLAG_INT) {
5424                 /* set register to trigger INT */
5425                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5426                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5427                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5428                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5429                 amdgpu_ring_write(ring, 0);
5430                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5431         }
5432 }
5433
5434 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5435                                          uint32_t flags)
5436 {
5437         uint32_t dw2 = 0;
5438
5439         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5440         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5441                 /* set load_global_config & load_global_uconfig */
5442                 dw2 |= 0x8001;
5443                 /* set load_cs_sh_regs */
5444                 dw2 |= 0x01000000;
5445                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5446                 dw2 |= 0x10002;
5447         }
5448
5449         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5450         amdgpu_ring_write(ring, dw2);
5451         amdgpu_ring_write(ring, 0);
5452 }
5453
5454 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
5455                                            u64 shadow_va, u64 csa_va,
5456                                            u64 gds_va, bool init_shadow,
5457                                            int vmid)
5458 {
5459         struct amdgpu_device *adev = ring->adev;
5460
5461         if (!adev->gfx.cp_gfx_shadow)
5462                 return;
5463
5464         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7));
5465         amdgpu_ring_write(ring, lower_32_bits(shadow_va));
5466         amdgpu_ring_write(ring, upper_32_bits(shadow_va));
5467         amdgpu_ring_write(ring, lower_32_bits(gds_va));
5468         amdgpu_ring_write(ring, upper_32_bits(gds_va));
5469         amdgpu_ring_write(ring, lower_32_bits(csa_va));
5470         amdgpu_ring_write(ring, upper_32_bits(csa_va));
5471         amdgpu_ring_write(ring, shadow_va ?
5472                           PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);
5473         amdgpu_ring_write(ring, init_shadow ?
5474                           PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);
5475 }
5476
5477 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5478 {
5479         unsigned ret;
5480
5481         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5482         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5483         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5484         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5485         ret = ring->wptr & ring->buf_mask;
5486         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5487
5488         return ret;
5489 }
5490
5491 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5492 {
5493         unsigned cur;
5494         BUG_ON(offset > ring->buf_mask);
5495         BUG_ON(ring->ring[offset] != 0x55aa55aa);
5496
5497         cur = (ring->wptr - 1) & ring->buf_mask;
5498         if (likely(cur > offset))
5499                 ring->ring[offset] = cur - offset;
5500         else
5501                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
5502 }
5503
5504 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5505 {
5506         int i, r = 0;
5507         struct amdgpu_device *adev = ring->adev;
5508         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5509         struct amdgpu_ring *kiq_ring = &kiq->ring;
5510         unsigned long flags;
5511
5512         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5513                 return -EINVAL;
5514
5515         spin_lock_irqsave(&kiq->ring_lock, flags);
5516
5517         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5518                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
5519                 return -ENOMEM;
5520         }
5521
5522         /* assert preemption condition */
5523         amdgpu_ring_set_preempt_cond_exec(ring, false);
5524
5525         /* assert IB preemption, emit the trailing fence */
5526         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5527                                    ring->trail_fence_gpu_addr,
5528                                    ++ring->trail_seq);
5529         amdgpu_ring_commit(kiq_ring);
5530
5531         spin_unlock_irqrestore(&kiq->ring_lock, flags);
5532
5533         /* poll the trailing fence */
5534         for (i = 0; i < adev->usec_timeout; i++) {
5535                 if (ring->trail_seq ==
5536                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
5537                         break;
5538                 udelay(1);
5539         }
5540
5541         if (i >= adev->usec_timeout) {
5542                 r = -EINVAL;
5543                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
5544         }
5545
5546         /* deassert preemption condition */
5547         amdgpu_ring_set_preempt_cond_exec(ring, true);
5548         return r;
5549 }
5550
5551 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
5552 {
5553         struct amdgpu_device *adev = ring->adev;
5554         struct v10_de_ib_state de_payload = {0};
5555         uint64_t offset, gds_addr, de_payload_gpu_addr;
5556         void *de_payload_cpu_addr;
5557         int cnt;
5558
5559         if (ring->is_mes_queue) {
5560                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5561                                   gfx[0].gfx_meta_data) +
5562                         offsetof(struct v10_gfx_meta_data, de_payload);
5563                 de_payload_gpu_addr =
5564                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5565                 de_payload_cpu_addr =
5566                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5567
5568                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5569                                   gfx[0].gds_backup) +
5570                         offsetof(struct v10_gfx_meta_data, de_payload);
5571                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5572         } else {
5573                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
5574                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5575                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5576
5577                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
5578                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
5579                                  PAGE_SIZE);
5580         }
5581
5582         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5583         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5584
5585         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5586         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5587         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5588                                  WRITE_DATA_DST_SEL(8) |
5589                                  WR_CONFIRM) |
5590                                  WRITE_DATA_CACHE_POLICY(0));
5591         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5592         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5593
5594         if (resume)
5595                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5596                                            sizeof(de_payload) >> 2);
5597         else
5598                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5599                                            sizeof(de_payload) >> 2);
5600 }
5601
5602 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5603                                     bool secure)
5604 {
5605         uint32_t v = secure ? FRAME_TMZ : 0;
5606
5607         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5608         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5609 }
5610
5611 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5612                                      uint32_t reg_val_offs)
5613 {
5614         struct amdgpu_device *adev = ring->adev;
5615
5616         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5617         amdgpu_ring_write(ring, 0 |     /* src: register*/
5618                                 (5 << 8) |      /* dst: memory */
5619                                 (1 << 20));     /* write confirm */
5620         amdgpu_ring_write(ring, reg);
5621         amdgpu_ring_write(ring, 0);
5622         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5623                                 reg_val_offs * 4));
5624         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5625                                 reg_val_offs * 4));
5626 }
5627
5628 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5629                                    uint32_t val)
5630 {
5631         uint32_t cmd = 0;
5632
5633         switch (ring->funcs->type) {
5634         case AMDGPU_RING_TYPE_GFX:
5635                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5636                 break;
5637         case AMDGPU_RING_TYPE_KIQ:
5638                 cmd = (1 << 16); /* no inc addr */
5639                 break;
5640         default:
5641                 cmd = WR_CONFIRM;
5642                 break;
5643         }
5644         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5645         amdgpu_ring_write(ring, cmd);
5646         amdgpu_ring_write(ring, reg);
5647         amdgpu_ring_write(ring, 0);
5648         amdgpu_ring_write(ring, val);
5649 }
5650
5651 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5652                                         uint32_t val, uint32_t mask)
5653 {
5654         gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5655 }
5656
5657 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5658                                                    uint32_t reg0, uint32_t reg1,
5659                                                    uint32_t ref, uint32_t mask)
5660 {
5661         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5662
5663         gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5664                                ref, mask, 0x20);
5665 }
5666
5667 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
5668                                          unsigned vmid)
5669 {
5670         struct amdgpu_device *adev = ring->adev;
5671         uint32_t value = 0;
5672
5673         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5674         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5675         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5676         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5677         WREG32_SOC15(GC, 0, regSQ_CMD, value);
5678 }
5679
5680 static void
5681 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5682                                       uint32_t me, uint32_t pipe,
5683                                       enum amdgpu_interrupt_state state)
5684 {
5685         uint32_t cp_int_cntl, cp_int_cntl_reg;
5686
5687         if (!me) {
5688                 switch (pipe) {
5689                 case 0:
5690                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
5691                         break;
5692                 case 1:
5693                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
5694                         break;
5695                 default:
5696                         DRM_DEBUG("invalid pipe %d\n", pipe);
5697                         return;
5698                 }
5699         } else {
5700                 DRM_DEBUG("invalid me %d\n", me);
5701                 return;
5702         }
5703
5704         switch (state) {
5705         case AMDGPU_IRQ_STATE_DISABLE:
5706                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5707                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5708                                             TIME_STAMP_INT_ENABLE, 0);
5709                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5710                                             GENERIC0_INT_ENABLE, 0);
5711                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5712                 break;
5713         case AMDGPU_IRQ_STATE_ENABLE:
5714                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5715                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5716                                             TIME_STAMP_INT_ENABLE, 1);
5717                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5718                                             GENERIC0_INT_ENABLE, 1);
5719                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5720                 break;
5721         default:
5722                 break;
5723         }
5724 }
5725
5726 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5727                                                      int me, int pipe,
5728                                                      enum amdgpu_interrupt_state state)
5729 {
5730         u32 mec_int_cntl, mec_int_cntl_reg;
5731
5732         /*
5733          * amdgpu controls only the first MEC. That's why this function only
5734          * handles the setting of interrupts for this specific MEC. All other
5735          * pipes' interrupts are set by amdkfd.
5736          */
5737
5738         if (me == 1) {
5739                 switch (pipe) {
5740                 case 0:
5741                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5742                         break;
5743                 case 1:
5744                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
5745                         break;
5746                 case 2:
5747                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
5748                         break;
5749                 case 3:
5750                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
5751                         break;
5752                 default:
5753                         DRM_DEBUG("invalid pipe %d\n", pipe);
5754                         return;
5755                 }
5756         } else {
5757                 DRM_DEBUG("invalid me %d\n", me);
5758                 return;
5759         }
5760
5761         switch (state) {
5762         case AMDGPU_IRQ_STATE_DISABLE:
5763                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5764                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5765                                              TIME_STAMP_INT_ENABLE, 0);
5766                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5767                                              GENERIC0_INT_ENABLE, 0);
5768                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5769                 break;
5770         case AMDGPU_IRQ_STATE_ENABLE:
5771                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5772                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5773                                              TIME_STAMP_INT_ENABLE, 1);
5774                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5775                                              GENERIC0_INT_ENABLE, 1);
5776                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5777                 break;
5778         default:
5779                 break;
5780         }
5781 }
5782
5783 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5784                                             struct amdgpu_irq_src *src,
5785                                             unsigned type,
5786                                             enum amdgpu_interrupt_state state)
5787 {
5788         switch (type) {
5789         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5790                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
5791                 break;
5792         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
5793                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
5794                 break;
5795         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5796                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5797                 break;
5798         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5799                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5800                 break;
5801         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5802                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5803                 break;
5804         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5805                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5806                 break;
5807         default:
5808                 break;
5809         }
5810         return 0;
5811 }
5812
5813 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
5814                              struct amdgpu_irq_src *source,
5815                              struct amdgpu_iv_entry *entry)
5816 {
5817         int i;
5818         u8 me_id, pipe_id, queue_id;
5819         struct amdgpu_ring *ring;
5820         uint32_t mes_queue_id = entry->src_data[0];
5821
5822         DRM_DEBUG("IH: CP EOP\n");
5823
5824         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
5825                 struct amdgpu_mes_queue *queue;
5826
5827                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
5828
5829                 spin_lock(&adev->mes.queue_id_lock);
5830                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5831                 if (queue) {
5832                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5833                         amdgpu_fence_process(queue->ring);
5834                 }
5835                 spin_unlock(&adev->mes.queue_id_lock);
5836         } else {
5837                 me_id = (entry->ring_id & 0x0c) >> 2;
5838                 pipe_id = (entry->ring_id & 0x03) >> 0;
5839                 queue_id = (entry->ring_id & 0x70) >> 4;
5840
5841                 switch (me_id) {
5842                 case 0:
5843                         if (pipe_id == 0)
5844                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5845                         else
5846                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5847                         break;
5848                 case 1:
5849                 case 2:
5850                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5851                                 ring = &adev->gfx.compute_ring[i];
5852                                 /* Per-queue interrupt is supported for MEC starting from VI.
5853                                  * The interrupt can only be enabled/disabled per pipe instead
5854                                  * of per queue.
5855                                  */
5856                                 if ((ring->me == me_id) &&
5857                                     (ring->pipe == pipe_id) &&
5858                                     (ring->queue == queue_id))
5859                                         amdgpu_fence_process(ring);
5860                         }
5861                         break;
5862                 }
5863         }
5864
5865         return 0;
5866 }
5867
5868 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5869                                               struct amdgpu_irq_src *source,
5870                                               unsigned type,
5871                                               enum amdgpu_interrupt_state state)
5872 {
5873         switch (state) {
5874         case AMDGPU_IRQ_STATE_DISABLE:
5875         case AMDGPU_IRQ_STATE_ENABLE:
5876                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5877                                PRIV_REG_INT_ENABLE,
5878                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5879                 break;
5880         default:
5881                 break;
5882         }
5883
5884         return 0;
5885 }
5886
5887 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5888                                                struct amdgpu_irq_src *source,
5889                                                unsigned type,
5890                                                enum amdgpu_interrupt_state state)
5891 {
5892         switch (state) {
5893         case AMDGPU_IRQ_STATE_DISABLE:
5894         case AMDGPU_IRQ_STATE_ENABLE:
5895                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5896                                PRIV_INSTR_INT_ENABLE,
5897                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5898                 break;
5899         default:
5900                 break;
5901         }
5902
5903         return 0;
5904 }
5905
5906 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
5907                                         struct amdgpu_iv_entry *entry)
5908 {
5909         u8 me_id, pipe_id, queue_id;
5910         struct amdgpu_ring *ring;
5911         int i;
5912
5913         me_id = (entry->ring_id & 0x0c) >> 2;
5914         pipe_id = (entry->ring_id & 0x03) >> 0;
5915         queue_id = (entry->ring_id & 0x70) >> 4;
5916
5917         switch (me_id) {
5918         case 0:
5919                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5920                         ring = &adev->gfx.gfx_ring[i];
5921                         /* we only enabled 1 gfx queue per pipe for now */
5922                         if (ring->me == me_id && ring->pipe == pipe_id)
5923                                 drm_sched_fault(&ring->sched);
5924                 }
5925                 break;
5926         case 1:
5927         case 2:
5928                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5929                         ring = &adev->gfx.compute_ring[i];
5930                         if (ring->me == me_id && ring->pipe == pipe_id &&
5931                             ring->queue == queue_id)
5932                                 drm_sched_fault(&ring->sched);
5933                 }
5934                 break;
5935         default:
5936                 BUG();
5937                 break;
5938         }
5939 }
5940
5941 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
5942                                   struct amdgpu_irq_src *source,
5943                                   struct amdgpu_iv_entry *entry)
5944 {
5945         DRM_ERROR("Illegal register access in command stream\n");
5946         gfx_v11_0_handle_priv_fault(adev, entry);
5947         return 0;
5948 }
5949
5950 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
5951                                    struct amdgpu_irq_src *source,
5952                                    struct amdgpu_iv_entry *entry)
5953 {
5954         DRM_ERROR("Illegal instruction in command stream\n");
5955         gfx_v11_0_handle_priv_fault(adev, entry);
5956         return 0;
5957 }
5958
5959 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev,
5960                                   struct amdgpu_irq_src *source,
5961                                   struct amdgpu_iv_entry *entry)
5962 {
5963         if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq)
5964                 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry);
5965
5966         return 0;
5967 }
5968
5969 #if 0
5970 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5971                                              struct amdgpu_irq_src *src,
5972                                              unsigned int type,
5973                                              enum amdgpu_interrupt_state state)
5974 {
5975         uint32_t tmp, target;
5976         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
5977
5978         target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5979         target += ring->pipe;
5980
5981         switch (type) {
5982         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5983                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5984                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
5985                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5986                                             GENERIC2_INT_ENABLE, 0);
5987                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
5988
5989                         tmp = RREG32_SOC15_IP(GC, target);
5990                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
5991                                             GENERIC2_INT_ENABLE, 0);
5992                         WREG32_SOC15_IP(GC, target, tmp);
5993                 } else {
5994                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
5995                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5996                                             GENERIC2_INT_ENABLE, 1);
5997                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
5998
5999                         tmp = RREG32_SOC15_IP(GC, target);
6000                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6001                                             GENERIC2_INT_ENABLE, 1);
6002                         WREG32_SOC15_IP(GC, target, tmp);
6003                 }
6004                 break;
6005         default:
6006                 BUG(); /* kiq only support GENERIC2_INT now */
6007                 break;
6008         }
6009         return 0;
6010 }
6011 #endif
6012
6013 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6014 {
6015         const unsigned int gcr_cntl =
6016                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6017                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6018                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6019                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6020                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6021                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6022                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6023                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6024
6025         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6026         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6027         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6028         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6029         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6030         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6031         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6032         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6033         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6034 }
6035
6036 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6037         .name = "gfx_v11_0",
6038         .early_init = gfx_v11_0_early_init,
6039         .late_init = gfx_v11_0_late_init,
6040         .sw_init = gfx_v11_0_sw_init,
6041         .sw_fini = gfx_v11_0_sw_fini,
6042         .hw_init = gfx_v11_0_hw_init,
6043         .hw_fini = gfx_v11_0_hw_fini,
6044         .suspend = gfx_v11_0_suspend,
6045         .resume = gfx_v11_0_resume,
6046         .is_idle = gfx_v11_0_is_idle,
6047         .wait_for_idle = gfx_v11_0_wait_for_idle,
6048         .soft_reset = gfx_v11_0_soft_reset,
6049         .check_soft_reset = gfx_v11_0_check_soft_reset,
6050         .post_soft_reset = gfx_v11_0_post_soft_reset,
6051         .set_clockgating_state = gfx_v11_0_set_clockgating_state,
6052         .set_powergating_state = gfx_v11_0_set_powergating_state,
6053         .get_clockgating_state = gfx_v11_0_get_clockgating_state,
6054 };
6055
6056 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6057         .type = AMDGPU_RING_TYPE_GFX,
6058         .align_mask = 0xff,
6059         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6060         .support_64bit_ptrs = true,
6061         .secure_submission_supported = true,
6062         .get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6063         .get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6064         .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6065         .emit_frame_size = /* totally 242 maximum if 16 IBs */
6066                 5 + /* COND_EXEC */
6067                 9 + /* SET_Q_PREEMPTION_MODE */
6068                 7 + /* PIPELINE_SYNC */
6069                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6070                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6071                 2 + /* VM_FLUSH */
6072                 8 + /* FENCE for VM_FLUSH */
6073                 20 + /* GDS switch */
6074                 5 + /* COND_EXEC */
6075                 7 + /* HDP_flush */
6076                 4 + /* VGT_flush */
6077                 31 + /* DE_META */
6078                 3 + /* CNTX_CTRL */
6079                 5 + /* HDP_INVL */
6080                 8 + 8 + /* FENCE x2 */
6081                 8, /* gfx_v11_0_emit_mem_sync */
6082         .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
6083         .emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6084         .emit_fence = gfx_v11_0_ring_emit_fence,
6085         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6086         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6087         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6088         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6089         .test_ring = gfx_v11_0_ring_test_ring,
6090         .test_ib = gfx_v11_0_ring_test_ib,
6091         .insert_nop = amdgpu_ring_insert_nop,
6092         .pad_ib = amdgpu_ring_generic_pad_ib,
6093         .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6094         .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
6095         .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6096         .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
6097         .preempt_ib = gfx_v11_0_ring_preempt_ib,
6098         .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6099         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6100         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6101         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6102         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6103         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6104 };
6105
6106 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6107         .type = AMDGPU_RING_TYPE_COMPUTE,
6108         .align_mask = 0xff,
6109         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6110         .support_64bit_ptrs = true,
6111         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6112         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6113         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6114         .emit_frame_size =
6115                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6116                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6117                 5 + /* hdp invalidate */
6118                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6119                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6120                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6121                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6122                 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6123                 8, /* gfx_v11_0_emit_mem_sync */
6124         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6125         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6126         .emit_fence = gfx_v11_0_ring_emit_fence,
6127         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6128         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6129         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6130         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6131         .test_ring = gfx_v11_0_ring_test_ring,
6132         .test_ib = gfx_v11_0_ring_test_ib,
6133         .insert_nop = amdgpu_ring_insert_nop,
6134         .pad_ib = amdgpu_ring_generic_pad_ib,
6135         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6136         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6137         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6138         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6139 };
6140
6141 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6142         .type = AMDGPU_RING_TYPE_KIQ,
6143         .align_mask = 0xff,
6144         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6145         .support_64bit_ptrs = true,
6146         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6147         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6148         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6149         .emit_frame_size =
6150                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6151                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6152                 5 + /*hdp invalidate */
6153                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6154                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6155                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6156                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6157                 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6158         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6159         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6160         .emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6161         .test_ring = gfx_v11_0_ring_test_ring,
6162         .test_ib = gfx_v11_0_ring_test_ib,
6163         .insert_nop = amdgpu_ring_insert_nop,
6164         .pad_ib = amdgpu_ring_generic_pad_ib,
6165         .emit_rreg = gfx_v11_0_ring_emit_rreg,
6166         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6167         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6168         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6169 };
6170
6171 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6172 {
6173         int i;
6174
6175         adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6176
6177         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6178                 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6179
6180         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6181                 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6182 }
6183
6184 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6185         .set = gfx_v11_0_set_eop_interrupt_state,
6186         .process = gfx_v11_0_eop_irq,
6187 };
6188
6189 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6190         .set = gfx_v11_0_set_priv_reg_fault_state,
6191         .process = gfx_v11_0_priv_reg_irq,
6192 };
6193
6194 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
6195         .set = gfx_v11_0_set_priv_inst_fault_state,
6196         .process = gfx_v11_0_priv_inst_irq,
6197 };
6198
6199 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
6200         .process = gfx_v11_0_rlc_gc_fed_irq,
6201 };
6202
6203 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
6204 {
6205         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6206         adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6207
6208         adev->gfx.priv_reg_irq.num_types = 1;
6209         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6210
6211         adev->gfx.priv_inst_irq.num_types = 1;
6212         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6213
6214         adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
6215         adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
6216
6217 }
6218
6219 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
6220 {
6221         if (adev->flags & AMD_IS_APU)
6222                 adev->gfx.imu.mode = MISSION_MODE;
6223         else
6224                 adev->gfx.imu.mode = DEBUG_MODE;
6225
6226         adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6227 }
6228
6229 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
6230 {
6231         adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6232 }
6233
6234 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
6235 {
6236         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6237                             adev->gfx.config.max_sh_per_se *
6238                             adev->gfx.config.max_shader_engines;
6239
6240         adev->gds.gds_size = 0x1000;
6241         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
6242         adev->gds.gws_size = 64;
6243         adev->gds.oa_size = 16;
6244 }
6245
6246 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
6247 {
6248         /* set gfx eng mqd */
6249         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
6250                 sizeof(struct v11_gfx_mqd);
6251         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
6252                 gfx_v11_0_gfx_mqd_init;
6253         /* set compute eng mqd */
6254         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
6255                 sizeof(struct v11_compute_mqd);
6256         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
6257                 gfx_v11_0_compute_mqd_init;
6258 }
6259
6260 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
6261                                                           u32 bitmap)
6262 {
6263         u32 data;
6264
6265         if (!bitmap)
6266                 return;
6267
6268         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6269         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6270
6271         WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
6272 }
6273
6274 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
6275 {
6276         u32 data, wgp_bitmask;
6277         data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
6278         data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
6279
6280         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6281         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6282
6283         wgp_bitmask =
6284                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6285
6286         return (~data) & wgp_bitmask;
6287 }
6288
6289 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
6290 {
6291         u32 wgp_idx, wgp_active_bitmap;
6292         u32 cu_bitmap_per_wgp, cu_active_bitmap;
6293
6294         wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
6295         cu_active_bitmap = 0;
6296
6297         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
6298                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
6299                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
6300                 if (wgp_active_bitmap & (1 << wgp_idx))
6301                         cu_active_bitmap |= cu_bitmap_per_wgp;
6302         }
6303
6304         return cu_active_bitmap;
6305 }
6306
6307 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
6308                                  struct amdgpu_cu_info *cu_info)
6309 {
6310         int i, j, k, counter, active_cu_number = 0;
6311         u32 mask, bitmap;
6312         unsigned disable_masks[8 * 2];
6313
6314         if (!adev || !cu_info)
6315                 return -EINVAL;
6316
6317         amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
6318
6319         mutex_lock(&adev->grbm_idx_mutex);
6320         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6321                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6322                         mask = 1;
6323                         counter = 0;
6324                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);
6325                         if (i < 8 && j < 2)
6326                                 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
6327                                         adev, disable_masks[i * 2 + j]);
6328                         bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
6329
6330                         /**
6331                          * GFX11 could support more than 4 SEs, while the bitmap
6332                          * in cu_info struct is 4x4 and ioctl interface struct
6333                          * drm_amdgpu_info_device should keep stable.
6334                          * So we use last two columns of bitmap to store cu mask for
6335                          * SEs 4 to 7, the layout of the bitmap is as below:
6336                          *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
6337                          *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
6338                          *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
6339                          *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
6340                          *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
6341                          *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
6342                          *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6343                          *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6344                          */
6345                         cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
6346
6347                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6348                                 if (bitmap & mask)
6349                                         counter++;
6350
6351                                 mask <<= 1;
6352                         }
6353                         active_cu_number += counter;
6354                 }
6355         }
6356         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
6357         mutex_unlock(&adev->grbm_idx_mutex);
6358
6359         cu_info->number = active_cu_number;
6360         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6361
6362         return 0;
6363 }
6364
6365 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
6366 {
6367         .type = AMD_IP_BLOCK_TYPE_GFX,
6368         .major = 11,
6369         .minor = 0,
6370         .rev = 0,
6371         .funcs = &gfx_v11_0_ip_funcs,
6372 };