drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_fourcc.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include "display/intel_atomic.h"
  36 #include "display/intel_atomic_plane.h"
  37 #include "display/intel_bw.h"
  38 #include "display/intel_de.h"
  39 #include "display/intel_display_types.h"
  40 #include "display/intel_fbc.h"
  41 #include "display/intel_sprite.h"
  42 #include "display/skl_universal_plane.h"
  43
  44 #include "gt/intel_llc.h"
  45
  46 #include "i915_drv.h"
  47 #include "i915_fixed.h"
  48 #include "i915_irq.h"
  49 #include "i915_trace.h"
  50 #include "intel_pm.h"
  51 #include "intel_sideband.h"
  52 #include "../../../platform/x86/intel_ips.h"
  53
  54 /* Stores plane specific WM parameters */
  55 struct skl_wm_params {
  56         bool x_tiled, y_tiled;
  57         bool rc_surface;
  58         bool is_planar;
  59         u32 width;
  60         u8 cpp;
  61         u32 plane_pixel_rate;
  62         u32 y_min_scanlines;
  63         u32 plane_bytes_per_line;
  64         uint_fixed_16_16_t plane_blocks_per_line;
  65         uint_fixed_16_16_t y_tile_minimum;
  66         u32 linetime_us;
  67         u32 dbuf_block_size;
  68 };
  69
  70 /* used in computing the new watermarks state */
  71 struct intel_wm_config {
  72         unsigned int num_pipes_active;
  73         bool sprites_enabled;
  74         bool sprites_scaled;
  75 };
  76
  77 static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
  78 {
  79         if (HAS_LLC(dev_priv)) {
  80                 /*
  81                  * WaCompressedResourceDisplayNewHashMode:skl,kbl
  82                  * Display WA #0390: skl,kbl
  83                  *
  84                  * Must match Sampler, Pixel Back End, and Media. See
  85                  * WaCompressedResourceSamplerPbeMediaNewHashMode.
  86                  */
  87                 intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
  88                            intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) |
  89                            SKL_DE_COMPRESSED_HASH_MODE);
  90         }
  91
  92         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
  93         intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
  94                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  95
  96         /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
  97         intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
  98                    intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  99
 100         /*
 101          * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
 102          * Display WA #0859: skl,bxt,kbl,glk,cfl
 103          */
 104         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 105                    DISP_FBC_MEMORY_WAKE);
 106 }
 107
 108 static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
 109 {
 110         gen9_init_clock_gating(dev_priv);
 111
 112         /* WaDisableSDEUnitClockGating:bxt */
 113         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 114                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 115
 116         /*
 117          * FIXME:
 118          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
 119          */
 120         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
 121                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 122
 123         /*
 124          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 125          * to stay fully on.
 126          */
 127         intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
 128                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 129
 130         /*
 131          * Lower the display internal timeout.
 132          * This is needed to avoid any hard hangs when DSI port PLL
 133          * is off and a MMIO access is attempted by any privilege
 134          * application, using batch buffers or any other means.
 135          */
 136         intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
 137
 138         /*
 139          * WaFbcTurnOffFbcWatermark:bxt
 140          * Display WA #0562: bxt
 141          */
 142         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
 143                    DISP_FBC_WM_DIS);
 144
 145         /*
 146          * WaFbcHighMemBwCorruptionAvoidance:bxt
 147          * Display WA #0883: bxt
 148          */
 149         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
 150                    ILK_DPFC_DISABLE_DUMMY0);
 151 }
 152
 153 static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
 154 {
 155         gen9_init_clock_gating(dev_priv);
 156
 157         /*
 158          * WaDisablePWMClockGating:glk
 159          * Backlight PWM may stop in the asserted state, causing backlight
 160          * to stay fully on.
 161          */
 162         intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
 163                    PWM1_GATING_DIS | PWM2_GATING_DIS);
 164 }
 165
 166 static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
 167 {
 168         u32 tmp;
 169
 170         tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
 171
 172         switch (tmp & CLKCFG_FSB_MASK) {
 173         case CLKCFG_FSB_533:
 174                 dev_priv->fsb_freq = 533; /* 133*4 */
 175                 break;
 176         case CLKCFG_FSB_800:
 177                 dev_priv->fsb_freq = 800; /* 200*4 */
 178                 break;
 179         case CLKCFG_FSB_667:
 180                 dev_priv->fsb_freq =  667; /* 167*4 */
 181                 break;
 182         case CLKCFG_FSB_400:
 183                 dev_priv->fsb_freq = 400; /* 100*4 */
 184                 break;
 185         }
 186
 187         switch (tmp & CLKCFG_MEM_MASK) {
 188         case CLKCFG_MEM_533:
 189                 dev_priv->mem_freq = 533;
 190                 break;
 191         case CLKCFG_MEM_667:
 192                 dev_priv->mem_freq = 667;
 193                 break;
 194         case CLKCFG_MEM_800:
 195                 dev_priv->mem_freq = 800;
 196                 break;
 197         }
 198
 199         /* detect pineview DDR3 setting */
 200         tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
 201         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 202 }
 203
 204 static void ilk_get_mem_freq(struct drm_i915_private *dev_priv)
 205 {
 206         u16 ddrpll, csipll;
 207
 208         ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
 209         csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
 210
 211         switch (ddrpll & 0xff) {
 212         case 0xc:
 213                 dev_priv->mem_freq = 800;
 214                 break;
 215         case 0x10:
 216                 dev_priv->mem_freq = 1066;
 217                 break;
 218         case 0x14:
 219                 dev_priv->mem_freq = 1333;
 220                 break;
 221         case 0x18:
 222                 dev_priv->mem_freq = 1600;
 223                 break;
 224         default:
 225                 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
 226                         ddrpll & 0xff);
 227                 dev_priv->mem_freq = 0;
 228                 break;
 229         }
 230
 231         switch (csipll & 0x3ff) {
 232         case 0x00c:
 233                 dev_priv->fsb_freq = 3200;
 234                 break;
 235         case 0x00e:
 236                 dev_priv->fsb_freq = 3733;
 237                 break;
 238         case 0x010:
 239                 dev_priv->fsb_freq = 4266;
 240                 break;
 241         case 0x012:
 242                 dev_priv->fsb_freq = 4800;
 243                 break;
 244         case 0x014:
 245                 dev_priv->fsb_freq = 5333;
 246                 break;
 247         case 0x016:
 248                 dev_priv->fsb_freq = 5866;
 249                 break;
 250         case 0x018:
 251                 dev_priv->fsb_freq = 6400;
 252                 break;
 253         default:
 254                 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
 255                         csipll & 0x3ff);
 256                 dev_priv->fsb_freq = 0;
 257                 break;
 258         }
 259 }
 260
 261 static const struct cxsr_latency cxsr_latency_table[] = {
 262         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 263         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 264         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 265         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 266         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 267
 268         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 269         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 270         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 271         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 272         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 273
 274         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 275         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 276         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 277         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 278         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 279
 280         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 281         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 282         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 283         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 284         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 285
 286         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 287         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 288         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 289         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 290         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 291
 292         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 293         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 294         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 295         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 296         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 297 };
 298
 299 static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
 300                                                          bool is_ddr3,
 301                                                          int fsb,
 302                                                          int mem)
 303 {
 304         const struct cxsr_latency *latency;
 305         int i;
 306
 307         if (fsb == 0 || mem == 0)
 308                 return NULL;
 309
 310         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 311                 latency = &cxsr_latency_table[i];
 312                 if (is_desktop == latency->is_desktop &&
 313                     is_ddr3 == latency->is_ddr3 &&
 314                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 315                         return latency;
 316         }
 317
 318         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 319
 320         return NULL;
 321 }
 322
 323 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 324 {
 325         u32 val;
 326
 327         vlv_punit_get(dev_priv);
 328
 329         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 330         if (enable)
 331                 val &= ~FORCE_DDR_HIGH_FREQ;
 332         else
 333                 val |= FORCE_DDR_HIGH_FREQ;
 334         val &= ~FORCE_DDR_LOW_FREQ;
 335         val |= FORCE_DDR_FREQ_REQ_ACK;
 336         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 337
 338         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 339                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 340                 drm_err(&dev_priv->drm,
 341                         "timed out waiting for Punit DDR DVFS request\n");
 342
 343         vlv_punit_put(dev_priv);
 344 }
 345
 346 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 347 {
 348         u32 val;
 349
 350         vlv_punit_get(dev_priv);
 351
 352         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 353         if (enable)
 354                 val |= DSP_MAXFIFO_PM5_ENABLE;
 355         else
 356                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 357         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 358
 359         vlv_punit_put(dev_priv);
 360 }
 361
 362 #define FW_WM(value, plane) \
 363         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 364
 365 static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 366 {
 367         bool was_enabled;
 368         u32 val;
 369
 370         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 371                 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 372                 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 373                 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF_VLV);
 374         } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
 375                 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 376                 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 377                 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 378         } else if (IS_PINEVIEW(dev_priv)) {
 379                 val = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 380                 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
 381                 if (enable)
 382                         val |= PINEVIEW_SELF_REFRESH_EN;
 383                 else
 384                         val &= ~PINEVIEW_SELF_REFRESH_EN;
 385                 intel_uncore_write(&dev_priv->uncore, DSPFW3, val);
 386                 intel_uncore_posting_read(&dev_priv->uncore, DSPFW3);
 387         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
 388                 was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
 389                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 390                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 391                 intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, val);
 392                 intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF);
 393         } else if (IS_I915GM(dev_priv)) {
 394                 /*
 395                  * FIXME can't find a bit like this for 915G, and
 396                  * and yet it does have the related watermark in
 397                  * FW_BLC_SELF. What's going on?
 398                  */
 399                 was_enabled = intel_uncore_read(&dev_priv->uncore, INSTPM) & INSTPM_SELF_EN;
 400                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 401                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 402                 intel_uncore_write(&dev_priv->uncore, INSTPM, val);
 403                 intel_uncore_posting_read(&dev_priv->uncore, INSTPM);
 404         } else {
 405                 return false;
 406         }
 407
 408         trace_intel_memory_cxsr(dev_priv, was_enabled, enable);
 409
 410         drm_dbg_kms(&dev_priv->drm, "memory self-refresh is %s (was %s)\n",
 411                     enableddisabled(enable),
 412                     enableddisabled(was_enabled));
 413
 414         return was_enabled;
 415 }
 416
 417 /**
 418  * intel_set_memory_cxsr - Configure CxSR state
 419  * @dev_priv: i915 device
 420  * @enable: Allow vs. disallow CxSR
 421  *
 422  * Allow or disallow the system to enter a special CxSR
 423  * (C-state self refresh) state. What typically happens in CxSR mode
 424  * is that several display FIFOs may get combined into a single larger
 425  * FIFO for a particular plane (so called max FIFO mode) to allow the
 426  * system to defer memory fetches longer, and the memory will enter
 427  * self refresh.
 428  *
 429  * Note that enabling CxSR does not guarantee that the system enter
 430  * this special mode, nor does it guarantee that the system stays
 431  * in that mode once entered. So this just allows/disallows the system
 432  * to autonomously utilize the CxSR mode. Other factors such as core
 433  * C-states will affect when/if the system actually enters/exits the
 434  * CxSR mode.
 435  *
 436  * Note that on VLV/CHV this actually only controls the max FIFO mode,
 437  * and the system is free to enter/exit memory self refresh at any time
 438  * even when the use of CxSR has been disallowed.
 439  *
 440  * While the system is actually in the CxSR/max FIFO mode, some plane
 441  * control registers will not get latched on vblank. Thus in order to
 442  * guarantee the system will respond to changes in the plane registers
 443  * we must always disallow CxSR prior to making changes to those registers.
 444  * Unfortunately the system will re-evaluate the CxSR conditions at
 445  * frame start which happens after vblank start (which is when the plane
 446  * registers would get latched), so we can't proceed with the plane update
 447  * during the same frame where we disallowed CxSR.
 448  *
 449  * Certain platforms also have a deeper HPLL SR mode. Fortunately the
 450  * HPLL SR mode depends on CxSR itself, so we don't have to hand hold
 451  * the hardware w.r.t. HPLL SR when writing to plane registers.
 452  * Disallowing just CxSR is sufficient.
 453  */
 454 bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 455 {
 456         bool ret;
 457
 458         mutex_lock(&dev_priv->wm.wm_mutex);
 459         ret = _intel_set_memory_cxsr(dev_priv, enable);
 460         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 461                 dev_priv->wm.vlv.cxsr = enable;
 462         else if (IS_G4X(dev_priv))
 463                 dev_priv->wm.g4x.cxsr = enable;
 464         mutex_unlock(&dev_priv->wm.wm_mutex);
 465
 466         return ret;
 467 }
 468
 469 /*
 470  * Latency for FIFO fetches is dependent on several factors:
 471  *   - memory configuration (speed, channels)
 472  *   - chipset
 473  *   - current MCH state
 474  * It can be fairly high in some situations, so here we assume a fairly
 475  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 476  * set this value too high, the FIFO will fetch frequently to stay full)
 477  * and power consumption (set it too low to save power and we might see
 478  * FIFO underruns and display "flicker").
 479  *
 480  * A value of 5us seems to be a good balance; safe for very low end
 481  * platforms but not overly aggressive on lower latency configs.
 482  */
 483 static const int pessimal_latency_ns = 5000;
 484
 485 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 486         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 487
 488 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 489 {
 490         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 491         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 492         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
 493         enum pipe pipe = crtc->pipe;
 494         int sprite0_start, sprite1_start;
 495         u32 dsparb, dsparb2, dsparb3;
 496
 497         switch (pipe) {
 498         case PIPE_A:
 499                 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 500                 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 501                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 502                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 503                 break;
 504         case PIPE_B:
 505                 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 506                 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 507                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 508                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 509                 break;
 510         case PIPE_C:
 511                 dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 512                 dsparb3 = intel_uncore_read(&dev_priv->uncore, DSPARB3);
 513                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 514                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 515                 break;
 516         default:
 517                 MISSING_CASE(pipe);
 518                 return;
 519         }
 520
 521         fifo_state->plane[PLANE_PRIMARY] = sprite0_start;
 522         fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start;
 523         fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start;
 524         fifo_state->plane[PLANE_CURSOR] = 63;
 525 }
 526
 527 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 528                               enum i9xx_plane_id i9xx_plane)
 529 {
 530         u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 531         int size;
 532
 533         size = dsparb & 0x7f;
 534         if (i9xx_plane == PLANE_B)
 535                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 536
 537         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 538                     dsparb, plane_name(i9xx_plane), size);
 539
 540         return size;
 541 }
 542
 543 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 544                               enum i9xx_plane_id i9xx_plane)
 545 {
 546         u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 547         int size;
 548
 549         size = dsparb & 0x1ff;
 550         if (i9xx_plane == PLANE_B)
 551                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 552         size >>= 1; /* Convert to cachelines */
 553
 554         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 555                     dsparb, plane_name(i9xx_plane), size);
 556
 557         return size;
 558 }
 559
 560 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 561                               enum i9xx_plane_id i9xx_plane)
 562 {
 563         u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
 564         int size;
 565
 566         size = dsparb & 0x7f;
 567         size >>= 2; /* Convert to cachelines */
 568
 569         drm_dbg_kms(&dev_priv->drm, "FIFO size - (0x%08x) %c: %d\n",
 570                     dsparb, plane_name(i9xx_plane), size);
 571
 572         return size;
 573 }
 574
 575 /* Pineview has different values for various configs */
 576 static const struct intel_watermark_params pnv_display_wm = {
 577         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 578         .max_wm = PINEVIEW_MAX_WM,
 579         .default_wm = PINEVIEW_DFT_WM,
 580         .guard_size = PINEVIEW_GUARD_WM,
 581         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 582 };
 583
 584 static const struct intel_watermark_params pnv_display_hplloff_wm = {
 585         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 586         .max_wm = PINEVIEW_MAX_WM,
 587         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 588         .guard_size = PINEVIEW_GUARD_WM,
 589         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 590 };
 591
 592 static const struct intel_watermark_params pnv_cursor_wm = {
 593         .fifo_size = PINEVIEW_CURSOR_FIFO,
 594         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 595         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 596         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 597         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 598 };
 599
 600 static const struct intel_watermark_params pnv_cursor_hplloff_wm = {
 601         .fifo_size = PINEVIEW_CURSOR_FIFO,
 602         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 603         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 604         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 605         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 606 };
 607
 608 static const struct intel_watermark_params i965_cursor_wm_info = {
 609         .fifo_size = I965_CURSOR_FIFO,
 610         .max_wm = I965_CURSOR_MAX_WM,
 611         .default_wm = I965_CURSOR_DFT_WM,
 612         .guard_size = 2,
 613         .cacheline_size = I915_FIFO_LINE_SIZE,
 614 };
 615
 616 static const struct intel_watermark_params i945_wm_info = {
 617         .fifo_size = I945_FIFO_SIZE,
 618         .max_wm = I915_MAX_WM,
 619         .default_wm = 1,
 620         .guard_size = 2,
 621         .cacheline_size = I915_FIFO_LINE_SIZE,
 622 };
 623
 624 static const struct intel_watermark_params i915_wm_info = {
 625         .fifo_size = I915_FIFO_SIZE,
 626         .max_wm = I915_MAX_WM,
 627         .default_wm = 1,
 628         .guard_size = 2,
 629         .cacheline_size = I915_FIFO_LINE_SIZE,
 630 };
 631
 632 static const struct intel_watermark_params i830_a_wm_info = {
 633         .fifo_size = I855GM_FIFO_SIZE,
 634         .max_wm = I915_MAX_WM,
 635         .default_wm = 1,
 636         .guard_size = 2,
 637         .cacheline_size = I830_FIFO_LINE_SIZE,
 638 };
 639
 640 static const struct intel_watermark_params i830_bc_wm_info = {
 641         .fifo_size = I855GM_FIFO_SIZE,
 642         .max_wm = I915_MAX_WM/2,
 643         .default_wm = 1,
 644         .guard_size = 2,
 645         .cacheline_size = I830_FIFO_LINE_SIZE,
 646 };
 647
 648 static const struct intel_watermark_params i845_wm_info = {
 649         .fifo_size = I830_FIFO_SIZE,
 650         .max_wm = I915_MAX_WM,
 651         .default_wm = 1,
 652         .guard_size = 2,
 653         .cacheline_size = I830_FIFO_LINE_SIZE,
 654 };
 655
 656 /**
 657  * intel_wm_method1 - Method 1 / "small buffer" watermark formula
 658  * @pixel_rate: Pipe pixel rate in kHz
 659  * @cpp: Plane bytes per pixel
 660  * @latency: Memory wakeup latency in 0.1us units
 661  *
 662  * Compute the watermark using the method 1 or "small buffer"
 663  * formula. The caller may additonally add extra cachelines
 664  * to account for TLB misses and clock crossings.
 665  *
 666  * This method is concerned with the short term drain rate
 667  * of the FIFO, ie. it does not account for blanking periods
 668  * which would effectively reduce the average drain rate across
 669  * a longer period. The name "small" refers to the fact the
 670  * FIFO is relatively small compared to the amount of data
 671  * fetched.
 672  *
 673  * The FIFO level vs. time graph might look something like:
 674  *
 675  *   |\   |\
 676  *   | \  | \
 677  * __---__---__ (- plane active, _ blanking)
 678  * -> time
 679  *
 680  * or perhaps like this:
 681  *
 682  *   |\|\  |\|\
 683  * __----__----__ (- plane active, _ blanking)
 684  * -> time
 685  *
 686  * Returns:
 687  * The watermark in bytes
 688  */
 689 static unsigned int intel_wm_method1(unsigned int pixel_rate,
 690                                      unsigned int cpp,
 691                                      unsigned int latency)
 692 {
 693         u64 ret;
 694
 695         ret = mul_u32_u32(pixel_rate, cpp * latency);
 696         ret = DIV_ROUND_UP_ULL(ret, 10000);
 697
 698         return ret;
 699 }
 700
 701 /**
 702  * intel_wm_method2 - Method 2 / "large buffer" watermark formula
 703  * @pixel_rate: Pipe pixel rate in kHz
 704  * @htotal: Pipe horizontal total
 705  * @width: Plane width in pixels
 706  * @cpp: Plane bytes per pixel
 707  * @latency: Memory wakeup latency in 0.1us units
 708  *
 709  * Compute the watermark using the method 2 or "large buffer"
 710  * formula. The caller may additonally add extra cachelines
 711  * to account for TLB misses and clock crossings.
 712  *
 713  * This method is concerned with the long term drain rate
 714  * of the FIFO, ie. it does account for blanking periods
 715  * which effectively reduce the average drain rate across
 716  * a longer period. The name "large" refers to the fact the
 717  * FIFO is relatively large compared to the amount of data
 718  * fetched.
 719  *
 720  * The FIFO level vs. time graph might look something like:
 721  *
 722  *    |\___       |\___
 723  *    |    \___   |    \___
 724  *    |        \  |        \
 725  * __ --__--__--__--__--__--__ (- plane active, _ blanking)
 726  * -> time
 727  *
 728  * Returns:
 729  * The watermark in bytes
 730  */
 731 static unsigned int intel_wm_method2(unsigned int pixel_rate,
 732                                      unsigned int htotal,
 733                                      unsigned int width,
 734                                      unsigned int cpp,
 735                                      unsigned int latency)
 736 {
 737         unsigned int ret;
 738
 739         /*
 740          * FIXME remove once all users are computing
 741          * watermarks in the correct place.
 742          */
 743         if (WARN_ON_ONCE(htotal == 0))
 744                 htotal = 1;
 745
 746         ret = (latency * pixel_rate) / (htotal * 10000);
 747         ret = (ret + 1) * width * cpp;
 748
 749         return ret;
 750 }
 751
 752 /**
 753  * intel_calculate_wm - calculate watermark level
 754  * @pixel_rate: pixel clock
 755  * @wm: chip FIFO params
 756  * @fifo_size: size of the FIFO buffer
 757  * @cpp: bytes per pixel
 758  * @latency_ns: memory latency for the platform
 759  *
 760  * Calculate the watermark level (the level at which the display plane will
 761  * start fetching from memory again).  Each chip has a different display
 762  * FIFO size and allocation, so the caller needs to figure that out and pass
 763  * in the correct intel_watermark_params structure.
 764  *
 765  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 766  * on the pixel size.  When it reaches the watermark level, it'll start
 767  * fetching FIFO line sized based chunks from memory until the FIFO fills
 768  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 769  * will occur, and a display engine hang could result.
 770  */
 771 static unsigned int intel_calculate_wm(int pixel_rate,
 772                                        const struct intel_watermark_params *wm,
 773                                        int fifo_size, int cpp,
 774                                        unsigned int latency_ns)
 775 {
 776         int entries, wm_size;
 777
 778         /*
 779          * Note: we need to make sure we don't overflow for various clock &
 780          * latency values.
 781          * clocks go from a few thousand to several hundred thousand.
 782          * latency is usually a few thousand
 783          */
 784         entries = intel_wm_method1(pixel_rate, cpp,
 785                                    latency_ns / 100);
 786         entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
 787                 wm->guard_size;
 788         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
 789
 790         wm_size = fifo_size - entries;
 791         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
 792
 793         /* Don't promote wm_size to unsigned... */
 794         if (wm_size > wm->max_wm)
 795                 wm_size = wm->max_wm;
 796         if (wm_size <= 0)
 797                 wm_size = wm->default_wm;
 798
 799         /*
 800          * Bspec seems to indicate that the value shouldn't be lower than
 801          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 802          * Lets go for 8 which is the burst size since certain platforms
 803          * already use a hardcoded 8 (which is what the spec says should be
 804          * done).
 805          */
 806         if (wm_size <= 8)
 807                 wm_size = 8;
 808
 809         return wm_size;
 810 }
 811
 812 static bool is_disabling(int old, int new, int threshold)
 813 {
 814         return old >= threshold && new < threshold;
 815 }
 816
 817 static bool is_enabling(int old, int new, int threshold)
 818 {
 819         return old < threshold && new >= threshold;
 820 }
 821
 822 static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
 823 {
 824         return dev_priv->wm.max_level + 1;
 825 }
 826
 827 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
 828                                    const struct intel_plane_state *plane_state)
 829 {
 830         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 831
 832         /* FIXME check the 'enable' instead */
 833         if (!crtc_state->hw.active)
 834                 return false;
 835
 836         /*
 837          * Treat cursor with fb as always visible since cursor updates
 838          * can happen faster than the vrefresh rate, and the current
 839          * watermark code doesn't handle that correctly. Cursor updates
 840          * which set/clear the fb or change the cursor size are going
 841          * to get throttled by intel_legacy_cursor_update() to work
 842          * around this problem with the watermark code.
 843          */
 844         if (plane->id == PLANE_CURSOR)
 845                 return plane_state->hw.fb != NULL;
 846         else
 847                 return plane_state->uapi.visible;
 848 }
 849
 850 static bool intel_crtc_active(struct intel_crtc *crtc)
 851 {
 852         /* Be paranoid as we can arrive here with only partial
 853          * state retrieved from the hardware during setup.
 854          *
 855          * We can ditch the adjusted_mode.crtc_clock check as soon
 856          * as Haswell has gained clock readout/fastboot support.
 857          *
 858          * We can ditch the crtc->primary->state->fb check as soon as we can
 859          * properly reconstruct framebuffers.
 860          *
 861          * FIXME: The intel_crtc->active here should be switched to
 862          * crtc->state->active once we have proper CRTC states wired up
 863          * for atomic.
 864          */
 865         return crtc->active && crtc->base.primary->state->fb &&
 866                 crtc->config->hw.adjusted_mode.crtc_clock;
 867 }
 868
 869 static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 870 {
 871         struct intel_crtc *crtc, *enabled = NULL;
 872
 873         for_each_intel_crtc(&dev_priv->drm, crtc) {
 874                 if (intel_crtc_active(crtc)) {
 875                         if (enabled)
 876                                 return NULL;
 877                         enabled = crtc;
 878                 }
 879         }
 880
 881         return enabled;
 882 }
 883
 884 static void pnv_update_wm(struct intel_crtc *unused_crtc)
 885 {
 886         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 887         struct intel_crtc *crtc;
 888         const struct cxsr_latency *latency;
 889         u32 reg;
 890         unsigned int wm;
 891
 892         latency = intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 893                                          dev_priv->is_ddr3,
 894                                          dev_priv->fsb_freq,
 895                                          dev_priv->mem_freq);
 896         if (!latency) {
 897                 drm_dbg_kms(&dev_priv->drm,
 898                             "Unknown FSB/MEM found, disable CxSR\n");
 899                 intel_set_memory_cxsr(dev_priv, false);
 900                 return;
 901         }
 902
 903         crtc = single_enabled_crtc(dev_priv);
 904         if (crtc) {
 905                 const struct drm_display_mode *pipe_mode =
 906                         &crtc->config->hw.pipe_mode;
 907                 const struct drm_framebuffer *fb =
 908                         crtc->base.primary->state->fb;
 909                 int cpp = fb->format->cpp[0];
 910                 int clock = pipe_mode->crtc_clock;
 911
 912                 /* Display SR */
 913                 wm = intel_calculate_wm(clock, &pnv_display_wm,
 914                                         pnv_display_wm.fifo_size,
 915                                         cpp, latency->display_sr);
 916                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW1);
 917                 reg &= ~DSPFW_SR_MASK;
 918                 reg |= FW_WM(wm, SR);
 919                 intel_uncore_write(&dev_priv->uncore, DSPFW1, reg);
 920                 drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg);
 921
 922                 /* cursor SR */
 923                 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
 924                                         pnv_display_wm.fifo_size,
 925                                         4, latency->cursor_sr);
 926                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 927                 reg &= ~DSPFW_CURSOR_SR_MASK;
 928                 reg |= FW_WM(wm, CURSOR_SR);
 929                 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 930
 931                 /* Display HPLL off SR */
 932                 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
 933                                         pnv_display_hplloff_wm.fifo_size,
 934                                         cpp, latency->display_hpll_disable);
 935                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 936                 reg &= ~DSPFW_HPLL_SR_MASK;
 937                 reg |= FW_WM(wm, HPLL_SR);
 938                 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 939
 940                 /* cursor HPLL off SR */
 941                 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
 942                                         pnv_display_hplloff_wm.fifo_size,
 943                                         4, latency->cursor_hpll_disable);
 944                 reg = intel_uncore_read(&dev_priv->uncore, DSPFW3);
 945                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 946                 reg |= FW_WM(wm, HPLL_CURSOR);
 947                 intel_uncore_write(&dev_priv->uncore, DSPFW3, reg);
 948                 drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg);
 949
 950                 intel_set_memory_cxsr(dev_priv, true);
 951         } else {
 952                 intel_set_memory_cxsr(dev_priv, false);
 953         }
 954 }
 955
 956 /*
 957  * Documentation says:
 958  * "If the line size is small, the TLB fetches can get in the way of the
 959  *  data fetches, causing some lag in the pixel data return which is not
 960  *  accounted for in the above formulas. The following adjustment only
 961  *  needs to be applied if eight whole lines fit in the buffer at once.
 962  *  The WM is adjusted upwards by the difference between the FIFO size
 963  *  and the size of 8 whole lines. This adjustment is always performed
 964  *  in the actual pixel depth regardless of whether FBC is enabled or not."
 965  */
 966 static unsigned int g4x_tlb_miss_wa(int fifo_size, int width, int cpp)
 967 {
 968         int tlb_miss = fifo_size * 64 - width * cpp * 8;
 969
 970         return max(0, tlb_miss);
 971 }
 972
 973 static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
 974                                 const struct g4x_wm_values *wm)
 975 {
 976         enum pipe pipe;
 977
 978         for_each_pipe(dev_priv, pipe)
 979                 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
 980
 981         intel_uncore_write(&dev_priv->uncore, DSPFW1,
 982                    FW_WM(wm->sr.plane, SR) |
 983                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
 984                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
 985                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
 986         intel_uncore_write(&dev_priv->uncore, DSPFW2,
 987                    (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
 988                    FW_WM(wm->sr.fbc, FBC_SR) |
 989                    FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
 990                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
 991                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
 992                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
 993         intel_uncore_write(&dev_priv->uncore, DSPFW3,
 994                    (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
 995                    FW_WM(wm->sr.cursor, CURSOR_SR) |
 996                    FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
 997                    FW_WM(wm->hpll.plane, HPLL_SR));
 998
 999         intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
1000 }
1001
1002 #define FW_WM_VLV(value, plane) \
1003         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
1004
1005 static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
1006                                 const struct vlv_wm_values *wm)
1007 {
1008         enum pipe pipe;
1009
1010         for_each_pipe(dev_priv, pipe) {
1011                 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1012
1013                 intel_uncore_write(&dev_priv->uncore, VLV_DDL(pipe),
1014                            (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1015                            (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1016                            (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1017                            (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1018         }
1019
1020         /*
1021          * Zero the (unused) WM1 watermarks, and also clear all the
1022          * high order bits so that there are no out of bounds values
1023          * present in the registers during the reprogramming.
1024          */
1025         intel_uncore_write(&dev_priv->uncore, DSPHOWM, 0);
1026         intel_uncore_write(&dev_priv->uncore, DSPHOWM1, 0);
1027         intel_uncore_write(&dev_priv->uncore, DSPFW4, 0);
1028         intel_uncore_write(&dev_priv->uncore, DSPFW5, 0);
1029         intel_uncore_write(&dev_priv->uncore, DSPFW6, 0);
1030
1031         intel_uncore_write(&dev_priv->uncore, DSPFW1,
1032                    FW_WM(wm->sr.plane, SR) |
1033                    FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1034                    FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1035                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1036         intel_uncore_write(&dev_priv->uncore, DSPFW2,
1037                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1038                    FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1039                    FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1040         intel_uncore_write(&dev_priv->uncore, DSPFW3,
1041                    FW_WM(wm->sr.cursor, CURSOR_SR));
1042
1043         if (IS_CHERRYVIEW(dev_priv)) {
1044                 intel_uncore_write(&dev_priv->uncore, DSPFW7_CHV,
1045                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1046                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1047                 intel_uncore_write(&dev_priv->uncore, DSPFW8_CHV,
1048                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1049                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1050                 intel_uncore_write(&dev_priv->uncore, DSPFW9_CHV,
1051                            FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1052                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1053                 intel_uncore_write(&dev_priv->uncore, DSPHOWM,
1054                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1055                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1056                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1057                            FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1058                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1059                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1060                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1061                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1062                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1063                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1064         } else {
1065                 intel_uncore_write(&dev_priv->uncore, DSPFW7,
1066                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1067                            FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1068                 intel_uncore_write(&dev_priv->uncore, DSPHOWM,
1069                            FW_WM(wm->sr.plane >> 9, SR_HI) |
1070                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1071                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1072                            FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1073                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1074                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1075                            FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1076         }
1077
1078         intel_uncore_posting_read(&dev_priv->uncore, DSPFW1);
1079 }
1080
1081 #undef FW_WM_VLV
1082
1083 static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
1084 {
1085         /* all latencies in usec */
1086         dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1087         dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1088         dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1089
1090         dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1091 }
1092
1093 static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
1094 {
1095         /*
1096          * DSPCNTR[13] supposedly controls whether the
1097          * primary plane can use the FIFO space otherwise
1098          * reserved for the sprite plane. It's not 100% clear
1099          * what the actual FIFO size is, but it looks like we
1100          * can happily set both primary and sprite watermarks
1101          * up to 127 cachelines. So that would seem to mean
1102          * that either DSPCNTR[13] doesn't do anything, or that
1103          * the total FIFO is >= 256 cachelines in size. Either
1104          * way, we don't seem to have to worry about this
1105          * repartitioning as the maximum watermark value the
1106          * register can hold for each plane is lower than the
1107          * minimum FIFO size.
1108          */
1109         switch (plane_id) {
1110         case PLANE_CURSOR:
1111                 return 63;
1112         case PLANE_PRIMARY:
1113                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 511;
1114         case PLANE_SPRITE0:
1115                 return level == G4X_WM_LEVEL_NORMAL ? 127 : 0;
1116         default:
1117                 MISSING_CASE(plane_id);
1118                 return 0;
1119         }
1120 }
1121
1122 static int g4x_fbc_fifo_size(int level)
1123 {
1124         switch (level) {
1125         case G4X_WM_LEVEL_SR:
1126                 return 7;
1127         case G4X_WM_LEVEL_HPLL:
1128                 return 15;
1129         default:
1130                 MISSING_CASE(level);
1131                 return 0;
1132         }
1133 }
1134
1135 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
1136                           const struct intel_plane_state *plane_state,
1137                           int level)
1138 {
1139         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1140         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1141         const struct drm_display_mode *pipe_mode =
1142                 &crtc_state->hw.pipe_mode;
1143         unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1144         unsigned int clock, htotal, cpp, width, wm;
1145
1146         if (latency == 0)
1147                 return USHRT_MAX;
1148
1149         if (!intel_wm_plane_visible(crtc_state, plane_state))
1150                 return 0;
1151
1152         cpp = plane_state->hw.fb->format->cpp[0];
1153
1154         /*
1155          * Not 100% sure which way ELK should go here as the
1156          * spec only says CL/CTG should assume 32bpp and BW
1157          * doesn't need to. But as these things followed the
1158          * mobile vs. desktop lines on gen3 as well, let's
1159          * assume ELK doesn't need this.
1160          *
1161          * The spec also fails to list such a restriction for
1162          * the HPLL watermark, which seems a little strange.
1163          * Let's use 32bpp for the HPLL watermark as well.
1164          */
1165         if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY &&
1166             level != G4X_WM_LEVEL_NORMAL)
1167                 cpp = max(cpp, 4u);
1168
1169         clock = pipe_mode->crtc_clock;
1170         htotal = pipe_mode->crtc_htotal;
1171
1172         width = drm_rect_width(&plane_state->uapi.dst);
1173
1174         if (plane->id == PLANE_CURSOR) {
1175                 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1176         } else if (plane->id == PLANE_PRIMARY &&
1177                    level == G4X_WM_LEVEL_NORMAL) {
1178                 wm = intel_wm_method1(clock, cpp, latency);
1179         } else {
1180                 unsigned int small, large;
1181
1182                 small = intel_wm_method1(clock, cpp, latency);
1183                 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1184
1185                 wm = min(small, large);
1186         }
1187
1188         wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1189                               width, cpp);
1190
1191         wm = DIV_ROUND_UP(wm, 64) + 2;
1192
1193         return min_t(unsigned int, wm, USHRT_MAX);
1194 }
1195
1196 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1197                                  int level, enum plane_id plane_id, u16 value)
1198 {
1199         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1200         bool dirty = false;
1201
1202         for (; level < intel_wm_num_levels(dev_priv); level++) {
1203                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1204
1205                 dirty |= raw->plane[plane_id] != value;
1206                 raw->plane[plane_id] = value;
1207         }
1208
1209         return dirty;
1210 }
1211
1212 static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
1213                                int level, u16 value)
1214 {
1215         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1216         bool dirty = false;
1217
1218         /* NORMAL level doesn't have an FBC watermark */
1219         level = max(level, G4X_WM_LEVEL_SR);
1220
1221         for (; level < intel_wm_num_levels(dev_priv); level++) {
1222                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1223
1224                 dirty |= raw->fbc != value;
1225                 raw->fbc = value;
1226         }
1227
1228         return dirty;
1229 }
1230
1231 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
1232                               const struct intel_plane_state *plane_state,
1233                               u32 pri_val);
1234
1235 static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1236                                      const struct intel_plane_state *plane_state)
1237 {
1238         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1239         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1240         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1241         enum plane_id plane_id = plane->id;
1242         bool dirty = false;
1243         int level;
1244
1245         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1246                 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1247                 if (plane_id == PLANE_PRIMARY)
1248                         dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0);
1249                 goto out;
1250         }
1251
1252         for (level = 0; level < num_levels; level++) {
1253                 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1254                 int wm, max_wm;
1255
1256                 wm = g4x_compute_wm(crtc_state, plane_state, level);
1257                 max_wm = g4x_plane_fifo_size(plane_id, level);
1258
1259                 if (wm > max_wm)
1260                         break;
1261
1262                 dirty |= raw->plane[plane_id] != wm;
1263                 raw->plane[plane_id] = wm;
1264
1265                 if (plane_id != PLANE_PRIMARY ||
1266                     level == G4X_WM_LEVEL_NORMAL)
1267                         continue;
1268
1269                 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1270                                         raw->plane[plane_id]);
1271                 max_wm = g4x_fbc_fifo_size(level);
1272
1273                 /*
1274                  * FBC wm is not mandatory as we
1275                  * can always just disable its use.
1276                  */
1277                 if (wm > max_wm)
1278                         wm = USHRT_MAX;
1279
1280                 dirty |= raw->fbc != wm;
1281                 raw->fbc = wm;
1282         }
1283
1284         /* mark watermarks as invalid */
1285         dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1286
1287         if (plane_id == PLANE_PRIMARY)
1288                 dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
1289
1290  out:
1291         if (dirty) {
1292                 drm_dbg_kms(&dev_priv->drm,
1293                             "%s watermarks: normal=%d, SR=%d, HPLL=%d\n",
1294                             plane->base.name,
1295                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1296                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1297                             crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1298
1299                 if (plane_id == PLANE_PRIMARY)
1300                         drm_dbg_kms(&dev_priv->drm,
1301                                     "FBC watermarks: SR=%d, HPLL=%d\n",
1302                                     crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1303                                     crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1304         }
1305
1306         return dirty;
1307 }
1308
1309 static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1310                                       enum plane_id plane_id, int level)
1311 {
1312         const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1313
1314         return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level);
1315 }
1316
1317 static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
1318                                      int level)
1319 {
1320         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1321
1322         if (level > dev_priv->wm.max_level)
1323                 return false;
1324
1325         return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1326                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1327                 g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1328 }
1329
1330 /* mark all levels starting from 'level' as invalid */
1331 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1332                                struct g4x_wm_state *wm_state, int level)
1333 {
1334         if (level <= G4X_WM_LEVEL_NORMAL) {
1335                 enum plane_id plane_id;
1336
1337                 for_each_plane_id_on_crtc(crtc, plane_id)
1338                         wm_state->wm.plane[plane_id] = USHRT_MAX;
1339         }
1340
1341         if (level <= G4X_WM_LEVEL_SR) {
1342                 wm_state->cxsr = false;
1343                 wm_state->sr.cursor = USHRT_MAX;
1344                 wm_state->sr.plane = USHRT_MAX;
1345                 wm_state->sr.fbc = USHRT_MAX;
1346         }
1347
1348         if (level <= G4X_WM_LEVEL_HPLL) {
1349                 wm_state->hpll_en = false;
1350                 wm_state->hpll.cursor = USHRT_MAX;
1351                 wm_state->hpll.plane = USHRT_MAX;
1352                 wm_state->hpll.fbc = USHRT_MAX;
1353         }
1354 }
1355
1356 static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
1357                                int level)
1358 {
1359         if (level < G4X_WM_LEVEL_SR)
1360                 return false;
1361
1362         if (level >= G4X_WM_LEVEL_SR &&
1363             wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
1364                 return false;
1365
1366         if (level >= G4X_WM_LEVEL_HPLL &&
1367             wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
1368                 return false;
1369
1370         return true;
1371 }
1372
1373 static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1374 {
1375         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1376         struct intel_atomic_state *state =
1377                 to_intel_atomic_state(crtc_state->uapi.state);
1378         struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1379         int num_active_planes = hweight8(crtc_state->active_planes &
1380                                          ~BIT(PLANE_CURSOR));
1381         const struct g4x_pipe_wm *raw;
1382         const struct intel_plane_state *old_plane_state;
1383         const struct intel_plane_state *new_plane_state;
1384         struct intel_plane *plane;
1385         enum plane_id plane_id;
1386         int i, level;
1387         unsigned int dirty = 0;
1388
1389         for_each_oldnew_intel_plane_in_state(state, plane,
1390                                              old_plane_state,
1391                                              new_plane_state, i) {
1392                 if (new_plane_state->hw.crtc != &crtc->base &&
1393                     old_plane_state->hw.crtc != &crtc->base)
1394                         continue;
1395
1396                 if (g4x_raw_plane_wm_compute(crtc_state, new_plane_state))
1397                         dirty |= BIT(plane->id);
1398         }
1399
1400         if (!dirty)
1401                 return 0;
1402
1403         level = G4X_WM_LEVEL_NORMAL;
1404         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1405                 goto out;
1406
1407         raw = &crtc_state->wm.g4x.raw[level];
1408         for_each_plane_id_on_crtc(crtc, plane_id)
1409                 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1410
1411         level = G4X_WM_LEVEL_SR;
1412         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1413                 goto out;
1414
1415         raw = &crtc_state->wm.g4x.raw[level];
1416         wm_state->sr.plane = raw->plane[PLANE_PRIMARY];
1417         wm_state->sr.cursor = raw->plane[PLANE_CURSOR];
1418         wm_state->sr.fbc = raw->fbc;
1419
1420         wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
1421
1422         level = G4X_WM_LEVEL_HPLL;
1423         if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
1424                 goto out;
1425
1426         raw = &crtc_state->wm.g4x.raw[level];
1427         wm_state->hpll.plane = raw->plane[PLANE_PRIMARY];
1428         wm_state->hpll.cursor = raw->plane[PLANE_CURSOR];
1429         wm_state->hpll.fbc = raw->fbc;
1430
1431         wm_state->hpll_en = wm_state->cxsr;
1432
1433         level++;
1434
1435  out:
1436         if (level == G4X_WM_LEVEL_NORMAL)
1437                 return -EINVAL;
1438
1439         /* invalidate the higher levels */
1440         g4x_invalidate_wms(crtc, wm_state, level);
1441
1442         /*
1443          * Determine if the FBC watermark(s) can be used. IF
1444          * this isn't the case we prefer to disable the FBC
1445          * watermark(s) rather than disable the SR/HPLL
1446          * level(s) entirely. 'level-1' is the highest valid
1447          * level here.
1448          */
1449         wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1);
1450
1451         return 0;
1452 }
1453
1454 static int g4x_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
1455 {
1456         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1457         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1458         struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1459         const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1460         struct intel_atomic_state *intel_state =
1461                 to_intel_atomic_state(new_crtc_state->uapi.state);
1462         const struct intel_crtc_state *old_crtc_state =
1463                 intel_atomic_get_old_crtc_state(intel_state, crtc);
1464         const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1465         enum plane_id plane_id;
1466
1467         if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
1468                 *intermediate = *optimal;
1469
1470                 intermediate->cxsr = false;
1471                 intermediate->hpll_en = false;
1472                 goto out;
1473         }
1474
1475         intermediate->cxsr = optimal->cxsr && active->cxsr &&
1476                 !new_crtc_state->disable_cxsr;
1477         intermediate->hpll_en = optimal->hpll_en && active->hpll_en &&
1478                 !new_crtc_state->disable_cxsr;
1479         intermediate->fbc_en = optimal->fbc_en && active->fbc_en;
1480
1481         for_each_plane_id_on_crtc(crtc, plane_id) {
1482                 intermediate->wm.plane[plane_id] =
1483                         max(optimal->wm.plane[plane_id],
1484                             active->wm.plane[plane_id]);
1485
1486                 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
1487                             g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL));
1488         }
1489
1490         intermediate->sr.plane = max(optimal->sr.plane,
1491                                      active->sr.plane);
1492         intermediate->sr.cursor = max(optimal->sr.cursor,
1493                                       active->sr.cursor);
1494         intermediate->sr.fbc = max(optimal->sr.fbc,
1495                                    active->sr.fbc);
1496
1497         intermediate->hpll.plane = max(optimal->hpll.plane,
1498                                        active->hpll.plane);
1499         intermediate->hpll.cursor = max(optimal->hpll.cursor,
1500                                         active->hpll.cursor);
1501         intermediate->hpll.fbc = max(optimal->hpll.fbc,
1502                                      active->hpll.fbc);
1503
1504         drm_WARN_ON(&dev_priv->drm,
1505                     (intermediate->sr.plane >
1506                      g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) ||
1507                      intermediate->sr.cursor >
1508                      g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) &&
1509                     intermediate->cxsr);
1510         drm_WARN_ON(&dev_priv->drm,
1511                     (intermediate->sr.plane >
1512                      g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) ||
1513                      intermediate->sr.cursor >
1514                      g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) &&
1515                     intermediate->hpll_en);
1516
1517         drm_WARN_ON(&dev_priv->drm,
1518                     intermediate->sr.fbc > g4x_fbc_fifo_size(1) &&
1519                     intermediate->fbc_en && intermediate->cxsr);
1520         drm_WARN_ON(&dev_priv->drm,
1521                     intermediate->hpll.fbc > g4x_fbc_fifo_size(2) &&
1522                     intermediate->fbc_en && intermediate->hpll_en);
1523
1524 out:
1525         /*
1526          * If our intermediate WM are identical to the final WM, then we can
1527          * omit the post-vblank programming; only update if it's different.
1528          */
1529         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
1530                 new_crtc_state->wm.need_postvbl_update = true;
1531
1532         return 0;
1533 }
1534
1535 static void g4x_merge_wm(struct drm_i915_private *dev_priv,
1536                          struct g4x_wm_values *wm)
1537 {
1538         struct intel_crtc *crtc;
1539         int num_active_pipes = 0;
1540
1541         wm->cxsr = true;
1542         wm->hpll_en = true;
1543         wm->fbc_en = true;
1544
1545         for_each_intel_crtc(&dev_priv->drm, crtc) {
1546                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1547
1548                 if (!crtc->active)
1549                         continue;
1550
1551                 if (!wm_state->cxsr)
1552                         wm->cxsr = false;
1553                 if (!wm_state->hpll_en)
1554                         wm->hpll_en = false;
1555                 if (!wm_state->fbc_en)
1556                         wm->fbc_en = false;
1557
1558                 num_active_pipes++;
1559         }
1560
1561         if (num_active_pipes != 1) {
1562                 wm->cxsr = false;
1563                 wm->hpll_en = false;
1564                 wm->fbc_en = false;
1565         }
1566
1567         for_each_intel_crtc(&dev_priv->drm, crtc) {
1568                 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1569                 enum pipe pipe = crtc->pipe;
1570
1571                 wm->pipe[pipe] = wm_state->wm;
1572                 if (crtc->active && wm->cxsr)
1573                         wm->sr = wm_state->sr;
1574                 if (crtc->active && wm->hpll_en)
1575                         wm->hpll = wm_state->hpll;
1576         }
1577 }
1578
1579 static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
1580 {
1581         struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1582         struct g4x_wm_values new_wm = {};
1583
1584         g4x_merge_wm(dev_priv, &new_wm);
1585
1586         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
1587                 return;
1588
1589         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
1590                 _intel_set_memory_cxsr(dev_priv, false);
1591
1592         g4x_write_wm_values(dev_priv, &new_wm);
1593
1594         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
1595                 _intel_set_memory_cxsr(dev_priv, true);
1596
1597         *old_wm = new_wm;
1598 }
1599
1600 static void g4x_initial_watermarks(struct intel_atomic_state *state,
1601                                    struct intel_crtc *crtc)
1602 {
1603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1604         const struct intel_crtc_state *crtc_state =
1605                 intel_atomic_get_new_crtc_state(state, crtc);
1606
1607         mutex_lock(&dev_priv->wm.wm_mutex);
1608         crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1609         g4x_program_watermarks(dev_priv);
1610         mutex_unlock(&dev_priv->wm.wm_mutex);
1611 }
1612
1613 static void g4x_optimize_watermarks(struct intel_atomic_state *state,
1614                                     struct intel_crtc *crtc)
1615 {
1616         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1617         const struct intel_crtc_state *crtc_state =
1618                 intel_atomic_get_new_crtc_state(state, crtc);
1619
1620         if (!crtc_state->wm.need_postvbl_update)
1621                 return;
1622
1623         mutex_lock(&dev_priv->wm.wm_mutex);
1624         crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1625         g4x_program_watermarks(dev_priv);
1626         mutex_unlock(&dev_priv->wm.wm_mutex);
1627 }
1628
1629 /* latency must be in 0.1us units. */
1630 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
1631                                    unsigned int htotal,
1632                                    unsigned int width,
1633                                    unsigned int cpp,
1634                                    unsigned int latency)
1635 {
1636         unsigned int ret;
1637
1638         ret = intel_wm_method2(pixel_rate, htotal,
1639                                width, cpp, latency);
1640         ret = DIV_ROUND_UP(ret, 64);
1641
1642         return ret;
1643 }
1644
1645 static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
1646 {
1647         /* all latencies in usec */
1648         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1649
1650         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1651
1652         if (IS_CHERRYVIEW(dev_priv)) {
1653                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1654                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1655
1656                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1657         }
1658 }
1659
1660 static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
1661                                 const struct intel_plane_state *plane_state,
1662                                 int level)
1663 {
1664         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1665         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1666         const struct drm_display_mode *pipe_mode =
1667                 &crtc_state->hw.pipe_mode;
1668         unsigned int clock, htotal, cpp, width, wm;
1669
1670         if (dev_priv->wm.pri_latency[level] == 0)
1671                 return USHRT_MAX;
1672
1673         if (!intel_wm_plane_visible(crtc_state, plane_state))
1674                 return 0;
1675
1676         cpp = plane_state->hw.fb->format->cpp[0];
1677         clock = pipe_mode->crtc_clock;
1678         htotal = pipe_mode->crtc_htotal;
1679         width = crtc_state->pipe_src_w;
1680
1681         if (plane->id == PLANE_CURSOR) {
1682                 /*
1683                  * FIXME the formula gives values that are
1684                  * too big for the cursor FIFO, and hence we
1685                  * would never be able to use cursors. For
1686                  * now just hardcode the watermark.
1687                  */
1688                 wm = 63;
1689         } else {
1690                 wm = vlv_wm_method2(clock, htotal, width, cpp,
1691                                     dev_priv->wm.pri_latency[level] * 10);
1692         }
1693
1694         return min_t(unsigned int, wm, USHRT_MAX);
1695 }
1696
1697 static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
1698 {
1699         return (active_planes & (BIT(PLANE_SPRITE0) |
1700                                  BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1);
1701 }
1702
1703 static int vlv_compute_fifo(struct intel_crtc_state *crtc_state)
1704 {
1705         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1706         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1707         const struct g4x_pipe_wm *raw =
1708                 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1709         struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1710         unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR);
1711         int num_active_planes = hweight8(active_planes);
1712         const int fifo_size = 511;
1713         int fifo_extra, fifo_left = fifo_size;
1714         int sprite0_fifo_extra = 0;
1715         unsigned int total_rate;
1716         enum plane_id plane_id;
1717
1718         /*
1719          * When enabling sprite0 after sprite1 has already been enabled
1720          * we tend to get an underrun unless sprite0 already has some
1721          * FIFO space allcoated. Hence we always allocate at least one
1722          * cacheline for sprite0 whenever sprite1 is enabled.
1723          *
1724          * All other plane enable sequences appear immune to this problem.
1725          */
1726         if (vlv_need_sprite0_fifo_workaround(active_planes))
1727                 sprite0_fifo_extra = 1;
1728
1729         total_rate = raw->plane[PLANE_PRIMARY] +
1730                 raw->plane[PLANE_SPRITE0] +
1731                 raw->plane[PLANE_SPRITE1] +
1732                 sprite0_fifo_extra;
1733
1734         if (total_rate > fifo_size)
1735                 return -EINVAL;
1736
1737         if (total_rate == 0)
1738                 total_rate = 1;
1739
1740         for_each_plane_id_on_crtc(crtc, plane_id) {
1741                 unsigned int rate;
1742
1743                 if ((active_planes & BIT(plane_id)) == 0) {
1744                         fifo_state->plane[plane_id] = 0;
1745                         continue;
1746                 }
1747
1748                 rate = raw->plane[plane_id];
1749                 fifo_state->plane[plane_id] = fifo_size * rate / total_rate;
1750                 fifo_left -= fifo_state->plane[plane_id];
1751         }
1752
1753         fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra;
1754         fifo_left -= sprite0_fifo_extra;
1755
1756         fifo_state->plane[PLANE_CURSOR] = 63;
1757
1758         fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1);
1759
1760         /* spread the remainder evenly */
1761         for_each_plane_id_on_crtc(crtc, plane_id) {
1762                 int plane_extra;
1763
1764                 if (fifo_left == 0)
1765                         break;
1766
1767                 if ((active_planes & BIT(plane_id)) == 0)
1768                         continue;
1769
1770                 plane_extra = min(fifo_extra, fifo_left);
1771                 fifo_state->plane[plane_id] += plane_extra;
1772                 fifo_left -= plane_extra;
1773         }
1774
1775         drm_WARN_ON(&dev_priv->drm, active_planes != 0 && fifo_left != 0);
1776
1777         /* give it all to the first plane if none are active */
1778         if (active_planes == 0) {
1779                 drm_WARN_ON(&dev_priv->drm, fifo_left != fifo_size);
1780                 fifo_state->plane[PLANE_PRIMARY] = fifo_left;
1781         }
1782
1783         return 0;
1784 }
1785
1786 /* mark all levels starting from 'level' as invalid */
1787 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1788                                struct vlv_wm_state *wm_state, int level)
1789 {
1790         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1791
1792         for (; level < intel_wm_num_levels(dev_priv); level++) {
1793                 enum plane_id plane_id;
1794
1795                 for_each_plane_id_on_crtc(crtc, plane_id)
1796                         wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1797
1798                 wm_state->sr[level].cursor = USHRT_MAX;
1799                 wm_state->sr[level].plane = USHRT_MAX;
1800         }
1801 }
1802
1803 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1804 {
1805         if (wm > fifo_size)
1806                 return USHRT_MAX;
1807         else
1808                 return fifo_size - wm;
1809 }
1810
1811 /*
1812  * Starting from 'level' set all higher
1813  * levels to 'value' in the "raw" watermarks.
1814  */
1815 static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
1816                                  int level, enum plane_id plane_id, u16 value)
1817 {
1818         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1819         int num_levels = intel_wm_num_levels(dev_priv);
1820         bool dirty = false;
1821
1822         for (; level < num_levels; level++) {
1823                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1824
1825                 dirty |= raw->plane[plane_id] != value;
1826                 raw->plane[plane_id] = value;
1827         }
1828
1829         return dirty;
1830 }
1831
1832 static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
1833                                      const struct intel_plane_state *plane_state)
1834 {
1835         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1836         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1837         enum plane_id plane_id = plane->id;
1838         int num_levels = intel_wm_num_levels(to_i915(plane->base.dev));
1839         int level;
1840         bool dirty = false;
1841
1842         if (!intel_wm_plane_visible(crtc_state, plane_state)) {
1843                 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0);
1844                 goto out;
1845         }
1846
1847         for (level = 0; level < num_levels; level++) {
1848                 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1849                 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1850                 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511;
1851
1852                 if (wm > max_wm)
1853                         break;
1854
1855                 dirty |= raw->plane[plane_id] != wm;
1856                 raw->plane[plane_id] = wm;
1857         }
1858
1859         /* mark all higher levels as invalid */
1860         dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
1861
1862 out:
1863         if (dirty)
1864                 drm_dbg_kms(&dev_priv->drm,
1865                             "%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n",
1866                             plane->base.name,
1867                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1868                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1869                             crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1870
1871         return dirty;
1872 }
1873
1874 static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state,
1875                                       enum plane_id plane_id, int level)
1876 {
1877         const struct g4x_pipe_wm *raw =
1878                 &crtc_state->wm.vlv.raw[level];
1879         const struct vlv_fifo_state *fifo_state =
1880                 &crtc_state->wm.vlv.fifo_state;
1881
1882         return raw->plane[plane_id] <= fifo_state->plane[plane_id];
1883 }
1884
1885 static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level)
1886 {
1887         return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
1888                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) &&
1889                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) &&
1890                 vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level);
1891 }
1892
1893 static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
1894 {
1895         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1896         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1897         struct intel_atomic_state *state =
1898                 to_intel_atomic_state(crtc_state->uapi.state);
1899         struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1900         const struct vlv_fifo_state *fifo_state =
1901                 &crtc_state->wm.vlv.fifo_state;
1902         int num_active_planes = hweight8(crtc_state->active_planes &
1903                                          ~BIT(PLANE_CURSOR));
1904         bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
1905         const struct intel_plane_state *old_plane_state;
1906         const struct intel_plane_state *new_plane_state;
1907         struct intel_plane *plane;
1908         enum plane_id plane_id;
1909         int level, ret, i;
1910         unsigned int dirty = 0;
1911
1912         for_each_oldnew_intel_plane_in_state(state, plane,
1913                                              old_plane_state,
1914                                              new_plane_state, i) {
1915                 if (new_plane_state->hw.crtc != &crtc->base &&
1916                     old_plane_state->hw.crtc != &crtc->base)
1917                         continue;
1918
1919                 if (vlv_raw_plane_wm_compute(crtc_state, new_plane_state))
1920                         dirty |= BIT(plane->id);
1921         }
1922
1923         /*
1924          * DSPARB registers may have been reset due to the
1925          * power well being turned off. Make sure we restore
1926          * them to a consistent state even if no primary/sprite
1927          * planes are initially active.
1928          */
1929         if (needs_modeset)
1930                 crtc_state->fifo_changed = true;
1931
1932         if (!dirty)
1933                 return 0;
1934
1935         /* cursor changes don't warrant a FIFO recompute */
1936         if (dirty & ~BIT(PLANE_CURSOR)) {
1937                 const struct intel_crtc_state *old_crtc_state =
1938                         intel_atomic_get_old_crtc_state(state, crtc);
1939                 const struct vlv_fifo_state *old_fifo_state =
1940                         &old_crtc_state->wm.vlv.fifo_state;
1941
1942                 ret = vlv_compute_fifo(crtc_state);
1943                 if (ret)
1944                         return ret;
1945
1946                 if (needs_modeset ||
1947                     memcmp(old_fifo_state, fifo_state,
1948                            sizeof(*fifo_state)) != 0)
1949                         crtc_state->fifo_changed = true;
1950         }
1951
1952         /* initially allow all levels */
1953         wm_state->num_levels = intel_wm_num_levels(dev_priv);
1954         /*
1955          * Note that enabling cxsr with no primary/sprite planes
1956          * enabled can wedge the pipe. Hence we only allow cxsr
1957          * with exactly one enabled primary/sprite plane.
1958          */
1959         wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1960
1961         for (level = 0; level < wm_state->num_levels; level++) {
1962                 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1963                 const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
1964
1965                 if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
1966                         break;
1967
1968                 for_each_plane_id_on_crtc(crtc, plane_id) {
1969                         wm_state->wm[level].plane[plane_id] =
1970                                 vlv_invert_wm_value(raw->plane[plane_id],
1971                                                     fifo_state->plane[plane_id]);
1972                 }
1973
1974                 wm_state->sr[level].plane =
1975                         vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY],
1976                                                  raw->plane[PLANE_SPRITE0],
1977                                                  raw->plane[PLANE_SPRITE1]),
1978                                             sr_fifo_size);
1979
1980                 wm_state->sr[level].cursor =
1981                         vlv_invert_wm_value(raw->plane[PLANE_CURSOR],
1982                                             63);
1983         }
1984
1985         if (level == 0)
1986                 return -EINVAL;
1987
1988         /* limit to only levels we can actually handle */
1989         wm_state->num_levels = level;
1990
1991         /* invalidate the higher levels */
1992         vlv_invalidate_wms(crtc, wm_state, level);
1993
1994         return 0;
1995 }
1996
1997 #define VLV_FIFO(plane, value) \
1998         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1999
2000 static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
2001                                    struct intel_crtc *crtc)
2002 {
2003         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2004         struct intel_uncore *uncore = &dev_priv->uncore;
2005         const struct intel_crtc_state *crtc_state =
2006                 intel_atomic_get_new_crtc_state(state, crtc);
2007         const struct vlv_fifo_state *fifo_state =
2008                 &crtc_state->wm.vlv.fifo_state;
2009         int sprite0_start, sprite1_start, fifo_size;
2010         u32 dsparb, dsparb2, dsparb3;
2011
2012         if (!crtc_state->fifo_changed)
2013                 return;
2014
2015         sprite0_start = fifo_state->plane[PLANE_PRIMARY];
2016         sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start;
2017         fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start;
2018
2019         drm_WARN_ON(&dev_priv->drm, fifo_state->plane[PLANE_CURSOR] != 63);
2020         drm_WARN_ON(&dev_priv->drm, fifo_size != 511);
2021
2022         trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
2023
2024         /*
2025          * uncore.lock serves a double purpose here. It allows us to
2026          * use the less expensive I915_{READ,WRITE}_FW() functions, and
2027          * it protects the DSPARB registers from getting clobbered by
2028          * parallel updates from multiple pipes.
2029          *
2030          * intel_pipe_update_start() has already disabled interrupts
2031          * for us, so a plain spin_lock() is sufficient here.
2032          */
2033         spin_lock(&uncore->lock);
2034
2035         switch (crtc->pipe) {
2036         case PIPE_A:
2037                 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2038                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2039
2040                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
2041                             VLV_FIFO(SPRITEB, 0xff));
2042                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
2043                            VLV_FIFO(SPRITEB, sprite1_start));
2044
2045                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
2046                              VLV_FIFO(SPRITEB_HI, 0x1));
2047                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
2048                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
2049
2050                 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2051                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2052                 break;
2053         case PIPE_B:
2054                 dsparb = intel_uncore_read_fw(uncore, DSPARB);
2055                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2056
2057                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
2058                             VLV_FIFO(SPRITED, 0xff));
2059                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
2060                            VLV_FIFO(SPRITED, sprite1_start));
2061
2062                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
2063                              VLV_FIFO(SPRITED_HI, 0xff));
2064                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
2065                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
2066
2067                 intel_uncore_write_fw(uncore, DSPARB, dsparb);
2068                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2069                 break;
2070         case PIPE_C:
2071                 dsparb3 = intel_uncore_read_fw(uncore, DSPARB3);
2072                 dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
2073
2074                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
2075                              VLV_FIFO(SPRITEF, 0xff));
2076                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
2077                             VLV_FIFO(SPRITEF, sprite1_start));
2078
2079                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
2080                              VLV_FIFO(SPRITEF_HI, 0xff));
2081                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
2082                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
2083
2084                 intel_uncore_write_fw(uncore, DSPARB3, dsparb3);
2085                 intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
2086                 break;
2087         default:
2088                 break;
2089         }
2090
2091         intel_uncore_posting_read_fw(uncore, DSPARB);
2092
2093         spin_unlock(&uncore->lock);
2094 }
2095
2096 #undef VLV_FIFO
2097
2098 static int vlv_compute_intermediate_wm(struct intel_crtc_state *new_crtc_state)
2099 {
2100         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2101         struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2102         const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2103         struct intel_atomic_state *intel_state =
2104                 to_intel_atomic_state(new_crtc_state->uapi.state);
2105         const struct intel_crtc_state *old_crtc_state =
2106                 intel_atomic_get_old_crtc_state(intel_state, crtc);
2107         const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2108         int level;
2109
2110         if (!new_crtc_state->hw.active || drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi)) {
2111                 *intermediate = *optimal;
2112
2113                 intermediate->cxsr = false;
2114                 goto out;
2115         }
2116
2117         intermediate->num_levels = min(optimal->num_levels, active->num_levels);
2118         intermediate->cxsr = optimal->cxsr && active->cxsr &&
2119                 !new_crtc_state->disable_cxsr;
2120
2121         for (level = 0; level < intermediate->num_levels; level++) {
2122                 enum plane_id plane_id;
2123
2124                 for_each_plane_id_on_crtc(crtc, plane_id) {
2125                         intermediate->wm[level].plane[plane_id] =
2126                                 min(optimal->wm[level].plane[plane_id],
2127                                     active->wm[level].plane[plane_id]);
2128                 }
2129
2130                 intermediate->sr[level].plane = min(optimal->sr[level].plane,
2131                                                     active->sr[level].plane);
2132                 intermediate->sr[level].cursor = min(optimal->sr[level].cursor,
2133                                                      active->sr[level].cursor);
2134         }
2135
2136         vlv_invalidate_wms(crtc, intermediate, level);
2137
2138 out:
2139         /*
2140          * If our intermediate WM are identical to the final WM, then we can
2141          * omit the post-vblank programming; only update if it's different.
2142          */
2143         if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
2144                 new_crtc_state->wm.need_postvbl_update = true;
2145
2146         return 0;
2147 }
2148
2149 static void vlv_merge_wm(struct drm_i915_private *dev_priv,
2150                          struct vlv_wm_values *wm)
2151 {
2152         struct intel_crtc *crtc;
2153         int num_active_pipes = 0;
2154
2155         wm->level = dev_priv->wm.max_level;
2156         wm->cxsr = true;
2157
2158         for_each_intel_crtc(&dev_priv->drm, crtc) {
2159                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2160
2161                 if (!crtc->active)
2162                         continue;
2163
2164                 if (!wm_state->cxsr)
2165                         wm->cxsr = false;
2166
2167                 num_active_pipes++;
2168                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2169         }
2170
2171         if (num_active_pipes != 1)
2172                 wm->cxsr = false;
2173
2174         if (num_active_pipes > 1)
2175                 wm->level = VLV_WM_LEVEL_PM2;
2176
2177         for_each_intel_crtc(&dev_priv->drm, crtc) {
2178                 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2179                 enum pipe pipe = crtc->pipe;
2180
2181                 wm->pipe[pipe] = wm_state->wm[wm->level];
2182                 if (crtc->active && wm->cxsr)
2183                         wm->sr = wm_state->sr[wm->level];
2184
2185                 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2186                 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2187                 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2188                 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2189         }
2190 }
2191
2192 static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
2193 {
2194         struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2195         struct vlv_wm_values new_wm = {};
2196
2197         vlv_merge_wm(dev_priv, &new_wm);
2198
2199         if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0)
2200                 return;
2201
2202         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2203                 chv_set_memory_dvfs(dev_priv, false);
2204
2205         if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2206                 chv_set_memory_pm5(dev_priv, false);
2207
2208         if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
2209                 _intel_set_memory_cxsr(dev_priv, false);
2210
2211         vlv_write_wm_values(dev_priv, &new_wm);
2212
2213         if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
2214                 _intel_set_memory_cxsr(dev_priv, true);
2215
2216         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
2217                 chv_set_memory_pm5(dev_priv, true);
2218
2219         if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
2220                 chv_set_memory_dvfs(dev_priv, true);
2221
2222         *old_wm = new_wm;
2223 }
2224
2225 static void vlv_initial_watermarks(struct intel_atomic_state *state,
2226                                    struct intel_crtc *crtc)
2227 {
2228         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2229         const struct intel_crtc_state *crtc_state =
2230                 intel_atomic_get_new_crtc_state(state, crtc);
2231
2232         mutex_lock(&dev_priv->wm.wm_mutex);
2233         crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2234         vlv_program_watermarks(dev_priv);
2235         mutex_unlock(&dev_priv->wm.wm_mutex);
2236 }
2237
2238 static void vlv_optimize_watermarks(struct intel_atomic_state *state,
2239                                     struct intel_crtc *crtc)
2240 {
2241         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2242         const struct intel_crtc_state *crtc_state =
2243                 intel_atomic_get_new_crtc_state(state, crtc);
2244
2245         if (!crtc_state->wm.need_postvbl_update)
2246                 return;
2247
2248         mutex_lock(&dev_priv->wm.wm_mutex);
2249         crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2250         vlv_program_watermarks(dev_priv);
2251         mutex_unlock(&dev_priv->wm.wm_mutex);
2252 }
2253
2254 static void i965_update_wm(struct intel_crtc *unused_crtc)
2255 {
2256         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2257         struct intel_crtc *crtc;
2258         int srwm = 1;
2259         int cursor_sr = 16;
2260         bool cxsr_enabled;
2261
2262         /* Calc sr entries for one plane configs */
2263         crtc = single_enabled_crtc(dev_priv);
2264         if (crtc) {
2265                 /* self-refresh has much higher latency */
2266                 static const int sr_latency_ns = 12000;
2267                 const struct drm_display_mode *pipe_mode =
2268                         &crtc->config->hw.pipe_mode;
2269                 const struct drm_framebuffer *fb =
2270                         crtc->base.primary->state->fb;
2271                 int clock = pipe_mode->crtc_clock;
2272                 int htotal = pipe_mode->crtc_htotal;
2273                 int hdisplay = crtc->config->pipe_src_w;
2274                 int cpp = fb->format->cpp[0];
2275                 int entries;
2276
2277                 entries = intel_wm_method2(clock, htotal,
2278                                            hdisplay, cpp, sr_latency_ns / 100);
2279                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
2280                 srwm = I965_FIFO_SIZE - entries;
2281                 if (srwm < 0)
2282                         srwm = 1;
2283                 srwm &= 0x1ff;
2284                 drm_dbg_kms(&dev_priv->drm,
2285                             "self-refresh entries: %d, wm: %d\n",
2286                             entries, srwm);
2287
2288                 entries = intel_wm_method2(clock, htotal,
2289                                            crtc->base.cursor->state->crtc_w, 4,
2290                                            sr_latency_ns / 100);
2291                 entries = DIV_ROUND_UP(entries,
2292                                        i965_cursor_wm_info.cacheline_size) +
2293                         i965_cursor_wm_info.guard_size;
2294
2295                 cursor_sr = i965_cursor_wm_info.fifo_size - entries;
2296                 if (cursor_sr > i965_cursor_wm_info.max_wm)
2297                         cursor_sr = i965_cursor_wm_info.max_wm;
2298
2299                 drm_dbg_kms(&dev_priv->drm,
2300                             "self-refresh watermark: display plane %d "
2301                             "cursor %d\n", srwm, cursor_sr);
2302
2303                 cxsr_enabled = true;
2304         } else {
2305                 cxsr_enabled = false;
2306                 /* Turn off self refresh if both pipes are enabled */
2307                 intel_set_memory_cxsr(dev_priv, false);
2308         }
2309
2310         drm_dbg_kms(&dev_priv->drm,
2311                     "Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2312                     srwm);
2313
2314         /* 965 has limitations... */
2315         intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) |
2316                    FW_WM(8, CURSORB) |
2317                    FW_WM(8, PLANEB) |
2318                    FW_WM(8, PLANEA));
2319         intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
2320                    FW_WM(8, PLANEC_OLD));
2321         /* update cursor SR watermark */
2322         intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
2323
2324         if (cxsr_enabled)
2325                 intel_set_memory_cxsr(dev_priv, true);
2326 }
2327
2328 #undef FW_WM
2329
2330 static void i9xx_update_wm(struct intel_crtc *unused_crtc)
2331 {
2332         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2333         const struct intel_watermark_params *wm_info;
2334         u32 fwater_lo;
2335         u32 fwater_hi;
2336         int cwm, srwm = 1;
2337         int fifo_size;
2338         int planea_wm, planeb_wm;
2339         struct intel_crtc *crtc, *enabled = NULL;
2340
2341         if (IS_I945GM(dev_priv))
2342                 wm_info = &i945_wm_info;
2343         else if (DISPLAY_VER(dev_priv) != 2)
2344                 wm_info = &i915_wm_info;
2345         else
2346                 wm_info = &i830_a_wm_info;
2347
2348         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
2349         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2350         if (intel_crtc_active(crtc)) {
2351                 const struct drm_display_mode *pipe_mode =
2352                         &crtc->config->hw.pipe_mode;
2353                 const struct drm_framebuffer *fb =
2354                         crtc->base.primary->state->fb;
2355                 int cpp;
2356
2357                 if (DISPLAY_VER(dev_priv) == 2)
2358                         cpp = 4;
2359                 else
2360                         cpp = fb->format->cpp[0];
2361
2362                 planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2363                                                wm_info, fifo_size, cpp,
2364                                                pessimal_latency_ns);
2365                 enabled = crtc;
2366         } else {
2367                 planea_wm = fifo_size - wm_info->guard_size;
2368                 if (planea_wm > (long)wm_info->max_wm)
2369                         planea_wm = wm_info->max_wm;
2370         }
2371
2372         if (DISPLAY_VER(dev_priv) == 2)
2373                 wm_info = &i830_bc_wm_info;
2374
2375         fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
2376         crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2377         if (intel_crtc_active(crtc)) {
2378                 const struct drm_display_mode *pipe_mode =
2379                         &crtc->config->hw.pipe_mode;
2380                 const struct drm_framebuffer *fb =
2381                         crtc->base.primary->state->fb;
2382                 int cpp;
2383
2384                 if (DISPLAY_VER(dev_priv) == 2)
2385                         cpp = 4;
2386                 else
2387                         cpp = fb->format->cpp[0];
2388
2389                 planeb_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2390                                                wm_info, fifo_size, cpp,
2391                                                pessimal_latency_ns);
2392                 if (enabled == NULL)
2393                         enabled = crtc;
2394                 else
2395                         enabled = NULL;
2396         } else {
2397                 planeb_wm = fifo_size - wm_info->guard_size;
2398                 if (planeb_wm > (long)wm_info->max_wm)
2399                         planeb_wm = wm_info->max_wm;
2400         }
2401
2402         drm_dbg_kms(&dev_priv->drm,
2403                     "FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2404
2405         if (IS_I915GM(dev_priv) && enabled) {
2406                 struct drm_i915_gem_object *obj;
2407
2408                 obj = intel_fb_obj(enabled->base.primary->state->fb);
2409
2410                 /* self-refresh seems busted with untiled */
2411                 if (!i915_gem_object_is_tiled(obj))
2412                         enabled = NULL;
2413         }
2414
2415         /*
2416          * Overlay gets an aggressive default since video jitter is bad.
2417          */
2418         cwm = 2;
2419
2420         /* Play safe and disable self-refresh before adjusting watermarks. */
2421         intel_set_memory_cxsr(dev_priv, false);
2422
2423         /* Calc sr entries for one plane configs */
2424         if (HAS_FW_BLC(dev_priv) && enabled) {
2425                 /* self-refresh has much higher latency */
2426                 static const int sr_latency_ns = 6000;
2427                 const struct drm_display_mode *pipe_mode =
2428                         &enabled->config->hw.pipe_mode;
2429                 const struct drm_framebuffer *fb =
2430                         enabled->base.primary->state->fb;
2431                 int clock = pipe_mode->crtc_clock;
2432                 int htotal = pipe_mode->crtc_htotal;
2433                 int hdisplay = enabled->config->pipe_src_w;
2434                 int cpp;
2435                 int entries;
2436
2437                 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2438                         cpp = 4;
2439                 else
2440                         cpp = fb->format->cpp[0];
2441
2442                 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
2443                                            sr_latency_ns / 100);
2444                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
2445                 drm_dbg_kms(&dev_priv->drm,
2446                             "self-refresh entries: %d\n", entries);
2447                 srwm = wm_info->fifo_size - entries;
2448                 if (srwm < 0)
2449                         srwm = 1;
2450
2451                 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2452                         intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF,
2453                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2454                 else
2455                         intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, srwm & 0x3f);
2456         }
2457
2458         drm_dbg_kms(&dev_priv->drm,
2459                     "Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2460                      planea_wm, planeb_wm, cwm, srwm);
2461
2462         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2463         fwater_hi = (cwm & 0x1f);
2464
2465         /* Set request length to 8 cachelines per fetch */
2466         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2467         fwater_hi = fwater_hi | (1 << 8);
2468
2469         intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
2470         intel_uncore_write(&dev_priv->uncore, FW_BLC2, fwater_hi);
2471
2472         if (enabled)
2473                 intel_set_memory_cxsr(dev_priv, true);
2474 }
2475
2476 static void i845_update_wm(struct intel_crtc *unused_crtc)
2477 {
2478         struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
2479         struct intel_crtc *crtc;
2480         const struct drm_display_mode *pipe_mode;
2481         u32 fwater_lo;
2482         int planea_wm;
2483
2484         crtc = single_enabled_crtc(dev_priv);
2485         if (crtc == NULL)
2486                 return;
2487
2488         pipe_mode = &crtc->config->hw.pipe_mode;
2489         planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
2490                                        &i845_wm_info,
2491                                        dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
2492                                        4, pessimal_latency_ns);
2493         fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
2494         fwater_lo |= (3<<8) | planea_wm;
2495
2496         drm_dbg_kms(&dev_priv->drm,
2497                     "Setting FIFO watermarks - A: %d\n", planea_wm);
2498
2499         intel_uncore_write(&dev_priv->uncore, FW_BLC, fwater_lo);
2500 }
2501
2502 /* latency must be in 0.1us units. */
2503 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
2504                                    unsigned int cpp,
2505                                    unsigned int latency)
2506 {
2507         unsigned int ret;
2508
2509         ret = intel_wm_method1(pixel_rate, cpp, latency);
2510         ret = DIV_ROUND_UP(ret, 64) + 2;
2511
2512         return ret;
2513 }
2514
2515 /* latency must be in 0.1us units. */
2516 static unsigned int ilk_wm_method2(unsigned int pixel_rate,
2517                                    unsigned int htotal,
2518                                    unsigned int width,
2519                                    unsigned int cpp,
2520                                    unsigned int latency)
2521 {
2522         unsigned int ret;
2523
2524         ret = intel_wm_method2(pixel_rate, htotal,
2525                                width, cpp, latency);
2526         ret = DIV_ROUND_UP(ret, 64) + 2;
2527
2528         return ret;
2529 }
2530
2531 static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
2532 {
2533         /*
2534          * Neither of these should be possible since this function shouldn't be
2535          * called if the CRTC is off or the plane is invisible.  But let's be
2536          * extra paranoid to avoid a potential divide-by-zero if we screw up
2537          * elsewhere in the driver.
2538          */
2539         if (WARN_ON(!cpp))
2540                 return 0;
2541         if (WARN_ON(!horiz_pixels))
2542                 return 0;
2543
2544         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
2545 }
2546
2547 struct ilk_wm_maximums {
2548         u16 pri;
2549         u16 spr;
2550         u16 cur;
2551         u16 fbc;
2552 };
2553
2554 /*
2555  * For both WM_PIPE and WM_LP.
2556  * mem_value must be in 0.1us units.
2557  */
2558 static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
2559                               const struct intel_plane_state *plane_state,
2560                               u32 mem_value, bool is_lp)
2561 {
2562         u32 method1, method2;
2563         int cpp;
2564
2565         if (mem_value == 0)
2566                 return U32_MAX;
2567
2568         if (!intel_wm_plane_visible(crtc_state, plane_state))
2569                 return 0;
2570
2571         cpp = plane_state->hw.fb->format->cpp[0];
2572
2573         method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2574
2575         if (!is_lp)
2576                 return method1;
2577
2578         method2 = ilk_wm_method2(crtc_state->pixel_rate,
2579                                  crtc_state->hw.pipe_mode.crtc_htotal,
2580                                  drm_rect_width(&plane_state->uapi.dst),
2581                                  cpp, mem_value);
2582
2583         return min(method1, method2);
2584 }
2585
2586 /*
2587  * For both WM_PIPE and WM_LP.
2588  * mem_value must be in 0.1us units.
2589  */
2590 static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
2591                               const struct intel_plane_state *plane_state,
2592                               u32 mem_value)
2593 {
2594         u32 method1, method2;
2595         int cpp;
2596
2597         if (mem_value == 0)
2598                 return U32_MAX;
2599
2600         if (!intel_wm_plane_visible(crtc_state, plane_state))
2601                 return 0;
2602
2603         cpp = plane_state->hw.fb->format->cpp[0];
2604
2605         method1 = ilk_wm_method1(crtc_state->pixel_rate, cpp, mem_value);
2606         method2 = ilk_wm_method2(crtc_state->pixel_rate,
2607                                  crtc_state->hw.pipe_mode.crtc_htotal,
2608                                  drm_rect_width(&plane_state->uapi.dst),
2609                                  cpp, mem_value);
2610         return min(method1, method2);
2611 }
2612
2613 /*
2614  * For both WM_PIPE and WM_LP.
2615  * mem_value must be in 0.1us units.
2616  */
2617 static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
2618                               const struct intel_plane_state *plane_state,
2619                               u32 mem_value)
2620 {
2621         int cpp;
2622
2623         if (mem_value == 0)
2624                 return U32_MAX;
2625
2626         if (!intel_wm_plane_visible(crtc_state, plane_state))
2627                 return 0;
2628
2629         cpp = plane_state->hw.fb->format->cpp[0];
2630
2631         return ilk_wm_method2(crtc_state->pixel_rate,
2632                               crtc_state->hw.pipe_mode.crtc_htotal,
2633                               drm_rect_width(&plane_state->uapi.dst),
2634                               cpp, mem_value);
2635 }
2636
2637 /* Only for WM_LP. */
2638 static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
2639                               const struct intel_plane_state *plane_state,
2640                               u32 pri_val)
2641 {
2642         int cpp;
2643
2644         if (!intel_wm_plane_visible(crtc_state, plane_state))
2645                 return 0;
2646
2647         cpp = plane_state->hw.fb->format->cpp[0];
2648
2649         return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->uapi.dst),
2650                           cpp);
2651 }
2652
2653 static unsigned int
2654 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
2655 {
2656         if (DISPLAY_VER(dev_priv) >= 8)
2657                 return 3072;
2658         else if (DISPLAY_VER(dev_priv) >= 7)
2659                 return 768;
2660         else
2661                 return 512;
2662 }
2663
2664 static unsigned int
2665 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
2666                      int level, bool is_sprite)
2667 {
2668         if (DISPLAY_VER(dev_priv) >= 8)
2669                 /* BDW primary/sprite plane watermarks */
2670                 return level == 0 ? 255 : 2047;
2671         else if (DISPLAY_VER(dev_priv) >= 7)
2672                 /* IVB/HSW primary/sprite plane watermarks */
2673                 return level == 0 ? 127 : 1023;
2674         else if (!is_sprite)
2675                 /* ILK/SNB primary plane watermarks */
2676                 return level == 0 ? 127 : 511;
2677         else
2678                 /* ILK/SNB sprite plane watermarks */
2679                 return level == 0 ? 63 : 255;
2680 }
2681
2682 static unsigned int
2683 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
2684 {
2685         if (DISPLAY_VER(dev_priv) >= 7)
2686                 return level == 0 ? 63 : 255;
2687         else
2688                 return level == 0 ? 31 : 63;
2689 }
2690
2691 static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
2692 {
2693         if (DISPLAY_VER(dev_priv) >= 8)
2694                 return 31;
2695         else
2696                 return 15;
2697 }
2698
2699 /* Calculate the maximum primary/sprite plane watermark */
2700 static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
2701                                      int level,
2702                                      const struct intel_wm_config *config,
2703                                      enum intel_ddb_partitioning ddb_partitioning,
2704                                      bool is_sprite)
2705 {
2706         unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
2707
2708         /* if sprites aren't enabled, sprites get nothing */
2709         if (is_sprite && !config->sprites_enabled)
2710                 return 0;
2711
2712         /* HSW allows LP1+ watermarks even with multiple pipes */
2713         if (level == 0 || config->num_pipes_active > 1) {
2714                 fifo_size /= INTEL_NUM_PIPES(dev_priv);
2715
2716                 /*
2717                  * For some reason the non self refresh
2718                  * FIFO size is only half of the self
2719                  * refresh FIFO size on ILK/SNB.
2720                  */
2721                 if (DISPLAY_VER(dev_priv) <= 6)
2722                         fifo_size /= 2;
2723         }
2724
2725         if (config->sprites_enabled) {
2726                 /* level 0 is always calculated with 1:1 split */
2727                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2728                         if (is_sprite)
2729                                 fifo_size *= 5;
2730                         fifo_size /= 6;
2731                 } else {
2732                         fifo_size /= 2;
2733                 }
2734         }
2735
2736         /* clamp to max that the registers can hold */
2737         return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
2738 }
2739
2740 /* Calculate the maximum cursor plane watermark */
2741 static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
2742                                       int level,
2743                                       const struct intel_wm_config *config)
2744 {
2745         /* HSW LP1+ watermarks w/ multiple pipes */
2746         if (level > 0 && config->num_pipes_active > 1)
2747                 return 64;
2748
2749         /* otherwise just report max that registers can hold */
2750         return ilk_cursor_wm_reg_max(dev_priv, level);
2751 }
2752
2753 static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
2754                                     int level,
2755                                     const struct intel_wm_config *config,
2756                                     enum intel_ddb_partitioning ddb_partitioning,
2757                                     struct ilk_wm_maximums *max)
2758 {
2759         max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
2760         max->spr = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, true);
2761         max->cur = ilk_cursor_wm_max(dev_priv, level, config);
2762         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2763 }
2764
2765 static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
2766                                         int level,
2767                                         struct ilk_wm_maximums *max)
2768 {
2769         max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
2770         max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
2771         max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
2772         max->fbc = ilk_fbc_wm_reg_max(dev_priv);
2773 }
2774
2775 static bool ilk_validate_wm_level(int level,
2776                                   const struct ilk_wm_maximums *max,
2777                                   struct intel_wm_level *result)
2778 {
2779         bool ret;
2780
2781         /* already determined to be invalid? */
2782         if (!result->enable)
2783                 return false;
2784
2785         result->enable = result->pri_val <= max->pri &&
2786                          result->spr_val <= max->spr &&
2787                          result->cur_val <= max->cur;
2788
2789         ret = result->enable;
2790
2791         /*
2792          * HACK until we can pre-compute everything,
2793          * and thus fail gracefully if LP0 watermarks
2794          * are exceeded...
2795          */
2796         if (level == 0 && !result->enable) {
2797                 if (result->pri_val > max->pri)
2798                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2799                                       level, result->pri_val, max->pri);
2800                 if (result->spr_val > max->spr)
2801                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2802                                       level, result->spr_val, max->spr);
2803                 if (result->cur_val > max->cur)
2804                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2805                                       level, result->cur_val, max->cur);
2806
2807                 result->pri_val = min_t(u32, result->pri_val, max->pri);
2808                 result->spr_val = min_t(u32, result->spr_val, max->spr);
2809                 result->cur_val = min_t(u32, result->cur_val, max->cur);
2810                 result->enable = true;
2811         }
2812
2813         return ret;
2814 }
2815
2816 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2817                                  const struct intel_crtc *crtc,
2818                                  int level,
2819                                  struct intel_crtc_state *crtc_state,
2820                                  const struct intel_plane_state *pristate,
2821                                  const struct intel_plane_state *sprstate,
2822                                  const struct intel_plane_state *curstate,
2823                                  struct intel_wm_level *result)
2824 {
2825         u16 pri_latency = dev_priv->wm.pri_latency[level];
2826         u16 spr_latency = dev_priv->wm.spr_latency[level];
2827         u16 cur_latency = dev_priv->wm.cur_latency[level];
2828
2829         /* WM1+ latency values stored in 0.5us units */
2830         if (level > 0) {
2831                 pri_latency *= 5;
2832                 spr_latency *= 5;
2833                 cur_latency *= 5;
2834         }
2835
2836         if (pristate) {
2837                 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2838                                                      pri_latency, level);
2839                 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2840         }
2841
2842         if (sprstate)
2843                 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2844
2845         if (curstate)
2846                 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2847
2848         result->enable = true;
2849 }
2850
2851 static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2852                                   u16 wm[8])
2853 {
2854         struct intel_uncore *uncore = &dev_priv->uncore;
2855
2856         if (DISPLAY_VER(dev_priv) >= 9) {
2857                 u32 val;
2858                 int ret, i;
2859                 int level, max_level = ilk_wm_max_level(dev_priv);
2860
2861                 /* read the first set of memory latencies[0:3] */
2862                 val = 0; /* data0 to be programmed to 0 for first set */
2863                 ret = sandybridge_pcode_read(dev_priv,
2864                                              GEN9_PCODE_READ_MEM_LATENCY,
2865                                              &val, NULL);
2866
2867                 if (ret) {
2868                         drm_err(&dev_priv->drm,
2869                                 "SKL Mailbox read error = %d\n", ret);
2870                         return;
2871                 }
2872
2873                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2874                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2875                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2876                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2877                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2878                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2879                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2880
2881                 /* read the second set of memory latencies[4:7] */
2882                 val = 1; /* data0 to be programmed to 1 for second set */
2883                 ret = sandybridge_pcode_read(dev_priv,
2884                                              GEN9_PCODE_READ_MEM_LATENCY,
2885                                              &val, NULL);
2886                 if (ret) {
2887                         drm_err(&dev_priv->drm,
2888                                 "SKL Mailbox read error = %d\n", ret);
2889                         return;
2890                 }
2891
2892                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2893                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2894                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2895                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2896                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2897                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2898                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2899
2900                 /*
2901                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2902                  * need to be disabled. We make sure to sanitize the values out
2903                  * of the punit to satisfy this requirement.
2904                  */
2905                 for (level = 1; level <= max_level; level++) {
2906                         if (wm[level] == 0) {
2907                                 for (i = level + 1; i <= max_level; i++)
2908                                         wm[i] = 0;
2909                                 break;
2910                         }
2911                 }
2912
2913                 /*
2914                  * WaWmMemoryReadLatency:skl+,glk
2915                  *
2916                  * punit doesn't take into account the read latency so we need
2917                  * to add 2us to the various latency levels we retrieve from the
2918                  * punit when level 0 response data us 0us.
2919                  */
2920                 if (wm[0] == 0) {
2921                         wm[0] += 2;
2922                         for (level = 1; level <= max_level; level++) {
2923                                 if (wm[level] == 0)
2924                                         break;
2925                                 wm[level] += 2;
2926                         }
2927                 }
2928
2929                 /*
2930                  * WA Level-0 adjustment for 16GB DIMMs: SKL+
2931                  * If we could not get dimm info enable this WA to prevent from
2932                  * any underrun. If not able to get Dimm info assume 16GB dimm
2933                  * to avoid any underrun.
2934                  */
2935                 if (dev_priv->dram_info.wm_lv_0_adjust_needed)
2936                         wm[0] += 1;
2937
2938         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2939                 u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
2940
2941                 wm[0] = (sskpd >> 56) & 0xFF;
2942                 if (wm[0] == 0)
2943                         wm[0] = sskpd & 0xF;
2944                 wm[1] = (sskpd >> 4) & 0xFF;
2945                 wm[2] = (sskpd >> 12) & 0xFF;
2946                 wm[3] = (sskpd >> 20) & 0x1FF;
2947                 wm[4] = (sskpd >> 32) & 0x1FF;
2948         } else if (DISPLAY_VER(dev_priv) >= 6) {
2949                 u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
2950
2951                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2952                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2953                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2954                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2955         } else if (DISPLAY_VER(dev_priv) >= 5) {
2956                 u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
2957
2958                 /* ILK primary LP0 latency is 700 ns */
2959                 wm[0] = 7;
2960                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2961                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2962         } else {
2963                 MISSING_CASE(INTEL_DEVID(dev_priv));
2964         }
2965 }
2966
2967 static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2968                                        u16 wm[5])
2969 {
2970         /* ILK sprite LP0 latency is 1300 ns */
2971         if (DISPLAY_VER(dev_priv) == 5)
2972                 wm[0] = 13;
2973 }
2974
2975 static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2976                                        u16 wm[5])
2977 {
2978         /* ILK cursor LP0 latency is 1300 ns */
2979         if (DISPLAY_VER(dev_priv) == 5)
2980                 wm[0] = 13;
2981 }
2982
2983 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
2984 {
2985         /* how many WM levels are we expecting */
2986         if (HAS_HW_SAGV_WM(dev_priv))
2987                 return 5;
2988         else if (DISPLAY_VER(dev_priv) >= 9)
2989                 return 7;
2990         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2991                 return 4;
2992         else if (DISPLAY_VER(dev_priv) >= 6)
2993                 return 3;
2994         else
2995                 return 2;
2996 }
2997
2998 static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
2999                                    const char *name,
3000                                    const u16 wm[])
3001 {
3002         int level, max_level = ilk_wm_max_level(dev_priv);
3003
3004         for (level = 0; level <= max_level; level++) {
3005                 unsigned int latency = wm[level];
3006
3007                 if (latency == 0) {
3008                         drm_dbg_kms(&dev_priv->drm,
3009                                     "%s WM%d latency not provided\n",
3010                                     name, level);
3011                         continue;
3012                 }
3013
3014                 /*
3015                  * - latencies are in us on gen9.
3016                  * - before then, WM1+ latency values are in 0.5us units
3017                  */
3018                 if (DISPLAY_VER(dev_priv) >= 9)
3019                         latency *= 10;
3020                 else if (level > 0)
3021                         latency *= 5;
3022
3023                 drm_dbg_kms(&dev_priv->drm,
3024                             "%s WM%d latency %u (%u.%u usec)\n", name, level,
3025                             wm[level], latency / 10, latency % 10);
3026         }
3027 }
3028
3029 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
3030                                     u16 wm[5], u16 min)
3031 {
3032         int level, max_level = ilk_wm_max_level(dev_priv);
3033
3034         if (wm[0] >= min)
3035                 return false;
3036
3037         wm[0] = max(wm[0], min);
3038         for (level = 1; level <= max_level; level++)
3039                 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3040
3041         return true;
3042 }
3043
3044 static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
3045 {
3046         bool changed;
3047
3048         /*
3049          * The BIOS provided WM memory latency values are often
3050          * inadequate for high resolution displays. Adjust them.
3051          */
3052         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
3053                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
3054                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3055
3056         if (!changed)
3057                 return;
3058
3059         drm_dbg_kms(&dev_priv->drm,
3060                     "WM latency values increased to avoid potential underruns\n");
3061         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3062         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3063         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3064 }
3065
3066 static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3067 {
3068         /*
3069          * On some SNB machines (Thinkpad X220 Tablet at least)
3070          * LP3 usage can cause vblank interrupts to be lost.
3071          * The DEIIR bit will go high but it looks like the CPU
3072          * never gets interrupted.
3073          *
3074          * It's not clear whether other interrupt source could
3075          * be affected or if this is somehow limited to vblank
3076          * interrupts only. To play it safe we disable LP3
3077          * watermarks entirely.
3078          */
3079         if (dev_priv->wm.pri_latency[3] == 0 &&
3080             dev_priv->wm.spr_latency[3] == 0 &&
3081             dev_priv->wm.cur_latency[3] == 0)
3082                 return;
3083
3084         dev_priv->wm.pri_latency[3] = 0;
3085         dev_priv->wm.spr_latency[3] = 0;
3086         dev_priv->wm.cur_latency[3] = 0;
3087
3088         drm_dbg_kms(&dev_priv->drm,
3089                     "LP3 watermarks disabled due to potential for lost interrupts\n");
3090         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3091         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3092         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3093 }
3094
3095 static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3096 {
3097         intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3098
3099         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3100                sizeof(dev_priv->wm.pri_latency));
3101         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3102                sizeof(dev_priv->wm.pri_latency));
3103
3104         intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3105         intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3106
3107         intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3108         intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3109         intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3110
3111         if (DISPLAY_VER(dev_priv) == 6) {
3112                 snb_wm_latency_quirk(dev_priv);
3113                 snb_wm_lp3_irq_quirk(dev_priv);
3114         }
3115 }
3116
3117 static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
3118 {
3119         intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3120         intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3121 }
3122
3123 static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
3124                                  struct intel_pipe_wm *pipe_wm)
3125 {
3126         /* LP0 watermark maximums depend on this pipe alone */
3127         const struct intel_wm_config config = {
3128                 .num_pipes_active = 1,
3129                 .sprites_enabled = pipe_wm->sprites_enabled,
3130                 .sprites_scaled = pipe_wm->sprites_scaled,
3131         };
3132         struct ilk_wm_maximums max;
3133
3134         /* LP0 watermarks always use 1/2 DDB partitioning */
3135         ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
3136
3137         /* At least LP0 must be valid */
3138         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3139                 drm_dbg_kms(&dev_priv->drm, "LP0 watermark invalid\n");
3140                 return false;
3141         }
3142
3143         return true;
3144 }
3145
3146 /* Compute new watermarks for the pipe */
3147 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
3148 {
3149         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3150         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3151         struct intel_pipe_wm *pipe_wm;
3152         struct intel_plane *plane;
3153         const struct intel_plane_state *plane_state;
3154         const struct intel_plane_state *pristate = NULL;
3155         const struct intel_plane_state *sprstate = NULL;
3156         const struct intel_plane_state *curstate = NULL;
3157         int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
3158         struct ilk_wm_maximums max;
3159
3160         pipe_wm = &crtc_state->wm.ilk.optimal;
3161
3162         intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
3163                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
3164                         pristate = plane_state;
3165                 else if (plane->base.type == DRM_PLANE_TYPE_OVERLAY)
3166                         sprstate = plane_state;
3167                 else if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
3168                         curstate = plane_state;
3169         }
3170
3171         pipe_wm->pipe_enabled = crtc_state->hw.active;
3172         if (sprstate) {
3173                 pipe_wm->sprites_enabled = sprstate->uapi.visible;
3174                 pipe_wm->sprites_scaled = sprstate->uapi.visible &&
3175                         (drm_rect_width(&sprstate->uapi.dst) != drm_rect_width(&sprstate->uapi.src) >> 16 ||
3176                          drm_rect_height(&sprstate->uapi.dst) != drm_rect_height(&sprstate->uapi.src) >> 16);
3177         }
3178
3179         usable_level = max_level;
3180
3181         /* ILK/SNB: LP2+ watermarks only w/o sprites */
3182         if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)
3183                 usable_level = 1;
3184
3185         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
3186         if (pipe_wm->sprites_scaled)
3187                 usable_level = 0;
3188
3189         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3190         ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
3191                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
3192
3193         if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
3194                 return -EINVAL;
3195
3196         ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
3197
3198         for (level = 1; level <= usable_level; level++) {
3199                 struct intel_wm_level *wm = &pipe_wm->wm[level];
3200
3201                 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
3202                                      pristate, sprstate, curstate, wm);
3203
3204                 /*
3205                  * Disable any watermark level that exceeds the
3206                  * register maximums since such watermarks are
3207                  * always invalid.
3208                  */
3209                 if (!ilk_validate_wm_level(level, &max, wm)) {
3210                         memset(wm, 0, sizeof(*wm));
3211                         break;
3212                 }
3213         }
3214
3215         return 0;
3216 }
3217
3218 /*
3219  * Build a set of 'intermediate' watermark values that satisfy both the old
3220  * state and the new state.  These can be programmed to the hardware
3221  * immediately.
3222  */
3223 static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
3224 {
3225         struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
3226         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3227         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3228         struct intel_atomic_state *intel_state =
3229                 to_intel_atomic_state(newstate->uapi.state);
3230         const struct intel_crtc_state *oldstate =
3231                 intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
3232         const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3233         int level, max_level = ilk_wm_max_level(dev_priv);
3234
3235         /*
3236          * Start with the final, target watermarks, then combine with the
3237          * currently active watermarks to get values that are safe both before
3238          * and after the vblank.
3239          */
3240         *a = newstate->wm.ilk.optimal;
3241         if (!newstate->hw.active || drm_atomic_crtc_needs_modeset(&newstate->uapi) ||
3242             intel_state->skip_intermediate_wm)
3243                 return 0;
3244
3245         a->pipe_enabled |= b->pipe_enabled;
3246         a->sprites_enabled |= b->sprites_enabled;
3247         a->sprites_scaled |= b->sprites_scaled;
3248
3249         for (level = 0; level <= max_level; level++) {
3250                 struct intel_wm_level *a_wm = &a->wm[level];
3251                 const struct intel_wm_level *b_wm = &b->wm[level];
3252
3253                 a_wm->enable &= b_wm->enable;
3254                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
3255                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
3256                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
3257                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
3258         }
3259
3260         /*
3261          * We need to make sure that these merged watermark values are
3262          * actually a valid configuration themselves.  If they're not,
3263          * there's no safe way to transition from the old state to
3264          * the new state, so we need to fail the atomic transaction.
3265          */
3266         if (!ilk_validate_pipe_wm(dev_priv, a))
3267                 return -EINVAL;
3268
3269         /*
3270          * If our intermediate WM are identical to the final WM, then we can
3271          * omit the post-vblank programming; only update if it's different.
3272          */
3273         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3274                 newstate->wm.need_postvbl_update = true;
3275
3276         return 0;
3277 }
3278
3279 /*
3280  * Merge the watermarks from all active pipes for a specific level.
3281  */
3282 static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
3283                                int level,
3284                                struct intel_wm_level *ret_wm)
3285 {
3286         const struct intel_crtc *intel_crtc;
3287
3288         ret_wm->enable = true;
3289
3290         for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3291                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3292                 const struct intel_wm_level *wm = &active->wm[level];
3293
3294                 if (!active->pipe_enabled)
3295                         continue;
3296
3297                 /*
3298                  * The watermark values may have been used in the past,
3299                  * so we must maintain them in the registers for some
3300                  * time even if the level is now disabled.
3301                  */
3302                 if (!wm->enable)
3303                         ret_wm->enable = false;
3304
3305                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3306                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3307                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3308                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3309         }
3310 }
3311
3312 /*
3313  * Merge all low power watermarks for all active pipes.
3314  */
3315 static void ilk_wm_merge(struct drm_i915_private *dev_priv,
3316                          const struct intel_wm_config *config,
3317                          const struct ilk_wm_maximums *max,
3318                          struct intel_pipe_wm *merged)
3319 {
3320         int level, max_level = ilk_wm_max_level(dev_priv);
3321         int last_enabled_level = max_level;
3322
3323         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3324         if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
3325             config->num_pipes_active > 1)
3326                 last_enabled_level = 0;
3327
3328         /* ILK: FBC WM must be disabled always */
3329         merged->fbc_wm_enabled = DISPLAY_VER(dev_priv) >= 6;
3330
3331         /* merge each WM1+ level */
3332         for (level = 1; level <= max_level; level++) {
3333                 struct intel_wm_level *wm = &merged->wm[level];
3334
3335                 ilk_merge_wm_level(dev_priv, level, wm);
3336
3337                 if (level > last_enabled_level)
3338                         wm->enable = false;
3339                 else if (!ilk_validate_wm_level(level, max, wm))
3340                         /* make sure all following levels get disabled */
3341                         last_enabled_level = level - 1;
3342
3343                 /*
3344                  * The spec says it is preferred to disable
3345                  * FBC WMs instead of disabling a WM level.
3346                  */
3347                 if (wm->fbc_val > max->fbc) {
3348                         if (wm->enable)
3349                                 merged->fbc_wm_enabled = false;
3350                         wm->fbc_val = 0;
3351                 }
3352         }
3353
3354         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3355         /*
3356          * FIXME this is racy. FBC might get enabled later.
3357          * What we should check here is whether FBC can be
3358          * enabled sometime later.
3359          */
3360         if (DISPLAY_VER(dev_priv) == 5 && !merged->fbc_wm_enabled &&
3361             intel_fbc_is_active(dev_priv)) {
3362                 for (level = 2; level <= max_level; level++) {
3363                         struct intel_wm_level *wm = &merged->wm[level];
3364
3365                         wm->enable = false;
3366                 }
3367         }
3368 }
3369
3370 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
3371 {
3372         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
3373         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3374 }
3375
3376 /* The value we need to program into the WM_LPx latency field */
3377 static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
3378                                       int level)
3379 {
3380         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
3381                 return 2 * level;
3382         else
3383                 return dev_priv->wm.pri_latency[level];
3384 }
3385
3386 static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
3387                                    const struct intel_pipe_wm *merged,
3388                                    enum intel_ddb_partitioning partitioning,
3389                                    struct ilk_wm_values *results)
3390 {
3391         struct intel_crtc *intel_crtc;
3392         int level, wm_lp;
3393
3394         results->enable_fbc_wm = merged->fbc_wm_enabled;
3395         results->partitioning = partitioning;
3396
3397         /* LP1+ register values */
3398         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3399                 const struct intel_wm_level *r;
3400
3401                 level = ilk_wm_lp_to_level(wm_lp, merged);
3402
3403                 r = &merged->wm[level];
3404
3405                 /*
3406                  * Maintain the watermark values even if the level is
3407                  * disabled. Doing otherwise could cause underruns.
3408                  */
3409                 results->wm_lp[wm_lp - 1] =
3410                         (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
3411                         (r->pri_val << WM1_LP_SR_SHIFT) |
3412                         r->cur_val;
3413
3414                 if (r->enable)
3415                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
3416
3417                 if (DISPLAY_VER(dev_priv) >= 8)
3418                         results->wm_lp[wm_lp - 1] |=
3419                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
3420                 else
3421                         results->wm_lp[wm_lp - 1] |=
3422                                 r->fbc_val << WM1_LP_FBC_SHIFT;
3423
3424                 /*
3425                  * Always set WM1S_LP_EN when spr_val != 0, even if the
3426                  * level is disabled. Doing otherwise could cause underruns.
3427                  */
3428                 if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {
3429                         drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
3430                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
3431                 } else
3432                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
3433         }
3434
3435         /* LP0 register values */
3436         for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
3437                 enum pipe pipe = intel_crtc->pipe;
3438                 const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
3439                 const struct intel_wm_level *r = &pipe_wm->wm[0];
3440
3441                 if (drm_WARN_ON(&dev_priv->drm, !r->enable))
3442                         continue;
3443
3444                 results->wm_pipe[pipe] =
3445                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
3446                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
3447                         r->cur_val;
3448         }
3449 }
3450
3451 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3452  * case both are at the same level. Prefer r1 in case they're the same. */
3453 static struct intel_pipe_wm *
3454 ilk_find_best_result(struct drm_i915_private *dev_priv,
3455                      struct intel_pipe_wm *r1,
3456                      struct intel_pipe_wm *r2)
3457 {
3458         int level, max_level = ilk_wm_max_level(dev_priv);
3459         int level1 = 0, level2 = 0;
3460
3461         for (level = 1; level <= max_level; level++) {
3462                 if (r1->wm[level].enable)
3463                         level1 = level;
3464                 if (r2->wm[level].enable)
3465                         level2 = level;
3466         }
3467
3468         if (level1 == level2) {
3469                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
3470                         return r2;
3471                 else
3472                         return r1;
3473         } else if (level1 > level2) {
3474                 return r1;
3475         } else {
3476                 return r2;
3477         }
3478 }
3479
3480 /* dirty bits used to track which watermarks need changes */
3481 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3482 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
3483 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
3484 #define WM_DIRTY_FBC (1 << 24)
3485 #define WM_DIRTY_DDB (1 << 25)
3486
3487 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
3488                                          const struct ilk_wm_values *old,
3489                                          const struct ilk_wm_values *new)
3490 {
3491         unsigned int dirty = 0;
3492         enum pipe pipe;
3493         int wm_lp;
3494
3495         for_each_pipe(dev_priv, pipe) {
3496                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3497                         dirty |= WM_DIRTY_PIPE(pipe);
3498                         /* Must disable LP1+ watermarks too */
3499                         dirty |= WM_DIRTY_LP_ALL;
3500                 }
3501         }
3502
3503         if (old->enable_fbc_wm != new->enable_fbc_wm) {
3504                 dirty |= WM_DIRTY_FBC;
3505                 /* Must disable LP1+ watermarks too */
3506                 dirty |= WM_DIRTY_LP_ALL;
3507         }
3508
3509         if (old->partitioning != new->partitioning) {
3510                 dirty |= WM_DIRTY_DDB;
3511                 /* Must disable LP1+ watermarks too */
3512                 dirty |= WM_DIRTY_LP_ALL;
3513         }
3514
3515         /* LP1+ watermarks already deemed dirty, no need to continue */
3516         if (dirty & WM_DIRTY_LP_ALL)
3517                 return dirty;
3518
3519         /* Find the lowest numbered LP1+ watermark in need of an update... */
3520         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
3521                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
3522                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
3523                         break;
3524         }
3525
3526         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
3527         for (; wm_lp <= 3; wm_lp++)
3528                 dirty |= WM_DIRTY_LP(wm_lp);
3529
3530         return dirty;
3531 }
3532
3533 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
3534                                unsigned int dirty)
3535 {
3536         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3537         bool changed = false;
3538
3539         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
3540                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
3541                 intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, previous->wm_lp[2]);
3542                 changed = true;
3543         }
3544         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
3545                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
3546                 intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, previous->wm_lp[1]);
3547                 changed = true;
3548         }
3549         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
3550                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
3551                 intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, previous->wm_lp[0]);
3552                 changed = true;
3553         }
3554
3555         /*
3556          * Don't touch WM1S_LP_EN here.
3557          * Doing so could cause underruns.
3558          */
3559
3560         return changed;
3561 }
3562
3563 /*
3564  * The spec says we shouldn't write when we don't need, because every write
3565  * causes WMs to be re-evaluated, expending some power.
3566  */
3567 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
3568                                 struct ilk_wm_values *results)
3569 {
3570         struct ilk_wm_values *previous = &dev_priv->wm.hw;
3571         unsigned int dirty;
3572         u32 val;
3573
3574         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
3575         if (!dirty)
3576                 return;
3577
3578         _ilk_disable_lp_wm(dev_priv, dirty);
3579
3580         if (dirty & WM_DIRTY_PIPE(PIPE_A))
3581                 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]);
3582         if (dirty & WM_DIRTY_PIPE(PIPE_B))
3583                 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]);
3584         if (dirty & WM_DIRTY_PIPE(PIPE_C))
3585                 intel_uncore_write(&dev_priv->uncore, WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]);
3586
3587         if (dirty & WM_DIRTY_DDB) {
3588                 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3589                         val = intel_uncore_read(&dev_priv->uncore, WM_MISC);
3590                         if (results->partitioning == INTEL_DDB_PART_1_2)
3591                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
3592                         else
3593                                 val |= WM_MISC_DATA_PARTITION_5_6;
3594                         intel_uncore_write(&dev_priv->uncore, WM_MISC, val);
3595                 } else {
3596                         val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
3597                         if (results->partitioning == INTEL_DDB_PART_1_2)
3598                                 val &= ~DISP_DATA_PARTITION_5_6;
3599                         else
3600                                 val |= DISP_DATA_PARTITION_5_6;
3601                         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
3602                 }
3603         }
3604
3605         if (dirty & WM_DIRTY_FBC) {
3606                 val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL);
3607                 if (results->enable_fbc_wm)
3608                         val &= ~DISP_FBC_WM_DIS;
3609                 else
3610                         val |= DISP_FBC_WM_DIS;
3611                 intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, val);
3612         }
3613
3614         if (dirty & WM_DIRTY_LP(1) &&
3615             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
3616                 intel_uncore_write(&dev_priv->uncore, WM1S_LP_ILK, results->wm_lp_spr[0]);
3617
3618         if (DISPLAY_VER(dev_priv) >= 7) {
3619                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
3620                         intel_uncore_write(&dev_priv->uncore, WM2S_LP_IVB, results->wm_lp_spr[1]);
3621                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
3622                         intel_uncore_write(&dev_priv->uncore, WM3S_LP_IVB, results->wm_lp_spr[2]);
3623         }
3624
3625         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
3626                 intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, results->wm_lp[0]);
3627         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
3628                 intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, results->wm_lp[1]);
3629         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
3630                 intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
3631
3632         dev_priv->wm.hw = *results;
3633 }
3634
3635 bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
3636 {
3637         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
3638 }
3639
3640 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
3641 {
3642         u8 enabled_slices = 0;
3643         enum dbuf_slice slice;
3644
3645         for_each_dbuf_slice(dev_priv, slice) {
3646                 if (intel_uncore_read(&dev_priv->uncore,
3647                                       DBUF_CTL_S(slice)) & DBUF_POWER_STATE)
3648                         enabled_slices |= BIT(slice);
3649         }
3650
3651         return enabled_slices;
3652 }
3653
3654 /*
3655  * FIXME: We still don't have the proper code detect if we need to apply the WA,
3656  * so assume we'll always need it in order to avoid underruns.
3657  */
3658 static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
3659 {
3660         return DISPLAY_VER(dev_priv) == 9;
3661 }
3662
3663 static bool
3664 intel_has_sagv(struct drm_i915_private *dev_priv)
3665 {
3666         return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) &&
3667                 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
3668 }
3669
3670 static void
3671 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
3672 {
3673         if (DISPLAY_VER(dev_priv) >= 12) {
3674                 u32 val = 0;
3675                 int ret;
3676
3677                 ret = sandybridge_pcode_read(dev_priv,
3678                                              GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
3679                                              &val, NULL);
3680                 if (!ret) {
3681                         dev_priv->sagv_block_time_us = val;
3682                         return;
3683                 }
3684
3685                 drm_dbg(&dev_priv->drm, "Couldn't read SAGV block time!\n");
3686         } else if (DISPLAY_VER(dev_priv) == 11) {
3687                 dev_priv->sagv_block_time_us = 10;
3688                 return;
3689         } else if (DISPLAY_VER(dev_priv) == 10) {
3690                 dev_priv->sagv_block_time_us = 20;
3691                 return;
3692         } else if (DISPLAY_VER(dev_priv) == 9) {
3693                 dev_priv->sagv_block_time_us = 30;
3694                 return;
3695         } else {
3696                 MISSING_CASE(DISPLAY_VER(dev_priv));
3697         }
3698
3699         /* Default to an unusable block time */
3700         dev_priv->sagv_block_time_us = -1;
3701 }
3702
3703 /*
3704  * SAGV dynamically adjusts the system agent voltage and clock frequencies
3705  * depending on power and performance requirements. The display engine access
3706  * to system memory is blocked during the adjustment time. Because of the
3707  * blocking time, having this enabled can cause full system hangs and/or pipe
3708  * underruns if we don't meet all of the following requirements:
3709  *
3710  *  - <= 1 pipe enabled
3711  *  - All planes can enable watermarks for latencies >= SAGV engine block time
3712  *  - We're not using an interlaced display configuration
3713  */
3714 static int
3715 intel_enable_sagv(struct drm_i915_private *dev_priv)
3716 {
3717         int ret;
3718
3719         if (!intel_has_sagv(dev_priv))
3720                 return 0;
3721
3722         if (dev_priv->sagv_status == I915_SAGV_ENABLED)
3723                 return 0;
3724
3725         drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
3726         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3727                                       GEN9_SAGV_ENABLE);
3728
3729         /* We don't need to wait for SAGV when enabling */
3730
3731         /*
3732          * Some skl systems, pre-release machines in particular,
3733          * don't actually have SAGV.
3734          */
3735         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3736                 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3737                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3738                 return 0;
3739         } else if (ret < 0) {
3740                 drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
3741                 return ret;
3742         }
3743
3744         dev_priv->sagv_status = I915_SAGV_ENABLED;
3745         return 0;
3746 }
3747
3748 static int
3749 intel_disable_sagv(struct drm_i915_private *dev_priv)
3750 {
3751         int ret;
3752
3753         if (!intel_has_sagv(dev_priv))
3754                 return 0;
3755
3756         if (dev_priv->sagv_status == I915_SAGV_DISABLED)
3757                 return 0;
3758
3759         drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
3760         /* bspec says to keep retrying for at least 1 ms */
3761         ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
3762                                 GEN9_SAGV_DISABLE,
3763                                 GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
3764                                 1);
3765         /*
3766          * Some skl systems, pre-release machines in particular,
3767          * don't actually have SAGV.
3768          */
3769         if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
3770                 drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
3771                 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
3772                 return 0;
3773         } else if (ret < 0) {
3774                 drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
3775                 return ret;
3776         }
3777
3778         dev_priv->sagv_status = I915_SAGV_DISABLED;
3779         return 0;
3780 }
3781
3782 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
3783 {
3784         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3785         const struct intel_bw_state *new_bw_state;
3786         const struct intel_bw_state *old_bw_state;
3787         u32 new_mask = 0;
3788
3789         /*
3790          * Just return if we can't control SAGV or don't have it.
3791          * This is different from situation when we have SAGV but just can't
3792          * afford it due to DBuf limitation - in case if SAGV is completely
3793          * disabled in a BIOS, we are not even allowed to send a PCode request,
3794          * as it will throw an error. So have to check it here.
3795          */
3796         if (!intel_has_sagv(dev_priv))
3797                 return;
3798
3799         new_bw_state = intel_atomic_get_new_bw_state(state);
3800         if (!new_bw_state)
3801                 return;
3802
3803         if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) {
3804                 intel_disable_sagv(dev_priv);
3805                 return;
3806         }
3807
3808         old_bw_state = intel_atomic_get_old_bw_state(state);
3809         /*
3810          * Nothing to mask
3811          */
3812         if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3813                 return;
3814
3815         new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
3816
3817         /*
3818          * If new mask is zero - means there is nothing to mask,
3819          * we can only unmask, which should be done in unmask.
3820          */
3821         if (!new_mask)
3822                 return;
3823
3824         /*
3825          * Restrict required qgv points before updating the configuration.
3826          * According to BSpec we can't mask and unmask qgv points at the same
3827          * time. Also masking should be done before updating the configuration
3828          * and unmasking afterwards.
3829          */
3830         icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3831 }
3832
3833 void intel_sagv_post_plane_update(struct intel_atomic_state *state)
3834 {
3835         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3836         const struct intel_bw_state *new_bw_state;
3837         const struct intel_bw_state *old_bw_state;
3838         u32 new_mask = 0;
3839
3840         /*
3841          * Just return if we can't control SAGV or don't have it.
3842          * This is different from situation when we have SAGV but just can't
3843          * afford it due to DBuf limitation - in case if SAGV is completely
3844          * disabled in a BIOS, we are not even allowed to send a PCode request,
3845          * as it will throw an error. So have to check it here.
3846          */
3847         if (!intel_has_sagv(dev_priv))
3848                 return;
3849
3850         new_bw_state = intel_atomic_get_new_bw_state(state);
3851         if (!new_bw_state)
3852                 return;
3853
3854         if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) {
3855                 intel_enable_sagv(dev_priv);
3856                 return;
3857         }
3858
3859         old_bw_state = intel_atomic_get_old_bw_state(state);
3860         /*
3861          * Nothing to unmask
3862          */
3863         if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
3864                 return;
3865
3866         new_mask = new_bw_state->qgv_points_mask;
3867
3868         /*
3869          * Allow required qgv points after updating the configuration.
3870          * According to BSpec we can't mask and unmask qgv points at the same
3871          * time. Also masking should be done before updating the configuration
3872          * and unmasking afterwards.
3873          */
3874         icl_pcode_restrict_qgv_points(dev_priv, new_mask);
3875 }
3876
3877 static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3878 {
3879         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3880         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3881         enum plane_id plane_id;
3882         int max_level = INT_MAX;
3883
3884         if (!intel_has_sagv(dev_priv))
3885                 return false;
3886
3887         if (!crtc_state->hw.active)
3888                 return true;
3889
3890         if (crtc_state->hw.pipe_mode.flags & DRM_MODE_FLAG_INTERLACE)
3891                 return false;
3892
3893         for_each_plane_id_on_crtc(crtc, plane_id) {
3894                 const struct skl_plane_wm *wm =
3895                         &crtc_state->wm.skl.optimal.planes[plane_id];
3896                 int level;
3897
3898                 /* Skip this plane if it's not enabled */
3899                 if (!wm->wm[0].enable)
3900                         continue;
3901
3902                 /* Find the highest enabled wm level for this plane */
3903                 for (level = ilk_wm_max_level(dev_priv);
3904                      !wm->wm[level].enable; --level)
3905                      { }
3906
3907                 /* Highest common enabled wm level for all planes */
3908                 max_level = min(level, max_level);
3909         }
3910
3911         /* No enabled planes? */
3912         if (max_level == INT_MAX)
3913                 return true;
3914
3915         for_each_plane_id_on_crtc(crtc, plane_id) {
3916                 const struct skl_plane_wm *wm =
3917                         &crtc_state->wm.skl.optimal.planes[plane_id];
3918
3919                 /*
3920                  * All enabled planes must have enabled a common wm level that
3921                  * can tolerate memory latencies higher than sagv_block_time_us
3922                  */
3923                 if (wm->wm[0].enable && !wm->wm[max_level].can_sagv)
3924                         return false;
3925         }
3926
3927         return true;
3928 }
3929
3930 static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3931 {
3932         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3933         enum plane_id plane_id;
3934
3935         if (!crtc_state->hw.active)
3936                 return true;
3937
3938         for_each_plane_id_on_crtc(crtc, plane_id) {
3939                 const struct skl_plane_wm *wm =
3940                         &crtc_state->wm.skl.optimal.planes[plane_id];
3941
3942                 if (wm->wm[0].enable && !wm->sagv.wm0.enable)
3943                         return false;
3944         }
3945
3946         return true;
3947 }
3948
3949 static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
3950 {
3951         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3952         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3953
3954         if (DISPLAY_VER(dev_priv) >= 12)
3955                 return tgl_crtc_can_enable_sagv(crtc_state);
3956         else
3957                 return skl_crtc_can_enable_sagv(crtc_state);
3958 }
3959
3960 bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
3961                            const struct intel_bw_state *bw_state)
3962 {
3963         if (DISPLAY_VER(dev_priv) < 11 &&
3964             bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
3965                 return false;
3966
3967         return bw_state->pipe_sagv_reject == 0;
3968 }
3969
3970 static int intel_compute_sagv_mask(struct intel_atomic_state *state)
3971 {
3972         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3973         int ret;
3974         struct intel_crtc *crtc;
3975         struct intel_crtc_state *new_crtc_state;
3976         struct intel_bw_state *new_bw_state = NULL;
3977         const struct intel_bw_state *old_bw_state = NULL;
3978         int i;
3979
3980         for_each_new_intel_crtc_in_state(state, crtc,
3981                                          new_crtc_state, i) {
3982                 new_bw_state = intel_atomic_get_bw_state(state);
3983                 if (IS_ERR(new_bw_state))
3984                         return PTR_ERR(new_bw_state);
3985
3986                 old_bw_state = intel_atomic_get_old_bw_state(state);
3987
3988                 if (intel_crtc_can_enable_sagv(new_crtc_state))
3989                         new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
3990                 else
3991                         new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
3992         }
3993
3994         if (!new_bw_state)
3995                 return 0;
3996
3997         new_bw_state->active_pipes =
3998                 intel_calc_active_pipes(state, old_bw_state->active_pipes);
3999
4000         if (new_bw_state->active_pipes != old_bw_state->active_pipes) {
4001                 ret = intel_atomic_lock_global_state(&new_bw_state->base);
4002                 if (ret)
4003                         return ret;
4004         }
4005
4006         for_each_new_intel_crtc_in_state(state, crtc,
4007                                          new_crtc_state, i) {
4008                 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
4009
4010                 /*
4011                  * We store use_sagv_wm in the crtc state rather than relying on
4012                  * that bw state since we have no convenient way to get at the
4013                  * latter from the plane commit hooks (especially in the legacy
4014                  * cursor case)
4015                  */
4016                 pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(dev_priv) &&
4017                         DISPLAY_VER(dev_priv) >= 12 &&
4018                         intel_can_enable_sagv(dev_priv, new_bw_state);
4019         }
4020
4021         if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
4022             intel_can_enable_sagv(dev_priv, old_bw_state)) {
4023                 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
4024                 if (ret)
4025                         return ret;
4026         } else if (new_bw_state->pipe_sagv_reject != old_bw_state->pipe_sagv_reject) {
4027                 ret = intel_atomic_lock_global_state(&new_bw_state->base);
4028                 if (ret)
4029                         return ret;
4030         }
4031
4032         return 0;
4033 }
4034
4035 static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
4036 {
4037         return INTEL_INFO(dev_priv)->dbuf.size /
4038                 hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
4039 }
4040
4041 static void
4042 skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
4043                          struct skl_ddb_entry *ddb)
4044 {
4045         int slice_size = intel_dbuf_slice_size(dev_priv);
4046
4047         if (!slice_mask) {
4048                 ddb->start = 0;
4049                 ddb->end = 0;
4050                 return;
4051         }
4052
4053         ddb->start = (ffs(slice_mask) - 1) * slice_size;
4054         ddb->end = fls(slice_mask) * slice_size;
4055
4056         WARN_ON(ddb->start >= ddb->end);
4057         WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
4058 }
4059
4060 static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
4061 {
4062         struct skl_ddb_entry ddb;
4063
4064         if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
4065                 slice_mask = BIT(DBUF_S1);
4066         else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
4067                 slice_mask = BIT(DBUF_S3);
4068
4069         skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
4070
4071         return ddb.start;
4072 }
4073
4074 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
4075                             const struct skl_ddb_entry *entry)
4076 {
4077         int slice_size = intel_dbuf_slice_size(dev_priv);
4078         enum dbuf_slice start_slice, end_slice;
4079         u8 slice_mask = 0;
4080
4081         if (!skl_ddb_entry_size(entry))
4082                 return 0;
4083
4084         start_slice = entry->start / slice_size;
4085         end_slice = (entry->end - 1) / slice_size;
4086
4087         /*
4088          * Per plane DDB entry can in a really worst case be on multiple slices
4089          * but single entry is anyway contigious.
4090          */
4091         while (start_slice <= end_slice) {
4092                 slice_mask |= BIT(start_slice);
4093                 start_slice++;
4094         }
4095
4096         return slice_mask;
4097 }
4098
4099 static unsigned int intel_crtc_ddb_weight(const struct intel_crtc_state *crtc_state)
4100 {
4101         const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4102         int hdisplay, vdisplay;
4103
4104         if (!crtc_state->hw.active)
4105                 return 0;
4106
4107         /*
4108          * Watermark/ddb requirement highly depends upon width of the
4109          * framebuffer, So instead of allocating DDB equally among pipes
4110          * distribute DDB based on resolution/width of the display.
4111          */
4112         drm_mode_get_hv_timing(pipe_mode, &hdisplay, &vdisplay);
4113
4114         return hdisplay;
4115 }
4116
4117 static void intel_crtc_dbuf_weights(const struct intel_dbuf_state *dbuf_state,
4118                                     enum pipe for_pipe,
4119                                     unsigned int *weight_start,
4120                                     unsigned int *weight_end,
4121                                     unsigned int *weight_total)
4122 {
4123         struct drm_i915_private *dev_priv =
4124                 to_i915(dbuf_state->base.state->base.dev);
4125         enum pipe pipe;
4126
4127         *weight_start = 0;
4128         *weight_end = 0;
4129         *weight_total = 0;
4130
4131         for_each_pipe(dev_priv, pipe) {
4132                 int weight = dbuf_state->weight[pipe];
4133
4134                 /*
4135                  * Do not account pipes using other slice sets
4136                  * luckily as of current BSpec slice sets do not partially
4137                  * intersect(pipes share either same one slice or same slice set
4138                  * i.e no partial intersection), so it is enough to check for
4139                  * equality for now.
4140                  */
4141                 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe])
4142                         continue;
4143
4144                 *weight_total += weight;
4145                 if (pipe < for_pipe) {
4146                         *weight_start += weight;
4147                         *weight_end += weight;
4148                 } else if (pipe == for_pipe) {
4149                         *weight_end += weight;
4150                 }
4151         }
4152 }
4153
4154 static int
4155 skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
4156 {
4157         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4158         unsigned int weight_total, weight_start, weight_end;
4159         const struct intel_dbuf_state *old_dbuf_state =
4160                 intel_atomic_get_old_dbuf_state(state);
4161         struct intel_dbuf_state *new_dbuf_state =
4162                 intel_atomic_get_new_dbuf_state(state);
4163         struct intel_crtc_state *crtc_state;
4164         struct skl_ddb_entry ddb_slices;
4165         enum pipe pipe = crtc->pipe;
4166         unsigned int mbus_offset = 0;
4167         u32 ddb_range_size;
4168         u32 dbuf_slice_mask;
4169         u32 start, end;
4170         int ret;
4171
4172         if (new_dbuf_state->weight[pipe] == 0) {
4173                 new_dbuf_state->ddb[pipe].start = 0;
4174                 new_dbuf_state->ddb[pipe].end = 0;
4175                 goto out;
4176         }
4177
4178         dbuf_slice_mask = new_dbuf_state->slices[pipe];
4179
4180         skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices);
4181         mbus_offset = mbus_ddb_offset(dev_priv, dbuf_slice_mask);
4182         ddb_range_size = skl_ddb_entry_size(&ddb_slices);
4183
4184         intel_crtc_dbuf_weights(new_dbuf_state, pipe,
4185                                 &weight_start, &weight_end, &weight_total);
4186
4187         start = ddb_range_size * weight_start / weight_total;
4188         end = ddb_range_size * weight_end / weight_total;
4189
4190         new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
4191         new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
4192 out:
4193         if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
4194             skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
4195                                 &new_dbuf_state->ddb[pipe]))
4196                 return 0;
4197
4198         ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
4199         if (ret)
4200                 return ret;
4201
4202         crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
4203         if (IS_ERR(crtc_state))
4204                 return PTR_ERR(crtc_state);
4205
4206         /*
4207          * Used for checking overlaps, so we need absolute
4208          * offsets instead of MBUS relative offsets.
4209          */
4210         crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
4211         crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
4212
4213         drm_dbg_kms(&dev_priv->drm,
4214                     "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
4215                     crtc->base.base.id, crtc->base.name,
4216                     old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe],
4217                     old_dbuf_state->ddb[pipe].start, old_dbuf_state->ddb[pipe].end,
4218                     new_dbuf_state->ddb[pipe].start, new_dbuf_state->ddb[pipe].end,
4219                     old_dbuf_state->active_pipes, new_dbuf_state->active_pipes);
4220
4221         return 0;
4222 }
4223
4224 static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
4225                                  int width, const struct drm_format_info *format,
4226                                  u64 modifier, unsigned int rotation,
4227                                  u32 plane_pixel_rate, struct skl_wm_params *wp,
4228                                  int color_plane);
4229 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
4230                                  int level,
4231                                  unsigned int latency,
4232                                  const struct skl_wm_params *wp,
4233                                  const struct skl_wm_level *result_prev,
4234                                  struct skl_wm_level *result /* out */);
4235
4236 static unsigned int
4237 skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
4238                       int num_active)
4239 {
4240         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4241         int level, max_level = ilk_wm_max_level(dev_priv);
4242         struct skl_wm_level wm = {};
4243         int ret, min_ddb_alloc = 0;
4244         struct skl_wm_params wp;
4245
4246         ret = skl_compute_wm_params(crtc_state, 256,
4247                                     drm_format_info(DRM_FORMAT_ARGB8888),
4248                                     DRM_FORMAT_MOD_LINEAR,
4249                                     DRM_MODE_ROTATE_0,
4250                                     crtc_state->pixel_rate, &wp, 0);
4251         drm_WARN_ON(&dev_priv->drm, ret);
4252
4253         for (level = 0; level <= max_level; level++) {
4254                 unsigned int latency = dev_priv->wm.skl_latency[level];
4255
4256                 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
4257                 if (wm.min_ddb_alloc == U16_MAX)
4258                         break;
4259
4260                 min_ddb_alloc = wm.min_ddb_alloc;
4261         }
4262
4263         return max(num_active == 1 ? 32 : 8, min_ddb_alloc);
4264 }
4265
4266 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
4267                                        struct skl_ddb_entry *entry, u32 reg)
4268 {
4269         entry->start = reg & DDB_ENTRY_MASK;
4270         entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
4271
4272         if (entry->end)
4273                 entry->end += 1;
4274 }
4275
4276 static void
4277 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
4278                            const enum pipe pipe,
4279                            const enum plane_id plane_id,
4280                            struct skl_ddb_entry *ddb_y,
4281                            struct skl_ddb_entry *ddb_uv)
4282 {
4283         u32 val, val2;
4284         u32 fourcc = 0;
4285
4286         /* Cursor doesn't support NV12/planar, so no extra calculation needed */
4287         if (plane_id == PLANE_CURSOR) {
4288                 val = intel_uncore_read(&dev_priv->uncore, CUR_BUF_CFG(pipe));
4289                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4290                 return;
4291         }
4292
4293         val = intel_uncore_read(&dev_priv->uncore, PLANE_CTL(pipe, plane_id));
4294
4295         /* No DDB allocated for disabled planes */
4296         if (val & PLANE_CTL_ENABLE)
4297                 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK,
4298                                               val & PLANE_CTL_ORDER_RGBX,
4299                                               val & PLANE_CTL_ALPHA_MASK);
4300
4301         if (DISPLAY_VER(dev_priv) >= 11) {
4302                 val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
4303                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4304         } else {
4305                 val = intel_uncore_read(&dev_priv->uncore, PLANE_BUF_CFG(pipe, plane_id));
4306                 val2 = intel_uncore_read(&dev_priv->uncore, PLANE_NV12_BUF_CFG(pipe, plane_id));
4307
4308                 if (fourcc &&
4309                     drm_format_info_is_yuv_semiplanar(drm_format_info(fourcc)))
4310                         swap(val, val2);
4311
4312                 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val);
4313                 skl_ddb_entry_init_from_hw(dev_priv, ddb_uv, val2);
4314         }
4315 }
4316
4317 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4318                                struct skl_ddb_entry *ddb_y,
4319                                struct skl_ddb_entry *ddb_uv)
4320 {
4321         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4322         enum intel_display_power_domain power_domain;
4323         enum pipe pipe = crtc->pipe;
4324         intel_wakeref_t wakeref;
4325         enum plane_id plane_id;
4326
4327         power_domain = POWER_DOMAIN_PIPE(pipe);
4328         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4329         if (!wakeref)
4330                 return;
4331
4332         for_each_plane_id_on_crtc(crtc, plane_id)
4333                 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4334                                            plane_id,
4335                                            &ddb_y[plane_id],
4336                                            &ddb_uv[plane_id]);
4337
4338         intel_display_power_put(dev_priv, power_domain, wakeref);
4339 }
4340
4341 /*
4342  * Determines the downscale amount of a plane for the purposes of watermark calculations.
4343  * The bspec defines downscale amount as:
4344  *
4345  * """
4346  * Horizontal down scale amount = maximum[1, Horizontal source size /
4347  *                                           Horizontal destination size]
4348  * Vertical down scale amount = maximum[1, Vertical source size /
4349  *                                         Vertical destination size]
4350  * Total down scale amount = Horizontal down scale amount *
4351  *                           Vertical down scale amount
4352  * """
4353  *
4354  * Return value is provided in 16.16 fixed point form to retain fractional part.
4355  * Caller should take care of dividing & rounding off the value.
4356  */
4357 static uint_fixed_16_16_t
4358 skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
4359                            const struct intel_plane_state *plane_state)
4360 {
4361         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4362         u32 src_w, src_h, dst_w, dst_h;
4363         uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
4364         uint_fixed_16_16_t downscale_h, downscale_w;
4365
4366         if (drm_WARN_ON(&dev_priv->drm,
4367                         !intel_wm_plane_visible(crtc_state, plane_state)))
4368                 return u32_to_fixed16(0);
4369
4370         /*
4371          * Src coordinates are already rotated by 270 degrees for
4372          * the 90/270 degree plane rotation cases (to match the
4373          * GTT mapping), hence no need to account for rotation here.
4374          *
4375          * n.b., src is 16.16 fixed point, dst is whole integer.
4376          */
4377         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4378         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4379         dst_w = drm_rect_width(&plane_state->uapi.dst);
4380         dst_h = drm_rect_height(&plane_state->uapi.dst);
4381
4382         fp_w_ratio = div_fixed16(src_w, dst_w);
4383         fp_h_ratio = div_fixed16(src_h, dst_h);
4384         downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
4385         downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
4386
4387         return mul_fixed16(downscale_w, downscale_h);
4388 }
4389
4390 struct dbuf_slice_conf_entry {
4391         u8 active_pipes;
4392         u8 dbuf_mask[I915_MAX_PIPES];
4393         bool join_mbus;
4394 };
4395
4396 /*
4397  * Table taken from Bspec 12716
4398  * Pipes do have some preferred DBuf slice affinity,
4399  * plus there are some hardcoded requirements on how
4400  * those should be distributed for multipipe scenarios.
4401  * For more DBuf slices algorithm can get even more messy
4402  * and less readable, so decided to use a table almost
4403  * as is from BSpec itself - that way it is at least easier
4404  * to compare, change and check.
4405  */
4406 static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] =
4407 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4408 {
4409         {
4410                 .active_pipes = BIT(PIPE_A),
4411                 .dbuf_mask = {
4412                         [PIPE_A] = BIT(DBUF_S1),
4413                 },
4414         },
4415         {
4416                 .active_pipes = BIT(PIPE_B),
4417                 .dbuf_mask = {
4418                         [PIPE_B] = BIT(DBUF_S1),
4419                 },
4420         },
4421         {
4422                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4423                 .dbuf_mask = {
4424                         [PIPE_A] = BIT(DBUF_S1),
4425                         [PIPE_B] = BIT(DBUF_S2),
4426                 },
4427         },
4428         {
4429                 .active_pipes = BIT(PIPE_C),
4430                 .dbuf_mask = {
4431                         [PIPE_C] = BIT(DBUF_S2),
4432                 },
4433         },
4434         {
4435                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4436                 .dbuf_mask = {
4437                         [PIPE_A] = BIT(DBUF_S1),
4438                         [PIPE_C] = BIT(DBUF_S2),
4439                 },
4440         },
4441         {
4442                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4443                 .dbuf_mask = {
4444                         [PIPE_B] = BIT(DBUF_S1),
4445                         [PIPE_C] = BIT(DBUF_S2),
4446                 },
4447         },
4448         {
4449                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4450                 .dbuf_mask = {
4451                         [PIPE_A] = BIT(DBUF_S1),
4452                         [PIPE_B] = BIT(DBUF_S1),
4453                         [PIPE_C] = BIT(DBUF_S2),
4454                 },
4455         },
4456         {}
4457 };
4458
4459 /*
4460  * Table taken from Bspec 49255
4461  * Pipes do have some preferred DBuf slice affinity,
4462  * plus there are some hardcoded requirements on how
4463  * those should be distributed for multipipe scenarios.
4464  * For more DBuf slices algorithm can get even more messy
4465  * and less readable, so decided to use a table almost
4466  * as is from BSpec itself - that way it is at least easier
4467  * to compare, change and check.
4468  */
4469 static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
4470 /* Autogenerated with igt/tools/intel_dbuf_map tool: */
4471 {
4472         {
4473                 .active_pipes = BIT(PIPE_A),
4474                 .dbuf_mask = {
4475                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4476                 },
4477         },
4478         {
4479                 .active_pipes = BIT(PIPE_B),
4480                 .dbuf_mask = {
4481                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
4482                 },
4483         },
4484         {
4485                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4486                 .dbuf_mask = {
4487                         [PIPE_A] = BIT(DBUF_S2),
4488                         [PIPE_B] = BIT(DBUF_S1),
4489                 },
4490         },
4491         {
4492                 .active_pipes = BIT(PIPE_C),
4493                 .dbuf_mask = {
4494                         [PIPE_C] = BIT(DBUF_S2) | BIT(DBUF_S1),
4495                 },
4496         },
4497         {
4498                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4499                 .dbuf_mask = {
4500                         [PIPE_A] = BIT(DBUF_S1),
4501                         [PIPE_C] = BIT(DBUF_S2),
4502                 },
4503         },
4504         {
4505                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4506                 .dbuf_mask = {
4507                         [PIPE_B] = BIT(DBUF_S1),
4508                         [PIPE_C] = BIT(DBUF_S2),
4509                 },
4510         },
4511         {
4512                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4513                 .dbuf_mask = {
4514                         [PIPE_A] = BIT(DBUF_S1),
4515                         [PIPE_B] = BIT(DBUF_S1),
4516                         [PIPE_C] = BIT(DBUF_S2),
4517                 },
4518         },
4519         {
4520                 .active_pipes = BIT(PIPE_D),
4521                 .dbuf_mask = {
4522                         [PIPE_D] = BIT(DBUF_S2) | BIT(DBUF_S1),
4523                 },
4524         },
4525         {
4526                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4527                 .dbuf_mask = {
4528                         [PIPE_A] = BIT(DBUF_S1),
4529                         [PIPE_D] = BIT(DBUF_S2),
4530                 },
4531         },
4532         {
4533                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4534                 .dbuf_mask = {
4535                         [PIPE_B] = BIT(DBUF_S1),
4536                         [PIPE_D] = BIT(DBUF_S2),
4537                 },
4538         },
4539         {
4540                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4541                 .dbuf_mask = {
4542                         [PIPE_A] = BIT(DBUF_S1),
4543                         [PIPE_B] = BIT(DBUF_S1),
4544                         [PIPE_D] = BIT(DBUF_S2),
4545                 },
4546         },
4547         {
4548                 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4549                 .dbuf_mask = {
4550                         [PIPE_C] = BIT(DBUF_S1),
4551                         [PIPE_D] = BIT(DBUF_S2),
4552                 },
4553         },
4554         {
4555                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4556                 .dbuf_mask = {
4557                         [PIPE_A] = BIT(DBUF_S1),
4558                         [PIPE_C] = BIT(DBUF_S2),
4559                         [PIPE_D] = BIT(DBUF_S2),
4560                 },
4561         },
4562         {
4563                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4564                 .dbuf_mask = {
4565                         [PIPE_B] = BIT(DBUF_S1),
4566                         [PIPE_C] = BIT(DBUF_S2),
4567                         [PIPE_D] = BIT(DBUF_S2),
4568                 },
4569         },
4570         {
4571                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4572                 .dbuf_mask = {
4573                         [PIPE_A] = BIT(DBUF_S1),
4574                         [PIPE_B] = BIT(DBUF_S1),
4575                         [PIPE_C] = BIT(DBUF_S2),
4576                         [PIPE_D] = BIT(DBUF_S2),
4577                 },
4578         },
4579         {}
4580 };
4581
4582 static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
4583         {
4584                 .active_pipes = BIT(PIPE_A),
4585                 .dbuf_mask = {
4586                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
4587                 },
4588                 .join_mbus = true,
4589         },
4590         {
4591                 .active_pipes = BIT(PIPE_B),
4592                 .dbuf_mask = {
4593                         [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
4594                 },
4595                 .join_mbus = true,
4596         },
4597         {
4598                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
4599                 .dbuf_mask = {
4600                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4601                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4602                 },
4603         },
4604         {
4605                 .active_pipes = BIT(PIPE_C),
4606                 .dbuf_mask = {
4607                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4608                 },
4609         },
4610         {
4611                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
4612                 .dbuf_mask = {
4613                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4614                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4615                 },
4616         },
4617         {
4618                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
4619                 .dbuf_mask = {
4620                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4621                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4622                 },
4623         },
4624         {
4625                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
4626                 .dbuf_mask = {
4627                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4628                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4629                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4630                 },
4631         },
4632         {
4633                 .active_pipes = BIT(PIPE_D),
4634                 .dbuf_mask = {
4635                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4636                 },
4637         },
4638         {
4639                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
4640                 .dbuf_mask = {
4641                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4642                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4643                 },
4644         },
4645         {
4646                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
4647                 .dbuf_mask = {
4648                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4649                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4650                 },
4651         },
4652         {
4653                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
4654                 .dbuf_mask = {
4655                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4656                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4657                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4658                 },
4659         },
4660         {
4661                 .active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
4662                 .dbuf_mask = {
4663                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4664                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4665                 },
4666         },
4667         {
4668                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
4669                 .dbuf_mask = {
4670                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4671                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4672                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4673                 },
4674         },
4675         {
4676                 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4677                 .dbuf_mask = {
4678                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4679                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4680                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4681                 },
4682         },
4683         {
4684                 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
4685                 .dbuf_mask = {
4686                         [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
4687                         [PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
4688                         [PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
4689                         [PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
4690                 },
4691         },
4692         {}
4693
4694 };
4695
4696 static bool check_mbus_joined(u8 active_pipes,
4697                               const struct dbuf_slice_conf_entry *dbuf_slices)
4698 {
4699         int i;
4700
4701         for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4702                 if (dbuf_slices[i].active_pipes == active_pipes)
4703                         return dbuf_slices[i].join_mbus;
4704         }
4705         return false;
4706 }
4707
4708 static bool adlp_check_mbus_joined(u8 active_pipes)
4709 {
4710         return check_mbus_joined(active_pipes, adlp_allowed_dbufs);
4711 }
4712
4713 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4714                               const struct dbuf_slice_conf_entry *dbuf_slices)
4715 {
4716         int i;
4717
4718         for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
4719                 if (dbuf_slices[i].active_pipes == active_pipes)
4720                         return dbuf_slices[i].dbuf_mask[pipe];
4721         }
4722         return 0;
4723 }
4724
4725 /*
4726  * This function finds an entry with same enabled pipe configuration and
4727  * returns correspondent DBuf slice mask as stated in BSpec for particular
4728  * platform.
4729  */
4730 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4731 {
4732         /*
4733          * FIXME: For ICL this is still a bit unclear as prev BSpec revision
4734          * required calculating "pipe ratio" in order to determine
4735          * if one or two slices can be used for single pipe configurations
4736          * as additional constraint to the existing table.
4737          * However based on recent info, it should be not "pipe ratio"
4738          * but rather ratio between pixel_rate and cdclk with additional
4739          * constants, so for now we are using only table until this is
4740          * clarified. Also this is the reason why crtc_state param is
4741          * still here - we will need it once those additional constraints
4742          * pop up.
4743          */
4744         return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
4745 }
4746
4747 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4748 {
4749         return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
4750 }
4751
4752 static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
4753 {
4754         return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
4755 }
4756
4757 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
4758 {
4759         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4760         enum pipe pipe = crtc->pipe;
4761
4762         if (IS_ALDERLAKE_P(dev_priv))
4763                 return adlp_compute_dbuf_slices(pipe, active_pipes);
4764         else if (DISPLAY_VER(dev_priv) == 12)
4765                 return tgl_compute_dbuf_slices(pipe, active_pipes);
4766         else if (DISPLAY_VER(dev_priv) == 11)
4767                 return icl_compute_dbuf_slices(pipe, active_pipes);
4768         /*
4769          * For anything else just return one slice yet.
4770          * Should be extended for other platforms.
4771          */
4772         return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
4773 }
4774
4775 static u64
4776 skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
4777                              const struct intel_plane_state *plane_state,
4778                              int color_plane)
4779 {
4780         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
4781         const struct drm_framebuffer *fb = plane_state->hw.fb;
4782         u32 data_rate;
4783         u32 width = 0, height = 0;
4784         uint_fixed_16_16_t down_scale_amount;
4785         u64 rate;
4786
4787         if (!plane_state->uapi.visible)
4788                 return 0;
4789
4790         if (plane->id == PLANE_CURSOR)
4791                 return 0;
4792
4793         if (color_plane == 1 &&
4794             !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
4795                 return 0;
4796
4797         /*
4798          * Src coordinates are already rotated by 270 degrees for
4799          * the 90/270 degree plane rotation cases (to match the
4800          * GTT mapping), hence no need to account for rotation here.
4801          */
4802         width = drm_rect_width(&plane_state->uapi.src) >> 16;
4803         height = drm_rect_height(&plane_state->uapi.src) >> 16;
4804
4805         /* UV plane does 1/2 pixel sub-sampling */
4806         if (color_plane == 1) {
4807                 width /= 2;
4808                 height /= 2;
4809         }
4810
4811         data_rate = width * height;
4812
4813         down_scale_amount = skl_plane_downscale_amount(crtc_state, plane_state);
4814
4815         rate = mul_round_up_u32_fixed16(data_rate, down_scale_amount);
4816
4817         rate *= fb->format->cpp[color_plane];
4818         return rate;
4819 }
4820
4821 static u64
4822 skl_get_total_relative_data_rate(struct intel_atomic_state *state,
4823                                  struct intel_crtc *crtc)
4824 {
4825         struct intel_crtc_state *crtc_state =
4826                 intel_atomic_get_new_crtc_state(state, crtc);
4827         const struct intel_plane_state *plane_state;
4828         struct intel_plane *plane;
4829         u64 total_data_rate = 0;
4830         enum plane_id plane_id;
4831         int i;
4832
4833         /* Calculate and cache data rate for each plane */
4834         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4835                 if (plane->pipe != crtc->pipe)
4836                         continue;
4837
4838                 plane_id = plane->id;
4839
4840                 /* packed/y */
4841                 crtc_state->plane_data_rate[plane_id] =
4842                         skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4843
4844                 /* uv-plane */
4845                 crtc_state->uv_plane_data_rate[plane_id] =
4846                         skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4847         }
4848
4849         for_each_plane_id_on_crtc(crtc, plane_id) {
4850                 total_data_rate += crtc_state->plane_data_rate[plane_id];
4851                 total_data_rate += crtc_state->uv_plane_data_rate[plane_id];
4852         }
4853
4854         return total_data_rate;
4855 }
4856
4857 static u64
4858 icl_get_total_relative_data_rate(struct intel_atomic_state *state,
4859                                  struct intel_crtc *crtc)
4860 {
4861         struct intel_crtc_state *crtc_state =
4862                 intel_atomic_get_new_crtc_state(state, crtc);
4863         const struct intel_plane_state *plane_state;
4864         struct intel_plane *plane;
4865         u64 total_data_rate = 0;
4866         enum plane_id plane_id;
4867         int i;
4868
4869         /* Calculate and cache data rate for each plane */
4870         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4871                 if (plane->pipe != crtc->pipe)
4872                         continue;
4873
4874                 plane_id = plane->id;
4875
4876                 if (!plane_state->planar_linked_plane) {
4877                         crtc_state->plane_data_rate[plane_id] =
4878                                 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4879                 } else {
4880                         enum plane_id y_plane_id;
4881
4882                         /*
4883                          * The slave plane might not iterate in
4884                          * intel_atomic_crtc_state_for_each_plane_state(),
4885                          * and needs the master plane state which may be
4886                          * NULL if we try get_new_plane_state(), so we
4887                          * always calculate from the master.
4888                          */
4889                         if (plane_state->planar_slave)
4890                                 continue;
4891
4892                         /* Y plane rate is calculated on the slave */
4893                         y_plane_id = plane_state->planar_linked_plane->id;
4894                         crtc_state->plane_data_rate[y_plane_id] =
4895                                 skl_plane_relative_data_rate(crtc_state, plane_state, 0);
4896
4897                         crtc_state->plane_data_rate[plane_id] =
4898                                 skl_plane_relative_data_rate(crtc_state, plane_state, 1);
4899                 }
4900         }
4901
4902         for_each_plane_id_on_crtc(crtc, plane_id)
4903                 total_data_rate += crtc_state->plane_data_rate[plane_id];
4904
4905         return total_data_rate;
4906 }
4907
4908 const struct skl_wm_level *
4909 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
4910                    enum plane_id plane_id,
4911                    int level)
4912 {
4913         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
4914
4915         if (level == 0 && pipe_wm->use_sagv_wm)
4916                 return &wm->sagv.wm0;
4917
4918         return &wm->wm[level];
4919 }
4920
4921 const struct skl_wm_level *
4922 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
4923                    enum plane_id plane_id)
4924 {
4925         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
4926
4927         if (pipe_wm->use_sagv_wm)
4928                 return &wm->sagv.trans_wm;
4929
4930         return &wm->trans_wm;
4931 }
4932
4933 /*
4934  * We only disable the watermarks for each plane if
4935  * they exceed the ddb allocation of said plane. This
4936  * is done so that we don't end up touching cursor
4937  * watermarks needlessly when some other plane reduces
4938  * our max possible watermark level.
4939  *
4940  * Bspec has this to say about the PLANE_WM enable bit:
4941  * "All the watermarks at this level for all enabled
4942  *  planes must be enabled before the level will be used."
4943  * So this is actually safe to do.
4944  */
4945 static void
4946 skl_check_wm_level(struct skl_wm_level *wm, u64 total)
4947 {
4948         if (wm->min_ddb_alloc > total)
4949                 memset(wm, 0, sizeof(*wm));
4950 }
4951
4952 static void
4953 skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
4954                         u64 total, u64 uv_total)
4955 {
4956         if (wm->min_ddb_alloc > total ||
4957             uv_wm->min_ddb_alloc > uv_total) {
4958                 memset(wm, 0, sizeof(*wm));
4959                 memset(uv_wm, 0, sizeof(*uv_wm));
4960         }
4961 }
4962
4963 static int
4964 skl_allocate_plane_ddb(struct intel_atomic_state *state,
4965                        struct intel_crtc *crtc)
4966 {
4967         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4968         struct intel_crtc_state *crtc_state =
4969                 intel_atomic_get_new_crtc_state(state, crtc);
4970         const struct intel_dbuf_state *dbuf_state =
4971                 intel_atomic_get_new_dbuf_state(state);
4972         const struct skl_ddb_entry *alloc = &dbuf_state->ddb[crtc->pipe];
4973         int num_active = hweight8(dbuf_state->active_pipes);
4974         u16 alloc_size, start = 0;
4975         u16 total[I915_MAX_PLANES] = {};
4976         u16 uv_total[I915_MAX_PLANES] = {};
4977         u64 total_data_rate;
4978         enum plane_id plane_id;
4979         u32 blocks;
4980         int level;
4981
4982         /* Clear the partitioning for disabled planes. */
4983         memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4984         memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
4985
4986         if (!crtc_state->hw.active)
4987                 return 0;
4988
4989         if (DISPLAY_VER(dev_priv) >= 11)
4990                 total_data_rate =
4991                         icl_get_total_relative_data_rate(state, crtc);
4992         else
4993                 total_data_rate =
4994                         skl_get_total_relative_data_rate(state, crtc);
4995
4996         alloc_size = skl_ddb_entry_size(alloc);
4997         if (alloc_size == 0)
4998                 return 0;
4999
5000         /* Allocate fixed number of blocks for cursor. */
5001         total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
5002         alloc_size -= total[PLANE_CURSOR];
5003         crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
5004                 alloc->end - total[PLANE_CURSOR];
5005         crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
5006
5007         if (total_data_rate == 0)
5008                 return 0;
5009
5010         /*
5011          * Find the highest watermark level for which we can satisfy the block
5012          * requirement of active planes.
5013          */
5014         for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
5015                 blocks = 0;
5016                 for_each_plane_id_on_crtc(crtc, plane_id) {
5017                         const struct skl_plane_wm *wm =
5018                                 &crtc_state->wm.skl.optimal.planes[plane_id];
5019
5020                         if (plane_id == PLANE_CURSOR) {
5021                                 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
5022                                         drm_WARN_ON(&dev_priv->drm,
5023                                                     wm->wm[level].min_ddb_alloc != U16_MAX);
5024                                         blocks = U32_MAX;
5025                                         break;
5026                                 }
5027                                 continue;
5028                         }
5029
5030                         blocks += wm->wm[level].min_ddb_alloc;
5031                         blocks += wm->uv_wm[level].min_ddb_alloc;
5032                 }
5033
5034                 if (blocks <= alloc_size) {
5035                         alloc_size -= blocks;
5036                         break;
5037                 }
5038         }
5039
5040         if (level < 0) {
5041                 drm_dbg_kms(&dev_priv->drm,
5042                             "Requested display configuration exceeds system DDB limitations");
5043                 drm_dbg_kms(&dev_priv->drm, "minimum required %d/%d\n",
5044                             blocks, alloc_size);
5045                 return -EINVAL;
5046         }
5047
5048         /*
5049          * Grant each plane the blocks it requires at the highest achievable
5050          * watermark level, plus an extra share of the leftover blocks
5051          * proportional to its relative data rate.
5052          */
5053         for_each_plane_id_on_crtc(crtc, plane_id) {
5054                 const struct skl_plane_wm *wm =
5055                         &crtc_state->wm.skl.optimal.planes[plane_id];
5056                 u64 rate;
5057                 u16 extra;
5058
5059                 if (plane_id == PLANE_CURSOR)
5060                         continue;
5061
5062                 /*
5063                  * We've accounted for all active planes; remaining planes are
5064                  * all disabled.
5065                  */
5066                 if (total_data_rate == 0)
5067                         break;
5068
5069                 rate = crtc_state->plane_data_rate[plane_id];
5070                 extra = min_t(u16, alloc_size,
5071                               DIV64_U64_ROUND_UP(alloc_size * rate,
5072                                                  total_data_rate));
5073                 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
5074                 alloc_size -= extra;
5075                 total_data_rate -= rate;
5076
5077                 if (total_data_rate == 0)
5078                         break;
5079
5080                 rate = crtc_state->uv_plane_data_rate[plane_id];
5081                 extra = min_t(u16, alloc_size,
5082                               DIV64_U64_ROUND_UP(alloc_size * rate,
5083                                                  total_data_rate));
5084                 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
5085                 alloc_size -= extra;
5086                 total_data_rate -= rate;
5087         }
5088         drm_WARN_ON(&dev_priv->drm, alloc_size != 0 || total_data_rate != 0);
5089
5090         /* Set the actual DDB start/end points for each plane */
5091         start = alloc->start;
5092         for_each_plane_id_on_crtc(crtc, plane_id) {
5093                 struct skl_ddb_entry *plane_alloc =
5094                         &crtc_state->wm.skl.plane_ddb_y[plane_id];
5095                 struct skl_ddb_entry *uv_plane_alloc =
5096                         &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5097
5098                 if (plane_id == PLANE_CURSOR)
5099                         continue;
5100
5101                 /* Gen11+ uses a separate plane for UV watermarks */
5102                 drm_WARN_ON(&dev_priv->drm,
5103                             DISPLAY_VER(dev_priv) >= 11 && uv_total[plane_id]);
5104
5105                 /* Leave disabled planes at (0,0) */
5106                 if (total[plane_id]) {
5107                         plane_alloc->start = start;
5108                         start += total[plane_id];
5109                         plane_alloc->end = start;
5110                 }
5111
5112                 if (uv_total[plane_id]) {
5113                         uv_plane_alloc->start = start;
5114                         start += uv_total[plane_id];
5115                         uv_plane_alloc->end = start;
5116                 }
5117         }
5118
5119         /*
5120          * When we calculated watermark values we didn't know how high
5121          * of a level we'd actually be able to hit, so we just marked
5122          * all levels as "enabled."  Go back now and disable the ones
5123          * that aren't actually possible.
5124          */
5125         for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
5126                 for_each_plane_id_on_crtc(crtc, plane_id) {
5127                         struct skl_plane_wm *wm =
5128                                 &crtc_state->wm.skl.optimal.planes[plane_id];
5129
5130                         skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
5131                                                 total[plane_id], uv_total[plane_id]);
5132
5133                         /*
5134                          * Wa_1408961008:icl, ehl
5135                          * Underruns with WM1+ disabled
5136                          */
5137                         if (DISPLAY_VER(dev_priv) == 11 &&
5138                             level == 1 && wm->wm[0].enable) {
5139                                 wm->wm[level].blocks = wm->wm[0].blocks;
5140                                 wm->wm[level].lines = wm->wm[0].lines;
5141                                 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
5142                         }
5143                 }
5144         }
5145
5146         /*
5147          * Go back and disable the transition and SAGV watermarks
5148          * if it turns out we don't have enough DDB blocks for them.
5149          */
5150         for_each_plane_id_on_crtc(crtc, plane_id) {
5151                 struct skl_plane_wm *wm =
5152                         &crtc_state->wm.skl.optimal.planes[plane_id];
5153
5154                 skl_check_wm_level(&wm->trans_wm, total[plane_id]);
5155                 skl_check_wm_level(&wm->sagv.wm0, total[plane_id]);
5156                 skl_check_wm_level(&wm->sagv.trans_wm, total[plane_id]);
5157         }
5158
5159         return 0;
5160 }
5161
5162 /*
5163  * The max latency should be 257 (max the punit can code is 255 and we add 2us
5164  * for the read latency) and cpp should always be <= 8, so that
5165  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
5166  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
5167 */
5168 static uint_fixed_16_16_t
5169 skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
5170                u8 cpp, u32 latency, u32 dbuf_block_size)
5171 {
5172         u32 wm_intermediate_val;
5173         uint_fixed_16_16_t ret;
5174
5175         if (latency == 0)
5176                 return FP_16_16_MAX;
5177
5178         wm_intermediate_val = latency * pixel_rate * cpp;
5179         ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
5180
5181         if (DISPLAY_VER(dev_priv) >= 10)
5182                 ret = add_fixed16_u32(ret, 1);
5183
5184         return ret;
5185 }
5186
5187 static uint_fixed_16_16_t
5188 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
5189                uint_fixed_16_16_t plane_blocks_per_line)
5190 {
5191         u32 wm_intermediate_val;
5192         uint_fixed_16_16_t ret;
5193
5194         if (latency == 0)
5195                 return FP_16_16_MAX;
5196
5197         wm_intermediate_val = latency * pixel_rate;
5198         wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val,
5199                                            pipe_htotal * 1000);
5200         ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line);
5201         return ret;
5202 }
5203
5204 static uint_fixed_16_16_t
5205 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
5206 {
5207         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5208         u32 pixel_rate;
5209         u32 crtc_htotal;
5210         uint_fixed_16_16_t linetime_us;
5211
5212         if (!crtc_state->hw.active)
5213                 return u32_to_fixed16(0);
5214
5215         pixel_rate = crtc_state->pixel_rate;
5216
5217         if (drm_WARN_ON(&dev_priv->drm, pixel_rate == 0))
5218                 return u32_to_fixed16(0);
5219
5220         crtc_htotal = crtc_state->hw.pipe_mode.crtc_htotal;
5221         linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate);
5222
5223         return linetime_us;
5224 }
5225
5226 static int
5227 skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
5228                       int width, const struct drm_format_info *format,
5229                       u64 modifier, unsigned int rotation,
5230                       u32 plane_pixel_rate, struct skl_wm_params *wp,
5231                       int color_plane)
5232 {
5233         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5234         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5235         u32 interm_pbpl;
5236
5237         /* only planar format has two planes */
5238         if (color_plane == 1 &&
5239             !intel_format_info_is_yuv_semiplanar(format, modifier)) {
5240                 drm_dbg_kms(&dev_priv->drm,
5241                             "Non planar format have single plane\n");
5242                 return -EINVAL;
5243         }
5244
5245         wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
5246                       modifier == I915_FORMAT_MOD_Yf_TILED ||
5247                       modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5248                       modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5249         wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED;
5250         wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
5251                          modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
5252         wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier);
5253
5254         wp->width = width;
5255         if (color_plane == 1 && wp->is_planar)
5256                 wp->width /= 2;
5257
5258         wp->cpp = format->cpp[color_plane];
5259         wp->plane_pixel_rate = plane_pixel_rate;
5260
5261         if (DISPLAY_VER(dev_priv) >= 11 &&
5262             modifier == I915_FORMAT_MOD_Yf_TILED  && wp->cpp == 1)
5263                 wp->dbuf_block_size = 256;
5264         else
5265                 wp->dbuf_block_size = 512;
5266
5267         if (drm_rotation_90_or_270(rotation)) {
5268                 switch (wp->cpp) {
5269                 case 1:
5270                         wp->y_min_scanlines = 16;
5271                         break;
5272                 case 2:
5273                         wp->y_min_scanlines = 8;
5274                         break;
5275                 case 4:
5276                         wp->y_min_scanlines = 4;
5277                         break;
5278                 default:
5279                         MISSING_CASE(wp->cpp);
5280                         return -EINVAL;
5281                 }
5282         } else {
5283                 wp->y_min_scanlines = 4;
5284         }
5285
5286         if (skl_needs_memory_bw_wa(dev_priv))
5287                 wp->y_min_scanlines *= 2;
5288
5289         wp->plane_bytes_per_line = wp->width * wp->cpp;
5290         if (wp->y_tiled) {
5291                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
5292                                            wp->y_min_scanlines,
5293                                            wp->dbuf_block_size);
5294
5295                 if (DISPLAY_VER(dev_priv) >= 10)
5296                         interm_pbpl++;
5297
5298                 wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
5299                                                         wp->y_min_scanlines);
5300         } else {
5301                 interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
5302                                            wp->dbuf_block_size);
5303
5304                 if (!wp->x_tiled || DISPLAY_VER(dev_priv) >= 10)
5305                         interm_pbpl++;
5306
5307                 wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
5308         }
5309
5310         wp->y_tile_minimum = mul_u32_fixed16(wp->y_min_scanlines,
5311                                              wp->plane_blocks_per_line);
5312
5313         wp->linetime_us = fixed16_to_u32_round_up(
5314                                         intel_get_linetime_us(crtc_state));
5315
5316         return 0;
5317 }
5318
5319 static int
5320 skl_compute_plane_wm_params(const struct intel_crtc_state *crtc_state,
5321                             const struct intel_plane_state *plane_state,
5322                             struct skl_wm_params *wp, int color_plane)
5323 {
5324         const struct drm_framebuffer *fb = plane_state->hw.fb;
5325         int width;
5326
5327         /*
5328          * Src coordinates are already rotated by 270 degrees for
5329          * the 90/270 degree plane rotation cases (to match the
5330          * GTT mapping), hence no need to account for rotation here.
5331          */
5332         width = drm_rect_width(&plane_state->uapi.src) >> 16;
5333
5334         return skl_compute_wm_params(crtc_state, width,
5335                                      fb->format, fb->modifier,
5336                                      plane_state->hw.rotation,
5337                                      intel_plane_pixel_rate(crtc_state, plane_state),
5338                                      wp, color_plane);
5339 }
5340
5341 static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
5342 {
5343         if (DISPLAY_VER(dev_priv) >= 10)
5344                 return true;
5345
5346         /* The number of lines are ignored for the level 0 watermark. */
5347         return level > 0;
5348 }
5349
5350 static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
5351 {
5352         if (DISPLAY_VER(dev_priv) >= 13)
5353                 return 255;
5354         else
5355                 return 31;
5356 }
5357
5358 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
5359                                  int level,
5360                                  unsigned int latency,
5361                                  const struct skl_wm_params *wp,
5362                                  const struct skl_wm_level *result_prev,
5363                                  struct skl_wm_level *result /* out */)
5364 {
5365         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5366         uint_fixed_16_16_t method1, method2;
5367         uint_fixed_16_16_t selected_result;
5368         u32 blocks, lines, min_ddb_alloc = 0;
5369
5370         if (latency == 0) {
5371                 /* reject it */
5372                 result->min_ddb_alloc = U16_MAX;
5373                 return;
5374         }
5375
5376         /*
5377          * WaIncreaseLatencyIPCEnabled: kbl,cfl
5378          * Display WA #1141: kbl,cfl
5379          */
5380         if ((IS_KABYLAKE(dev_priv) ||
5381              IS_COFFEELAKE(dev_priv) ||
5382              IS_COMETLAKE(dev_priv)) &&
5383             dev_priv->ipc_enabled)
5384                 latency += 4;
5385
5386         if (skl_needs_memory_bw_wa(dev_priv) && wp->x_tiled)
5387                 latency += 15;
5388
5389         method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
5390                                  wp->cpp, latency, wp->dbuf_block_size);
5391         method2 = skl_wm_method2(wp->plane_pixel_rate,
5392                                  crtc_state->hw.pipe_mode.crtc_htotal,
5393                                  latency,
5394                                  wp->plane_blocks_per_line);
5395
5396         if (wp->y_tiled) {
5397                 selected_result = max_fixed16(method2, wp->y_tile_minimum);
5398         } else {
5399                 if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
5400                      wp->dbuf_block_size < 1) &&
5401                      (wp->plane_bytes_per_line / wp->dbuf_block_size < 1)) {
5402                         selected_result = method2;
5403                 } else if (latency >= wp->linetime_us) {
5404                         if (DISPLAY_VER(dev_priv) == 9)
5405                                 selected_result = min_fixed16(method1, method2);
5406                         else
5407                                 selected_result = method2;
5408                 } else {
5409                         selected_result = method1;
5410                 }
5411         }
5412
5413         blocks = fixed16_to_u32_round_up(selected_result) + 1;
5414         lines = div_round_up_fixed16(selected_result,
5415                                      wp->plane_blocks_per_line);
5416
5417         if (DISPLAY_VER(dev_priv) == 9) {
5418                 /* Display WA #1125: skl,bxt,kbl */
5419                 if (level == 0 && wp->rc_surface)
5420                         blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
5421
5422                 /* Display WA #1126: skl,bxt,kbl */
5423                 if (level >= 1 && level <= 7) {
5424                         if (wp->y_tiled) {
5425                                 blocks += fixed16_to_u32_round_up(wp->y_tile_minimum);
5426                                 lines += wp->y_min_scanlines;
5427                         } else {
5428                                 blocks++;
5429                         }
5430
5431                         /*
5432                          * Make sure result blocks for higher latency levels are
5433                          * atleast as high as level below the current level.
5434                          * Assumption in DDB algorithm optimization for special
5435                          * cases. Also covers Display WA #1125 for RC.
5436                          */
5437                         if (result_prev->blocks > blocks)
5438                                 blocks = result_prev->blocks;
5439                 }
5440         }
5441
5442         if (DISPLAY_VER(dev_priv) >= 11) {
5443                 if (wp->y_tiled) {
5444                         int extra_lines;
5445
5446                         if (lines % wp->y_min_scanlines == 0)
5447                                 extra_lines = wp->y_min_scanlines;
5448                         else
5449                                 extra_lines = wp->y_min_scanlines * 2 -
5450                                         lines % wp->y_min_scanlines;
5451
5452                         min_ddb_alloc = mul_round_up_u32_fixed16(lines + extra_lines,
5453                                                                  wp->plane_blocks_per_line);
5454                 } else {
5455                         min_ddb_alloc = blocks + DIV_ROUND_UP(blocks, 10);
5456                 }
5457         }
5458
5459         if (!skl_wm_has_lines(dev_priv, level))
5460                 lines = 0;
5461
5462         if (lines > skl_wm_max_lines(dev_priv)) {
5463                 /* reject it */
5464                 result->min_ddb_alloc = U16_MAX;
5465                 return;
5466         }
5467
5468         /*
5469          * If lines is valid, assume we can use this watermark level
5470          * for now.  We'll come back and disable it after we calculate the
5471          * DDB allocation if it turns out we don't actually have enough
5472          * blocks to satisfy it.
5473          */
5474         result->blocks = blocks;
5475         result->lines = lines;
5476         /* Bspec says: value >= plane ddb allocation -> invalid, hence the +1 here */
5477         result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
5478         result->enable = true;
5479
5480         if (DISPLAY_VER(dev_priv) < 12)
5481                 result->can_sagv = latency >= dev_priv->sagv_block_time_us;
5482 }
5483
5484 static void
5485 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
5486                       const struct skl_wm_params *wm_params,
5487                       struct skl_wm_level *levels)
5488 {
5489         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5490         int level, max_level = ilk_wm_max_level(dev_priv);
5491         struct skl_wm_level *result_prev = &levels[0];
5492
5493         for (level = 0; level <= max_level; level++) {
5494                 struct skl_wm_level *result = &levels[level];
5495                 unsigned int latency = dev_priv->wm.skl_latency[level];
5496
5497                 skl_compute_plane_wm(crtc_state, level, latency,
5498                                      wm_params, result_prev, result);
5499
5500                 result_prev = result;
5501         }
5502 }
5503
5504 static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
5505                                 const struct skl_wm_params *wm_params,
5506                                 struct skl_plane_wm *plane_wm)
5507 {
5508         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5509         struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
5510         struct skl_wm_level *levels = plane_wm->wm;
5511         unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
5512
5513         skl_compute_plane_wm(crtc_state, 0, latency,
5514                              wm_params, &levels[0],
5515                              sagv_wm);
5516 }
5517
5518 static void skl_compute_transition_wm(struct drm_i915_private *dev_priv,
5519                                       struct skl_wm_level *trans_wm,
5520                                       const struct skl_wm_level *wm0,
5521                                       const struct skl_wm_params *wp)
5522 {
5523         u16 trans_min, trans_amount, trans_y_tile_min;
5524         u16 wm0_blocks, trans_offset, blocks;
5525
5526         /* Transition WM don't make any sense if ipc is disabled */
5527         if (!dev_priv->ipc_enabled)
5528                 return;
5529
5530         /*
5531          * WaDisableTWM:skl,kbl,cfl,bxt
5532          * Transition WM are not recommended by HW team for GEN9
5533          */
5534         if (DISPLAY_VER(dev_priv) == 9)
5535                 return;
5536
5537         if (DISPLAY_VER(dev_priv) >= 11)
5538                 trans_min = 4;
5539         else
5540                 trans_min = 14;
5541
5542         /* Display WA #1140: glk,cnl */
5543         if (DISPLAY_VER(dev_priv) == 10)
5544                 trans_amount = 0;
5545         else
5546                 trans_amount = 10; /* This is configurable amount */
5547
5548         trans_offset = trans_min + trans_amount;
5549
5550         /*
5551          * The spec asks for Selected Result Blocks for wm0 (the real value),
5552          * not Result Blocks (the integer value). Pay attention to the capital
5553          * letters. The value wm_l0->blocks is actually Result Blocks, but
5554          * since Result Blocks is the ceiling of Selected Result Blocks plus 1,
5555          * and since we later will have to get the ceiling of the sum in the
5556          * transition watermarks calculation, we can just pretend Selected
5557          * Result Blocks is Result Blocks minus 1 and it should work for the
5558          * current platforms.
5559          */
5560         wm0_blocks = wm0->blocks - 1;
5561
5562         if (wp->y_tiled) {
5563                 trans_y_tile_min =
5564                         (u16)mul_round_up_u32_fixed16(2, wp->y_tile_minimum);
5565                 blocks = max(wm0_blocks, trans_y_tile_min) + trans_offset;
5566         } else {
5567                 blocks = wm0_blocks + trans_offset;
5568         }
5569         blocks++;
5570
5571         /*
5572          * Just assume we can enable the transition watermark.  After
5573          * computing the DDB we'll come back and disable it if that
5574          * assumption turns out to be false.
5575          */
5576         trans_wm->blocks = blocks;
5577         trans_wm->min_ddb_alloc = max_t(u16, wm0->min_ddb_alloc, blocks + 1);
5578         trans_wm->enable = true;
5579 }
5580
5581 static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
5582                                      const struct intel_plane_state *plane_state,
5583                                      enum plane_id plane_id, int color_plane)
5584 {
5585         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5586         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5587         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5588         struct skl_wm_params wm_params;
5589         int ret;
5590
5591         ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5592                                           &wm_params, color_plane);
5593         if (ret)
5594                 return ret;
5595
5596         skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5597
5598         skl_compute_transition_wm(dev_priv, &wm->trans_wm,
5599                                   &wm->wm[0], &wm_params);
5600
5601         if (DISPLAY_VER(dev_priv) >= 12) {
5602                 tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5603
5604                 skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
5605                                           &wm->sagv.wm0, &wm_params);
5606         }
5607
5608         return 0;
5609 }
5610
5611 static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
5612                                  const struct intel_plane_state *plane_state,
5613                                  enum plane_id plane_id)
5614 {
5615         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5616         struct skl_wm_params wm_params;
5617         int ret;
5618
5619         wm->is_planar = true;
5620
5621         /* uv plane watermarks must also be validated for NV12/Planar */
5622         ret = skl_compute_plane_wm_params(crtc_state, plane_state,
5623                                           &wm_params, 1);
5624         if (ret)
5625                 return ret;
5626
5627         skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5628
5629         return 0;
5630 }
5631
5632 static int skl_build_plane_wm(struct intel_crtc_state *crtc_state,
5633                               const struct intel_plane_state *plane_state)
5634 {
5635         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5636         enum plane_id plane_id = plane->id;
5637         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5638         const struct drm_framebuffer *fb = plane_state->hw.fb;
5639         int ret;
5640
5641         memset(wm, 0, sizeof(*wm));
5642
5643         if (!intel_wm_plane_visible(crtc_state, plane_state))
5644                 return 0;
5645
5646         ret = skl_build_plane_wm_single(crtc_state, plane_state,
5647                                         plane_id, 0);
5648         if (ret)
5649                 return ret;
5650
5651         if (fb->format->is_yuv && fb->format->num_planes > 1) {
5652                 ret = skl_build_plane_wm_uv(crtc_state, plane_state,
5653                                             plane_id);
5654                 if (ret)
5655                         return ret;
5656         }
5657
5658         return 0;
5659 }
5660
5661 static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
5662                               const struct intel_plane_state *plane_state)
5663 {
5664         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
5665         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5666         enum plane_id plane_id = plane->id;
5667         struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id];
5668         int ret;
5669
5670         /* Watermarks calculated in master */
5671         if (plane_state->planar_slave)
5672                 return 0;
5673
5674         memset(wm, 0, sizeof(*wm));
5675
5676         if (plane_state->planar_linked_plane) {
5677                 const struct drm_framebuffer *fb = plane_state->hw.fb;
5678                 enum plane_id y_plane_id = plane_state->planar_linked_plane->id;
5679
5680                 drm_WARN_ON(&dev_priv->drm,
5681                             !intel_wm_plane_visible(crtc_state, plane_state));
5682                 drm_WARN_ON(&dev_priv->drm, !fb->format->is_yuv ||
5683                             fb->format->num_planes == 1);
5684
5685                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5686                                                 y_plane_id, 0);
5687                 if (ret)
5688                         return ret;
5689
5690                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5691                                                 plane_id, 1);
5692                 if (ret)
5693                         return ret;
5694         } else if (intel_wm_plane_visible(crtc_state, plane_state)) {
5695                 ret = skl_build_plane_wm_single(crtc_state, plane_state,
5696                                                 plane_id, 0);
5697                 if (ret)
5698                         return ret;
5699         }
5700
5701         return 0;
5702 }
5703
5704 static int skl_build_pipe_wm(struct intel_atomic_state *state,
5705                              struct intel_crtc *crtc)
5706 {
5707         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5708         struct intel_crtc_state *crtc_state =
5709                 intel_atomic_get_new_crtc_state(state, crtc);
5710         const struct intel_plane_state *plane_state;
5711         struct intel_plane *plane;
5712         int ret, i;
5713
5714         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5715                 /*
5716                  * FIXME should perhaps check {old,new}_plane_crtc->hw.crtc
5717                  * instead but we don't populate that correctly for NV12 Y
5718                  * planes so for now hack this.
5719                  */
5720                 if (plane->pipe != crtc->pipe)
5721                         continue;
5722
5723                 if (DISPLAY_VER(dev_priv) >= 11)
5724                         ret = icl_build_plane_wm(crtc_state, plane_state);
5725                 else
5726                         ret = skl_build_plane_wm(crtc_state, plane_state);
5727                 if (ret)
5728                         return ret;
5729         }
5730
5731         crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw;
5732
5733         return 0;
5734 }
5735
5736 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
5737                                 i915_reg_t reg,
5738                                 const struct skl_ddb_entry *entry)
5739 {
5740         if (entry->end)
5741                 intel_de_write_fw(dev_priv, reg,
5742                                   (entry->end - 1) << 16 | entry->start);
5743         else
5744                 intel_de_write_fw(dev_priv, reg, 0);
5745 }
5746
5747 static void skl_write_wm_level(struct drm_i915_private *dev_priv,
5748                                i915_reg_t reg,
5749                                const struct skl_wm_level *level)
5750 {
5751         u32 val = 0;
5752
5753         if (level->enable)
5754                 val |= PLANE_WM_EN;
5755         if (level->ignore_lines)
5756                 val |= PLANE_WM_IGNORE_LINES;
5757         val |= level->blocks;
5758         val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
5759
5760         intel_de_write_fw(dev_priv, reg, val);
5761 }
5762
5763 void skl_write_plane_wm(struct intel_plane *plane,
5764                         const struct intel_crtc_state *crtc_state)
5765 {
5766         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5767         int level, max_level = ilk_wm_max_level(dev_priv);
5768         enum plane_id plane_id = plane->id;
5769         enum pipe pipe = plane->pipe;
5770         const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5771         const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
5772         const struct skl_ddb_entry *ddb_y =
5773                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5774         const struct skl_ddb_entry *ddb_uv =
5775                 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5776
5777         for (level = 0; level <= max_level; level++)
5778                 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5779                                    skl_plane_wm_level(pipe_wm, plane_id, level));
5780
5781         skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5782                            skl_plane_trans_wm(pipe_wm, plane_id));
5783
5784         if (HAS_HW_SAGV_WM(dev_priv)) {
5785                 skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
5786                                    &wm->sagv.wm0);
5787                 skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
5788                                    &wm->sagv.trans_wm);
5789         }
5790
5791         if (DISPLAY_VER(dev_priv) >= 11) {
5792                 skl_ddb_entry_write(dev_priv,
5793                                     PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5794                 return;
5795         }
5796
5797         if (wm->is_planar)
5798                 swap(ddb_y, ddb_uv);
5799
5800         skl_ddb_entry_write(dev_priv,
5801                             PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5802         skl_ddb_entry_write(dev_priv,
5803                             PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5804 }
5805
5806 void skl_write_cursor_wm(struct intel_plane *plane,
5807                          const struct intel_crtc_state *crtc_state)
5808 {
5809         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
5810         int level, max_level = ilk_wm_max_level(dev_priv);
5811         enum plane_id plane_id = plane->id;
5812         enum pipe pipe = plane->pipe;
5813         const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5814         const struct skl_ddb_entry *ddb =
5815                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5816
5817         for (level = 0; level <= max_level; level++)
5818                 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5819                                    skl_plane_wm_level(pipe_wm, plane_id, level));
5820
5821         skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe),
5822                            skl_plane_trans_wm(pipe_wm, plane_id));
5823
5824         if (HAS_HW_SAGV_WM(dev_priv)) {
5825                 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
5826
5827                 skl_write_wm_level(dev_priv, CUR_WM_SAGV(pipe),
5828                                    &wm->sagv.wm0);
5829                 skl_write_wm_level(dev_priv, CUR_WM_SAGV_TRANS(pipe),
5830                                    &wm->sagv.trans_wm);
5831         }
5832
5833         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5834 }
5835
5836 bool skl_wm_level_equals(const struct skl_wm_level *l1,
5837                          const struct skl_wm_level *l2)
5838 {
5839         return l1->enable == l2->enable &&
5840                 l1->ignore_lines == l2->ignore_lines &&
5841                 l1->lines == l2->lines &&
5842                 l1->blocks == l2->blocks;
5843 }
5844
5845 static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
5846                                 const struct skl_plane_wm *wm1,
5847                                 const struct skl_plane_wm *wm2)
5848 {
5849         int level, max_level = ilk_wm_max_level(dev_priv);
5850
5851         for (level = 0; level <= max_level; level++) {
5852                 /*
5853                  * We don't check uv_wm as the hardware doesn't actually
5854                  * use it. It only gets used for calculating the required
5855                  * ddb allocation.
5856                  */
5857                 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
5858                         return false;
5859         }
5860
5861         return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) &&
5862                 skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0) &&
5863                 skl_wm_level_equals(&wm1->sagv.trans_wm, &wm2->sagv.trans_wm);
5864 }
5865
5866 static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
5867                                     const struct skl_ddb_entry *b)
5868 {
5869         return a->start < b->end && b->start < a->end;
5870 }
5871
5872 static void skl_ddb_entry_union(struct skl_ddb_entry *a,
5873                                 const struct skl_ddb_entry *b)
5874 {
5875         if (a->end && b->end) {
5876                 a->start = min(a->start, b->start);
5877                 a->end = max(a->end, b->end);
5878         } else if (b->end) {
5879                 a->start = b->start;
5880                 a->end = b->end;
5881         }
5882 }
5883
5884 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
5885                                  const struct skl_ddb_entry *entries,
5886                                  int num_entries, int ignore_idx)
5887 {
5888         int i;
5889
5890         for (i = 0; i < num_entries; i++) {
5891                 if (i != ignore_idx &&
5892                     skl_ddb_entries_overlap(ddb, &entries[i]))
5893                         return true;
5894         }
5895
5896         return false;
5897 }
5898
5899 static int
5900 skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
5901                             struct intel_crtc_state *new_crtc_state)
5902 {
5903         struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state);
5904         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5905         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5906         struct intel_plane *plane;
5907
5908         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5909                 struct intel_plane_state *plane_state;
5910                 enum plane_id plane_id = plane->id;
5911
5912                 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5913                                         &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5914                     skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5915                                         &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5916                         continue;
5917
5918                 plane_state = intel_atomic_get_plane_state(state, plane);
5919                 if (IS_ERR(plane_state))
5920                         return PTR_ERR(plane_state);
5921
5922                 new_crtc_state->update_planes |= BIT(plane_id);
5923         }
5924
5925         return 0;
5926 }
5927
5928 static u8 intel_dbuf_enabled_slices(const struct intel_dbuf_state *dbuf_state)
5929 {
5930         struct drm_i915_private *dev_priv = to_i915(dbuf_state->base.state->base.dev);
5931         u8 enabled_slices;
5932         enum pipe pipe;
5933
5934         /*
5935          * FIXME: For now we always enable slice S1 as per
5936          * the Bspec display initialization sequence.
5937          */
5938         enabled_slices = BIT(DBUF_S1);
5939
5940         for_each_pipe(dev_priv, pipe)
5941                 enabled_slices |= dbuf_state->slices[pipe];
5942
5943         return enabled_slices;
5944 }
5945
5946 static int
5947 skl_compute_ddb(struct intel_atomic_state *state)
5948 {
5949         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5950         const struct intel_dbuf_state *old_dbuf_state;
5951         struct intel_dbuf_state *new_dbuf_state = NULL;
5952         const struct intel_crtc_state *old_crtc_state;
5953         struct intel_crtc_state *new_crtc_state;
5954         struct intel_crtc *crtc;
5955         int ret, i;
5956
5957         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5958                 new_dbuf_state = intel_atomic_get_dbuf_state(state);
5959                 if (IS_ERR(new_dbuf_state))
5960                         return PTR_ERR(new_dbuf_state);
5961
5962                 old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
5963                 break;
5964         }
5965
5966         if (!new_dbuf_state)
5967                 return 0;
5968
5969         new_dbuf_state->active_pipes =
5970                 intel_calc_active_pipes(state, old_dbuf_state->active_pipes);
5971
5972         if (old_dbuf_state->active_pipes != new_dbuf_state->active_pipes) {
5973                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
5974                 if (ret)
5975                         return ret;
5976         }
5977
5978         for_each_intel_crtc(&dev_priv->drm, crtc) {
5979                 enum pipe pipe = crtc->pipe;
5980
5981                 new_dbuf_state->slices[pipe] =
5982                         skl_compute_dbuf_slices(crtc, new_dbuf_state->active_pipes);
5983
5984                 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe])
5985                         continue;
5986
5987                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
5988                 if (ret)
5989                         return ret;
5990         }
5991
5992         new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state);
5993
5994         if (IS_ALDERLAKE_P(dev_priv))
5995                 new_dbuf_state->joined_mbus = adlp_check_mbus_joined(new_dbuf_state->active_pipes);
5996
5997         if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||
5998             old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
5999                 ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
6000                 if (ret)
6001                         return ret;
6002
6003                 if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
6004                         /* TODO: Implement vblank synchronized MBUS joining changes */
6005                         ret = intel_modeset_all_pipes(state);
6006                         if (ret)
6007                                 return ret;
6008                 }
6009
6010                 drm_dbg_kms(&dev_priv->drm,
6011                             "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
6012                             old_dbuf_state->enabled_slices,
6013                             new_dbuf_state->enabled_slices,
6014                             INTEL_INFO(dev_priv)->dbuf.slice_mask,
6015                             yesno(old_dbuf_state->joined_mbus),
6016                             yesno(new_dbuf_state->joined_mbus));
6017         }
6018
6019         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6020                 enum pipe pipe = crtc->pipe;
6021
6022                 new_dbuf_state->weight[pipe] = intel_crtc_ddb_weight(new_crtc_state);
6023
6024                 if (old_dbuf_state->weight[pipe] == new_dbuf_state->weight[pipe])
6025                         continue;
6026
6027                 ret = intel_atomic_lock_global_state(&new_dbuf_state->base);
6028                 if (ret)
6029                         return ret;
6030         }
6031
6032         for_each_intel_crtc(&dev_priv->drm, crtc) {
6033                 ret = skl_crtc_allocate_ddb(state, crtc);
6034                 if (ret)
6035                         return ret;
6036         }
6037
6038         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6039                                             new_crtc_state, i) {
6040                 ret = skl_allocate_plane_ddb(state, crtc);
6041                 if (ret)
6042                         return ret;
6043
6044                 ret = skl_ddb_add_affected_planes(old_crtc_state,
6045                                                   new_crtc_state);
6046                 if (ret)
6047                         return ret;
6048         }
6049
6050         return 0;
6051 }
6052
6053 static char enast(bool enable)
6054 {
6055         return enable ? '*' : ' ';
6056 }
6057
6058 static void
6059 skl_print_wm_changes(struct intel_atomic_state *state)
6060 {
6061         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6062         const struct intel_crtc_state *old_crtc_state;
6063         const struct intel_crtc_state *new_crtc_state;
6064         struct intel_plane *plane;
6065         struct intel_crtc *crtc;
6066         int i;
6067
6068         if (!drm_debug_enabled(DRM_UT_KMS))
6069                 return;
6070
6071         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6072                                             new_crtc_state, i) {
6073                 const struct skl_pipe_wm *old_pipe_wm, *new_pipe_wm;
6074
6075                 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
6076                 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
6077
6078                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6079                         enum plane_id plane_id = plane->id;
6080                         const struct skl_ddb_entry *old, *new;
6081
6082                         old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
6083                         new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
6084
6085                         if (skl_ddb_entry_equal(old, new))
6086                                 continue;
6087
6088                         drm_dbg_kms(&dev_priv->drm,
6089                                     "[PLANE:%d:%s] ddb (%4d - %4d) -> (%4d - %4d), size %4d -> %4d\n",
6090                                     plane->base.base.id, plane->base.name,
6091                                     old->start, old->end, new->start, new->end,
6092                                     skl_ddb_entry_size(old), skl_ddb_entry_size(new));
6093                 }
6094
6095                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6096                         enum plane_id plane_id = plane->id;
6097                         const struct skl_plane_wm *old_wm, *new_wm;
6098
6099                         old_wm = &old_pipe_wm->planes[plane_id];
6100                         new_wm = &new_pipe_wm->planes[plane_id];
6101
6102                         if (skl_plane_wm_equals(dev_priv, old_wm, new_wm))
6103                                 continue;
6104
6105                         drm_dbg_kms(&dev_priv->drm,
6106                                     "[PLANE:%d:%s]   level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
6107                                     " -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
6108                                     plane->base.base.id, plane->base.name,
6109                                     enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
6110                                     enast(old_wm->wm[2].enable), enast(old_wm->wm[3].enable),
6111                                     enast(old_wm->wm[4].enable), enast(old_wm->wm[5].enable),
6112                                     enast(old_wm->wm[6].enable), enast(old_wm->wm[7].enable),
6113                                     enast(old_wm->trans_wm.enable),
6114                                     enast(old_wm->sagv.wm0.enable),
6115                                     enast(old_wm->sagv.trans_wm.enable),
6116                                     enast(new_wm->wm[0].enable), enast(new_wm->wm[1].enable),
6117                                     enast(new_wm->wm[2].enable), enast(new_wm->wm[3].enable),
6118                                     enast(new_wm->wm[4].enable), enast(new_wm->wm[5].enable),
6119                                     enast(new_wm->wm[6].enable), enast(new_wm->wm[7].enable),
6120                                     enast(new_wm->trans_wm.enable),
6121                                     enast(new_wm->sagv.wm0.enable),
6122                                     enast(new_wm->sagv.trans_wm.enable));
6123
6124                         drm_dbg_kms(&dev_priv->drm,
6125                                     "[PLANE:%d:%s]   lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
6126                                       " -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
6127                                     plane->base.base.id, plane->base.name,
6128                                     enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
6129                                     enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].lines,
6130                                     enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].lines,
6131                                     enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].lines,
6132                                     enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].lines,
6133                                     enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].lines,
6134                                     enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].lines,
6135                                     enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].lines,
6136                                     enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.lines,
6137                                     enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.lines,
6138                                     enast(old_wm->sagv.trans_wm.ignore_lines), old_wm->sagv.trans_wm.lines,
6139                                     enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].lines,
6140                                     enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].lines,
6141                                     enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].lines,
6142                                     enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].lines,
6143                                     enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].lines,
6144                                     enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].lines,
6145                                     enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].lines,
6146                                     enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].lines,
6147                                     enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.lines,
6148                                     enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.lines,
6149                                     enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
6150
6151                         drm_dbg_kms(&dev_priv->drm,
6152                                     "[PLANE:%d:%s]  blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
6153                                     " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
6154                                     plane->base.base.id, plane->base.name,
6155                                     old_wm->wm[0].blocks, old_wm->wm[1].blocks,
6156                                     old_wm->wm[2].blocks, old_wm->wm[3].blocks,
6157                                     old_wm->wm[4].blocks, old_wm->wm[5].blocks,
6158                                     old_wm->wm[6].blocks, old_wm->wm[7].blocks,
6159                                     old_wm->trans_wm.blocks,
6160                                     old_wm->sagv.wm0.blocks,
6161                                     old_wm->sagv.trans_wm.blocks,
6162                                     new_wm->wm[0].blocks, new_wm->wm[1].blocks,
6163                                     new_wm->wm[2].blocks, new_wm->wm[3].blocks,
6164                                     new_wm->wm[4].blocks, new_wm->wm[5].blocks,
6165                                     new_wm->wm[6].blocks, new_wm->wm[7].blocks,
6166                                     new_wm->trans_wm.blocks,
6167                                     new_wm->sagv.wm0.blocks,
6168                                     new_wm->sagv.trans_wm.blocks);
6169
6170                         drm_dbg_kms(&dev_priv->drm,
6171                                     "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
6172                                     " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
6173                                     plane->base.base.id, plane->base.name,
6174                                     old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
6175                                     old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
6176                                     old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
6177                                     old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
6178                                     old_wm->trans_wm.min_ddb_alloc,
6179                                     old_wm->sagv.wm0.min_ddb_alloc,
6180                                     old_wm->sagv.trans_wm.min_ddb_alloc,
6181                                     new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
6182                                     new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
6183                                     new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
6184                                     new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
6185                                     new_wm->trans_wm.min_ddb_alloc,
6186                                     new_wm->sagv.wm0.min_ddb_alloc,
6187                                     new_wm->sagv.trans_wm.min_ddb_alloc);
6188                 }
6189         }
6190 }
6191
6192 static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
6193                                          const struct skl_pipe_wm *old_pipe_wm,
6194                                          const struct skl_pipe_wm *new_pipe_wm)
6195 {
6196         struct drm_i915_private *i915 = to_i915(plane->base.dev);
6197         int level, max_level = ilk_wm_max_level(i915);
6198
6199         for (level = 0; level <= max_level; level++) {
6200                 /*
6201                  * We don't check uv_wm as the hardware doesn't actually
6202                  * use it. It only gets used for calculating the required
6203                  * ddb allocation.
6204                  */
6205                 if (!skl_wm_level_equals(skl_plane_wm_level(old_pipe_wm, plane->id, level),
6206                                          skl_plane_wm_level(new_pipe_wm, plane->id, level)))
6207                         return false;
6208         }
6209
6210         if (HAS_HW_SAGV_WM(i915)) {
6211                 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
6212                 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
6213
6214                 if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||
6215                     !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm))
6216                         return false;
6217         }
6218
6219         return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),
6220                                    skl_plane_trans_wm(new_pipe_wm, plane->id));
6221 }
6222
6223 /*
6224  * To make sure the cursor watermark registers are always consistent
6225  * with our computed state the following scenario needs special
6226  * treatment:
6227  *
6228  * 1. enable cursor
6229  * 2. move cursor entirely offscreen
6230  * 3. disable cursor
6231  *
6232  * Step 2. does call .disable_plane() but does not zero the watermarks
6233  * (since we consider an offscreen cursor still active for the purposes
6234  * of watermarks). Step 3. would not normally call .disable_plane()
6235  * because the actual plane visibility isn't changing, and we don't
6236  * deallocate the cursor ddb until the pipe gets disabled. So we must
6237  * force step 3. to call .disable_plane() to update the watermark
6238  * registers properly.
6239  *
6240  * Other planes do not suffer from this issues as their watermarks are
6241  * calculated based on the actual plane visibility. The only time this
6242  * can trigger for the other planes is during the initial readout as the
6243  * default value of the watermarks registers is not zero.
6244  */
6245 static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
6246                                       struct intel_crtc *crtc)
6247 {
6248         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6249         const struct intel_crtc_state *old_crtc_state =
6250                 intel_atomic_get_old_crtc_state(state, crtc);
6251         struct intel_crtc_state *new_crtc_state =
6252                 intel_atomic_get_new_crtc_state(state, crtc);
6253         struct intel_plane *plane;
6254
6255         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6256                 struct intel_plane_state *plane_state;
6257                 enum plane_id plane_id = plane->id;
6258
6259                 /*
6260                  * Force a full wm update for every plane on modeset.
6261                  * Required because the reset value of the wm registers
6262                  * is non-zero, whereas we want all disabled planes to
6263                  * have zero watermarks. So if we turn off the relevant
6264                  * power well the hardware state will go out of sync
6265                  * with the software state.
6266                  */
6267                 if (!drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi) &&
6268                     skl_plane_selected_wm_equals(plane,
6269                                                  &old_crtc_state->wm.skl.optimal,
6270                                                  &new_crtc_state->wm.skl.optimal))
6271                         continue;
6272
6273                 plane_state = intel_atomic_get_plane_state(state, plane);
6274                 if (IS_ERR(plane_state))
6275                         return PTR_ERR(plane_state);
6276
6277                 new_crtc_state->update_planes |= BIT(plane_id);
6278         }
6279
6280         return 0;
6281 }
6282
6283 static int
6284 skl_compute_wm(struct intel_atomic_state *state)
6285 {
6286         struct intel_crtc *crtc;
6287         struct intel_crtc_state *new_crtc_state;
6288         int ret, i;
6289
6290         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6291                 ret = skl_build_pipe_wm(state, crtc);
6292                 if (ret)
6293                         return ret;
6294         }
6295
6296         ret = skl_compute_ddb(state);
6297         if (ret)
6298                 return ret;
6299
6300         ret = intel_compute_sagv_mask(state);
6301         if (ret)
6302                 return ret;
6303
6304         /*
6305          * skl_compute_ddb() will have adjusted the final watermarks
6306          * based on how much ddb is available. Now we can actually
6307          * check if the final watermarks changed.
6308          */
6309         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6310                 ret = skl_wm_add_affected_planes(state, crtc);
6311                 if (ret)
6312                         return ret;
6313         }
6314
6315         skl_print_wm_changes(state);
6316
6317         return 0;
6318 }
6319
6320 static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
6321                                   struct intel_wm_config *config)
6322 {
6323         struct intel_crtc *crtc;
6324
6325         /* Compute the currently _active_ config */
6326         for_each_intel_crtc(&dev_priv->drm, crtc) {
6327                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
6328
6329                 if (!wm->pipe_enabled)
6330                         continue;
6331
6332                 config->sprites_enabled |= wm->sprites_enabled;
6333                 config->sprites_scaled |= wm->sprites_scaled;
6334                 config->num_pipes_active++;
6335         }
6336 }
6337
6338 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
6339 {
6340         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
6341         struct ilk_wm_maximums max;
6342         struct intel_wm_config config = {};
6343         struct ilk_wm_values results = {};
6344         enum intel_ddb_partitioning partitioning;
6345
6346         ilk_compute_wm_config(dev_priv, &config);
6347
6348         ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
6349         ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
6350
6351         /* 5/6 split only in single pipe config on IVB+ */
6352         if (DISPLAY_VER(dev_priv) >= 7 &&
6353             config.num_pipes_active == 1 && config.sprites_enabled) {
6354                 ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
6355                 ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
6356
6357                 best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
6358         } else {
6359                 best_lp_wm = &lp_wm_1_2;
6360         }
6361
6362         partitioning = (best_lp_wm == &lp_wm_1_2) ?
6363                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
6364
6365         ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
6366
6367         ilk_write_wm_values(dev_priv, &results);
6368 }
6369
6370 static void ilk_initial_watermarks(struct intel_atomic_state *state,
6371                                    struct intel_crtc *crtc)
6372 {
6373         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6374         const struct intel_crtc_state *crtc_state =
6375                 intel_atomic_get_new_crtc_state(state, crtc);
6376
6377         mutex_lock(&dev_priv->wm.wm_mutex);
6378         crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
6379         ilk_program_watermarks(dev_priv);
6380         mutex_unlock(&dev_priv->wm.wm_mutex);
6381 }
6382
6383 static void ilk_optimize_watermarks(struct intel_atomic_state *state,
6384                                     struct intel_crtc *crtc)
6385 {
6386         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6387         const struct intel_crtc_state *crtc_state =
6388                 intel_atomic_get_new_crtc_state(state, crtc);
6389
6390         if (!crtc_state->wm.need_postvbl_update)
6391                 return;
6392
6393         mutex_lock(&dev_priv->wm.wm_mutex);
6394         crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
6395         ilk_program_watermarks(dev_priv);
6396         mutex_unlock(&dev_priv->wm.wm_mutex);
6397 }
6398
6399 static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
6400 {
6401         level->enable = val & PLANE_WM_EN;
6402         level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
6403         level->blocks = val & PLANE_WM_BLOCKS_MASK;
6404         level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
6405 }
6406
6407 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
6408                               struct skl_pipe_wm *out)
6409 {
6410         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6411         enum pipe pipe = crtc->pipe;
6412         int level, max_level;
6413         enum plane_id plane_id;
6414         u32 val;
6415
6416         max_level = ilk_wm_max_level(dev_priv);
6417
6418         for_each_plane_id_on_crtc(crtc, plane_id) {
6419                 struct skl_plane_wm *wm = &out->planes[plane_id];
6420
6421                 for (level = 0; level <= max_level; level++) {
6422                         if (plane_id != PLANE_CURSOR)
6423                                 val = intel_uncore_read(&dev_priv->uncore, PLANE_WM(pipe, plane_id, level));
6424                         else
6425                                 val = intel_uncore_read(&dev_priv->uncore, CUR_WM(pipe, level));
6426
6427                         skl_wm_level_from_reg_val(val, &wm->wm[level]);
6428                 }
6429
6430                 if (plane_id != PLANE_CURSOR)
6431                         val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
6432                 else
6433                         val = intel_uncore_read(&dev_priv->uncore, CUR_WM_TRANS(pipe));
6434
6435                 skl_wm_level_from_reg_val(val, &wm->trans_wm);
6436
6437                 if (HAS_HW_SAGV_WM(dev_priv)) {
6438                         if (plane_id != PLANE_CURSOR)
6439                                 val = intel_uncore_read(&dev_priv->uncore,
6440                                                         PLANE_WM_SAGV(pipe, plane_id));
6441                         else
6442                                 val = intel_uncore_read(&dev_priv->uncore,
6443                                                         CUR_WM_SAGV(pipe));
6444
6445                         skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
6446
6447                         if (plane_id != PLANE_CURSOR)
6448                                 val = intel_uncore_read(&dev_priv->uncore,
6449                                                         PLANE_WM_SAGV_TRANS(pipe, plane_id));
6450                         else
6451                                 val = intel_uncore_read(&dev_priv->uncore,
6452                                                         CUR_WM_SAGV_TRANS(pipe));
6453
6454                         skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
6455                 } else if (DISPLAY_VER(dev_priv) >= 12) {
6456                         wm->sagv.wm0 = wm->wm[0];
6457                         wm->sagv.trans_wm = wm->trans_wm;
6458                 }
6459         }
6460 }
6461
6462 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
6463 {
6464         struct intel_dbuf_state *dbuf_state =
6465                 to_intel_dbuf_state(dev_priv->dbuf.obj.state);
6466         struct intel_crtc *crtc;
6467
6468         if (IS_ALDERLAKE_P(dev_priv))
6469                 dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
6470
6471         for_each_intel_crtc(&dev_priv->drm, crtc) {
6472                 struct intel_crtc_state *crtc_state =
6473                         to_intel_crtc_state(crtc->base.state);
6474                 enum pipe pipe = crtc->pipe;
6475                 unsigned int mbus_offset;
6476                 enum plane_id plane_id;
6477
6478                 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
6479                 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal;
6480
6481                 memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe]));
6482
6483                 for_each_plane_id_on_crtc(crtc, plane_id) {
6484                         struct skl_ddb_entry *ddb_y =
6485                                 &crtc_state->wm.skl.plane_ddb_y[plane_id];
6486                         struct skl_ddb_entry *ddb_uv =
6487                                 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
6488
6489                         skl_ddb_get_hw_plane_state(dev_priv, crtc->pipe,
6490                                                    plane_id, ddb_y, ddb_uv);
6491
6492                         skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_y);
6493                         skl_ddb_entry_union(&dbuf_state->ddb[pipe], ddb_uv);
6494                 }
6495
6496                 dbuf_state->slices[pipe] =
6497                         skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes);
6498
6499                 dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
6500
6501                 /*
6502                  * Used for checking overlaps, so we need absolute
6503                  * offsets instead of MBUS relative offsets.
6504                  */
6505                 mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
6506                 crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
6507                 crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
6508
6509                 drm_dbg_kms(&dev_priv->drm,
6510                             "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
6511                             crtc->base.base.id, crtc->base.name,
6512                             dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
6513                             dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,
6514                             yesno(dbuf_state->joined_mbus));
6515         }
6516
6517         dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
6518 }
6519
6520 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
6521 {
6522         struct drm_device *dev = crtc->base.dev;
6523         struct drm_i915_private *dev_priv = to_i915(dev);
6524         struct ilk_wm_values *hw = &dev_priv->wm.hw;
6525         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
6526         struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
6527         enum pipe pipe = crtc->pipe;
6528
6529         hw->wm_pipe[pipe] = intel_uncore_read(&dev_priv->uncore, WM0_PIPE_ILK(pipe));
6530
6531         memset(active, 0, sizeof(*active));
6532
6533         active->pipe_enabled = crtc->active;
6534
6535         if (active->pipe_enabled) {
6536                 u32 tmp = hw->wm_pipe[pipe];
6537
6538                 /*
6539                  * For active pipes LP0 watermark is marked as
6540                  * enabled, and LP1+ watermaks as disabled since
6541                  * we can't really reverse compute them in case
6542                  * multiple pipes are active.
6543                  */
6544                 active->wm[0].enable = true;
6545                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
6546                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
6547                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
6548         } else {
6549                 int level, max_level = ilk_wm_max_level(dev_priv);
6550
6551                 /*
6552                  * For inactive pipes, all watermark levels
6553                  * should be marked as enabled but zeroed,
6554                  * which is what we'd compute them to.
6555                  */
6556                 for (level = 0; level <= max_level; level++)
6557                         active->wm[level].enable = true;
6558         }
6559
6560         crtc->wm.active.ilk = *active;
6561 }
6562
6563 #define _FW_WM(value, plane) \
6564         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
6565 #define _FW_WM_VLV(value, plane) \
6566         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
6567
6568 static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
6569                                struct g4x_wm_values *wm)
6570 {
6571         u32 tmp;
6572
6573         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
6574         wm->sr.plane = _FW_WM(tmp, SR);
6575         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6576         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6577         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6578
6579         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
6580         wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
6581         wm->sr.fbc = _FW_WM(tmp, FBC_SR);
6582         wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
6583         wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6584         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6585         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6586
6587         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
6588         wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
6589         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6590         wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
6591         wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
6592 }
6593
6594 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
6595                                struct vlv_wm_values *wm)
6596 {
6597         enum pipe pipe;
6598         u32 tmp;
6599
6600         for_each_pipe(dev_priv, pipe) {
6601                 tmp = intel_uncore_read(&dev_priv->uncore, VLV_DDL(pipe));
6602
6603                 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6604                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6605                 wm->ddl[pipe].plane[PLANE_CURSOR] =
6606                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6607                 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6608                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6609                 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6610                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
6611         }
6612
6613         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1);
6614         wm->sr.plane = _FW_WM(tmp, SR);
6615         wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6616         wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6617         wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6618
6619         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
6620         wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6621         wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6622         wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6623
6624         tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3);
6625         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6626
6627         if (IS_CHERRYVIEW(dev_priv)) {
6628                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7_CHV);
6629                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6630                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6631
6632                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW8_CHV);
6633                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6634                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6635
6636                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW9_CHV);
6637                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6638                 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6639
6640                 tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
6641                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6642                 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6643                 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6644                 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6645                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6646                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6647                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6648                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6649                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6650                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6651         } else {
6652                 tmp = intel_uncore_read(&dev_priv->uncore, DSPFW7);
6653                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6654                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6655
6656                 tmp = intel_uncore_read(&dev_priv->uncore, DSPHOWM);
6657                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6658                 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6659                 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6660                 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6661                 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6662                 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6663                 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6664         }
6665 }
6666
6667 #undef _FW_WM
6668 #undef _FW_WM_VLV
6669
6670 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
6671 {
6672         struct g4x_wm_values *wm = &dev_priv->wm.g4x;
6673         struct intel_crtc *crtc;
6674
6675         g4x_read_wm_values(dev_priv, wm);
6676
6677         wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN;
6678
6679         for_each_intel_crtc(&dev_priv->drm, crtc) {
6680                 struct intel_crtc_state *crtc_state =
6681                         to_intel_crtc_state(crtc->base.state);
6682                 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6683                 struct g4x_pipe_wm *raw;
6684                 enum pipe pipe = crtc->pipe;
6685                 enum plane_id plane_id;
6686                 int level, max_level;
6687
6688                 active->cxsr = wm->cxsr;
6689                 active->hpll_en = wm->hpll_en;
6690                 active->fbc_en = wm->fbc_en;
6691
6692                 active->sr = wm->sr;
6693                 active->hpll = wm->hpll;
6694
6695                 for_each_plane_id_on_crtc(crtc, plane_id) {
6696                         active->wm.plane[plane_id] =
6697                                 wm->pipe[pipe].plane[plane_id];
6698                 }
6699
6700                 if (wm->cxsr && wm->hpll_en)
6701                         max_level = G4X_WM_LEVEL_HPLL;
6702                 else if (wm->cxsr)
6703                         max_level = G4X_WM_LEVEL_SR;
6704                 else
6705                         max_level = G4X_WM_LEVEL_NORMAL;
6706
6707                 level = G4X_WM_LEVEL_NORMAL;
6708                 raw = &crtc_state->wm.g4x.raw[level];
6709                 for_each_plane_id_on_crtc(crtc, plane_id)
6710                         raw->plane[plane_id] = active->wm.plane[plane_id];
6711
6712                 if (++level > max_level)
6713                         goto out;
6714
6715                 raw = &crtc_state->wm.g4x.raw[level];
6716                 raw->plane[PLANE_PRIMARY] = active->sr.plane;
6717                 raw->plane[PLANE_CURSOR] = active->sr.cursor;
6718                 raw->plane[PLANE_SPRITE0] = 0;
6719                 raw->fbc = active->sr.fbc;
6720
6721                 if (++level > max_level)
6722                         goto out;
6723
6724                 raw = &crtc_state->wm.g4x.raw[level];
6725                 raw->plane[PLANE_PRIMARY] = active->hpll.plane;
6726                 raw->plane[PLANE_CURSOR] = active->hpll.cursor;
6727                 raw->plane[PLANE_SPRITE0] = 0;
6728                 raw->fbc = active->hpll.fbc;
6729
6730         out:
6731                 for_each_plane_id_on_crtc(crtc, plane_id)
6732                         g4x_raw_plane_wm_set(crtc_state, level,
6733                                              plane_id, USHRT_MAX);
6734                 g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
6735
6736                 crtc_state->wm.g4x.optimal = *active;
6737                 crtc_state->wm.g4x.intermediate = *active;
6738
6739                 drm_dbg_kms(&dev_priv->drm,
6740                             "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6741                             pipe_name(pipe),
6742                             wm->pipe[pipe].plane[PLANE_PRIMARY],
6743                             wm->pipe[pipe].plane[PLANE_CURSOR],
6744                             wm->pipe[pipe].plane[PLANE_SPRITE0]);
6745         }
6746
6747         drm_dbg_kms(&dev_priv->drm,
6748                     "Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n",
6749                     wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6750         drm_dbg_kms(&dev_priv->drm,
6751                     "Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n",
6752                     wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6753         drm_dbg_kms(&dev_priv->drm, "Initial SR=%s HPLL=%s FBC=%s\n",
6754                     yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6755 }
6756
6757 void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
6758 {
6759         struct intel_plane *plane;
6760         struct intel_crtc *crtc;
6761
6762         mutex_lock(&dev_priv->wm.wm_mutex);
6763
6764         for_each_intel_plane(&dev_priv->drm, plane) {
6765                 struct intel_crtc *crtc =
6766                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6767                 struct intel_crtc_state *crtc_state =
6768                         to_intel_crtc_state(crtc->base.state);
6769                 struct intel_plane_state *plane_state =
6770                         to_intel_plane_state(plane->base.state);
6771                 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6772                 enum plane_id plane_id = plane->id;
6773                 int level;
6774
6775                 if (plane_state->uapi.visible)
6776                         continue;
6777
6778                 for (level = 0; level < 3; level++) {
6779                         struct g4x_pipe_wm *raw =
6780                                 &crtc_state->wm.g4x.raw[level];
6781
6782                         raw->plane[plane_id] = 0;
6783                         wm_state->wm.plane[plane_id] = 0;
6784                 }
6785
6786                 if (plane_id == PLANE_PRIMARY) {
6787                         for (level = 0; level < 3; level++) {
6788                                 struct g4x_pipe_wm *raw =
6789                                         &crtc_state->wm.g4x.raw[level];
6790                                 raw->fbc = 0;
6791                         }
6792
6793                         wm_state->sr.fbc = 0;
6794                         wm_state->hpll.fbc = 0;
6795                         wm_state->fbc_en = false;
6796                 }
6797         }
6798
6799         for_each_intel_crtc(&dev_priv->drm, crtc) {
6800                 struct intel_crtc_state *crtc_state =
6801                         to_intel_crtc_state(crtc->base.state);
6802
6803                 crtc_state->wm.g4x.intermediate =
6804                         crtc_state->wm.g4x.optimal;
6805                 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6806         }
6807
6808         g4x_program_watermarks(dev_priv);
6809
6810         mutex_unlock(&dev_priv->wm.wm_mutex);
6811 }
6812
6813 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
6814 {
6815         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6816         struct intel_crtc *crtc;
6817         u32 val;
6818
6819         vlv_read_wm_values(dev_priv, wm);
6820
6821         wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6822         wm->level = VLV_WM_LEVEL_PM2;
6823
6824         if (IS_CHERRYVIEW(dev_priv)) {
6825                 vlv_punit_get(dev_priv);
6826
6827                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
6828                 if (val & DSP_MAXFIFO_PM5_ENABLE)
6829                         wm->level = VLV_WM_LEVEL_PM5;
6830
6831                 /*
6832                  * If DDR DVFS is disabled in the BIOS, Punit
6833                  * will never ack the request. So if that happens
6834                  * assume we don't have to enable/disable DDR DVFS
6835                  * dynamically. To test that just set the REQ_ACK
6836                  * bit to poke the Punit, but don't change the
6837                  * HIGH/LOW bits so that we don't actually change
6838                  * the current state.
6839                  */
6840                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6841                 val |= FORCE_DDR_FREQ_REQ_ACK;
6842                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
6843
6844                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
6845                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
6846                         drm_dbg_kms(&dev_priv->drm,
6847                                     "Punit not acking DDR DVFS request, "
6848                                     "assuming DDR DVFS is disabled\n");
6849                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6850                 } else {
6851                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
6852                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
6853                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6854                 }
6855
6856                 vlv_punit_put(dev_priv);
6857         }
6858
6859         for_each_intel_crtc(&dev_priv->drm, crtc) {
6860                 struct intel_crtc_state *crtc_state =
6861                         to_intel_crtc_state(crtc->base.state);
6862                 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6863                 const struct vlv_fifo_state *fifo_state =
6864                         &crtc_state->wm.vlv.fifo_state;
6865                 enum pipe pipe = crtc->pipe;
6866                 enum plane_id plane_id;
6867                 int level;
6868
6869                 vlv_get_fifo_size(crtc_state);
6870
6871                 active->num_levels = wm->level + 1;
6872                 active->cxsr = wm->cxsr;
6873
6874                 for (level = 0; level < active->num_levels; level++) {
6875                         struct g4x_pipe_wm *raw =
6876                                 &crtc_state->wm.vlv.raw[level];
6877
6878                         active->sr[level].plane = wm->sr.plane;
6879                         active->sr[level].cursor = wm->sr.cursor;
6880
6881                         for_each_plane_id_on_crtc(crtc, plane_id) {
6882                                 active->wm[level].plane[plane_id] =
6883                                         wm->pipe[pipe].plane[plane_id];
6884
6885                                 raw->plane[plane_id] =
6886                                         vlv_invert_wm_value(active->wm[level].plane[plane_id],
6887                                                             fifo_state->plane[plane_id]);
6888                         }
6889                 }
6890
6891                 for_each_plane_id_on_crtc(crtc, plane_id)
6892                         vlv_raw_plane_wm_set(crtc_state, level,
6893                                              plane_id, USHRT_MAX);
6894                 vlv_invalidate_wms(crtc, active, level);
6895
6896                 crtc_state->wm.vlv.optimal = *active;
6897                 crtc_state->wm.vlv.intermediate = *active;
6898
6899                 drm_dbg_kms(&dev_priv->drm,
6900                             "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6901                             pipe_name(pipe),
6902                             wm->pipe[pipe].plane[PLANE_PRIMARY],
6903                             wm->pipe[pipe].plane[PLANE_CURSOR],
6904                             wm->pipe[pipe].plane[PLANE_SPRITE0],
6905                             wm->pipe[pipe].plane[PLANE_SPRITE1]);
6906         }
6907
6908         drm_dbg_kms(&dev_priv->drm,
6909                     "Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
6910                     wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
6911 }
6912
6913 void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
6914 {
6915         struct intel_plane *plane;
6916         struct intel_crtc *crtc;
6917
6918         mutex_lock(&dev_priv->wm.wm_mutex);
6919
6920         for_each_intel_plane(&dev_priv->drm, plane) {
6921                 struct intel_crtc *crtc =
6922                         intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6923                 struct intel_crtc_state *crtc_state =
6924                         to_intel_crtc_state(crtc->base.state);
6925                 struct intel_plane_state *plane_state =
6926                         to_intel_plane_state(plane->base.state);
6927                 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6928                 const struct vlv_fifo_state *fifo_state =
6929                         &crtc_state->wm.vlv.fifo_state;
6930                 enum plane_id plane_id = plane->id;
6931                 int level;
6932
6933                 if (plane_state->uapi.visible)
6934                         continue;
6935
6936                 for (level = 0; level < wm_state->num_levels; level++) {
6937                         struct g4x_pipe_wm *raw =
6938                                 &crtc_state->wm.vlv.raw[level];
6939
6940                         raw->plane[plane_id] = 0;
6941
6942                         wm_state->wm[level].plane[plane_id] =
6943                                 vlv_invert_wm_value(raw->plane[plane_id],
6944                                                     fifo_state->plane[plane_id]);
6945                 }
6946         }
6947
6948         for_each_intel_crtc(&dev_priv->drm, crtc) {
6949                 struct intel_crtc_state *crtc_state =
6950                         to_intel_crtc_state(crtc->base.state);
6951
6952                 crtc_state->wm.vlv.intermediate =
6953                         crtc_state->wm.vlv.optimal;
6954                 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6955         }
6956
6957         vlv_program_watermarks(dev_priv);
6958
6959         mutex_unlock(&dev_priv->wm.wm_mutex);
6960 }
6961
6962 /*
6963  * FIXME should probably kill this and improve
6964  * the real watermark readout/sanitation instead
6965  */
6966 static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
6967 {
6968         intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK) & ~WM1_LP_SR_EN);
6969         intel_uncore_write(&dev_priv->uncore, WM2_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK) & ~WM1_LP_SR_EN);
6970         intel_uncore_write(&dev_priv->uncore, WM1_LP_ILK, intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK) & ~WM1_LP_SR_EN);
6971
6972         /*
6973          * Don't touch WM1S_LP_EN here.
6974          * Doing so could cause underruns.
6975          */
6976 }
6977
6978 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
6979 {
6980         struct ilk_wm_values *hw = &dev_priv->wm.hw;
6981         struct intel_crtc *crtc;
6982
6983         ilk_init_lp_watermarks(dev_priv);
6984
6985         for_each_intel_crtc(&dev_priv->drm, crtc)
6986                 ilk_pipe_wm_get_hw_state(crtc);
6987
6988         hw->wm_lp[0] = intel_uncore_read(&dev_priv->uncore, WM1_LP_ILK);
6989         hw->wm_lp[1] = intel_uncore_read(&dev_priv->uncore, WM2_LP_ILK);
6990         hw->wm_lp[2] = intel_uncore_read(&dev_priv->uncore, WM3_LP_ILK);
6991
6992         hw->wm_lp_spr[0] = intel_uncore_read(&dev_priv->uncore, WM1S_LP_ILK);
6993         if (DISPLAY_VER(dev_priv) >= 7) {
6994                 hw->wm_lp_spr[1] = intel_uncore_read(&dev_priv->uncore, WM2S_LP_IVB);
6995                 hw->wm_lp_spr[2] = intel_uncore_read(&dev_priv->uncore, WM3S_LP_IVB);
6996         }
6997
6998         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6999                 hw->partitioning = (intel_uncore_read(&dev_priv->uncore, WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
7000                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
7001         else if (IS_IVYBRIDGE(dev_priv))
7002                 hw->partitioning = (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
7003                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
7004
7005         hw->enable_fbc_wm =
7006                 !(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
7007 }
7008
7009 /**
7010  * intel_update_watermarks - update FIFO watermark values based on current modes
7011  * @crtc: the #intel_crtc on which to compute the WM
7012  *
7013  * Calculate watermark values for the various WM regs based on current mode
7014  * and plane configuration.
7015  *
7016  * There are several cases to deal with here:
7017  *   - normal (i.e. non-self-refresh)
7018  *   - self-refresh (SR) mode
7019  *   - lines are large relative to FIFO size (buffer can hold up to 2)
7020  *   - lines are small relative to FIFO size (buffer can hold more than 2
7021  *     lines), so need to account for TLB latency
7022  *
7023  *   The normal calculation is:
7024  *     watermark = dotclock * bytes per pixel * latency
7025  *   where latency is platform & configuration dependent (we assume pessimal
7026  *   values here).
7027  *
7028  *   The SR calculation is:
7029  *     watermark = (trunc(latency/line time)+1) * surface width *
7030  *       bytes per pixel
7031  *   where
7032  *     line time = htotal / dotclock
7033  *     surface width = hdisplay for normal plane and 64 for cursor
7034  *   and latency is assumed to be high, as above.
7035  *
7036  * The final value programmed to the register should always be rounded up,
7037  * and include an extra 2 entries to account for clock crossings.
7038  *
7039  * We don't use the sprite, so we can ignore that.  And on Crestline we have
7040  * to set the non-SR watermarks to 8.
7041  */
7042 void intel_update_watermarks(struct intel_crtc *crtc)
7043 {
7044         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7045
7046         if (dev_priv->display.update_wm)
7047                 dev_priv->display.update_wm(crtc);
7048 }
7049
7050 void intel_enable_ipc(struct drm_i915_private *dev_priv)
7051 {
7052         u32 val;
7053
7054         if (!HAS_IPC(dev_priv))
7055                 return;
7056
7057         val = intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL2);
7058
7059         if (dev_priv->ipc_enabled)
7060                 val |= DISP_IPC_ENABLE;
7061         else
7062                 val &= ~DISP_IPC_ENABLE;
7063
7064         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL2, val);
7065 }
7066
7067 static bool intel_can_enable_ipc(struct drm_i915_private *dev_priv)
7068 {
7069         /* Display WA #0477 WaDisableIPC: skl */
7070         if (IS_SKYLAKE(dev_priv))
7071                 return false;
7072
7073         /* Display WA #1141: SKL:all KBL:all CFL */
7074         if (IS_KABYLAKE(dev_priv) ||
7075             IS_COFFEELAKE(dev_priv) ||
7076             IS_COMETLAKE(dev_priv))
7077                 return dev_priv->dram_info.symmetric_memory;
7078
7079         return true;
7080 }
7081
7082 void intel_init_ipc(struct drm_i915_private *dev_priv)
7083 {
7084         if (!HAS_IPC(dev_priv))
7085                 return;
7086
7087         dev_priv->ipc_enabled = intel_can_enable_ipc(dev_priv);
7088
7089         intel_enable_ipc(dev_priv);
7090 }
7091
7092 static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
7093 {
7094         /*
7095          * On Ibex Peak and Cougar Point, we need to disable clock
7096          * gating for the panel power sequencer or it will fail to
7097          * start up when no ports are active.
7098          */
7099         intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7100 }
7101
7102 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
7103 {
7104         enum pipe pipe;
7105
7106         for_each_pipe(dev_priv, pipe) {
7107                 intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
7108                            intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
7109                            DISPPLANE_TRICKLE_FEED_DISABLE);
7110
7111                 intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
7112                 intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
7113         }
7114 }
7115
7116 static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
7117 {
7118         u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7119
7120         /*
7121          * Required for FBC
7122          * WaFbcDisableDpfcClockGating:ilk
7123          */
7124         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
7125                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
7126                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
7127
7128         intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
7129                    MARIUNIT_CLOCK_GATE_DISABLE |
7130                    SVSMUNIT_CLOCK_GATE_DISABLE);
7131         intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
7132                    VFMUNIT_CLOCK_GATE_DISABLE);
7133
7134         /*
7135          * According to the spec the following bits should be set in
7136          * order to enable memory self-refresh
7137          * The bit 22/21 of 0x42004
7138          * The bit 5 of 0x42020
7139          * The bit 15 of 0x45000
7140          */
7141         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7142                    (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7143                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7144         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
7145         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
7146                    (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7147                     DISP_FBC_WM_DIS));
7148
7149         /*
7150          * Based on the document from hardware guys the following bits
7151          * should be set unconditionally in order to enable FBC.
7152          * The bit 22 of 0x42000
7153          * The bit 22 of 0x42004
7154          * The bit 7,8,9 of 0x42020.
7155          */
7156         if (IS_IRONLAKE_M(dev_priv)) {
7157                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
7158                 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
7159                            intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
7160                            ILK_FBCQ_DIS);
7161                 intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7162                            intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7163                            ILK_DPARB_GATE);
7164         }
7165
7166         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
7167
7168         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7169                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7170                    ILK_ELPIN_409_SELECT);
7171
7172         g4x_disable_trickle_feed(dev_priv);
7173
7174         ibx_init_clock_gating(dev_priv);
7175 }
7176
7177 static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
7178 {
7179         enum pipe pipe;
7180         u32 val;
7181
7182         /*
7183          * On Ibex Peak and Cougar Point, we need to disable clock
7184          * gating for the panel power sequencer or it will fail to
7185          * start up when no ports are active.
7186          */
7187         intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
7188                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
7189                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
7190         intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN2, intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN2) |
7191                    DPLS_EDP_PPS_FIX_DIS);
7192         /* The below fixes the weird display corruption, a few pixels shifted
7193          * downward, on (only) LVDS of some HP laptops with IVY.
7194          */
7195         for_each_pipe(dev_priv, pipe) {
7196                 val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
7197                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7198                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7199                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
7200                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
7201                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7202                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
7203                 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
7204         }
7205         /* WADP0ClockGatingDisable */
7206         for_each_pipe(dev_priv, pipe) {
7207                 intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
7208                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7209         }
7210 }
7211
7212 static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
7213 {
7214         u32 tmp;
7215
7216         tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
7217         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7218                 drm_dbg_kms(&dev_priv->drm,
7219                             "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7220                             tmp);
7221 }
7222
7223 static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
7224 {
7225         u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
7226
7227         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
7228
7229         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7230                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7231                    ILK_ELPIN_409_SELECT);
7232
7233         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
7234                    intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
7235                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7236                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7237
7238         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7239          * gating disable must be set.  Failure to set it results in
7240          * flickering pixels due to Z write ordering failures after
7241          * some amount of runtime in the Mesa "fire" demo, and Unigine
7242          * Sanctuary and Tropics, and apparently anything else with
7243          * alpha test or pixel discard.
7244          *
7245          * According to the spec, bit 11 (RCCUNIT) must also be set,
7246          * but we didn't debug actual testcases to find it out.
7247          *
7248          * WaDisableRCCUnitClockGating:snb
7249          * WaDisableRCPBUnitClockGating:snb
7250          */
7251         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
7252                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7253                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7254
7255         /*
7256          * According to the spec the following bits should be
7257          * set in order to enable memory self-refresh and fbc:
7258          * The bit21 and bit22 of 0x42000
7259          * The bit21 and bit22 of 0x42004
7260          * The bit5 and bit7 of 0x42020
7261          * The bit14 of 0x70180
7262          * The bit14 of 0x71180
7263          *
7264          * WaFbcAsynchFlipDisableFbcQueue:snb
7265          */
7266         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
7267                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
7268                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7269         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
7270                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
7271                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7272         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
7273                    intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
7274                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7275                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7276
7277         g4x_disable_trickle_feed(dev_priv);
7278
7279         cpt_init_clock_gating(dev_priv);
7280
7281         gen6_check_mch_setup(dev_priv);
7282 }
7283
7284 static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
7285 {
7286         /*
7287          * TODO: this bit should only be enabled when really needed, then
7288          * disabled when not needed anymore in order to save power.
7289          */
7290         if (HAS_PCH_LPT_LP(dev_priv))
7291                 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
7292                            intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
7293                            PCH_LP_PARTITION_LEVEL_DISABLE);
7294
7295         /* WADPOClockGatingDisable:hsw */
7296         intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
7297                    intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A)) |
7298                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7299 }
7300
7301 static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7302 {
7303         if (HAS_PCH_LPT_LP(dev_priv)) {
7304                 u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
7305
7306                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7307                 intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
7308         }
7309 }
7310
7311 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7312                                    int general_prio_credits,
7313                                    int high_prio_credits)
7314 {
7315         u32 misccpctl;
7316         u32 val;
7317
7318         /* WaTempDisableDOPClkGating:bdw */
7319         misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
7320         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7321
7322         val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
7323         val &= ~L3_PRIO_CREDITS_MASK;
7324         val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
7325         val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
7326         intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
7327
7328         /*
7329          * Wait at least 100 clocks before re-enabling clock gating.
7330          * See the definition of L3SQCREG1 in BSpec.
7331          */
7332         intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
7333         udelay(1);
7334         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
7335 }
7336
7337 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
7338 {
7339         /* Wa_1409120013:icl,ehl */
7340         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
7341                    ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7342
7343         /* This is not an Wa. Enable to reduce Sampler power */
7344         intel_uncore_write(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
7345                    intel_uncore_read(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
7346
7347         /*Wa_14010594013:icl, ehl */
7348         intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
7349                          0, CNL_DELAY_PMRSP);
7350 }
7351
7352 static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
7353 {
7354         /* Wa_1409120013:tgl,rkl,adl_s,dg1 */
7355         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN,
7356                            ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
7357
7358         /* Wa_1409825376:tgl (pre-prod)*/
7359         if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1))
7360                 intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
7361                            TGL_VRH_GATING_DIS);
7362
7363         /* Wa_14011059788:tgl,rkl,adl_s,dg1 */
7364         intel_uncore_rmw(&dev_priv->uncore, GEN10_DFR_RATIO_EN_AND_CHICKEN,
7365                          0, DFR_DISABLE);
7366
7367         /* Wa_14013723622:tgl,rkl,dg1,adl-s */
7368         if (DISPLAY_VER(dev_priv) == 12)
7369                 intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
7370                                  CLKREQ_POLICY_MEM_UP_OVRD, 0);
7371 }
7372
7373 static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
7374 {
7375         gen12lp_init_clock_gating(dev_priv);
7376
7377         /* Wa_22011091694:adlp */
7378         intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
7379 }
7380
7381 static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
7382 {
7383         gen12lp_init_clock_gating(dev_priv);
7384
7385         /* Wa_1409836686:dg1[a0] */
7386         if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
7387                 intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
7388                            DPT_GATING_DIS);
7389 }
7390
7391 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
7392 {
7393         if (!HAS_PCH_CNP(dev_priv))
7394                 return;
7395
7396         /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
7397         intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D) |
7398                    CNP_PWM_CGE_GATING_DISABLE);
7399 }
7400
7401 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
7402 {
7403         u32 val;
7404         cnp_init_clock_gating(dev_priv);
7405
7406         /* This is not an Wa. Enable for better image quality */
7407         intel_uncore_write(&dev_priv->uncore, _3D_CHICKEN3,
7408                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
7409
7410         /* WaEnableChickenDCPR:cnl */
7411         intel_uncore_write(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
7412                    intel_uncore_read(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
7413
7414         /*
7415          * WaFbcWakeMemOn:cnl
7416          * Display WA #0859: cnl
7417          */
7418         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7419                    DISP_FBC_MEMORY_WAKE);
7420
7421         val = intel_uncore_read(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE);
7422         /* ReadHitWriteOnlyDisable:cnl */
7423         val |= RCCUNIT_CLKGATE_DIS;
7424         intel_uncore_write(&dev_priv->uncore, SLICE_UNIT_LEVEL_CLKGATE, val);
7425
7426         /* Wa_2201832410:cnl */
7427         val = intel_uncore_read(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE);
7428         val |= GWUNIT_CLKGATE_DIS;
7429         intel_uncore_write(&dev_priv->uncore, SUBSLICE_UNIT_LEVEL_CLKGATE, val);
7430
7431         /* WaDisableVFclkgate:cnl */
7432         /* WaVFUnitClockGatingDisable:cnl */
7433         val = intel_uncore_read(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE);
7434         val |= VFUNIT_CLKGATE_DIS;
7435         intel_uncore_write(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, val);
7436 }
7437
7438 static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
7439 {
7440         cnp_init_clock_gating(dev_priv);
7441         gen9_init_clock_gating(dev_priv);
7442
7443         /* WAC6entrylatency:cfl */
7444         intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
7445                    FBC_LLC_FULLY_OPEN);
7446
7447         /*
7448          * WaFbcTurnOffFbcWatermark:cfl
7449          * Display WA #0562: cfl
7450          */
7451         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7452                    DISP_FBC_WM_DIS);
7453
7454         /*
7455          * WaFbcNukeOnHostModify:cfl
7456          * Display WA #0873: cfl
7457          */
7458         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7459                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7460 }
7461
7462 static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
7463 {
7464         gen9_init_clock_gating(dev_priv);
7465
7466         /* WAC6entrylatency:kbl */
7467         intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
7468                    FBC_LLC_FULLY_OPEN);
7469
7470         /* WaDisableSDEUnitClockGating:kbl */
7471         if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
7472                 intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
7473                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7474
7475         /* WaDisableGamClockGating:kbl */
7476         if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0))
7477                 intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
7478                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7479
7480         /*
7481          * WaFbcTurnOffFbcWatermark:kbl
7482          * Display WA #0562: kbl
7483          */
7484         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7485                    DISP_FBC_WM_DIS);
7486
7487         /*
7488          * WaFbcNukeOnHostModify:kbl
7489          * Display WA #0873: kbl
7490          */
7491         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7492                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7493 }
7494
7495 static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
7496 {
7497         gen9_init_clock_gating(dev_priv);
7498
7499         /* WaDisableDopClockGating:skl */
7500         intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
7501                    ~GEN7_DOP_CLOCK_GATE_ENABLE);
7502
7503         /* WAC6entrylatency:skl */
7504         intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
7505                    FBC_LLC_FULLY_OPEN);
7506
7507         /*
7508          * WaFbcTurnOffFbcWatermark:skl
7509          * Display WA #0562: skl
7510          */
7511         intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL, intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
7512                    DISP_FBC_WM_DIS);
7513
7514         /*
7515          * WaFbcNukeOnHostModify:skl
7516          * Display WA #0873: skl
7517          */
7518         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7519                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7520
7521         /*
7522          * WaFbcHighMemBwCorruptionAvoidance:skl
7523          * Display WA #0883: skl
7524          */
7525         intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, intel_uncore_read(&dev_priv->uncore, ILK_DPFC_CHICKEN) |
7526                    ILK_DPFC_DISABLE_DUMMY0);
7527 }
7528
7529 static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
7530 {
7531         enum pipe pipe;
7532
7533         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7534         intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
7535                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
7536                    HSW_FBCQ_DIS);
7537
7538         /* WaSwitchSolVfFArbitrationPriority:bdw */
7539         intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7540
7541         /* WaPsrDPAMaskVBlankInSRD:bdw */
7542         intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR1_1,
7543                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7544
7545         for_each_pipe(dev_priv, pipe) {
7546                 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7547                 intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
7548                            intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe)) |
7549                            BDW_DPRS_MASK_VBLANK_SRD);
7550
7551                 /* Undocumented but fixes async flip + VT-d corruption */
7552                 if (intel_vtd_active())
7553                         intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
7554                                          HSW_PRI_STRETCH_MAX_MASK, HSW_PRI_STRETCH_MAX_X1);
7555         }
7556
7557         /* WaVSRefCountFullforceMissDisable:bdw */
7558         /* WaDSRefCountFullforceMissDisable:bdw */
7559         intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
7560                    intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
7561                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7562
7563         intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
7564                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7565
7566         /* WaDisableSDEUnitClockGating:bdw */
7567         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
7568                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7569
7570         /* WaProgramL3SqcReg1Default:bdw */
7571         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7572
7573         /* WaKVMNotificationOnConfigChange:bdw */
7574         intel_uncore_write(&dev_priv->uncore, CHICKEN_PAR2_1, intel_uncore_read(&dev_priv->uncore, CHICKEN_PAR2_1)
7575                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7576
7577         lpt_init_clock_gating(dev_priv);
7578
7579         /* WaDisableDopClockGating:bdw
7580          *
7581          * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
7582          * clock gating.
7583          */
7584         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
7585                    intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
7586 }
7587
7588 static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
7589 {
7590         enum pipe pipe;
7591
7592         /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
7593         intel_uncore_write(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A),
7594                    intel_uncore_read(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A)) |
7595                    HSW_FBCQ_DIS);
7596
7597         for_each_pipe(dev_priv, pipe) {
7598                 /* Undocumented but fixes async flip + VT-d corruption */
7599                 if (intel_vtd_active())
7600                         intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
7601                                          HSW_PRI_STRETCH_MAX_MASK, HSW_PRI_STRETCH_MAX_X1);
7602         }
7603
7604         /* This is required by WaCatErrorRejectionIssue:hsw */
7605         intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7606                    intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7607                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7608
7609         /* WaSwitchSolVfFArbitrationPriority:hsw */
7610         intel_uncore_write(&dev_priv->uncore, GAM_ECOCHK, intel_uncore_read(&dev_priv->uncore, GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7611
7612         lpt_init_clock_gating(dev_priv);
7613 }
7614
7615 static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
7616 {
7617         u32 snpcr;
7618
7619         intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7620
7621         /* WaFbcAsynchFlipDisableFbcQueue:ivb */
7622         intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
7623                    intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
7624                    ILK_FBCQ_DIS);
7625
7626         /* WaDisableBackToBackFlipFix:ivb */
7627         intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
7628                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7629                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7630
7631         if (IS_IVB_GT1(dev_priv))
7632                 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
7633                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7634         else {
7635                 /* must write both registers */
7636                 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
7637                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7638                 intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
7639                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7640         }
7641
7642         /*
7643          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7644          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7645          */
7646         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
7647                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7648
7649         /* This is required by WaCatErrorRejectionIssue:ivb */
7650         intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7651                         intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7652                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7653
7654         g4x_disable_trickle_feed(dev_priv);
7655
7656         snpcr = intel_uncore_read(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR);
7657         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7658         snpcr |= GEN6_MBC_SNPCR_MED;
7659         intel_uncore_write(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, snpcr);
7660
7661         if (!HAS_PCH_NOP(dev_priv))
7662                 cpt_init_clock_gating(dev_priv);
7663
7664         gen6_check_mch_setup(dev_priv);
7665 }
7666
7667 static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
7668 {
7669         /* WaDisableBackToBackFlipFix:vlv */
7670         intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
7671                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7672                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7673
7674         /* WaDisableDopClockGating:vlv */
7675         intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
7676                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7677
7678         /* This is required by WaCatErrorRejectionIssue:vlv */
7679         intel_uncore_write(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7680                    intel_uncore_read(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7681                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7682
7683         /*
7684          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7685          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7686          */
7687         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
7688                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7689
7690         /* WaDisableL3Bank2xClockGate:vlv
7691          * Disabling L3 clock gating- MMIO 940c[25] = 1
7692          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7693         intel_uncore_write(&dev_priv->uncore, GEN7_UCGCTL4,
7694                    intel_uncore_read(&dev_priv->uncore, GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7695
7696         /*
7697          * WaDisableVLVClockGating_VBIIssue:vlv
7698          * Disable clock gating on th GCFG unit to prevent a delay
7699          * in the reporting of vblank events.
7700          */
7701         intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7702 }
7703
7704 static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
7705 {
7706         /* WaVSRefCountFullforceMissDisable:chv */
7707         /* WaDSRefCountFullforceMissDisable:chv */
7708         intel_uncore_write(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
7709                    intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &
7710                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7711
7712         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7713         intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,
7714                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7715
7716         /* WaDisableCSUnitClockGating:chv */
7717         intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
7718                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7719
7720         /* WaDisableSDEUnitClockGating:chv */
7721         intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) |
7722                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7723
7724         /*
7725          * WaProgramL3SqcReg1Default:chv
7726          * See gfxspecs/Related Documents/Performance Guide/
7727          * LSQC Setting Recommendations.
7728          */
7729         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7730 }
7731
7732 static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
7733 {
7734         u32 dspclk_gate;
7735
7736         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
7737         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7738                    GS_UNIT_CLOCK_GATE_DISABLE |
7739                    CL_UNIT_CLOCK_GATE_DISABLE);
7740         intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
7741         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7742                 OVRUNIT_CLOCK_GATE_DISABLE |
7743                 OVCUNIT_CLOCK_GATE_DISABLE;
7744         if (IS_GM45(dev_priv))
7745                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7746         intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D, dspclk_gate);
7747
7748         g4x_disable_trickle_feed(dev_priv);
7749 }
7750
7751 static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
7752 {
7753         struct intel_uncore *uncore = &dev_priv->uncore;
7754
7755         intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7756         intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
7757         intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
7758         intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
7759         intel_uncore_write16(uncore, DEUC, 0);
7760         intel_uncore_write(uncore,
7761                            MI_ARB_STATE,
7762                            _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7763 }
7764
7765 static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
7766 {
7767         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7768                    I965_RCC_CLOCK_GATE_DISABLE |
7769                    I965_RCPB_CLOCK_GATE_DISABLE |
7770                    I965_ISC_CLOCK_GATE_DISABLE |
7771                    I965_FBC_CLOCK_GATE_DISABLE);
7772         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
7773         intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
7774                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7775 }
7776
7777 static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
7778 {
7779         u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
7780
7781         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7782                 DSTATE_DOT_CLOCK_GATING;
7783         intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
7784
7785         if (IS_PINEVIEW(dev_priv))
7786                 intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7787
7788         /* IIR "flip pending" means done if this bit is set */
7789         intel_uncore_write(&dev_priv->uncore, ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7790
7791         /* interrupts should cause a wake up from C3 */
7792         intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7793
7794         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7795         intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7796
7797         intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
7798                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7799 }
7800
7801 static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
7802 {
7803         intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7804
7805         /* interrupts should cause a wake up from C3 */
7806         intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7807                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7808
7809         intel_uncore_write(&dev_priv->uncore, MEM_MODE,
7810                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7811
7812         /*
7813          * Have FBC ignore 3D activity since we use software
7814          * render tracking, and otherwise a pure 3D workload
7815          * (even if it just renders a single frame and then does
7816          * abosultely nothing) would not allow FBC to recompress
7817          * until a 2D blit occurs.
7818          */
7819         intel_uncore_write(&dev_priv->uncore, SCPD0,
7820                    _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
7821 }
7822
7823 static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
7824 {
7825         intel_uncore_write(&dev_priv->uncore, MEM_MODE,
7826                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7827                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7828 }
7829
7830 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
7831 {
7832         dev_priv->display.init_clock_gating(dev_priv);
7833 }
7834
7835 void intel_suspend_hw(struct drm_i915_private *dev_priv)
7836 {
7837         if (HAS_PCH_LPT(dev_priv))
7838                 lpt_suspend_hw(dev_priv);
7839 }
7840
7841 static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
7842 {
7843         drm_dbg_kms(&dev_priv->drm,
7844                     "No clock gating settings or workarounds applied.\n");
7845 }
7846
7847 /**
7848  * intel_init_clock_gating_hooks - setup the clock gating hooks
7849  * @dev_priv: device private
7850  *
7851  * Setup the hooks that configure which clocks of a given platform can be
7852  * gated and also apply various GT and display specific workarounds for these
7853  * platforms. Note that some GT specific workarounds are applied separately
7854  * when GPU contexts or batchbuffers start their execution.
7855  */
7856 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7857 {
7858         if (IS_ALDERLAKE_P(dev_priv))
7859                 dev_priv->display.init_clock_gating = adlp_init_clock_gating;
7860         else if (IS_DG1(dev_priv))
7861                 dev_priv->display.init_clock_gating = dg1_init_clock_gating;
7862         else if (GRAPHICS_VER(dev_priv) == 12)
7863                 dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
7864         else if (GRAPHICS_VER(dev_priv) == 11)
7865                 dev_priv->display.init_clock_gating = icl_init_clock_gating;
7866         else if (IS_CANNONLAKE(dev_priv))
7867                 dev_priv->display.init_clock_gating = cnl_init_clock_gating;
7868         else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
7869                 dev_priv->display.init_clock_gating = cfl_init_clock_gating;
7870         else if (IS_SKYLAKE(dev_priv))
7871                 dev_priv->display.init_clock_gating = skl_init_clock_gating;
7872         else if (IS_KABYLAKE(dev_priv))
7873                 dev_priv->display.init_clock_gating = kbl_init_clock_gating;
7874         else if (IS_BROXTON(dev_priv))
7875                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7876         else if (IS_GEMINILAKE(dev_priv))
7877                 dev_priv->display.init_clock_gating = glk_init_clock_gating;
7878         else if (IS_BROADWELL(dev_priv))
7879                 dev_priv->display.init_clock_gating = bdw_init_clock_gating;
7880         else if (IS_CHERRYVIEW(dev_priv))
7881                 dev_priv->display.init_clock_gating = chv_init_clock_gating;
7882         else if (IS_HASWELL(dev_priv))
7883                 dev_priv->display.init_clock_gating = hsw_init_clock_gating;
7884         else if (IS_IVYBRIDGE(dev_priv))
7885                 dev_priv->display.init_clock_gating = ivb_init_clock_gating;
7886         else if (IS_VALLEYVIEW(dev_priv))
7887                 dev_priv->display.init_clock_gating = vlv_init_clock_gating;
7888         else if (GRAPHICS_VER(dev_priv) == 6)
7889                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7890         else if (GRAPHICS_VER(dev_priv) == 5)
7891                 dev_priv->display.init_clock_gating = ilk_init_clock_gating;
7892         else if (IS_G4X(dev_priv))
7893                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7894         else if (IS_I965GM(dev_priv))
7895                 dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
7896         else if (IS_I965G(dev_priv))
7897                 dev_priv->display.init_clock_gating = i965g_init_clock_gating;
7898         else if (GRAPHICS_VER(dev_priv) == 3)
7899                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7900         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7901                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7902         else if (GRAPHICS_VER(dev_priv) == 2)
7903                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7904         else {
7905                 MISSING_CASE(INTEL_DEVID(dev_priv));
7906                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7907         }
7908 }
7909
7910 /* Set up chip specific power management-related functions */
7911 void intel_init_pm(struct drm_i915_private *dev_priv)
7912 {
7913         /* For cxsr */
7914         if (IS_PINEVIEW(dev_priv))
7915                 pnv_get_mem_freq(dev_priv);
7916         else if (GRAPHICS_VER(dev_priv) == 5)
7917                 ilk_get_mem_freq(dev_priv);
7918
7919         if (intel_has_sagv(dev_priv))
7920                 skl_setup_sagv_block_time(dev_priv);
7921
7922         /* For FIFO watermark updates */
7923         if (DISPLAY_VER(dev_priv) >= 9) {
7924                 skl_setup_wm_latency(dev_priv);
7925                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7926         } else if (HAS_PCH_SPLIT(dev_priv)) {
7927                 ilk_setup_wm_latency(dev_priv);
7928
7929                 if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
7930                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7931                     (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
7932                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7933                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7934                         dev_priv->display.compute_intermediate_wm =
7935                                 ilk_compute_intermediate_wm;
7936                         dev_priv->display.initial_watermarks =
7937                                 ilk_initial_watermarks;
7938                         dev_priv->display.optimize_watermarks =
7939                                 ilk_optimize_watermarks;
7940                 } else {
7941                         drm_dbg_kms(&dev_priv->drm,
7942                                     "Failed to read display plane latency. "
7943                                     "Disable CxSR\n");
7944                 }
7945         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7946                 vlv_setup_wm_latency(dev_priv);
7947                 dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
7948                 dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
7949                 dev_priv->display.initial_watermarks = vlv_initial_watermarks;
7950                 dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
7951                 dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
7952         } else if (IS_G4X(dev_priv)) {
7953                 g4x_setup_wm_latency(dev_priv);
7954                 dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
7955                 dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
7956                 dev_priv->display.initial_watermarks = g4x_initial_watermarks;
7957                 dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
7958         } else if (IS_PINEVIEW(dev_priv)) {
7959                 if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
7960                                             dev_priv->is_ddr3,
7961                                             dev_priv->fsb_freq,
7962                                             dev_priv->mem_freq)) {
7963                         drm_info(&dev_priv->drm,
7964                                  "failed to find known CxSR latency "
7965                                  "(found ddr%s fsb freq %d, mem freq %d), "
7966                                  "disabling CxSR\n",
7967                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7968                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7969                         /* Disable CxSR and never update its watermark again */
7970                         intel_set_memory_cxsr(dev_priv, false);
7971                         dev_priv->display.update_wm = NULL;
7972                 } else
7973                         dev_priv->display.update_wm = pnv_update_wm;
7974         } else if (DISPLAY_VER(dev_priv) == 4) {
7975                 dev_priv->display.update_wm = i965_update_wm;
7976         } else if (DISPLAY_VER(dev_priv) == 3) {
7977                 dev_priv->display.update_wm = i9xx_update_wm;
7978                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7979         } else if (DISPLAY_VER(dev_priv) == 2) {
7980                 if (INTEL_NUM_PIPES(dev_priv) == 1) {
7981                         dev_priv->display.update_wm = i845_update_wm;
7982                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7983                 } else {
7984                         dev_priv->display.update_wm = i9xx_update_wm;
7985                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7986                 }
7987         } else {
7988                 drm_err(&dev_priv->drm,
7989                         "unexpected fall-through in %s\n", __func__);
7990         }
7991 }
7992
7993 void intel_pm_setup(struct drm_i915_private *dev_priv)
7994 {
7995         dev_priv->runtime_pm.suspended = false;
7996         atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
7997 }
7998
7999 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
8000 {
8001         struct intel_dbuf_state *dbuf_state;
8002
8003         dbuf_state = kmemdup(obj->state, sizeof(*dbuf_state), GFP_KERNEL);
8004         if (!dbuf_state)
8005                 return NULL;
8006
8007         return &dbuf_state->base;
8008 }
8009
8010 static void intel_dbuf_destroy_state(struct intel_global_obj *obj,
8011                                      struct intel_global_state *state)
8012 {
8013         kfree(state);
8014 }
8015
8016 static const struct intel_global_state_funcs intel_dbuf_funcs = {
8017         .atomic_duplicate_state = intel_dbuf_duplicate_state,
8018         .atomic_destroy_state = intel_dbuf_destroy_state,
8019 };
8020
8021 struct intel_dbuf_state *
8022 intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
8023 {
8024         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8025         struct intel_global_state *dbuf_state;
8026
8027         dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
8028         if (IS_ERR(dbuf_state))
8029                 return ERR_CAST(dbuf_state);
8030
8031         return to_intel_dbuf_state(dbuf_state);
8032 }
8033
8034 int intel_dbuf_init(struct drm_i915_private *dev_priv)
8035 {
8036         struct intel_dbuf_state *dbuf_state;
8037
8038         dbuf_state = kzalloc(sizeof(*dbuf_state), GFP_KERNEL);
8039         if (!dbuf_state)
8040                 return -ENOMEM;
8041
8042         intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
8043                                      &dbuf_state->base, &intel_dbuf_funcs);
8044
8045         return 0;
8046 }
8047
8048 /*
8049  * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
8050  * update the request state of all DBUS slices.
8051  */
8052 static void update_mbus_pre_enable(struct intel_atomic_state *state)
8053 {
8054         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8055         u32 mbus_ctl, dbuf_min_tracker_val;
8056         enum dbuf_slice slice;
8057         const struct intel_dbuf_state *dbuf_state =
8058                 intel_atomic_get_new_dbuf_state(state);
8059
8060         if (!IS_ALDERLAKE_P(dev_priv))
8061                 return;
8062
8063         /*
8064          * TODO: Implement vblank synchronized MBUS joining changes.
8065          * Must be properly coordinated with dbuf reprogramming.
8066          */
8067         if (dbuf_state->joined_mbus) {
8068                 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
8069                         MBUS_JOIN_PIPE_SELECT_NONE;
8070                 dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
8071         } else {
8072                 mbus_ctl = MBUS_HASHING_MODE_2x2 |
8073                         MBUS_JOIN_PIPE_SELECT_NONE;
8074                 dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
8075         }
8076
8077         intel_de_rmw(dev_priv, MBUS_CTL,
8078                      MBUS_HASHING_MODE_MASK | MBUS_JOIN |
8079                      MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
8080
8081         for_each_dbuf_slice(dev_priv, slice)
8082                 intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
8083                              DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
8084                              dbuf_min_tracker_val);
8085 }
8086
8087 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
8088 {
8089         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8090         const struct intel_dbuf_state *new_dbuf_state =
8091                 intel_atomic_get_new_dbuf_state(state);
8092         const struct intel_dbuf_state *old_dbuf_state =
8093                 intel_atomic_get_old_dbuf_state(state);
8094
8095         if (!new_dbuf_state ||
8096             ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
8097             && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)))
8098                 return;
8099
8100         WARN_ON(!new_dbuf_state->base.changed);
8101
8102         update_mbus_pre_enable(state);
8103         gen9_dbuf_slices_update(dev_priv,
8104                                 old_dbuf_state->enabled_slices |
8105                                 new_dbuf_state->enabled_slices);
8106 }
8107
8108 void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
8109 {
8110         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
8111         const struct intel_dbuf_state *new_dbuf_state =
8112                 intel_atomic_get_new_dbuf_state(state);
8113         const struct intel_dbuf_state *old_dbuf_state =
8114                 intel_atomic_get_old_dbuf_state(state);
8115
8116         if (!new_dbuf_state ||
8117             ((new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices)
8118             && (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus)))
8119                 return;
8120
8121         WARN_ON(!new_dbuf_state->base.changed);
8122
8123         gen9_dbuf_slices_update(dev_priv,
8124                                 new_dbuf_state->enabled_slices);
8125 }