1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Freescale eSDHC controller driver generics for OF and pltfm.
5 * Copyright (c) 2007 Freescale Semiconductor, Inc.
6 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Copyright (c) 2010 Pengutronix e.K.
11 #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
12 #define _DRIVERS_MMC_SDHCI_ESDHC_H
15 * Ops and quirks for the Freescale eSDHC controller.
18 #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
19 SDHCI_QUIRK_32BIT_DMA_ADDR | \
20 SDHCI_QUIRK_NO_BUSY_IRQ | \
21 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
22 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
23 SDHCI_QUIRK_NO_HISPD_BIT)
26 #define ESDHC_HOST_CONTROL_LE 0x20
29 * eSDHC register definition
32 /* Present State Register */
33 #define ESDHC_PRSSTAT 0x24
34 #define ESDHC_CLOCK_STABLE 0x00000008
36 /* Protocol Control Register */
37 #define ESDHC_PROCTL 0x28
38 #define ESDHC_VOLT_SEL 0x00000400
39 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
40 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
41 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
42 #define ESDHC_HOST_CONTROL_RES 0x01
44 /* System Control Register */
45 #define ESDHC_SYSTEM_CONTROL 0x2c
46 #define ESDHC_CLOCK_MASK 0x0000fff0
47 #define ESDHC_PREDIV_SHIFT 8
48 #define ESDHC_DIVIDER_SHIFT 4
49 #define ESDHC_CLOCK_SDCLKEN 0x00000008
50 #define ESDHC_CLOCK_PEREN 0x00000004
51 #define ESDHC_CLOCK_HCKEN 0x00000002
52 #define ESDHC_CLOCK_IPGEN 0x00000001
54 /* Host Controller Capabilities Register 2 */
55 #define ESDHC_CAPABILITIES_1 0x114
57 /* Tuning Block Control Register */
58 #define ESDHC_TBCTL 0x120
59 #define ESDHC_HS400_WNDW_ADJUST 0x00000040
60 #define ESDHC_HS400_MODE 0x00000010
61 #define ESDHC_TB_EN 0x00000004
62 #define ESDHC_TBPTR 0x128
64 /* SD Clock Control Register */
65 #define ESDHC_SDCLKCTL 0x144
66 #define ESDHC_LPBK_CLK_SEL 0x80000000
67 #define ESDHC_CMD_CLK_CTL 0x00008000
69 /* SD Timing Control Register */
70 #define ESDHC_SDTIMNGCTL 0x148
71 #define ESDHC_FLW_CTL_BG 0x00008000
73 /* DLL Config 0 Register */
74 #define ESDHC_DLLCFG0 0x160
75 #define ESDHC_DLL_ENABLE 0x80000000
76 #define ESDHC_DLL_FREQ_SEL 0x08000000
78 /* DLL Config 1 Register */
79 #define ESDHC_DLLCFG1 0x164
80 #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
82 /* DLL Status 0 Register */
83 #define ESDHC_DLLSTAT0 0x170
84 #define ESDHC_DLL_STS_SLV_LOCK 0x08000000
86 /* Control Register for DMA transfer */
87 #define ESDHC_DMA_SYSCTL 0x40c
88 #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
89 #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
90 #define ESDHC_DMA_SNOOP 0x00000040
92 #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */