2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
42 #include <linux/sched/mm.h>
43 #include <linux/sched/task.h>
46 #include <net/addrconf.h>
47 #include <net/devlink.h>
49 #include <rdma/ib_smi.h>
50 #include <rdma/ib_user_verbs.h>
51 #include <rdma/ib_addr.h>
52 #include <rdma/ib_cache.h>
54 #include <net/bonding.h>
56 #include <linux/mlx4/driver.h>
57 #include <linux/mlx4/cmd.h>
58 #include <linux/mlx4/qp.h>
61 #include <rdma/mlx4-abi.h>
63 #define DRV_NAME MLX4_IB_DRV_NAME
64 #define DRV_VERSION "4.0-0"
66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
68 #define MLX4_IB_CARD_REV_A0 0xA0
70 MODULE_AUTHOR("Roland Dreier");
71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72 MODULE_LICENSE("Dual BSD/GPL");
74 int mlx4_ib_sm_guid_assign = 0;
75 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
76 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
78 static const char mlx4_ib_version[] =
79 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
82 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83 static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
86 static struct workqueue_struct *wq;
88 static void init_query_mad(struct ib_smp *mad)
90 mad->base_version = 1;
91 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92 mad->class_version = 1;
93 mad->method = IB_MGMT_METHOD_GET;
96 static int check_flow_steering_support(struct mlx4_dev *dev)
98 int eth_num_ports = 0;
101 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
105 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
107 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
109 dmfs &= (!ib_num_ports ||
110 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113 if (ib_num_ports && mlx4_is_mfunc(dev)) {
114 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
121 static int num_ib_ports(struct mlx4_dev *dev)
126 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
132 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
134 struct mlx4_ib_dev *ibdev = to_mdev(device);
135 struct net_device *dev;
138 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
141 if (mlx4_is_bonded(ibdev->dev)) {
142 struct net_device *upper = NULL;
144 upper = netdev_master_upper_dev_get_rcu(dev);
146 struct net_device *active;
148 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
161 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162 struct mlx4_ib_dev *ibdev,
165 struct mlx4_cmd_mailbox *mailbox;
167 struct mlx4_dev *dev = ibdev->dev;
169 union ib_gid *gid_tbl;
171 mailbox = mlx4_alloc_cmd_mailbox(dev);
175 gid_tbl = mailbox->buf;
177 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
180 err = mlx4_cmd(dev, mailbox->dma,
181 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
184 if (mlx4_is_bonded(dev))
185 err += mlx4_cmd(dev, mailbox->dma,
186 MLX4_SET_PORT_GID_TABLE << 8 | 2,
187 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
190 mlx4_free_cmd_mailbox(dev, mailbox);
194 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195 struct mlx4_ib_dev *ibdev,
198 struct mlx4_cmd_mailbox *mailbox;
200 struct mlx4_dev *dev = ibdev->dev;
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
215 gid_tbl = mailbox->buf;
216 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219 gid_tbl[i].version = 2;
220 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
225 err = mlx4_cmd(dev, mailbox->dma,
226 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
229 if (mlx4_is_bonded(dev))
230 err += mlx4_cmd(dev, mailbox->dma,
231 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
235 mlx4_free_cmd_mailbox(dev, mailbox);
239 static int mlx4_ib_update_gids(struct gid_entry *gids,
240 struct mlx4_ib_dev *ibdev,
243 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
246 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
249 static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context)
251 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
252 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
253 struct mlx4_port_gid_table *port_gid_table;
254 int free = -1, found = -1;
258 struct gid_entry *gids = NULL;
260 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
263 if (attr->port_num > MLX4_MAX_PORTS)
269 port_gid_table = &iboe->gids[attr->port_num - 1];
270 spin_lock_bh(&iboe->lock);
271 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
272 if (!memcmp(&port_gid_table->gids[i].gid,
273 &attr->gid, sizeof(attr->gid)) &&
274 port_gid_table->gids[i].gid_type == attr->gid_type) {
278 if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
279 free = i; /* HW has space */
286 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
287 if (!port_gid_table->gids[free].ctx) {
290 *context = port_gid_table->gids[free].ctx;
291 memcpy(&port_gid_table->gids[free].gid,
292 &attr->gid, sizeof(attr->gid));
293 port_gid_table->gids[free].gid_type = attr->gid_type;
294 port_gid_table->gids[free].ctx->real_index = free;
295 port_gid_table->gids[free].ctx->refcount = 1;
300 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
304 if (!ret && hw_update) {
305 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
310 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
311 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
312 gids[i].gid_type = port_gid_table->gids[i].gid_type;
316 spin_unlock_bh(&iboe->lock);
318 if (!ret && hw_update) {
319 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
326 static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
328 struct gid_cache_context *ctx = *context;
329 struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
330 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
331 struct mlx4_port_gid_table *port_gid_table;
334 struct gid_entry *gids = NULL;
336 if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
339 if (attr->port_num > MLX4_MAX_PORTS)
342 port_gid_table = &iboe->gids[attr->port_num - 1];
343 spin_lock_bh(&iboe->lock);
346 if (!ctx->refcount) {
347 unsigned int real_index = ctx->real_index;
349 memset(&port_gid_table->gids[real_index].gid, 0,
350 sizeof(port_gid_table->gids[real_index].gid));
351 kfree(port_gid_table->gids[real_index].ctx);
352 port_gid_table->gids[real_index].ctx = NULL;
356 if (!ret && hw_update) {
359 gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
364 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
366 &port_gid_table->gids[i].gid,
367 sizeof(union ib_gid));
369 port_gid_table->gids[i].gid_type;
373 spin_unlock_bh(&iboe->lock);
375 if (!ret && hw_update) {
376 ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
382 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
383 const struct ib_gid_attr *attr)
385 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
386 struct gid_cache_context *ctx = NULL;
387 struct mlx4_port_gid_table *port_gid_table;
388 int real_index = -EINVAL;
391 u8 port_num = attr->port_num;
393 if (port_num > MLX4_MAX_PORTS)
396 if (mlx4_is_bonded(ibdev->dev))
399 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
402 spin_lock_irqsave(&iboe->lock, flags);
403 port_gid_table = &iboe->gids[port_num - 1];
405 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
406 if (!memcmp(&port_gid_table->gids[i].gid,
407 &attr->gid, sizeof(attr->gid)) &&
408 attr->gid_type == port_gid_table->gids[i].gid_type) {
409 ctx = port_gid_table->gids[i].ctx;
413 real_index = ctx->real_index;
414 spin_unlock_irqrestore(&iboe->lock, flags);
418 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
419 sizeof(((type *)0)->fld) <= (sz))
421 static int mlx4_ib_query_device(struct ib_device *ibdev,
422 struct ib_device_attr *props,
423 struct ib_udata *uhw)
425 struct mlx4_ib_dev *dev = to_mdev(ibdev);
426 struct ib_smp *in_mad = NULL;
427 struct ib_smp *out_mad = NULL;
430 struct mlx4_uverbs_ex_query_device cmd;
431 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
432 struct mlx4_clock_params clock_params;
435 if (uhw->inlen < sizeof(cmd))
438 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
449 resp.response_length = offsetof(typeof(resp), response_length) +
450 sizeof(resp.response_length);
451 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
452 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
454 if (!in_mad || !out_mad)
457 init_query_mad(in_mad);
458 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
460 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
461 1, NULL, NULL, in_mad, out_mad);
465 memset(props, 0, sizeof *props);
467 have_ib_ports = num_ib_ports(dev->dev);
469 props->fw_ver = dev->dev->caps.fw_ver;
470 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
471 IB_DEVICE_PORT_ACTIVE_EVENT |
472 IB_DEVICE_SYS_IMAGE_GUID |
473 IB_DEVICE_RC_RNR_NAK_GEN |
474 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
475 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
476 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
477 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
478 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
479 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
480 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
481 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
482 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
483 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
484 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
485 if (dev->dev->caps.max_gso_sz &&
486 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
487 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
488 props->device_cap_flags |= IB_DEVICE_UD_TSO;
489 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
490 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
491 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
492 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
493 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
494 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
495 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
496 props->device_cap_flags |= IB_DEVICE_XRC;
497 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
498 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
499 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
500 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
501 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
503 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
505 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
506 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
508 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
510 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
512 props->vendor_part_id = dev->dev->persist->pdev->device;
513 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
514 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
516 props->max_mr_size = ~0ull;
517 props->page_size_cap = dev->dev->caps.page_size_cap;
518 props->max_qp = dev->dev->quotas.qp;
519 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
520 props->max_send_sge =
521 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
522 props->max_recv_sge =
523 min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
524 props->max_sge_rd = MLX4_MAX_SGE_RD;
525 props->max_cq = dev->dev->quotas.cq;
526 props->max_cqe = dev->dev->caps.max_cqes;
527 props->max_mr = dev->dev->quotas.mpt;
528 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
529 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
530 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
531 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
532 props->max_srq = dev->dev->quotas.srq;
533 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
534 props->max_srq_sge = dev->dev->caps.max_srq_sge;
535 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
536 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
537 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
538 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
539 props->masked_atomic_cap = props->atomic_cap;
540 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
541 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
542 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
543 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
544 props->max_mcast_grp;
545 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
546 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
547 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
548 props->max_ah = INT_MAX;
550 if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
551 mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
552 if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
553 props->rss_caps.max_rwq_indirection_tables =
555 props->rss_caps.max_rwq_indirection_table_size =
556 dev->dev->caps.max_rss_tbl_sz;
557 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
558 props->max_wq_type_rq = props->max_qp;
561 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
562 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
565 props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
566 props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
568 if (!mlx4_is_slave(dev->dev))
569 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
571 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
572 resp.response_length += sizeof(resp.hca_core_clock_offset);
573 if (!err && !mlx4_is_slave(dev->dev)) {
574 resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
575 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
579 if (uhw->outlen >= resp.response_length +
580 sizeof(resp.max_inl_recv_sz)) {
581 resp.response_length += sizeof(resp.max_inl_recv_sz);
582 resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
583 sizeof(struct mlx4_wqe_data_seg);
586 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
587 if (props->rss_caps.supported_qpts) {
588 resp.rss_caps.rx_hash_function =
589 MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
591 resp.rss_caps.rx_hash_fields_mask =
592 MLX4_IB_RX_HASH_SRC_IPV4 |
593 MLX4_IB_RX_HASH_DST_IPV4 |
594 MLX4_IB_RX_HASH_SRC_IPV6 |
595 MLX4_IB_RX_HASH_DST_IPV6 |
596 MLX4_IB_RX_HASH_SRC_PORT_TCP |
597 MLX4_IB_RX_HASH_DST_PORT_TCP |
598 MLX4_IB_RX_HASH_SRC_PORT_UDP |
599 MLX4_IB_RX_HASH_DST_PORT_UDP;
601 if (dev->dev->caps.tunnel_offload_mode ==
602 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
603 resp.rss_caps.rx_hash_fields_mask |=
604 MLX4_IB_RX_HASH_INNER;
606 resp.response_length = offsetof(typeof(resp), rss_caps) +
607 sizeof(resp.rss_caps);
610 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
611 if (dev->dev->caps.max_gso_sz &&
612 ((mlx4_ib_port_link_layer(ibdev, 1) ==
613 IB_LINK_LAYER_ETHERNET) ||
614 (mlx4_ib_port_link_layer(ibdev, 2) ==
615 IB_LINK_LAYER_ETHERNET))) {
616 resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
617 resp.tso_caps.supported_qpts |=
618 1 << IB_QPT_RAW_PACKET;
620 resp.response_length = offsetof(typeof(resp), tso_caps) +
621 sizeof(resp.tso_caps);
625 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
636 static enum rdma_link_layer
637 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
639 struct mlx4_dev *dev = to_mdev(device)->dev;
641 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
642 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
645 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
646 struct ib_port_attr *props, int netw_view)
648 struct ib_smp *in_mad = NULL;
649 struct ib_smp *out_mad = NULL;
650 int ext_active_speed;
651 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
654 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
655 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
656 if (!in_mad || !out_mad)
659 init_query_mad(in_mad);
660 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
661 in_mad->attr_mod = cpu_to_be32(port);
663 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
664 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
666 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
672 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
673 props->lmc = out_mad->data[34] & 0x7;
674 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
675 props->sm_sl = out_mad->data[36] & 0xf;
676 props->state = out_mad->data[32] & 0xf;
677 props->phys_state = out_mad->data[33] >> 4;
678 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
680 props->gid_tbl_len = out_mad->data[50];
682 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
683 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
684 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
685 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
686 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
687 props->active_width = out_mad->data[31] & 0xf;
688 props->active_speed = out_mad->data[35] >> 4;
689 props->max_mtu = out_mad->data[41] & 0xf;
690 props->active_mtu = out_mad->data[36] >> 4;
691 props->subnet_timeout = out_mad->data[51] & 0x1f;
692 props->max_vl_num = out_mad->data[37] >> 4;
693 props->init_type_reply = out_mad->data[41] >> 4;
695 /* Check if extended speeds (EDR/FDR/...) are supported */
696 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
697 ext_active_speed = out_mad->data[62] >> 4;
699 switch (ext_active_speed) {
701 props->active_speed = IB_SPEED_FDR;
704 props->active_speed = IB_SPEED_EDR;
709 /* If reported active speed is QDR, check if is FDR-10 */
710 if (props->active_speed == IB_SPEED_QDR) {
711 init_query_mad(in_mad);
712 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
713 in_mad->attr_mod = cpu_to_be32(port);
715 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
716 NULL, NULL, in_mad, out_mad);
720 /* Checking LinkSpeedActive for FDR-10 */
721 if (out_mad->data[15] & 0x1)
722 props->active_speed = IB_SPEED_FDR10;
725 /* Avoid wrong speed value returned by FW if the IB link is down. */
726 if (props->state == IB_PORT_DOWN)
727 props->active_speed = IB_SPEED_SDR;
735 static u8 state_to_phys_state(enum ib_port_state state)
737 return state == IB_PORT_ACTIVE ?
738 IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED;
741 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
742 struct ib_port_attr *props)
745 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
746 struct mlx4_ib_iboe *iboe = &mdev->iboe;
747 struct net_device *ndev;
749 struct mlx4_cmd_mailbox *mailbox;
751 int is_bonded = mlx4_is_bonded(mdev->dev);
753 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
755 return PTR_ERR(mailbox);
757 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
758 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
763 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
764 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
765 IB_WIDTH_4X : IB_WIDTH_1X;
766 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
767 IB_SPEED_FDR : IB_SPEED_QDR;
768 props->port_cap_flags = IB_PORT_CM_SUP;
769 props->ip_gids = true;
770 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
771 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
772 props->pkey_tbl_len = 1;
773 props->max_mtu = IB_MTU_4096;
774 props->max_vl_num = 2;
775 props->state = IB_PORT_DOWN;
776 props->phys_state = state_to_phys_state(props->state);
777 props->active_mtu = IB_MTU_256;
778 spin_lock_bh(&iboe->lock);
779 ndev = iboe->netdevs[port - 1];
780 if (ndev && is_bonded) {
781 rcu_read_lock(); /* required to get upper dev */
782 ndev = netdev_master_upper_dev_get_rcu(ndev);
788 tmp = iboe_get_mtu(ndev->mtu);
789 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
791 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
792 IB_PORT_ACTIVE : IB_PORT_DOWN;
793 props->phys_state = state_to_phys_state(props->state);
795 spin_unlock_bh(&iboe->lock);
797 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
801 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
802 struct ib_port_attr *props, int netw_view)
806 /* props being zeroed by the caller, avoid zeroing it here */
808 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
809 ib_link_query_port(ibdev, port, props, netw_view) :
810 eth_link_query_port(ibdev, port, props);
815 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
816 struct ib_port_attr *props)
818 /* returns host view */
819 return __mlx4_ib_query_port(ibdev, port, props, 0);
822 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
823 union ib_gid *gid, int netw_view)
825 struct ib_smp *in_mad = NULL;
826 struct ib_smp *out_mad = NULL;
828 struct mlx4_ib_dev *dev = to_mdev(ibdev);
830 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
832 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
833 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
834 if (!in_mad || !out_mad)
837 init_query_mad(in_mad);
838 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
839 in_mad->attr_mod = cpu_to_be32(port);
841 if (mlx4_is_mfunc(dev->dev) && netw_view)
842 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
844 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
848 memcpy(gid->raw, out_mad->data + 8, 8);
850 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
852 /* For any index > 0, return the null guid */
859 init_query_mad(in_mad);
860 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
861 in_mad->attr_mod = cpu_to_be32(index / 8);
863 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
864 NULL, NULL, in_mad, out_mad);
868 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
872 memset(gid->raw + 8, 0, 8);
878 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
881 if (rdma_protocol_ib(ibdev, port))
882 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
886 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
888 union sl2vl_tbl_to_u64 sl2vl64;
889 struct ib_smp *in_mad = NULL;
890 struct ib_smp *out_mad = NULL;
891 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
895 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
900 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
901 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
902 if (!in_mad || !out_mad)
905 init_query_mad(in_mad);
906 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
907 in_mad->attr_mod = 0;
909 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
910 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
912 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
917 for (jj = 0; jj < 8; jj++)
918 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
919 *sl2vl_tbl = sl2vl64.sl64;
927 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
933 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
934 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
936 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
938 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
942 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
946 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
947 u16 *pkey, int netw_view)
949 struct ib_smp *in_mad = NULL;
950 struct ib_smp *out_mad = NULL;
951 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
954 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
955 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
956 if (!in_mad || !out_mad)
959 init_query_mad(in_mad);
960 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
961 in_mad->attr_mod = cpu_to_be32(index / 32);
963 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
964 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
966 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
971 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
979 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
981 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
984 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
985 struct ib_device_modify *props)
987 struct mlx4_cmd_mailbox *mailbox;
990 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
993 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
996 if (mlx4_is_slave(to_mdev(ibdev)->dev))
999 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
1000 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1001 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
1004 * If possible, pass node desc to FW, so it can generate
1005 * a 144 trap. If cmd fails, just ignore.
1007 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1008 if (IS_ERR(mailbox))
1011 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1012 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
1013 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1015 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
1020 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1023 struct mlx4_cmd_mailbox *mailbox;
1026 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1027 if (IS_ERR(mailbox))
1028 return PTR_ERR(mailbox);
1030 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1031 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1032 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1034 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1035 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1038 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1039 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1042 mlx4_free_cmd_mailbox(dev->dev, mailbox);
1046 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1047 struct ib_port_modify *props)
1049 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1050 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1051 struct ib_port_attr attr;
1055 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1056 * of whether port link layer is ETH or IB. For ETH ports, qkey
1057 * violations and port capabilities are not meaningful.
1062 mutex_lock(&mdev->cap_mask_mutex);
1064 err = ib_query_port(ibdev, port, &attr);
1068 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1069 ~props->clr_port_cap_mask;
1071 err = mlx4_ib_SET_PORT(mdev, port,
1072 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1076 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1080 static int mlx4_ib_alloc_ucontext(struct ib_ucontext *uctx,
1081 struct ib_udata *udata)
1083 struct ib_device *ibdev = uctx->device;
1084 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1085 struct mlx4_ib_ucontext *context = to_mucontext(uctx);
1086 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1087 struct mlx4_ib_alloc_ucontext_resp resp;
1090 if (!dev->ib_active)
1093 if (ibdev->ops.uverbs_abi_ver ==
1094 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1095 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1096 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1097 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1099 resp.dev_caps = dev->dev->caps.userspace_caps;
1100 resp.qp_tab_size = dev->dev->caps.num_qps;
1101 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1102 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1103 resp.cqe_size = dev->dev->caps.cqe_size;
1106 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1110 INIT_LIST_HEAD(&context->db_page_list);
1111 mutex_init(&context->db_page_mutex);
1113 INIT_LIST_HEAD(&context->wqn_ranges_list);
1114 mutex_init(&context->wqn_ranges_mutex);
1116 if (ibdev->ops.uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1117 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1119 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1122 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1129 static void mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1131 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1133 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1136 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1140 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1142 struct mlx4_ib_dev *dev = to_mdev(context->device);
1144 switch (vma->vm_pgoff) {
1146 return rdma_user_mmap_io(context, vma,
1147 to_mucontext(context)->uar.pfn,
1149 pgprot_noncached(vma->vm_page_prot));
1152 if (dev->dev->caps.bf_reg_size == 0)
1154 return rdma_user_mmap_io(
1156 to_mucontext(context)->uar.pfn +
1157 dev->dev->caps.num_uars,
1158 PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot));
1161 struct mlx4_clock_params params;
1164 ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1168 return rdma_user_mmap_io(
1170 (pci_resource_start(dev->dev->persist->pdev,
1174 PAGE_SIZE, pgprot_noncached(vma->vm_page_prot));
1182 static int mlx4_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
1184 struct mlx4_ib_pd *pd = to_mpd(ibpd);
1185 struct ib_device *ibdev = ibpd->device;
1188 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1192 if (udata && ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) {
1193 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1199 static void mlx4_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
1201 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1204 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1205 struct ib_udata *udata)
1207 struct mlx4_ib_xrcd *xrcd;
1208 struct ib_cq_init_attr cq_attr = {};
1211 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1212 return ERR_PTR(-ENOSYS);
1214 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1216 return ERR_PTR(-ENOMEM);
1218 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1222 xrcd->pd = ib_alloc_pd(ibdev, 0);
1223 if (IS_ERR(xrcd->pd)) {
1224 err = PTR_ERR(xrcd->pd);
1229 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1230 if (IS_ERR(xrcd->cq)) {
1231 err = PTR_ERR(xrcd->cq);
1235 return &xrcd->ibxrcd;
1238 ib_dealloc_pd(xrcd->pd);
1240 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1243 return ERR_PTR(err);
1246 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
1248 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1249 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1250 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1256 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1258 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1259 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1260 struct mlx4_ib_gid_entry *ge;
1262 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1267 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1268 ge->port = mqp->port;
1272 mutex_lock(&mqp->mutex);
1273 list_add_tail(&ge->list, &mqp->gid_list);
1274 mutex_unlock(&mqp->mutex);
1279 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1280 struct mlx4_ib_counters *ctr_table)
1282 struct counter_index *counter, *tmp_count;
1284 mutex_lock(&ctr_table->mutex);
1285 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1287 if (counter->allocated)
1288 mlx4_counter_free(ibdev->dev, counter->index);
1289 list_del(&counter->list);
1292 mutex_unlock(&ctr_table->mutex);
1295 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1298 struct net_device *ndev;
1304 spin_lock_bh(&mdev->iboe.lock);
1305 ndev = mdev->iboe.netdevs[mqp->port - 1];
1308 spin_unlock_bh(&mdev->iboe.lock);
1318 struct mlx4_ib_steering {
1319 struct list_head list;
1320 struct mlx4_flow_reg_id reg_id;
1324 #define LAST_ETH_FIELD vlan_tag
1325 #define LAST_IB_FIELD sl
1326 #define LAST_IPV4_FIELD dst_ip
1327 #define LAST_TCP_UDP_FIELD src_port
1329 /* Field is the last supported field */
1330 #define FIELDS_NOT_SUPPORTED(filter, field)\
1331 memchr_inv((void *)&filter.field +\
1332 sizeof(filter.field), 0,\
1334 offsetof(typeof(filter), field) -\
1335 sizeof(filter.field))
1337 static int parse_flow_attr(struct mlx4_dev *dev,
1339 union ib_flow_spec *ib_spec,
1340 struct _rule_hw *mlx4_spec)
1342 enum mlx4_net_trans_rule_id type;
1344 switch (ib_spec->type) {
1345 case IB_FLOW_SPEC_ETH:
1346 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1349 type = MLX4_NET_TRANS_RULE_ID_ETH;
1350 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1352 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1354 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1355 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1357 case IB_FLOW_SPEC_IB:
1358 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1361 type = MLX4_NET_TRANS_RULE_ID_IB;
1362 mlx4_spec->ib.l3_qpn =
1363 cpu_to_be32(qp_num);
1364 mlx4_spec->ib.qpn_mask =
1365 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1369 case IB_FLOW_SPEC_IPV4:
1370 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1373 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1374 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1375 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1376 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1377 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1380 case IB_FLOW_SPEC_TCP:
1381 case IB_FLOW_SPEC_UDP:
1382 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1385 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1386 MLX4_NET_TRANS_RULE_ID_TCP :
1387 MLX4_NET_TRANS_RULE_ID_UDP;
1388 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1389 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1390 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1391 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1397 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1398 mlx4_hw_rule_sz(dev, type) < 0)
1400 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1401 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1402 return mlx4_hw_rule_sz(dev, type);
1405 struct default_rules {
1406 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1407 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1408 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1411 static const struct default_rules default_table[] = {
1413 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1414 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1415 .rules_create_list = {IB_FLOW_SPEC_IB},
1416 .link_layer = IB_LINK_LAYER_INFINIBAND
1420 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1421 struct ib_flow_attr *flow_attr)
1425 const struct default_rules *pdefault_rules = default_table;
1426 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1428 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1429 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1430 memset(&field_types, 0, sizeof(field_types));
1432 if (link_layer != pdefault_rules->link_layer)
1435 ib_flow = flow_attr + 1;
1436 /* we assume the specs are sorted */
1437 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1438 j < flow_attr->num_of_specs; k++) {
1439 union ib_flow_spec *current_flow =
1440 (union ib_flow_spec *)ib_flow;
1442 /* same layer but different type */
1443 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1444 (pdefault_rules->mandatory_fields[k] &
1445 IB_FLOW_SPEC_LAYER_MASK)) &&
1446 (current_flow->type !=
1447 pdefault_rules->mandatory_fields[k]))
1450 /* same layer, try match next one */
1451 if (current_flow->type ==
1452 pdefault_rules->mandatory_fields[k]) {
1455 ((union ib_flow_spec *)ib_flow)->size;
1459 ib_flow = flow_attr + 1;
1460 for (j = 0; j < flow_attr->num_of_specs;
1461 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1462 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1463 /* same layer and same type */
1464 if (((union ib_flow_spec *)ib_flow)->type ==
1465 pdefault_rules->mandatory_not_fields[k])
1474 static int __mlx4_ib_create_default_rules(
1475 struct mlx4_ib_dev *mdev,
1477 const struct default_rules *pdefault_rules,
1478 struct _rule_hw *mlx4_spec) {
1482 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1484 union ib_flow_spec ib_spec;
1485 switch (pdefault_rules->rules_create_list[i]) {
1489 case IB_FLOW_SPEC_IB:
1490 ib_spec.type = IB_FLOW_SPEC_IB;
1491 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1498 /* We must put empty rule, qpn is being ignored */
1499 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1502 pr_info("invalid parsing\n");
1506 mlx4_spec = (void *)mlx4_spec + ret;
1512 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1514 enum mlx4_net_trans_promisc_mode flow_type,
1520 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1521 struct mlx4_cmd_mailbox *mailbox;
1522 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1525 static const u16 __mlx4_domain[] = {
1526 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1527 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1528 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1529 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1532 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1533 pr_err("Invalid priority value %d\n", flow_attr->priority);
1537 if (domain >= IB_FLOW_DOMAIN_NUM) {
1538 pr_err("Invalid domain value %d\n", domain);
1542 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1545 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1546 if (IS_ERR(mailbox))
1547 return PTR_ERR(mailbox);
1548 ctrl = mailbox->buf;
1550 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1551 flow_attr->priority);
1552 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1553 ctrl->port = flow_attr->port;
1554 ctrl->qpn = cpu_to_be32(qp->qp_num);
1556 ib_flow = flow_attr + 1;
1557 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1558 /* Add default flows */
1559 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1560 if (default_flow >= 0) {
1561 ret = __mlx4_ib_create_default_rules(
1562 mdev, qp, default_table + default_flow,
1563 mailbox->buf + size);
1565 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1570 for (i = 0; i < flow_attr->num_of_specs; i++) {
1571 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1572 mailbox->buf + size);
1574 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1577 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1581 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1582 flow_attr->num_of_specs == 1) {
1583 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1584 enum ib_flow_spec_type header_spec =
1585 ((union ib_flow_spec *)(flow_attr + 1))->type;
1587 if (header_spec == IB_FLOW_SPEC_ETH)
1588 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1591 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1592 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1595 pr_err("mcg table is full. Fail to register network rule.\n");
1596 else if (ret == -ENXIO)
1597 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1599 pr_err("Invalid argument. Fail to register network rule.\n");
1601 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1605 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1608 err = mlx4_cmd(dev, reg_id, 0, 0,
1609 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1612 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1617 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1621 union ib_flow_spec *ib_spec;
1622 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1625 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1626 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1627 return 0; /* do nothing */
1629 ib_flow = flow_attr + 1;
1630 ib_spec = (union ib_flow_spec *)ib_flow;
1632 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1633 return 0; /* do nothing */
1635 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1636 flow_attr->port, qp->qp_num,
1637 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1642 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1643 struct ib_flow_attr *flow_attr,
1644 enum mlx4_net_trans_promisc_mode *type)
1648 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1649 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1650 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1654 if (flow_attr->num_of_specs == 0) {
1655 type[0] = MLX4_FS_MC_SNIFFER;
1656 type[1] = MLX4_FS_UC_SNIFFER;
1658 union ib_flow_spec *ib_spec;
1660 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1661 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1664 /* if all is zero than MC and UC */
1665 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1666 type[0] = MLX4_FS_MC_SNIFFER;
1667 type[1] = MLX4_FS_UC_SNIFFER;
1669 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1670 ib_spec->eth.mask.dst_mac[1],
1671 ib_spec->eth.mask.dst_mac[2],
1672 ib_spec->eth.mask.dst_mac[3],
1673 ib_spec->eth.mask.dst_mac[4],
1674 ib_spec->eth.mask.dst_mac[5]};
1676 /* Above xor was only on MC bit, non empty mask is valid
1677 * only if this bit is set and rest are zero.
1679 if (!is_zero_ether_addr(&mac[0]))
1682 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1683 type[0] = MLX4_FS_MC_SNIFFER;
1685 type[0] = MLX4_FS_UC_SNIFFER;
1692 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1693 struct ib_flow_attr *flow_attr,
1694 int domain, struct ib_udata *udata)
1696 int err = 0, i = 0, j = 0;
1697 struct mlx4_ib_flow *mflow;
1698 enum mlx4_net_trans_promisc_mode type[2];
1699 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1700 int is_bonded = mlx4_is_bonded(dev);
1702 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1703 return ERR_PTR(-EINVAL);
1705 if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
1706 return ERR_PTR(-EOPNOTSUPP);
1708 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1709 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1710 return ERR_PTR(-EOPNOTSUPP);
1713 udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
1714 return ERR_PTR(-EOPNOTSUPP);
1716 memset(type, 0, sizeof(type));
1718 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1724 switch (flow_attr->type) {
1725 case IB_FLOW_ATTR_NORMAL:
1726 /* If dont trap flag (continue match) is set, under specific
1727 * condition traffic be replicated to given qp,
1728 * without stealing it
1730 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1731 err = mlx4_ib_add_dont_trap_rule(dev,
1737 type[0] = MLX4_FS_REGULAR;
1741 case IB_FLOW_ATTR_ALL_DEFAULT:
1742 type[0] = MLX4_FS_ALL_DEFAULT;
1745 case IB_FLOW_ATTR_MC_DEFAULT:
1746 type[0] = MLX4_FS_MC_DEFAULT;
1749 case IB_FLOW_ATTR_SNIFFER:
1750 type[0] = MLX4_FS_MIRROR_RX_PORT;
1751 type[1] = MLX4_FS_MIRROR_SX_PORT;
1759 while (i < ARRAY_SIZE(type) && type[i]) {
1760 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1761 &mflow->reg_id[i].id);
1763 goto err_create_flow;
1765 /* Application always sees one port so the mirror rule
1766 * must be on port #2
1768 flow_attr->port = 2;
1769 err = __mlx4_ib_create_flow(qp, flow_attr,
1771 &mflow->reg_id[j].mirror);
1772 flow_attr->port = 1;
1774 goto err_create_flow;
1781 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1782 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1783 &mflow->reg_id[i].id);
1785 goto err_create_flow;
1788 flow_attr->port = 2;
1789 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1790 &mflow->reg_id[j].mirror);
1791 flow_attr->port = 1;
1793 goto err_create_flow;
1796 /* function to create mirror rule */
1800 return &mflow->ibflow;
1804 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1805 mflow->reg_id[i].id);
1810 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1811 mflow->reg_id[j].mirror);
1816 return ERR_PTR(err);
1819 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1823 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1824 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1826 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1827 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1830 if (mflow->reg_id[i].mirror) {
1831 err = __mlx4_ib_destroy_flow(mdev->dev,
1832 mflow->reg_id[i].mirror);
1843 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1846 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1847 struct mlx4_dev *dev = mdev->dev;
1848 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1849 struct mlx4_ib_steering *ib_steering = NULL;
1850 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1851 struct mlx4_flow_reg_id reg_id;
1853 if (mdev->dev->caps.steering_mode ==
1854 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1855 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1860 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1862 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1865 pr_err("multicast attach op failed, err %d\n", err);
1870 if (mlx4_is_bonded(dev)) {
1871 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1872 (mqp->port == 1) ? 2 : 1,
1874 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1875 prot, ®_id.mirror);
1880 err = add_gid_entry(ibqp, gid);
1885 memcpy(ib_steering->gid.raw, gid->raw, 16);
1886 ib_steering->reg_id = reg_id;
1887 mutex_lock(&mqp->mutex);
1888 list_add(&ib_steering->list, &mqp->steering_rules);
1889 mutex_unlock(&mqp->mutex);
1894 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1897 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1898 prot, reg_id.mirror);
1905 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1907 struct mlx4_ib_gid_entry *ge;
1908 struct mlx4_ib_gid_entry *tmp;
1909 struct mlx4_ib_gid_entry *ret = NULL;
1911 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1912 if (!memcmp(raw, ge->gid.raw, 16)) {
1921 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1924 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1925 struct mlx4_dev *dev = mdev->dev;
1926 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1927 struct net_device *ndev;
1928 struct mlx4_ib_gid_entry *ge;
1929 struct mlx4_flow_reg_id reg_id = {0, 0};
1930 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1932 if (mdev->dev->caps.steering_mode ==
1933 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1934 struct mlx4_ib_steering *ib_steering;
1936 mutex_lock(&mqp->mutex);
1937 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
1938 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
1939 list_del(&ib_steering->list);
1943 mutex_unlock(&mqp->mutex);
1944 if (&ib_steering->list == &mqp->steering_rules) {
1945 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
1948 reg_id = ib_steering->reg_id;
1952 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1957 if (mlx4_is_bonded(dev)) {
1958 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1959 prot, reg_id.mirror);
1964 mutex_lock(&mqp->mutex);
1965 ge = find_gid_entry(mqp, gid->raw);
1967 spin_lock_bh(&mdev->iboe.lock);
1968 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
1971 spin_unlock_bh(&mdev->iboe.lock);
1974 list_del(&ge->list);
1977 pr_warn("could not find mgid entry\n");
1979 mutex_unlock(&mqp->mutex);
1984 static int init_node_data(struct mlx4_ib_dev *dev)
1986 struct ib_smp *in_mad = NULL;
1987 struct ib_smp *out_mad = NULL;
1988 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
1991 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
1992 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1993 if (!in_mad || !out_mad)
1996 init_query_mad(in_mad);
1997 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
1998 if (mlx4_is_master(dev->dev))
1999 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2001 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2005 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2007 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2009 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2013 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2014 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2022 static ssize_t hca_type_show(struct device *device,
2023 struct device_attribute *attr, char *buf)
2025 struct mlx4_ib_dev *dev =
2026 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2027 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2029 static DEVICE_ATTR_RO(hca_type);
2031 static ssize_t hw_rev_show(struct device *device,
2032 struct device_attribute *attr, char *buf)
2034 struct mlx4_ib_dev *dev =
2035 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2036 return sprintf(buf, "%x\n", dev->dev->rev_id);
2038 static DEVICE_ATTR_RO(hw_rev);
2040 static ssize_t board_id_show(struct device *device,
2041 struct device_attribute *attr, char *buf)
2043 struct mlx4_ib_dev *dev =
2044 rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2046 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2047 dev->dev->board_id);
2049 static DEVICE_ATTR_RO(board_id);
2051 static struct attribute *mlx4_class_attributes[] = {
2052 &dev_attr_hw_rev.attr,
2053 &dev_attr_hca_type.attr,
2054 &dev_attr_board_id.attr,
2058 static const struct attribute_group mlx4_attr_group = {
2059 .attrs = mlx4_class_attributes,
2062 struct diag_counter {
2067 #define DIAG_COUNTER(_name, _offset) \
2068 { .name = #_name, .offset = _offset }
2070 static const struct diag_counter diag_basic[] = {
2071 DIAG_COUNTER(rq_num_lle, 0x00),
2072 DIAG_COUNTER(sq_num_lle, 0x04),
2073 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2074 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2075 DIAG_COUNTER(rq_num_lpe, 0x18),
2076 DIAG_COUNTER(sq_num_lpe, 0x1C),
2077 DIAG_COUNTER(rq_num_wrfe, 0x20),
2078 DIAG_COUNTER(sq_num_wrfe, 0x24),
2079 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2080 DIAG_COUNTER(sq_num_bre, 0x34),
2081 DIAG_COUNTER(sq_num_rire, 0x44),
2082 DIAG_COUNTER(rq_num_rire, 0x48),
2083 DIAG_COUNTER(sq_num_rae, 0x4C),
2084 DIAG_COUNTER(rq_num_rae, 0x50),
2085 DIAG_COUNTER(sq_num_roe, 0x54),
2086 DIAG_COUNTER(sq_num_tree, 0x5C),
2087 DIAG_COUNTER(sq_num_rree, 0x64),
2088 DIAG_COUNTER(rq_num_rnr, 0x68),
2089 DIAG_COUNTER(sq_num_rnr, 0x6C),
2090 DIAG_COUNTER(rq_num_oos, 0x100),
2091 DIAG_COUNTER(sq_num_oos, 0x104),
2094 static const struct diag_counter diag_ext[] = {
2095 DIAG_COUNTER(rq_num_dup, 0x130),
2096 DIAG_COUNTER(sq_num_to, 0x134),
2099 static const struct diag_counter diag_device_only[] = {
2100 DIAG_COUNTER(num_cqovf, 0x1A0),
2101 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2104 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2107 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2108 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2110 if (!diag[!!port_num].name)
2113 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2114 diag[!!port_num].num_counters,
2115 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2118 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2119 struct rdma_hw_stats *stats,
2122 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2123 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2124 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2125 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2129 ret = mlx4_query_diag_counters(dev->dev,
2130 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2131 diag[!!port].offset, hw_value,
2132 diag[!!port].num_counters, port);
2137 for (i = 0; i < diag[!!port].num_counters; i++)
2138 stats->value[i] = hw_value[i];
2140 return diag[!!port].num_counters;
2143 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2151 num_counters = ARRAY_SIZE(diag_basic);
2153 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2154 num_counters += ARRAY_SIZE(diag_ext);
2157 num_counters += ARRAY_SIZE(diag_device_only);
2159 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2163 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2167 *num = num_counters;
2176 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2184 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2185 name[i] = diag_basic[i].name;
2186 offset[i] = diag_basic[i].offset;
2189 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2190 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2191 name[j] = diag_ext[i].name;
2192 offset[j] = diag_ext[i].offset;
2197 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2198 name[j] = diag_device_only[i].name;
2199 offset[j] = diag_device_only[i].offset;
2204 static const struct ib_device_ops mlx4_ib_hw_stats_ops = {
2205 .alloc_hw_stats = mlx4_ib_alloc_hw_stats,
2206 .get_hw_stats = mlx4_ib_get_hw_stats,
2209 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2211 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2214 bool per_port = !!(ibdev->dev->caps.flags2 &
2215 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2217 if (mlx4_is_slave(ibdev->dev))
2220 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2221 /* i == 1 means we are building port counters */
2225 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2227 &diag[i].num_counters, i);
2231 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2235 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_hw_stats_ops);
2241 kfree(diag[i - 1].name);
2242 kfree(diag[i - 1].offset);
2248 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2252 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2253 kfree(ibdev->diag_counters[i].offset);
2254 kfree(ibdev->diag_counters[i].name);
2258 #define MLX4_IB_INVALID_MAC ((u64)-1)
2259 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2260 struct net_device *dev,
2264 u64 release_mac = MLX4_IB_INVALID_MAC;
2265 struct mlx4_ib_qp *qp;
2267 read_lock(&dev_base_lock);
2268 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2269 read_unlock(&dev_base_lock);
2271 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2273 /* no need for update QP1 and mac registration in non-SRIOV */
2274 if (!mlx4_is_mfunc(ibdev->dev))
2277 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2278 qp = ibdev->qp1_proxy[port - 1];
2282 struct mlx4_update_qp_params update_params;
2284 mutex_lock(&qp->mutex);
2285 old_smac = qp->pri.smac;
2286 if (new_smac == old_smac)
2289 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2291 if (new_smac_index < 0)
2294 update_params.smac_index = new_smac_index;
2295 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2297 release_mac = new_smac;
2300 /* if old port was zero, no mac was yet registered for this QP */
2301 if (qp->pri.smac_port)
2302 release_mac = old_smac;
2303 qp->pri.smac = new_smac;
2304 qp->pri.smac_port = port;
2305 qp->pri.smac_index = new_smac_index;
2309 if (release_mac != MLX4_IB_INVALID_MAC)
2310 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2312 mutex_unlock(&qp->mutex);
2313 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2316 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2317 struct net_device *dev,
2318 unsigned long event)
2321 struct mlx4_ib_iboe *iboe;
2322 int update_qps_port = -1;
2327 iboe = &ibdev->iboe;
2329 spin_lock_bh(&iboe->lock);
2330 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2332 iboe->netdevs[port - 1] =
2333 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2335 if (dev == iboe->netdevs[port - 1] &&
2336 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2337 event == NETDEV_UP || event == NETDEV_CHANGE))
2338 update_qps_port = port;
2340 if (dev == iboe->netdevs[port - 1] &&
2341 (event == NETDEV_UP || event == NETDEV_DOWN)) {
2342 enum ib_port_state port_state;
2343 struct ib_event ibev = { };
2345 if (ib_get_cached_port_state(&ibdev->ib_dev, port,
2349 if (event == NETDEV_UP &&
2350 (port_state != IB_PORT_ACTIVE ||
2351 iboe->last_port_state[port - 1] != IB_PORT_DOWN))
2353 if (event == NETDEV_DOWN &&
2354 (port_state != IB_PORT_DOWN ||
2355 iboe->last_port_state[port - 1] != IB_PORT_ACTIVE))
2357 iboe->last_port_state[port - 1] = port_state;
2359 ibev.device = &ibdev->ib_dev;
2360 ibev.element.port_num = port;
2361 ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE :
2363 ib_dispatch_event(&ibev);
2367 spin_unlock_bh(&iboe->lock);
2369 if (update_qps_port > 0)
2370 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2373 static int mlx4_ib_netdev_event(struct notifier_block *this,
2374 unsigned long event, void *ptr)
2376 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2377 struct mlx4_ib_dev *ibdev;
2379 if (!net_eq(dev_net(dev), &init_net))
2382 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2383 mlx4_ib_scan_netdevs(ibdev, dev, event);
2388 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2394 if (mlx4_is_master(ibdev->dev)) {
2395 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2397 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2399 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2401 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2402 /* master has the identity virt2phys pkey mapping */
2403 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2404 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2405 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2406 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2410 /* initialize pkey cache */
2411 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2413 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2415 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2421 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2423 int i, j, eq = 0, total_eqs = 0;
2425 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2426 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2427 if (!ibdev->eq_table)
2430 for (i = 1; i <= dev->caps.num_ports; i++) {
2431 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2433 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2435 ibdev->eq_table[eq] = total_eqs;
2436 if (!mlx4_assign_eq(dev, i,
2437 &ibdev->eq_table[eq]))
2440 ibdev->eq_table[eq] = -1;
2444 for (i = eq; i < dev->caps.num_comp_vectors;
2445 ibdev->eq_table[i++] = -1)
2448 /* Advertise the new number of EQs to clients */
2449 ibdev->ib_dev.num_comp_vectors = eq;
2452 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2455 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2457 /* no eqs were allocated */
2458 if (!ibdev->eq_table)
2461 /* Reset the advertised EQ number */
2462 ibdev->ib_dev.num_comp_vectors = 0;
2464 for (i = 0; i < total_eqs; i++)
2465 mlx4_release_eq(dev, ibdev->eq_table[i]);
2467 kfree(ibdev->eq_table);
2468 ibdev->eq_table = NULL;
2471 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2472 struct ib_port_immutable *immutable)
2474 struct ib_port_attr attr;
2475 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2478 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2479 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2480 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2482 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2483 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2484 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2485 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2486 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2487 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2488 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2489 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2490 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2493 err = ib_query_port(ibdev, port_num, &attr);
2497 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2498 immutable->gid_tbl_len = attr.gid_tbl_len;
2503 static void get_fw_ver_str(struct ib_device *device, char *str)
2505 struct mlx4_ib_dev *dev =
2506 container_of(device, struct mlx4_ib_dev, ib_dev);
2507 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
2508 (int) (dev->dev->caps.fw_ver >> 32),
2509 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2510 (int) dev->dev->caps.fw_ver & 0xffff);
2513 static const struct ib_device_ops mlx4_ib_dev_ops = {
2514 .owner = THIS_MODULE,
2515 .driver_id = RDMA_DRIVER_MLX4,
2516 .uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION,
2518 .add_gid = mlx4_ib_add_gid,
2519 .alloc_mr = mlx4_ib_alloc_mr,
2520 .alloc_pd = mlx4_ib_alloc_pd,
2521 .alloc_ucontext = mlx4_ib_alloc_ucontext,
2522 .attach_mcast = mlx4_ib_mcg_attach,
2523 .create_ah = mlx4_ib_create_ah,
2524 .create_cq = mlx4_ib_create_cq,
2525 .create_qp = mlx4_ib_create_qp,
2526 .create_srq = mlx4_ib_create_srq,
2527 .dealloc_pd = mlx4_ib_dealloc_pd,
2528 .dealloc_ucontext = mlx4_ib_dealloc_ucontext,
2529 .del_gid = mlx4_ib_del_gid,
2530 .dereg_mr = mlx4_ib_dereg_mr,
2531 .destroy_ah = mlx4_ib_destroy_ah,
2532 .destroy_cq = mlx4_ib_destroy_cq,
2533 .destroy_qp = mlx4_ib_destroy_qp,
2534 .destroy_srq = mlx4_ib_destroy_srq,
2535 .detach_mcast = mlx4_ib_mcg_detach,
2536 .disassociate_ucontext = mlx4_ib_disassociate_ucontext,
2537 .drain_rq = mlx4_ib_drain_rq,
2538 .drain_sq = mlx4_ib_drain_sq,
2539 .get_dev_fw_str = get_fw_ver_str,
2540 .get_dma_mr = mlx4_ib_get_dma_mr,
2541 .get_link_layer = mlx4_ib_port_link_layer,
2542 .get_netdev = mlx4_ib_get_netdev,
2543 .get_port_immutable = mlx4_port_immutable,
2544 .map_mr_sg = mlx4_ib_map_mr_sg,
2545 .mmap = mlx4_ib_mmap,
2546 .modify_cq = mlx4_ib_modify_cq,
2547 .modify_device = mlx4_ib_modify_device,
2548 .modify_port = mlx4_ib_modify_port,
2549 .modify_qp = mlx4_ib_modify_qp,
2550 .modify_srq = mlx4_ib_modify_srq,
2551 .poll_cq = mlx4_ib_poll_cq,
2552 .post_recv = mlx4_ib_post_recv,
2553 .post_send = mlx4_ib_post_send,
2554 .post_srq_recv = mlx4_ib_post_srq_recv,
2555 .process_mad = mlx4_ib_process_mad,
2556 .query_ah = mlx4_ib_query_ah,
2557 .query_device = mlx4_ib_query_device,
2558 .query_gid = mlx4_ib_query_gid,
2559 .query_pkey = mlx4_ib_query_pkey,
2560 .query_port = mlx4_ib_query_port,
2561 .query_qp = mlx4_ib_query_qp,
2562 .query_srq = mlx4_ib_query_srq,
2563 .reg_user_mr = mlx4_ib_reg_user_mr,
2564 .req_notify_cq = mlx4_ib_arm_cq,
2565 .rereg_user_mr = mlx4_ib_rereg_user_mr,
2566 .resize_cq = mlx4_ib_resize_cq,
2568 INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah),
2569 INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq),
2570 INIT_RDMA_OBJ_SIZE(ib_pd, mlx4_ib_pd, ibpd),
2571 INIT_RDMA_OBJ_SIZE(ib_srq, mlx4_ib_srq, ibsrq),
2572 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx4_ib_ucontext, ibucontext),
2575 static const struct ib_device_ops mlx4_ib_dev_wq_ops = {
2576 .create_rwq_ind_table = mlx4_ib_create_rwq_ind_table,
2577 .create_wq = mlx4_ib_create_wq,
2578 .destroy_rwq_ind_table = mlx4_ib_destroy_rwq_ind_table,
2579 .destroy_wq = mlx4_ib_destroy_wq,
2580 .modify_wq = mlx4_ib_modify_wq,
2583 static const struct ib_device_ops mlx4_ib_dev_fmr_ops = {
2584 .alloc_fmr = mlx4_ib_fmr_alloc,
2585 .dealloc_fmr = mlx4_ib_fmr_dealloc,
2586 .map_phys_fmr = mlx4_ib_map_phys_fmr,
2587 .unmap_fmr = mlx4_ib_unmap_fmr,
2590 static const struct ib_device_ops mlx4_ib_dev_mw_ops = {
2591 .alloc_mw = mlx4_ib_alloc_mw,
2592 .dealloc_mw = mlx4_ib_dealloc_mw,
2595 static const struct ib_device_ops mlx4_ib_dev_xrc_ops = {
2596 .alloc_xrcd = mlx4_ib_alloc_xrcd,
2597 .dealloc_xrcd = mlx4_ib_dealloc_xrcd,
2600 static const struct ib_device_ops mlx4_ib_dev_fs_ops = {
2601 .create_flow = mlx4_ib_create_flow,
2602 .destroy_flow = mlx4_ib_destroy_flow,
2605 static void *mlx4_ib_add(struct mlx4_dev *dev)
2607 struct mlx4_ib_dev *ibdev;
2611 struct mlx4_ib_iboe *iboe;
2612 int ib_num_ports = 0;
2613 int num_req_counters;
2616 struct counter_index *new_counter_index = NULL;
2618 pr_info_once("%s", mlx4_ib_version);
2621 mlx4_foreach_ib_transport_port(i, dev)
2624 /* No point in registering a device with no ports... */
2628 ibdev = ib_alloc_device(mlx4_ib_dev, ib_dev);
2630 dev_err(&dev->persist->pdev->dev,
2631 "Device struct alloc failed\n");
2635 iboe = &ibdev->iboe;
2637 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2640 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2643 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2645 if (!ibdev->uar_map)
2647 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2650 ibdev->bond_next_port = 0;
2652 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2653 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2654 ibdev->num_ports = num_ports;
2655 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2656 1 : ibdev->num_ports;
2657 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2658 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
2660 ibdev->ib_dev.uverbs_cmd_mask =
2661 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2662 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2663 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2664 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2665 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2666 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2667 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2668 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2669 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2670 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2671 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2672 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2673 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2674 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2675 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2676 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2677 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2678 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2679 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2680 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2681 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2682 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2683 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2684 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2686 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_ops);
2687 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2688 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
2689 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2690 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2691 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2693 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2694 ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2695 IB_LINK_LAYER_ETHERNET) ||
2696 (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2697 IB_LINK_LAYER_ETHERNET))) {
2698 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2699 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2700 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2701 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2702 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2703 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
2704 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_wq_ops);
2707 if (!mlx4_is_slave(ibdev->dev))
2708 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fmr_ops);
2710 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2711 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2712 ibdev->ib_dev.uverbs_cmd_mask |=
2713 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2714 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2715 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_mw_ops);
2718 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2719 ibdev->ib_dev.uverbs_cmd_mask |=
2720 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2721 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2722 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_xrc_ops);
2725 if (check_flow_steering_support(dev)) {
2726 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2727 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2728 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2729 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2730 ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fs_ops);
2733 if (!dev->caps.userspace_caps)
2734 ibdev->ib_dev.ops.uverbs_abi_ver =
2735 MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2737 mlx4_ib_alloc_eqs(dev, ibdev);
2739 spin_lock_init(&iboe->lock);
2741 if (init_node_data(ibdev))
2743 mlx4_init_sl2vl_tbl(ibdev);
2745 for (i = 0; i < ibdev->num_ports; ++i) {
2746 mutex_init(&ibdev->counters_table[i].mutex);
2747 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2748 iboe->last_port_state[i] = IB_PORT_DOWN;
2751 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2752 for (i = 0; i < num_req_counters; ++i) {
2753 mutex_init(&ibdev->qp1_proxy_lock[i]);
2755 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2756 IB_LINK_LAYER_ETHERNET) {
2757 err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2758 MLX4_RES_USAGE_DRIVER);
2759 /* if failed to allocate a new counter, use default */
2762 mlx4_get_default_counter_index(dev,
2766 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2767 counter_index = mlx4_get_default_counter_index(dev,
2770 new_counter_index = kmalloc(sizeof(*new_counter_index),
2772 if (!new_counter_index) {
2774 mlx4_counter_free(ibdev->dev, counter_index);
2777 new_counter_index->index = counter_index;
2778 new_counter_index->allocated = allocated;
2779 list_add_tail(&new_counter_index->list,
2780 &ibdev->counters_table[i].counters_list);
2781 ibdev->counters_table[i].default_counter = counter_index;
2782 pr_info("counter index %d for port %d allocated %d\n",
2783 counter_index, i + 1, allocated);
2785 if (mlx4_is_bonded(dev))
2786 for (i = 1; i < ibdev->num_ports ; ++i) {
2788 kmalloc(sizeof(struct counter_index),
2790 if (!new_counter_index)
2792 new_counter_index->index = counter_index;
2793 new_counter_index->allocated = 0;
2794 list_add_tail(&new_counter_index->list,
2795 &ibdev->counters_table[i].counters_list);
2796 ibdev->counters_table[i].default_counter =
2800 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2803 spin_lock_init(&ibdev->sm_lock);
2804 mutex_init(&ibdev->cap_mask_mutex);
2805 INIT_LIST_HEAD(&ibdev->qp_list);
2806 spin_lock_init(&ibdev->reset_flow_resource_lock);
2808 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2810 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2811 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2812 MLX4_IB_UC_STEER_QPN_ALIGN,
2813 &ibdev->steer_qpn_base, 0,
2814 MLX4_RES_USAGE_DRIVER);
2818 ibdev->ib_uc_qpns_bitmap =
2819 kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
2822 if (!ibdev->ib_uc_qpns_bitmap)
2823 goto err_steer_qp_release;
2825 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2826 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2827 ibdev->steer_qpn_count);
2828 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2829 dev, ibdev->steer_qpn_base,
2830 ibdev->steer_qpn_base +
2831 ibdev->steer_qpn_count - 1);
2833 goto err_steer_free_bitmap;
2835 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2836 ibdev->steer_qpn_count);
2840 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2841 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2843 if (mlx4_ib_alloc_diag_counters(ibdev))
2844 goto err_steer_free_bitmap;
2846 rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group);
2847 if (ib_register_device(&ibdev->ib_dev, "mlx4_%d"))
2848 goto err_diag_counters;
2850 if (mlx4_ib_mad_init(ibdev))
2853 if (mlx4_ib_init_sriov(ibdev))
2856 if (!iboe->nb.notifier_call) {
2857 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2858 err = register_netdevice_notifier(&iboe->nb);
2860 iboe->nb.notifier_call = NULL;
2864 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2865 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2870 ibdev->ib_active = true;
2871 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2872 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2875 if (mlx4_is_mfunc(ibdev->dev))
2878 /* create paravirt contexts for any VFs which are active */
2879 if (mlx4_is_master(ibdev->dev)) {
2880 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2881 if (j == mlx4_master_func_num(ibdev->dev))
2883 if (mlx4_is_slave_active(ibdev->dev, j))
2884 do_slave_init(ibdev, j, 1);
2890 if (ibdev->iboe.nb.notifier_call) {
2891 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2892 pr_warn("failure unregistering notifier\n");
2893 ibdev->iboe.nb.notifier_call = NULL;
2895 flush_workqueue(wq);
2897 mlx4_ib_close_sriov(ibdev);
2900 mlx4_ib_mad_cleanup(ibdev);
2903 ib_unregister_device(&ibdev->ib_dev);
2906 mlx4_ib_diag_cleanup(ibdev);
2908 err_steer_free_bitmap:
2909 kfree(ibdev->ib_uc_qpns_bitmap);
2911 err_steer_qp_release:
2912 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2913 ibdev->steer_qpn_count);
2915 for (i = 0; i < ibdev->num_ports; ++i)
2916 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2919 mlx4_ib_free_eqs(dev, ibdev);
2920 iounmap(ibdev->uar_map);
2923 mlx4_uar_free(dev, &ibdev->priv_uar);
2926 mlx4_pd_free(dev, ibdev->priv_pdn);
2929 ib_dealloc_device(&ibdev->ib_dev);
2934 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2938 WARN_ON(!dev->ib_uc_qpns_bitmap);
2940 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2941 dev->steer_qpn_count,
2942 get_count_order(count));
2946 *qpn = dev->steer_qpn_base + offset;
2950 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2953 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2956 if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
2957 qpn, dev->steer_qpn_base))
2958 /* not supposed to be here */
2961 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2962 qpn - dev->steer_qpn_base,
2963 get_count_order(count));
2966 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2971 struct ib_flow_attr *flow = NULL;
2972 struct ib_flow_spec_ib *ib_spec;
2975 flow_size = sizeof(struct ib_flow_attr) +
2976 sizeof(struct ib_flow_spec_ib);
2977 flow = kzalloc(flow_size, GFP_KERNEL);
2980 flow->port = mqp->port;
2981 flow->num_of_specs = 1;
2982 flow->size = flow_size;
2983 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2984 ib_spec->type = IB_FLOW_SPEC_IB;
2985 ib_spec->size = sizeof(struct ib_flow_spec_ib);
2986 /* Add an empty rule for IB L2 */
2987 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2989 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
2994 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3000 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3002 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3006 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3007 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3008 ibdev->ib_active = false;
3009 flush_workqueue(wq);
3011 mlx4_ib_close_sriov(ibdev);
3012 mlx4_ib_mad_cleanup(ibdev);
3013 ib_unregister_device(&ibdev->ib_dev);
3014 mlx4_ib_diag_cleanup(ibdev);
3015 if (ibdev->iboe.nb.notifier_call) {
3016 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3017 pr_warn("failure unregistering notifier\n");
3018 ibdev->iboe.nb.notifier_call = NULL;
3021 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3022 ibdev->steer_qpn_count);
3023 kfree(ibdev->ib_uc_qpns_bitmap);
3025 iounmap(ibdev->uar_map);
3026 for (p = 0; p < ibdev->num_ports; ++p)
3027 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3029 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3030 mlx4_CLOSE_PORT(dev, p);
3032 mlx4_ib_free_eqs(dev, ibdev);
3034 mlx4_uar_free(dev, &ibdev->priv_uar);
3035 mlx4_pd_free(dev, ibdev->priv_pdn);
3036 ib_dealloc_device(&ibdev->ib_dev);
3039 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3041 struct mlx4_ib_demux_work **dm = NULL;
3042 struct mlx4_dev *dev = ibdev->dev;
3044 unsigned long flags;
3045 struct mlx4_active_ports actv_ports;
3047 unsigned int first_port;
3049 if (!mlx4_is_master(dev))
3052 actv_ports = mlx4_get_active_ports(dev, slave);
3053 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3054 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3056 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3060 for (i = 0; i < ports; i++) {
3061 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3067 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3068 dm[i]->port = first_port + i + 1;
3069 dm[i]->slave = slave;
3070 dm[i]->do_init = do_init;
3073 /* initialize or tear down tunnel QPs for the slave */
3074 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3075 if (!ibdev->sriov.is_going_down) {
3076 for (i = 0; i < ports; i++)
3077 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3078 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3080 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3081 for (i = 0; i < ports; i++)
3089 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3091 struct mlx4_ib_qp *mqp;
3092 unsigned long flags_qp;
3093 unsigned long flags_cq;
3094 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3095 struct list_head cq_notify_list;
3096 struct mlx4_cq *mcq;
3097 unsigned long flags;
3099 pr_warn("mlx4_ib_handle_catas_error was started\n");
3100 INIT_LIST_HEAD(&cq_notify_list);
3102 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3103 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3105 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3106 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3107 if (mqp->sq.tail != mqp->sq.head) {
3108 send_mcq = to_mcq(mqp->ibqp.send_cq);
3109 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3110 if (send_mcq->mcq.comp &&
3111 mqp->ibqp.send_cq->comp_handler) {
3112 if (!send_mcq->mcq.reset_notify_added) {
3113 send_mcq->mcq.reset_notify_added = 1;
3114 list_add_tail(&send_mcq->mcq.reset_notify,
3118 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3120 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3121 /* Now, handle the QP's receive queue */
3122 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3123 /* no handling is needed for SRQ */
3124 if (!mqp->ibqp.srq) {
3125 if (mqp->rq.tail != mqp->rq.head) {
3126 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3127 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3128 if (recv_mcq->mcq.comp &&
3129 mqp->ibqp.recv_cq->comp_handler) {
3130 if (!recv_mcq->mcq.reset_notify_added) {
3131 recv_mcq->mcq.reset_notify_added = 1;
3132 list_add_tail(&recv_mcq->mcq.reset_notify,
3136 spin_unlock_irqrestore(&recv_mcq->lock,
3140 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3143 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3146 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3147 pr_warn("mlx4_ib_handle_catas_error ended\n");
3150 static void handle_bonded_port_state_event(struct work_struct *work)
3152 struct ib_event_work *ew =
3153 container_of(work, struct ib_event_work, work);
3154 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3155 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3157 struct ib_event ibev;
3160 spin_lock_bh(&ibdev->iboe.lock);
3161 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3162 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3163 enum ib_port_state curr_port_state;
3169 (netif_running(curr_netdev) &&
3170 netif_carrier_ok(curr_netdev)) ?
3171 IB_PORT_ACTIVE : IB_PORT_DOWN;
3173 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3174 curr_port_state : IB_PORT_ACTIVE;
3176 spin_unlock_bh(&ibdev->iboe.lock);
3178 ibev.device = &ibdev->ib_dev;
3179 ibev.element.port_num = 1;
3180 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3181 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3183 ib_dispatch_event(&ibev);
3186 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3191 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3193 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3197 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3200 static void ib_sl2vl_update_work(struct work_struct *work)
3202 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3203 struct mlx4_ib_dev *mdev = ew->ib_dev;
3204 int port = ew->port;
3206 mlx4_ib_sl2vl_update(mdev, port);
3211 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3214 struct ib_event_work *ew;
3216 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3218 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3221 queue_work(wq, &ew->work);
3225 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3226 enum mlx4_dev_event event, unsigned long param)
3228 struct ib_event ibev;
3229 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3230 struct mlx4_eqe *eqe = NULL;
3231 struct ib_event_work *ew;
3234 if (mlx4_is_bonded(dev) &&
3235 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3236 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3237 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3240 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3242 queue_work(wq, &ew->work);
3246 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3247 eqe = (struct mlx4_eqe *)param;
3252 case MLX4_DEV_EVENT_PORT_UP:
3253 if (p > ibdev->num_ports)
3255 if (!mlx4_is_slave(dev) &&
3256 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3257 IB_LINK_LAYER_INFINIBAND) {
3258 if (mlx4_is_master(dev))
3259 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3260 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3261 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3262 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3264 ibev.event = IB_EVENT_PORT_ACTIVE;
3267 case MLX4_DEV_EVENT_PORT_DOWN:
3268 if (p > ibdev->num_ports)
3270 ibev.event = IB_EVENT_PORT_ERR;
3273 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3274 ibdev->ib_active = false;
3275 ibev.event = IB_EVENT_DEVICE_FATAL;
3276 mlx4_ib_handle_catas_error(ibdev);
3279 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3280 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3284 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3285 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3287 /* need to queue only for port owner, which uses GEN_EQE */
3288 if (mlx4_is_master(dev))
3289 queue_work(wq, &ew->work);
3291 handle_port_mgmt_change_event(&ew->work);
3294 case MLX4_DEV_EVENT_SLAVE_INIT:
3295 /* here, p is the slave id */
3296 do_slave_init(ibdev, p, 1);
3297 if (mlx4_is_master(dev)) {
3300 for (i = 1; i <= ibdev->num_ports; i++) {
3301 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3302 == IB_LINK_LAYER_INFINIBAND)
3303 mlx4_ib_slave_alias_guid_event(ibdev,
3310 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3311 if (mlx4_is_master(dev)) {
3314 for (i = 1; i <= ibdev->num_ports; i++) {
3315 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3316 == IB_LINK_LAYER_INFINIBAND)
3317 mlx4_ib_slave_alias_guid_event(ibdev,
3322 /* here, p is the slave id */
3323 do_slave_init(ibdev, p, 0);
3330 ibev.device = ibdev_ptr;
3331 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3333 ib_dispatch_event(&ibev);
3336 static struct mlx4_interface mlx4_ib_interface = {
3338 .remove = mlx4_ib_remove,
3339 .event = mlx4_ib_event,
3340 .protocol = MLX4_PROT_IB_IPV6,
3341 .flags = MLX4_INTFF_BONDING
3344 static int __init mlx4_ib_init(void)
3348 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3352 err = mlx4_ib_mcg_init();
3356 err = mlx4_register_interface(&mlx4_ib_interface);
3363 mlx4_ib_mcg_destroy();
3366 destroy_workqueue(wq);
3370 static void __exit mlx4_ib_cleanup(void)
3372 mlx4_unregister_interface(&mlx4_ib_interface);
3373 mlx4_ib_mcg_destroy();
3374 destroy_workqueue(wq);
3377 module_init(mlx4_ib_init);
3378 module_exit(mlx4_ib_cleanup);