drivers/clk/meson/meson8b.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <[email protected]>
   5  *
   6  * Copyright (c) 2016 BayLibre, Inc.
   7  * Michael Turquette <[email protected]>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/init.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of_address.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17 #include <linux/regmap.h>
  18
  19 #include "meson8b.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-mpll.h"
  23
  24 static DEFINE_SPINLOCK(meson_clk_lock);
  25
  26 struct meson8b_clk_reset {
  27         struct reset_controller_dev reset;
  28         struct regmap *regmap;
  29 };
  30
  31 static const struct pll_params_table sys_pll_params_table[] = {
  32         PLL_PARAMS(50, 1),
  33         PLL_PARAMS(51, 1),
  34         PLL_PARAMS(52, 1),
  35         PLL_PARAMS(53, 1),
  36         PLL_PARAMS(54, 1),
  37         PLL_PARAMS(55, 1),
  38         PLL_PARAMS(56, 1),
  39         PLL_PARAMS(57, 1),
  40         PLL_PARAMS(58, 1),
  41         PLL_PARAMS(59, 1),
  42         PLL_PARAMS(60, 1),
  43         PLL_PARAMS(61, 1),
  44         PLL_PARAMS(62, 1),
  45         PLL_PARAMS(63, 1),
  46         PLL_PARAMS(64, 1),
  47         PLL_PARAMS(65, 1),
  48         PLL_PARAMS(66, 1),
  49         PLL_PARAMS(67, 1),
  50         PLL_PARAMS(68, 1),
  51         PLL_PARAMS(84, 1),
  52         { /* sentinel */ },
  53 };
  54
  55 static struct clk_fixed_rate meson8b_xtal = {
  56         .fixed_rate = 24000000,
  57         .hw.init = &(struct clk_init_data){
  58                 .name = "xtal",
  59                 .num_parents = 0,
  60                 .ops = &clk_fixed_rate_ops,
  61         },
  62 };
  63
  64 static struct clk_regmap meson8b_fixed_pll_dco = {
  65         .data = &(struct meson_clk_pll_data){
  66                 .en = {
  67                         .reg_off = HHI_MPLL_CNTL,
  68                         .shift   = 30,
  69                         .width   = 1,
  70                 },
  71                 .m = {
  72                         .reg_off = HHI_MPLL_CNTL,
  73                         .shift   = 0,
  74                         .width   = 9,
  75                 },
  76                 .n = {
  77                         .reg_off = HHI_MPLL_CNTL,
  78                         .shift   = 9,
  79                         .width   = 5,
  80                 },
  81                 .frac = {
  82                         .reg_off = HHI_MPLL_CNTL2,
  83                         .shift   = 0,
  84                         .width   = 12,
  85                 },
  86                 .l = {
  87                         .reg_off = HHI_MPLL_CNTL,
  88                         .shift   = 31,
  89                         .width   = 1,
  90                 },
  91                 .rst = {
  92                         .reg_off = HHI_MPLL_CNTL,
  93                         .shift   = 29,
  94                         .width   = 1,
  95                 },
  96         },
  97         .hw.init = &(struct clk_init_data){
  98                 .name = "fixed_pll_dco",
  99                 .ops = &meson_clk_pll_ro_ops,
 100                 .parent_hws = (const struct clk_hw *[]) {
 101                         &meson8b_xtal.hw
 102                 },
 103                 .num_parents = 1,
 104         },
 105 };
 106
 107 static struct clk_regmap meson8b_fixed_pll = {
 108         .data = &(struct clk_regmap_div_data){
 109                 .offset = HHI_MPLL_CNTL,
 110                 .shift = 16,
 111                 .width = 2,
 112                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 113         },
 114         .hw.init = &(struct clk_init_data){
 115                 .name = "fixed_pll",
 116                 .ops = &clk_regmap_divider_ro_ops,
 117                 .parent_hws = (const struct clk_hw *[]) {
 118                         &meson8b_fixed_pll_dco.hw
 119                 },
 120                 .num_parents = 1,
 121                 /*
 122                  * This clock won't ever change at runtime so
 123                  * CLK_SET_RATE_PARENT is not required
 124                  */
 125         },
 126 };
 127
 128 static struct clk_regmap meson8b_hdmi_pll_dco = {
 129         .data = &(struct meson_clk_pll_data){
 130                 .en = {
 131                         .reg_off = HHI_VID_PLL_CNTL,
 132                         .shift   = 30,
 133                         .width   = 1,
 134                 },
 135                 .m = {
 136                         .reg_off = HHI_VID_PLL_CNTL,
 137                         .shift   = 0,
 138                         .width   = 9,
 139                 },
 140                 .n = {
 141                         .reg_off = HHI_VID_PLL_CNTL,
 142                         .shift   = 10,
 143                         .width   = 5,
 144                 },
 145                 .frac = {
 146                         .reg_off = HHI_VID_PLL_CNTL2,
 147                         .shift   = 0,
 148                         .width   = 12,
 149                 },
 150                 .l = {
 151                         .reg_off = HHI_VID_PLL_CNTL,
 152                         .shift   = 31,
 153                         .width   = 1,
 154                 },
 155                 .rst = {
 156                         .reg_off = HHI_VID_PLL_CNTL,
 157                         .shift   = 29,
 158                         .width   = 1,
 159                 },
 160         },
 161         .hw.init = &(struct clk_init_data){
 162                 /* sometimes also called "HPLL" or "HPLL PLL" */
 163                 .name = "hdmi_pll_dco",
 164                 .ops = &meson_clk_pll_ro_ops,
 165                 .parent_hws = (const struct clk_hw *[]) {
 166                         &meson8b_xtal.hw
 167                 },
 168                 .num_parents = 1,
 169         },
 170 };
 171
 172 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
 173         .data = &(struct clk_regmap_div_data){
 174                 .offset = HHI_VID_PLL_CNTL,
 175                 .shift = 16,
 176                 .width = 2,
 177                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 178         },
 179         .hw.init = &(struct clk_init_data){
 180                 .name = "hdmi_pll_lvds_out",
 181                 .ops = &clk_regmap_divider_ro_ops,
 182                 .parent_hws = (const struct clk_hw *[]) {
 183                         &meson8b_hdmi_pll_dco.hw
 184                 },
 185                 .num_parents = 1,
 186                 .flags = CLK_SET_RATE_PARENT,
 187         },
 188 };
 189
 190 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
 191         .data = &(struct clk_regmap_div_data){
 192                 .offset = HHI_VID_PLL_CNTL,
 193                 .shift = 18,
 194                 .width = 2,
 195                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 196         },
 197         .hw.init = &(struct clk_init_data){
 198                 .name = "hdmi_pll_hdmi_out",
 199                 .ops = &clk_regmap_divider_ro_ops,
 200                 .parent_hws = (const struct clk_hw *[]) {
 201                         &meson8b_hdmi_pll_dco.hw
 202                 },
 203                 .num_parents = 1,
 204                 .flags = CLK_SET_RATE_PARENT,
 205         },
 206 };
 207
 208 static struct clk_regmap meson8b_sys_pll_dco = {
 209         .data = &(struct meson_clk_pll_data){
 210                 .en = {
 211                         .reg_off = HHI_SYS_PLL_CNTL,
 212                         .shift   = 30,
 213                         .width   = 1,
 214                 },
 215                 .m = {
 216                         .reg_off = HHI_SYS_PLL_CNTL,
 217                         .shift   = 0,
 218                         .width   = 9,
 219                 },
 220                 .n = {
 221                         .reg_off = HHI_SYS_PLL_CNTL,
 222                         .shift   = 9,
 223                         .width   = 5,
 224                 },
 225                 .l = {
 226                         .reg_off = HHI_SYS_PLL_CNTL,
 227                         .shift   = 31,
 228                         .width   = 1,
 229                 },
 230                 .rst = {
 231                         .reg_off = HHI_SYS_PLL_CNTL,
 232                         .shift   = 29,
 233                         .width   = 1,
 234                 },
 235                 .table = sys_pll_params_table,
 236         },
 237         .hw.init = &(struct clk_init_data){
 238                 .name = "sys_pll_dco",
 239                 .ops = &meson_clk_pll_ops,
 240                 .parent_hws = (const struct clk_hw *[]) {
 241                         &meson8b_xtal.hw
 242                 },
 243                 .num_parents = 1,
 244         },
 245 };
 246
 247 static struct clk_regmap meson8b_sys_pll = {
 248         .data = &(struct clk_regmap_div_data){
 249                 .offset = HHI_SYS_PLL_CNTL,
 250                 .shift = 16,
 251                 .width = 2,
 252                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 253         },
 254         .hw.init = &(struct clk_init_data){
 255                 .name = "sys_pll",
 256                 .ops = &clk_regmap_divider_ops,
 257                 .parent_hws = (const struct clk_hw *[]) {
 258                         &meson8b_sys_pll_dco.hw
 259                 },
 260                 .num_parents = 1,
 261                 .flags = CLK_SET_RATE_PARENT,
 262         },
 263 };
 264
 265 static struct clk_fixed_factor meson8b_fclk_div2_div = {
 266         .mult = 1,
 267         .div = 2,
 268         .hw.init = &(struct clk_init_data){
 269                 .name = "fclk_div2_div",
 270                 .ops = &clk_fixed_factor_ops,
 271                 .parent_hws = (const struct clk_hw *[]) {
 272                         &meson8b_fixed_pll.hw
 273                 },
 274                 .num_parents = 1,
 275         },
 276 };
 277
 278 static struct clk_regmap meson8b_fclk_div2 = {
 279         .data = &(struct clk_regmap_gate_data){
 280                 .offset = HHI_MPLL_CNTL6,
 281                 .bit_idx = 27,
 282         },
 283         .hw.init = &(struct clk_init_data){
 284                 .name = "fclk_div2",
 285                 .ops = &clk_regmap_gate_ops,
 286                 .parent_hws = (const struct clk_hw *[]) {
 287                         &meson8b_fclk_div2_div.hw
 288                 },
 289                 .num_parents = 1,
 290                 /*
 291                  * FIXME: Ethernet with a RGMII PHYs is not working if
 292                  * fclk_div2 is disabled. it is currently unclear why this
 293                  * is. keep it enabled until the Ethernet driver knows how
 294                  * to manage this clock.
 295                  */
 296                 .flags = CLK_IS_CRITICAL,
 297         },
 298 };
 299
 300 static struct clk_fixed_factor meson8b_fclk_div3_div = {
 301         .mult = 1,
 302         .div = 3,
 303         .hw.init = &(struct clk_init_data){
 304                 .name = "fclk_div3_div",
 305                 .ops = &clk_fixed_factor_ops,
 306                 .parent_hws = (const struct clk_hw *[]) {
 307                         &meson8b_fixed_pll.hw
 308                 },
 309                 .num_parents = 1,
 310         },
 311 };
 312
 313 static struct clk_regmap meson8b_fclk_div3 = {
 314         .data = &(struct clk_regmap_gate_data){
 315                 .offset = HHI_MPLL_CNTL6,
 316                 .bit_idx = 28,
 317         },
 318         .hw.init = &(struct clk_init_data){
 319                 .name = "fclk_div3",
 320                 .ops = &clk_regmap_gate_ops,
 321                 .parent_hws = (const struct clk_hw *[]) {
 322                         &meson8b_fclk_div3_div.hw
 323                 },
 324                 .num_parents = 1,
 325         },
 326 };
 327
 328 static struct clk_fixed_factor meson8b_fclk_div4_div = {
 329         .mult = 1,
 330         .div = 4,
 331         .hw.init = &(struct clk_init_data){
 332                 .name = "fclk_div4_div",
 333                 .ops = &clk_fixed_factor_ops,
 334                 .parent_hws = (const struct clk_hw *[]) {
 335                         &meson8b_fixed_pll.hw
 336                 },
 337                 .num_parents = 1,
 338         },
 339 };
 340
 341 static struct clk_regmap meson8b_fclk_div4 = {
 342         .data = &(struct clk_regmap_gate_data){
 343                 .offset = HHI_MPLL_CNTL6,
 344                 .bit_idx = 29,
 345         },
 346         .hw.init = &(struct clk_init_data){
 347                 .name = "fclk_div4",
 348                 .ops = &clk_regmap_gate_ops,
 349                 .parent_hws = (const struct clk_hw *[]) {
 350                         &meson8b_fclk_div4_div.hw
 351                 },
 352                 .num_parents = 1,
 353         },
 354 };
 355
 356 static struct clk_fixed_factor meson8b_fclk_div5_div = {
 357         .mult = 1,
 358         .div = 5,
 359         .hw.init = &(struct clk_init_data){
 360                 .name = "fclk_div5_div",
 361                 .ops = &clk_fixed_factor_ops,
 362                 .parent_hws = (const struct clk_hw *[]) {
 363                         &meson8b_fixed_pll.hw
 364                 },
 365                 .num_parents = 1,
 366         },
 367 };
 368
 369 static struct clk_regmap meson8b_fclk_div5 = {
 370         .data = &(struct clk_regmap_gate_data){
 371                 .offset = HHI_MPLL_CNTL6,
 372                 .bit_idx = 30,
 373         },
 374         .hw.init = &(struct clk_init_data){
 375                 .name = "fclk_div5",
 376                 .ops = &clk_regmap_gate_ops,
 377                 .parent_hws = (const struct clk_hw *[]) {
 378                         &meson8b_fclk_div5_div.hw
 379                 },
 380                 .num_parents = 1,
 381         },
 382 };
 383
 384 static struct clk_fixed_factor meson8b_fclk_div7_div = {
 385         .mult = 1,
 386         .div = 7,
 387         .hw.init = &(struct clk_init_data){
 388                 .name = "fclk_div7_div",
 389                 .ops = &clk_fixed_factor_ops,
 390                 .parent_hws = (const struct clk_hw *[]) {
 391                         &meson8b_fixed_pll.hw
 392                 },
 393                 .num_parents = 1,
 394         },
 395 };
 396
 397 static struct clk_regmap meson8b_fclk_div7 = {
 398         .data = &(struct clk_regmap_gate_data){
 399                 .offset = HHI_MPLL_CNTL6,
 400                 .bit_idx = 31,
 401         },
 402         .hw.init = &(struct clk_init_data){
 403                 .name = "fclk_div7",
 404                 .ops = &clk_regmap_gate_ops,
 405                 .parent_hws = (const struct clk_hw *[]) {
 406                         &meson8b_fclk_div7_div.hw
 407                 },
 408                 .num_parents = 1,
 409         },
 410 };
 411
 412 static struct clk_regmap meson8b_mpll_prediv = {
 413         .data = &(struct clk_regmap_div_data){
 414                 .offset = HHI_MPLL_CNTL5,
 415                 .shift = 12,
 416                 .width = 1,
 417         },
 418         .hw.init = &(struct clk_init_data){
 419                 .name = "mpll_prediv",
 420                 .ops = &clk_regmap_divider_ro_ops,
 421                 .parent_hws = (const struct clk_hw *[]) {
 422                         &meson8b_fixed_pll.hw
 423                 },
 424                 .num_parents = 1,
 425         },
 426 };
 427
 428 static struct clk_regmap meson8b_mpll0_div = {
 429         .data = &(struct meson_clk_mpll_data){
 430                 .sdm = {
 431                         .reg_off = HHI_MPLL_CNTL7,
 432                         .shift   = 0,
 433                         .width   = 14,
 434                 },
 435                 .sdm_en = {
 436                         .reg_off = HHI_MPLL_CNTL7,
 437                         .shift   = 15,
 438                         .width   = 1,
 439                 },
 440                 .n2 = {
 441                         .reg_off = HHI_MPLL_CNTL7,
 442                         .shift   = 16,
 443                         .width   = 9,
 444                 },
 445                 .ssen = {
 446                         .reg_off = HHI_MPLL_CNTL,
 447                         .shift   = 25,
 448                         .width   = 1,
 449                 },
 450                 .lock = &meson_clk_lock,
 451         },
 452         .hw.init = &(struct clk_init_data){
 453                 .name = "mpll0_div",
 454                 .ops = &meson_clk_mpll_ops,
 455                 .parent_hws = (const struct clk_hw *[]) {
 456                         &meson8b_mpll_prediv.hw
 457                 },
 458                 .num_parents = 1,
 459         },
 460 };
 461
 462 static struct clk_regmap meson8b_mpll0 = {
 463         .data = &(struct clk_regmap_gate_data){
 464                 .offset = HHI_MPLL_CNTL7,
 465                 .bit_idx = 14,
 466         },
 467         .hw.init = &(struct clk_init_data){
 468                 .name = "mpll0",
 469                 .ops = &clk_regmap_gate_ops,
 470                 .parent_hws = (const struct clk_hw *[]) {
 471                         &meson8b_mpll0_div.hw
 472                 },
 473                 .num_parents = 1,
 474                 .flags = CLK_SET_RATE_PARENT,
 475         },
 476 };
 477
 478 static struct clk_regmap meson8b_mpll1_div = {
 479         .data = &(struct meson_clk_mpll_data){
 480                 .sdm = {
 481                         .reg_off = HHI_MPLL_CNTL8,
 482                         .shift   = 0,
 483                         .width   = 14,
 484                 },
 485                 .sdm_en = {
 486                         .reg_off = HHI_MPLL_CNTL8,
 487                         .shift   = 15,
 488                         .width   = 1,
 489                 },
 490                 .n2 = {
 491                         .reg_off = HHI_MPLL_CNTL8,
 492                         .shift   = 16,
 493                         .width   = 9,
 494                 },
 495                 .lock = &meson_clk_lock,
 496         },
 497         .hw.init = &(struct clk_init_data){
 498                 .name = "mpll1_div",
 499                 .ops = &meson_clk_mpll_ops,
 500                 .parent_hws = (const struct clk_hw *[]) {
 501                         &meson8b_mpll_prediv.hw
 502                 },
 503                 .num_parents = 1,
 504         },
 505 };
 506
 507 static struct clk_regmap meson8b_mpll1 = {
 508         .data = &(struct clk_regmap_gate_data){
 509                 .offset = HHI_MPLL_CNTL8,
 510                 .bit_idx = 14,
 511         },
 512         .hw.init = &(struct clk_init_data){
 513                 .name = "mpll1",
 514                 .ops = &clk_regmap_gate_ops,
 515                 .parent_hws = (const struct clk_hw *[]) {
 516                         &meson8b_mpll1_div.hw
 517                 },
 518                 .num_parents = 1,
 519                 .flags = CLK_SET_RATE_PARENT,
 520         },
 521 };
 522
 523 static struct clk_regmap meson8b_mpll2_div = {
 524         .data = &(struct meson_clk_mpll_data){
 525                 .sdm = {
 526                         .reg_off = HHI_MPLL_CNTL9,
 527                         .shift   = 0,
 528                         .width   = 14,
 529                 },
 530                 .sdm_en = {
 531                         .reg_off = HHI_MPLL_CNTL9,
 532                         .shift   = 15,
 533                         .width   = 1,
 534                 },
 535                 .n2 = {
 536                         .reg_off = HHI_MPLL_CNTL9,
 537                         .shift   = 16,
 538                         .width   = 9,
 539                 },
 540                 .lock = &meson_clk_lock,
 541         },
 542         .hw.init = &(struct clk_init_data){
 543                 .name = "mpll2_div",
 544                 .ops = &meson_clk_mpll_ops,
 545                 .parent_hws = (const struct clk_hw *[]) {
 546                         &meson8b_mpll_prediv.hw
 547                 },
 548                 .num_parents = 1,
 549         },
 550 };
 551
 552 static struct clk_regmap meson8b_mpll2 = {
 553         .data = &(struct clk_regmap_gate_data){
 554                 .offset = HHI_MPLL_CNTL9,
 555                 .bit_idx = 14,
 556         },
 557         .hw.init = &(struct clk_init_data){
 558                 .name = "mpll2",
 559                 .ops = &clk_regmap_gate_ops,
 560                 .parent_hws = (const struct clk_hw *[]) {
 561                         &meson8b_mpll2_div.hw
 562                 },
 563                 .num_parents = 1,
 564                 .flags = CLK_SET_RATE_PARENT,
 565         },
 566 };
 567
 568 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 569 static struct clk_regmap meson8b_mpeg_clk_sel = {
 570         .data = &(struct clk_regmap_mux_data){
 571                 .offset = HHI_MPEG_CLK_CNTL,
 572                 .mask = 0x7,
 573                 .shift = 12,
 574                 .table = mux_table_clk81,
 575         },
 576         .hw.init = &(struct clk_init_data){
 577                 .name = "mpeg_clk_sel",
 578                 .ops = &clk_regmap_mux_ro_ops,
 579                 /*
 580                  * FIXME bits 14:12 selects from 8 possible parents:
 581                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 582                  * fclk_div4, fclk_div3, fclk_div5
 583                  */
 584                 .parent_hws = (const struct clk_hw *[]) {
 585                         &meson8b_fclk_div3.hw,
 586                         &meson8b_fclk_div4.hw,
 587                         &meson8b_fclk_div5.hw,
 588                 },
 589                 .num_parents = 3,
 590         },
 591 };
 592
 593 static struct clk_regmap meson8b_mpeg_clk_div = {
 594         .data = &(struct clk_regmap_div_data){
 595                 .offset = HHI_MPEG_CLK_CNTL,
 596                 .shift = 0,
 597                 .width = 7,
 598         },
 599         .hw.init = &(struct clk_init_data){
 600                 .name = "mpeg_clk_div",
 601                 .ops = &clk_regmap_divider_ro_ops,
 602                 .parent_hws = (const struct clk_hw *[]) {
 603                         &meson8b_mpeg_clk_sel.hw
 604                 },
 605                 .num_parents = 1,
 606         },
 607 };
 608
 609 static struct clk_regmap meson8b_clk81 = {
 610         .data = &(struct clk_regmap_gate_data){
 611                 .offset = HHI_MPEG_CLK_CNTL,
 612                 .bit_idx = 7,
 613         },
 614         .hw.init = &(struct clk_init_data){
 615                 .name = "clk81",
 616                 .ops = &clk_regmap_gate_ops,
 617                 .parent_hws = (const struct clk_hw *[]) {
 618                         &meson8b_mpeg_clk_div.hw
 619                 },
 620                 .num_parents = 1,
 621                 .flags = CLK_IS_CRITICAL,
 622         },
 623 };
 624
 625 static struct clk_regmap meson8b_cpu_in_sel = {
 626         .data = &(struct clk_regmap_mux_data){
 627                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 628                 .mask = 0x1,
 629                 .shift = 0,
 630         },
 631         .hw.init = &(struct clk_init_data){
 632                 .name = "cpu_in_sel",
 633                 .ops = &clk_regmap_mux_ops,
 634                 .parent_hws = (const struct clk_hw *[]) {
 635                         &meson8b_xtal.hw,
 636                         &meson8b_sys_pll.hw,
 637                 },
 638                 .num_parents = 2,
 639                 .flags = (CLK_SET_RATE_PARENT |
 640                           CLK_SET_RATE_NO_REPARENT),
 641         },
 642 };
 643
 644 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
 645         .mult = 1,
 646         .div = 2,
 647         .hw.init = &(struct clk_init_data){
 648                 .name = "cpu_in_div2",
 649                 .ops = &clk_fixed_factor_ops,
 650                 .parent_hws = (const struct clk_hw *[]) {
 651                         &meson8b_cpu_in_sel.hw
 652                 },
 653                 .num_parents = 1,
 654                 .flags = CLK_SET_RATE_PARENT,
 655         },
 656 };
 657
 658 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
 659         .mult = 1,
 660         .div = 3,
 661         .hw.init = &(struct clk_init_data){
 662                 .name = "cpu_in_div3",
 663                 .ops = &clk_fixed_factor_ops,
 664                 .parent_hws = (const struct clk_hw *[]) {
 665                         &meson8b_cpu_in_sel.hw
 666                 },
 667                 .num_parents = 1,
 668                 .flags = CLK_SET_RATE_PARENT,
 669         },
 670 };
 671
 672 static const struct clk_div_table cpu_scale_table[] = {
 673         { .val = 1, .div = 4 },
 674         { .val = 2, .div = 6 },
 675         { .val = 3, .div = 8 },
 676         { .val = 4, .div = 10 },
 677         { .val = 5, .div = 12 },
 678         { .val = 6, .div = 14 },
 679         { .val = 7, .div = 16 },
 680         { .val = 8, .div = 18 },
 681         { /* sentinel */ },
 682 };
 683
 684 static struct clk_regmap meson8b_cpu_scale_div = {
 685         .data = &(struct clk_regmap_div_data){
 686                 .offset =  HHI_SYS_CPU_CLK_CNTL1,
 687                 .shift = 20,
 688                 .width = 10,
 689                 .table = cpu_scale_table,
 690                 .flags = CLK_DIVIDER_ALLOW_ZERO,
 691         },
 692         .hw.init = &(struct clk_init_data){
 693                 .name = "cpu_scale_div",
 694                 .ops = &clk_regmap_divider_ops,
 695                 .parent_hws = (const struct clk_hw *[]) {
 696                         &meson8b_cpu_in_sel.hw
 697                 },
 698                 .num_parents = 1,
 699                 .flags = CLK_SET_RATE_PARENT,
 700         },
 701 };
 702
 703 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
 704 static struct clk_regmap meson8b_cpu_scale_out_sel = {
 705         .data = &(struct clk_regmap_mux_data){
 706                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 707                 .mask = 0x3,
 708                 .shift = 2,
 709                 .table = mux_table_cpu_scale_out_sel,
 710         },
 711         .hw.init = &(struct clk_init_data){
 712                 .name = "cpu_scale_out_sel",
 713                 .ops = &clk_regmap_mux_ops,
 714                 /*
 715                  * NOTE: We are skipping the parent with value 0x2 (which is
 716                  * meson8b_cpu_in_div3) because it results in a duty cycle of
 717                  * 33% which makes the system unstable and can result in a
 718                  * lockup of the whole system.
 719                  */
 720                 .parent_hws = (const struct clk_hw *[]) {
 721                         &meson8b_cpu_in_sel.hw,
 722                         &meson8b_cpu_in_div2.hw,
 723                         &meson8b_cpu_scale_div.hw,
 724                 },
 725                 .num_parents = 3,
 726                 .flags = CLK_SET_RATE_PARENT,
 727         },
 728 };
 729
 730 static struct clk_regmap meson8b_cpu_clk = {
 731         .data = &(struct clk_regmap_mux_data){
 732                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 733                 .mask = 0x1,
 734                 .shift = 7,
 735         },
 736         .hw.init = &(struct clk_init_data){
 737                 .name = "cpu_clk",
 738                 .ops = &clk_regmap_mux_ops,
 739                 .parent_hws = (const struct clk_hw *[]) {
 740                         &meson8b_xtal.hw,
 741                         &meson8b_cpu_scale_out_sel.hw,
 742                 },
 743                 .num_parents = 2,
 744                 .flags = (CLK_SET_RATE_PARENT |
 745                           CLK_SET_RATE_NO_REPARENT |
 746                           CLK_IS_CRITICAL),
 747         },
 748 };
 749
 750 static struct clk_regmap meson8b_nand_clk_sel = {
 751         .data = &(struct clk_regmap_mux_data){
 752                 .offset = HHI_NAND_CLK_CNTL,
 753                 .mask = 0x7,
 754                 .shift = 9,
 755                 .flags = CLK_MUX_ROUND_CLOSEST,
 756         },
 757         .hw.init = &(struct clk_init_data){
 758                 .name = "nand_clk_sel",
 759                 .ops = &clk_regmap_mux_ops,
 760                 /* FIXME all other parents are unknown: */
 761                 .parent_hws = (const struct clk_hw *[]) {
 762                         &meson8b_fclk_div4.hw,
 763                         &meson8b_fclk_div3.hw,
 764                         &meson8b_fclk_div5.hw,
 765                         &meson8b_fclk_div7.hw,
 766                         &meson8b_xtal.hw,
 767                 },
 768                 .num_parents = 5,
 769                 .flags = CLK_SET_RATE_PARENT,
 770         },
 771 };
 772
 773 static struct clk_regmap meson8b_nand_clk_div = {
 774         .data = &(struct clk_regmap_div_data){
 775                 .offset =  HHI_NAND_CLK_CNTL,
 776                 .shift = 0,
 777                 .width = 7,
 778                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 779         },
 780         .hw.init = &(struct clk_init_data){
 781                 .name = "nand_clk_div",
 782                 .ops = &clk_regmap_divider_ops,
 783                 .parent_hws = (const struct clk_hw *[]) {
 784                         &meson8b_nand_clk_sel.hw
 785                 },
 786                 .num_parents = 1,
 787                 .flags = CLK_SET_RATE_PARENT,
 788         },
 789 };
 790
 791 static struct clk_regmap meson8b_nand_clk_gate = {
 792         .data = &(struct clk_regmap_gate_data){
 793                 .offset = HHI_NAND_CLK_CNTL,
 794                 .bit_idx = 8,
 795         },
 796         .hw.init = &(struct clk_init_data){
 797                 .name = "nand_clk_gate",
 798                 .ops = &clk_regmap_gate_ops,
 799                 .parent_hws = (const struct clk_hw *[]) {
 800                         &meson8b_nand_clk_div.hw
 801                 },
 802                 .num_parents = 1,
 803                 .flags = CLK_SET_RATE_PARENT,
 804         },
 805 };
 806
 807 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
 808         .mult = 1,
 809         .div = 2,
 810         .hw.init = &(struct clk_init_data){
 811                 .name = "cpu_clk_div2",
 812                 .ops = &clk_fixed_factor_ops,
 813                 .parent_hws = (const struct clk_hw *[]) {
 814                         &meson8b_cpu_clk.hw
 815                 },
 816                 .num_parents = 1,
 817         },
 818 };
 819
 820 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
 821         .mult = 1,
 822         .div = 3,
 823         .hw.init = &(struct clk_init_data){
 824                 .name = "cpu_clk_div3",
 825                 .ops = &clk_fixed_factor_ops,
 826                 .parent_hws = (const struct clk_hw *[]) {
 827                         &meson8b_cpu_clk.hw
 828                 },
 829                 .num_parents = 1,
 830         },
 831 };
 832
 833 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
 834         .mult = 1,
 835         .div = 4,
 836         .hw.init = &(struct clk_init_data){
 837                 .name = "cpu_clk_div4",
 838                 .ops = &clk_fixed_factor_ops,
 839                 .parent_hws = (const struct clk_hw *[]) {
 840                         &meson8b_cpu_clk.hw
 841                 },
 842                 .num_parents = 1,
 843         },
 844 };
 845
 846 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
 847         .mult = 1,
 848         .div = 5,
 849         .hw.init = &(struct clk_init_data){
 850                 .name = "cpu_clk_div5",
 851                 .ops = &clk_fixed_factor_ops,
 852                 .parent_hws = (const struct clk_hw *[]) {
 853                         &meson8b_cpu_clk.hw
 854                 },
 855                 .num_parents = 1,
 856         },
 857 };
 858
 859 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
 860         .mult = 1,
 861         .div = 6,
 862         .hw.init = &(struct clk_init_data){
 863                 .name = "cpu_clk_div6",
 864                 .ops = &clk_fixed_factor_ops,
 865                 .parent_hws = (const struct clk_hw *[]) {
 866                         &meson8b_cpu_clk.hw
 867                 },
 868                 .num_parents = 1,
 869         },
 870 };
 871
 872 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
 873         .mult = 1,
 874         .div = 7,
 875         .hw.init = &(struct clk_init_data){
 876                 .name = "cpu_clk_div7",
 877                 .ops = &clk_fixed_factor_ops,
 878                 .parent_hws = (const struct clk_hw *[]) {
 879                         &meson8b_cpu_clk.hw
 880                 },
 881                 .num_parents = 1,
 882         },
 883 };
 884
 885 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
 886         .mult = 1,
 887         .div = 8,
 888         .hw.init = &(struct clk_init_data){
 889                 .name = "cpu_clk_div8",
 890                 .ops = &clk_fixed_factor_ops,
 891                 .parent_hws = (const struct clk_hw *[]) {
 892                         &meson8b_cpu_clk.hw
 893                 },
 894                 .num_parents = 1,
 895         },
 896 };
 897
 898 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
 899 static struct clk_regmap meson8b_apb_clk_sel = {
 900         .data = &(struct clk_regmap_mux_data){
 901                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 902                 .mask = 0x7,
 903                 .shift = 3,
 904                 .table = mux_table_apb,
 905         },
 906         .hw.init = &(struct clk_init_data){
 907                 .name = "apb_clk_sel",
 908                 .ops = &clk_regmap_mux_ops,
 909                 .parent_hws = (const struct clk_hw *[]) {
 910                         &meson8b_cpu_clk_div2.hw,
 911                         &meson8b_cpu_clk_div3.hw,
 912                         &meson8b_cpu_clk_div4.hw,
 913                         &meson8b_cpu_clk_div5.hw,
 914                         &meson8b_cpu_clk_div6.hw,
 915                         &meson8b_cpu_clk_div7.hw,
 916                         &meson8b_cpu_clk_div8.hw,
 917                 },
 918                 .num_parents = 7,
 919         },
 920 };
 921
 922 static struct clk_regmap meson8b_apb_clk_gate = {
 923         .data = &(struct clk_regmap_gate_data){
 924                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 925                 .bit_idx = 16,
 926                 .flags = CLK_GATE_SET_TO_DISABLE,
 927         },
 928         .hw.init = &(struct clk_init_data){
 929                 .name = "apb_clk_dis",
 930                 .ops = &clk_regmap_gate_ro_ops,
 931                 .parent_hws = (const struct clk_hw *[]) {
 932                         &meson8b_apb_clk_sel.hw
 933                 },
 934                 .num_parents = 1,
 935                 .flags = CLK_SET_RATE_PARENT,
 936         },
 937 };
 938
 939 static struct clk_regmap meson8b_periph_clk_sel = {
 940         .data = &(struct clk_regmap_mux_data){
 941                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 942                 .mask = 0x7,
 943                 .shift = 6,
 944         },
 945         .hw.init = &(struct clk_init_data){
 946                 .name = "periph_clk_sel",
 947                 .ops = &clk_regmap_mux_ops,
 948                 .parent_hws = (const struct clk_hw *[]) {
 949                         &meson8b_cpu_clk_div2.hw,
 950                         &meson8b_cpu_clk_div3.hw,
 951                         &meson8b_cpu_clk_div4.hw,
 952                         &meson8b_cpu_clk_div5.hw,
 953                         &meson8b_cpu_clk_div6.hw,
 954                         &meson8b_cpu_clk_div7.hw,
 955                         &meson8b_cpu_clk_div8.hw,
 956                 },
 957                 .num_parents = 7,
 958         },
 959 };
 960
 961 static struct clk_regmap meson8b_periph_clk_gate = {
 962         .data = &(struct clk_regmap_gate_data){
 963                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 964                 .bit_idx = 17,
 965                 .flags = CLK_GATE_SET_TO_DISABLE,
 966         },
 967         .hw.init = &(struct clk_init_data){
 968                 .name = "periph_clk_dis",
 969                 .ops = &clk_regmap_gate_ro_ops,
 970                 .parent_hws = (const struct clk_hw *[]) {
 971                         &meson8b_periph_clk_sel.hw
 972                 },
 973                 .num_parents = 1,
 974                 .flags = CLK_SET_RATE_PARENT,
 975         },
 976 };
 977
 978 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
 979 static struct clk_regmap meson8b_axi_clk_sel = {
 980         .data = &(struct clk_regmap_mux_data){
 981                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 982                 .mask = 0x7,
 983                 .shift = 9,
 984                 .table = mux_table_axi,
 985         },
 986         .hw.init = &(struct clk_init_data){
 987                 .name = "axi_clk_sel",
 988                 .ops = &clk_regmap_mux_ops,
 989                 .parent_hws = (const struct clk_hw *[]) {
 990                         &meson8b_cpu_clk_div2.hw,
 991                         &meson8b_cpu_clk_div3.hw,
 992                         &meson8b_cpu_clk_div4.hw,
 993                         &meson8b_cpu_clk_div5.hw,
 994                         &meson8b_cpu_clk_div6.hw,
 995                         &meson8b_cpu_clk_div7.hw,
 996                         &meson8b_cpu_clk_div8.hw,
 997                 },
 998                 .num_parents = 7,
 999         },
1000 };
1001
1002 static struct clk_regmap meson8b_axi_clk_gate = {
1003         .data = &(struct clk_regmap_gate_data){
1004                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1005                 .bit_idx = 18,
1006                 .flags = CLK_GATE_SET_TO_DISABLE,
1007         },
1008         .hw.init = &(struct clk_init_data){
1009                 .name = "axi_clk_dis",
1010                 .ops = &clk_regmap_gate_ro_ops,
1011                 .parent_hws = (const struct clk_hw *[]) {
1012                         &meson8b_axi_clk_sel.hw
1013                 },
1014                 .num_parents = 1,
1015                 .flags = CLK_SET_RATE_PARENT,
1016         },
1017 };
1018
1019 static struct clk_regmap meson8b_l2_dram_clk_sel = {
1020         .data = &(struct clk_regmap_mux_data){
1021                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1022                 .mask = 0x7,
1023                 .shift = 12,
1024         },
1025         .hw.init = &(struct clk_init_data){
1026                 .name = "l2_dram_clk_sel",
1027                 .ops = &clk_regmap_mux_ops,
1028                 .parent_hws = (const struct clk_hw *[]) {
1029                         &meson8b_cpu_clk_div2.hw,
1030                         &meson8b_cpu_clk_div3.hw,
1031                         &meson8b_cpu_clk_div4.hw,
1032                         &meson8b_cpu_clk_div5.hw,
1033                         &meson8b_cpu_clk_div6.hw,
1034                         &meson8b_cpu_clk_div7.hw,
1035                         &meson8b_cpu_clk_div8.hw,
1036                 },
1037                 .num_parents = 7,
1038         },
1039 };
1040
1041 static struct clk_regmap meson8b_l2_dram_clk_gate = {
1042         .data = &(struct clk_regmap_gate_data){
1043                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1044                 .bit_idx = 19,
1045                 .flags = CLK_GATE_SET_TO_DISABLE,
1046         },
1047         .hw.init = &(struct clk_init_data){
1048                 .name = "l2_dram_clk_dis",
1049                 .ops = &clk_regmap_gate_ro_ops,
1050                 .parent_hws = (const struct clk_hw *[]) {
1051                         &meson8b_l2_dram_clk_sel.hw
1052                 },
1053                 .num_parents = 1,
1054                 .flags = CLK_SET_RATE_PARENT,
1055         },
1056 };
1057
1058 static struct clk_regmap meson8b_vid_pll_in_sel = {
1059         .data = &(struct clk_regmap_mux_data){
1060                 .offset = HHI_VID_DIVIDER_CNTL,
1061                 .mask = 0x1,
1062                 .shift = 15,
1063         },
1064         .hw.init = &(struct clk_init_data){
1065                 .name = "vid_pll_in_sel",
1066                 .ops = &clk_regmap_mux_ro_ops,
1067                 /*
1068                  * TODO: depending on the SoC there is also a second parent:
1069                  * Meson8: unknown
1070                  * Meson8b: hdmi_pll_dco
1071                  * Meson8m2: vid2_pll
1072                  */
1073                 .parent_hws = (const struct clk_hw *[]) {
1074                         &meson8b_hdmi_pll_dco.hw
1075                 },
1076                 .num_parents = 1,
1077                 .flags = CLK_SET_RATE_PARENT,
1078         },
1079 };
1080
1081 static struct clk_regmap meson8b_vid_pll_in_en = {
1082         .data = &(struct clk_regmap_gate_data){
1083                 .offset = HHI_VID_DIVIDER_CNTL,
1084                 .bit_idx = 16,
1085         },
1086         .hw.init = &(struct clk_init_data){
1087                 .name = "vid_pll_in_en",
1088                 .ops = &clk_regmap_gate_ro_ops,
1089                 .parent_hws = (const struct clk_hw *[]) {
1090                         &meson8b_vid_pll_in_sel.hw
1091                 },
1092                 .num_parents = 1,
1093                 .flags = CLK_SET_RATE_PARENT,
1094         },
1095 };
1096
1097 static struct clk_regmap meson8b_vid_pll_pre_div = {
1098         .data = &(struct clk_regmap_div_data){
1099                 .offset =  HHI_VID_DIVIDER_CNTL,
1100                 .shift = 4,
1101                 .width = 3,
1102         },
1103         .hw.init = &(struct clk_init_data){
1104                 .name = "vid_pll_pre_div",
1105                 .ops = &clk_regmap_divider_ro_ops,
1106                 .parent_hws = (const struct clk_hw *[]) {
1107                         &meson8b_vid_pll_in_en.hw
1108                 },
1109                 .num_parents = 1,
1110                 .flags = CLK_SET_RATE_PARENT,
1111         },
1112 };
1113
1114 static struct clk_regmap meson8b_vid_pll_post_div = {
1115         .data = &(struct clk_regmap_div_data){
1116                 .offset =  HHI_VID_DIVIDER_CNTL,
1117                 .shift = 12,
1118                 .width = 3,
1119         },
1120         .hw.init = &(struct clk_init_data){
1121                 .name = "vid_pll_post_div",
1122                 .ops = &clk_regmap_divider_ro_ops,
1123                 .parent_hws = (const struct clk_hw *[]) {
1124                         &meson8b_vid_pll_pre_div.hw
1125                 },
1126                 .num_parents = 1,
1127                 .flags = CLK_SET_RATE_PARENT,
1128         },
1129 };
1130
1131 static struct clk_regmap meson8b_vid_pll = {
1132         .data = &(struct clk_regmap_mux_data){
1133                 .offset = HHI_VID_DIVIDER_CNTL,
1134                 .mask = 0x3,
1135                 .shift = 8,
1136         },
1137         .hw.init = &(struct clk_init_data){
1138                 .name = "vid_pll",
1139                 .ops = &clk_regmap_mux_ro_ops,
1140                 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1141                 .parent_hws = (const struct clk_hw *[]) {
1142                         &meson8b_vid_pll_pre_div.hw,
1143                         &meson8b_vid_pll_post_div.hw,
1144                 },
1145                 .num_parents = 2,
1146                 .flags = CLK_SET_RATE_PARENT,
1147         },
1148 };
1149
1150 static struct clk_regmap meson8b_vid_pll_final_div = {
1151         .data = &(struct clk_regmap_div_data){
1152                 .offset =  HHI_VID_CLK_DIV,
1153                 .shift = 0,
1154                 .width = 8,
1155         },
1156         .hw.init = &(struct clk_init_data){
1157                 .name = "vid_pll_final_div",
1158                 .ops = &clk_regmap_divider_ro_ops,
1159                 .parent_hws = (const struct clk_hw *[]) {
1160                         &meson8b_vid_pll.hw
1161                 },
1162                 .num_parents = 1,
1163                 .flags = CLK_SET_RATE_PARENT,
1164         },
1165 };
1166
1167 static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1168         &meson8b_vid_pll_final_div.hw,
1169         &meson8b_fclk_div4.hw,
1170         &meson8b_fclk_div3.hw,
1171         &meson8b_fclk_div5.hw,
1172         &meson8b_vid_pll_final_div.hw,
1173         &meson8b_fclk_div7.hw,
1174         &meson8b_mpll1.hw,
1175 };
1176
1177 static struct clk_regmap meson8b_vclk_in_sel = {
1178         .data = &(struct clk_regmap_mux_data){
1179                 .offset = HHI_VID_CLK_CNTL,
1180                 .mask = 0x7,
1181                 .shift = 16,
1182         },
1183         .hw.init = &(struct clk_init_data){
1184                 .name = "vclk_in_sel",
1185                 .ops = &clk_regmap_mux_ro_ops,
1186                 .parent_hws = meson8b_vclk_mux_parent_hws,
1187                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1188                 .flags = CLK_SET_RATE_PARENT,
1189         },
1190 };
1191
1192 static struct clk_regmap meson8b_vclk_in_en = {
1193         .data = &(struct clk_regmap_gate_data){
1194                 .offset = HHI_VID_CLK_DIV,
1195                 .bit_idx = 16,
1196         },
1197         .hw.init = &(struct clk_init_data){
1198                 .name = "vclk_in_en",
1199                 .ops = &clk_regmap_gate_ro_ops,
1200                 .parent_hws = (const struct clk_hw *[]) {
1201                         &meson8b_vclk_in_sel.hw
1202                 },
1203                 .num_parents = 1,
1204                 .flags = CLK_SET_RATE_PARENT,
1205         },
1206 };
1207
1208 static struct clk_regmap meson8b_vclk_div1_gate = {
1209         .data = &(struct clk_regmap_gate_data){
1210                 .offset = HHI_VID_CLK_DIV,
1211                 .bit_idx = 0,
1212         },
1213         .hw.init = &(struct clk_init_data){
1214                 .name = "vclk_div1_en",
1215                 .ops = &clk_regmap_gate_ro_ops,
1216                 .parent_hws = (const struct clk_hw *[]) {
1217                         &meson8b_vclk_in_en.hw
1218                 },
1219                 .num_parents = 1,
1220                 .flags = CLK_SET_RATE_PARENT,
1221         },
1222 };
1223
1224 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1225         .mult = 1,
1226         .div = 2,
1227         .hw.init = &(struct clk_init_data){
1228                 .name = "vclk_div2",
1229                 .ops = &clk_fixed_factor_ops,
1230                 .parent_hws = (const struct clk_hw *[]) {
1231                         &meson8b_vclk_in_en.hw
1232                 },
1233                 .num_parents = 1,
1234                 .flags = CLK_SET_RATE_PARENT,
1235         }
1236 };
1237
1238 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1239         .data = &(struct clk_regmap_gate_data){
1240                 .offset = HHI_VID_CLK_DIV,
1241                 .bit_idx = 1,
1242         },
1243         .hw.init = &(struct clk_init_data){
1244                 .name = "vclk_div2_en",
1245                 .ops = &clk_regmap_gate_ro_ops,
1246                 .parent_hws = (const struct clk_hw *[]) {
1247                         &meson8b_vclk_div2_div.hw
1248                 },
1249                 .num_parents = 1,
1250                 .flags = CLK_SET_RATE_PARENT,
1251         },
1252 };
1253
1254 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1255         .mult = 1,
1256         .div = 4,
1257         .hw.init = &(struct clk_init_data){
1258                 .name = "vclk_div4",
1259                 .ops = &clk_fixed_factor_ops,
1260                 .parent_hws = (const struct clk_hw *[]) {
1261                         &meson8b_vclk_in_en.hw
1262                 },
1263                 .num_parents = 1,
1264                 .flags = CLK_SET_RATE_PARENT,
1265         }
1266 };
1267
1268 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1269         .data = &(struct clk_regmap_gate_data){
1270                 .offset = HHI_VID_CLK_DIV,
1271                 .bit_idx = 2,
1272         },
1273         .hw.init = &(struct clk_init_data){
1274                 .name = "vclk_div4_en",
1275                 .ops = &clk_regmap_gate_ro_ops,
1276                 .parent_hws = (const struct clk_hw *[]) {
1277                         &meson8b_vclk_div4_div.hw
1278                 },
1279                 .num_parents = 1,
1280                 .flags = CLK_SET_RATE_PARENT,
1281         },
1282 };
1283
1284 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1285         .mult = 1,
1286         .div = 6,
1287         .hw.init = &(struct clk_init_data){
1288                 .name = "vclk_div6",
1289                 .ops = &clk_fixed_factor_ops,
1290                 .parent_hws = (const struct clk_hw *[]) {
1291                         &meson8b_vclk_in_en.hw
1292                 },
1293                 .num_parents = 1,
1294                 .flags = CLK_SET_RATE_PARENT,
1295         }
1296 };
1297
1298 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1299         .data = &(struct clk_regmap_gate_data){
1300                 .offset = HHI_VID_CLK_DIV,
1301                 .bit_idx = 3,
1302         },
1303         .hw.init = &(struct clk_init_data){
1304                 .name = "vclk_div6_en",
1305                 .ops = &clk_regmap_gate_ro_ops,
1306                 .parent_hws = (const struct clk_hw *[]) {
1307                         &meson8b_vclk_div6_div.hw
1308                 },
1309                 .num_parents = 1,
1310                 .flags = CLK_SET_RATE_PARENT,
1311         },
1312 };
1313
1314 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1315         .mult = 1,
1316         .div = 12,
1317         .hw.init = &(struct clk_init_data){
1318                 .name = "vclk_div12",
1319                 .ops = &clk_fixed_factor_ops,
1320                 .parent_hws = (const struct clk_hw *[]) {
1321                         &meson8b_vclk_in_en.hw
1322                 },
1323                 .num_parents = 1,
1324                 .flags = CLK_SET_RATE_PARENT,
1325         }
1326 };
1327
1328 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1329         .data = &(struct clk_regmap_gate_data){
1330                 .offset = HHI_VID_CLK_DIV,
1331                 .bit_idx = 4,
1332         },
1333         .hw.init = &(struct clk_init_data){
1334                 .name = "vclk_div12_en",
1335                 .ops = &clk_regmap_gate_ro_ops,
1336                 .parent_hws = (const struct clk_hw *[]) {
1337                         &meson8b_vclk_div12_div.hw
1338                 },
1339                 .num_parents = 1,
1340                 .flags = CLK_SET_RATE_PARENT,
1341         },
1342 };
1343
1344 static struct clk_regmap meson8b_vclk2_in_sel = {
1345         .data = &(struct clk_regmap_mux_data){
1346                 .offset = HHI_VIID_CLK_CNTL,
1347                 .mask = 0x7,
1348                 .shift = 16,
1349         },
1350         .hw.init = &(struct clk_init_data){
1351                 .name = "vclk2_in_sel",
1352                 .ops = &clk_regmap_mux_ro_ops,
1353                 .parent_hws = meson8b_vclk_mux_parent_hws,
1354                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1355                 .flags = CLK_SET_RATE_PARENT,
1356         },
1357 };
1358
1359 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1360         .data = &(struct clk_regmap_gate_data){
1361                 .offset = HHI_VIID_CLK_DIV,
1362                 .bit_idx = 16,
1363         },
1364         .hw.init = &(struct clk_init_data){
1365                 .name = "vclk2_in_en",
1366                 .ops = &clk_regmap_gate_ro_ops,
1367                 .parent_hws = (const struct clk_hw *[]) {
1368                         &meson8b_vclk2_in_sel.hw
1369                 },
1370                 .num_parents = 1,
1371                 .flags = CLK_SET_RATE_PARENT,
1372         },
1373 };
1374
1375 static struct clk_regmap meson8b_vclk2_div1_gate = {
1376         .data = &(struct clk_regmap_gate_data){
1377                 .offset = HHI_VIID_CLK_DIV,
1378                 .bit_idx = 0,
1379         },
1380         .hw.init = &(struct clk_init_data){
1381                 .name = "vclk2_div1_en",
1382                 .ops = &clk_regmap_gate_ro_ops,
1383                 .parent_hws = (const struct clk_hw *[]) {
1384                         &meson8b_vclk2_clk_in_en.hw
1385                 },
1386                 .num_parents = 1,
1387                 .flags = CLK_SET_RATE_PARENT,
1388         },
1389 };
1390
1391 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1392         .mult = 1,
1393         .div = 2,
1394         .hw.init = &(struct clk_init_data){
1395                 .name = "vclk2_div2",
1396                 .ops = &clk_fixed_factor_ops,
1397                 .parent_hws = (const struct clk_hw *[]) {
1398                         &meson8b_vclk2_clk_in_en.hw
1399                 },
1400                 .num_parents = 1,
1401                 .flags = CLK_SET_RATE_PARENT,
1402         }
1403 };
1404
1405 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1406         .data = &(struct clk_regmap_gate_data){
1407                 .offset = HHI_VIID_CLK_DIV,
1408                 .bit_idx = 1,
1409         },
1410         .hw.init = &(struct clk_init_data){
1411                 .name = "vclk2_div2_en",
1412                 .ops = &clk_regmap_gate_ro_ops,
1413                 .parent_hws = (const struct clk_hw *[]) {
1414                         &meson8b_vclk2_div2_div.hw
1415                 },
1416                 .num_parents = 1,
1417                 .flags = CLK_SET_RATE_PARENT,
1418         },
1419 };
1420
1421 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1422         .mult = 1,
1423         .div = 4,
1424         .hw.init = &(struct clk_init_data){
1425                 .name = "vclk2_div4",
1426                 .ops = &clk_fixed_factor_ops,
1427                 .parent_hws = (const struct clk_hw *[]) {
1428                         &meson8b_vclk2_clk_in_en.hw
1429                 },
1430                 .num_parents = 1,
1431                 .flags = CLK_SET_RATE_PARENT,
1432         }
1433 };
1434
1435 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1436         .data = &(struct clk_regmap_gate_data){
1437                 .offset = HHI_VIID_CLK_DIV,
1438                 .bit_idx = 2,
1439         },
1440         .hw.init = &(struct clk_init_data){
1441                 .name = "vclk2_div4_en",
1442                 .ops = &clk_regmap_gate_ro_ops,
1443                 .parent_hws = (const struct clk_hw *[]) {
1444                         &meson8b_vclk2_div4_div.hw
1445                 },
1446                 .num_parents = 1,
1447                 .flags = CLK_SET_RATE_PARENT,
1448         },
1449 };
1450
1451 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1452         .mult = 1,
1453         .div = 6,
1454         .hw.init = &(struct clk_init_data){
1455                 .name = "vclk2_div6",
1456                 .ops = &clk_fixed_factor_ops,
1457                 .parent_hws = (const struct clk_hw *[]) {
1458                         &meson8b_vclk2_clk_in_en.hw
1459                 },
1460                 .num_parents = 1,
1461                 .flags = CLK_SET_RATE_PARENT,
1462         }
1463 };
1464
1465 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1466         .data = &(struct clk_regmap_gate_data){
1467                 .offset = HHI_VIID_CLK_DIV,
1468                 .bit_idx = 3,
1469         },
1470         .hw.init = &(struct clk_init_data){
1471                 .name = "vclk2_div6_en",
1472                 .ops = &clk_regmap_gate_ro_ops,
1473                 .parent_hws = (const struct clk_hw *[]) {
1474                         &meson8b_vclk2_div6_div.hw
1475                 },
1476                 .num_parents = 1,
1477                 .flags = CLK_SET_RATE_PARENT,
1478         },
1479 };
1480
1481 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1482         .mult = 1,
1483         .div = 12,
1484         .hw.init = &(struct clk_init_data){
1485                 .name = "vclk2_div12",
1486                 .ops = &clk_fixed_factor_ops,
1487                 .parent_hws = (const struct clk_hw *[]) {
1488                         &meson8b_vclk2_clk_in_en.hw
1489                 },
1490                 .num_parents = 1,
1491                 .flags = CLK_SET_RATE_PARENT,
1492         }
1493 };
1494
1495 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1496         .data = &(struct clk_regmap_gate_data){
1497                 .offset = HHI_VIID_CLK_DIV,
1498                 .bit_idx = 4,
1499         },
1500         .hw.init = &(struct clk_init_data){
1501                 .name = "vclk2_div12_en",
1502                 .ops = &clk_regmap_gate_ro_ops,
1503                 .parent_hws = (const struct clk_hw *[]) {
1504                         &meson8b_vclk2_div12_div.hw
1505                 },
1506                 .num_parents = 1,
1507                 .flags = CLK_SET_RATE_PARENT,
1508         },
1509 };
1510
1511 static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1512         &meson8b_vclk_div1_gate.hw,
1513         &meson8b_vclk_div2_div_gate.hw,
1514         &meson8b_vclk_div4_div_gate.hw,
1515         &meson8b_vclk_div6_div_gate.hw,
1516         &meson8b_vclk_div12_div_gate.hw,
1517 };
1518
1519 static struct clk_regmap meson8b_cts_enct_sel = {
1520         .data = &(struct clk_regmap_mux_data){
1521                 .offset = HHI_VID_CLK_DIV,
1522                 .mask = 0xf,
1523                 .shift = 20,
1524         },
1525         .hw.init = &(struct clk_init_data){
1526                 .name = "cts_enct_sel",
1527                 .ops = &clk_regmap_mux_ro_ops,
1528                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1529                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1530                 .flags = CLK_SET_RATE_PARENT,
1531         },
1532 };
1533
1534 static struct clk_regmap meson8b_cts_enct = {
1535         .data = &(struct clk_regmap_gate_data){
1536                 .offset = HHI_VID_CLK_CNTL2,
1537                 .bit_idx = 1,
1538         },
1539         .hw.init = &(struct clk_init_data){
1540                 .name = "cts_enct",
1541                 .ops = &clk_regmap_gate_ro_ops,
1542                 .parent_hws = (const struct clk_hw *[]) {
1543                         &meson8b_cts_enct_sel.hw
1544                 },
1545                 .num_parents = 1,
1546                 .flags = CLK_SET_RATE_PARENT,
1547         },
1548 };
1549
1550 static struct clk_regmap meson8b_cts_encp_sel = {
1551         .data = &(struct clk_regmap_mux_data){
1552                 .offset = HHI_VID_CLK_DIV,
1553                 .mask = 0xf,
1554                 .shift = 24,
1555         },
1556         .hw.init = &(struct clk_init_data){
1557                 .name = "cts_encp_sel",
1558                 .ops = &clk_regmap_mux_ro_ops,
1559                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1560                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1561                 .flags = CLK_SET_RATE_PARENT,
1562         },
1563 };
1564
1565 static struct clk_regmap meson8b_cts_encp = {
1566         .data = &(struct clk_regmap_gate_data){
1567                 .offset = HHI_VID_CLK_CNTL2,
1568                 .bit_idx = 2,
1569         },
1570         .hw.init = &(struct clk_init_data){
1571                 .name = "cts_encp",
1572                 .ops = &clk_regmap_gate_ro_ops,
1573                 .parent_hws = (const struct clk_hw *[]) {
1574                         &meson8b_cts_encp_sel.hw
1575                 },
1576                 .num_parents = 1,
1577                 .flags = CLK_SET_RATE_PARENT,
1578         },
1579 };
1580
1581 static struct clk_regmap meson8b_cts_enci_sel = {
1582         .data = &(struct clk_regmap_mux_data){
1583                 .offset = HHI_VID_CLK_DIV,
1584                 .mask = 0xf,
1585                 .shift = 28,
1586         },
1587         .hw.init = &(struct clk_init_data){
1588                 .name = "cts_enci_sel",
1589                 .ops = &clk_regmap_mux_ro_ops,
1590                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1591                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1592                 .flags = CLK_SET_RATE_PARENT,
1593         },
1594 };
1595
1596 static struct clk_regmap meson8b_cts_enci = {
1597         .data = &(struct clk_regmap_gate_data){
1598                 .offset = HHI_VID_CLK_CNTL2,
1599                 .bit_idx = 0,
1600         },
1601         .hw.init = &(struct clk_init_data){
1602                 .name = "cts_enci",
1603                 .ops = &clk_regmap_gate_ro_ops,
1604                 .parent_hws = (const struct clk_hw *[]) {
1605                         &meson8b_cts_enci_sel.hw
1606                 },
1607                 .num_parents = 1,
1608                 .flags = CLK_SET_RATE_PARENT,
1609         },
1610 };
1611
1612 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1613         .data = &(struct clk_regmap_mux_data){
1614                 .offset = HHI_HDMI_CLK_CNTL,
1615                 .mask = 0xf,
1616                 .shift = 16,
1617         },
1618         .hw.init = &(struct clk_init_data){
1619                 .name = "hdmi_tx_pixel_sel",
1620                 .ops = &clk_regmap_mux_ro_ops,
1621                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1622                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1623                 .flags = CLK_SET_RATE_PARENT,
1624         },
1625 };
1626
1627 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1628         .data = &(struct clk_regmap_gate_data){
1629                 .offset = HHI_VID_CLK_CNTL2,
1630                 .bit_idx = 5,
1631         },
1632         .hw.init = &(struct clk_init_data){
1633                 .name = "hdmi_tx_pixel",
1634                 .ops = &clk_regmap_gate_ro_ops,
1635                 .parent_hws = (const struct clk_hw *[]) {
1636                         &meson8b_hdmi_tx_pixel_sel.hw
1637                 },
1638                 .num_parents = 1,
1639                 .flags = CLK_SET_RATE_PARENT,
1640         },
1641 };
1642
1643 static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1644         &meson8b_vclk2_div1_gate.hw,
1645         &meson8b_vclk2_div2_div_gate.hw,
1646         &meson8b_vclk2_div4_div_gate.hw,
1647         &meson8b_vclk2_div6_div_gate.hw,
1648         &meson8b_vclk2_div12_div_gate.hw,
1649 };
1650
1651 static struct clk_regmap meson8b_cts_encl_sel = {
1652         .data = &(struct clk_regmap_mux_data){
1653                 .offset = HHI_VIID_CLK_DIV,
1654                 .mask = 0xf,
1655                 .shift = 12,
1656         },
1657         .hw.init = &(struct clk_init_data){
1658                 .name = "cts_encl_sel",
1659                 .ops = &clk_regmap_mux_ro_ops,
1660                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1661                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1662                 .flags = CLK_SET_RATE_PARENT,
1663         },
1664 };
1665
1666 static struct clk_regmap meson8b_cts_encl = {
1667         .data = &(struct clk_regmap_gate_data){
1668                 .offset = HHI_VID_CLK_CNTL2,
1669                 .bit_idx = 3,
1670         },
1671         .hw.init = &(struct clk_init_data){
1672                 .name = "cts_encl",
1673                 .ops = &clk_regmap_gate_ro_ops,
1674                 .parent_hws = (const struct clk_hw *[]) {
1675                         &meson8b_cts_encl_sel.hw
1676                 },
1677                 .num_parents = 1,
1678                 .flags = CLK_SET_RATE_PARENT,
1679         },
1680 };
1681
1682 static struct clk_regmap meson8b_cts_vdac0_sel = {
1683         .data = &(struct clk_regmap_mux_data){
1684                 .offset = HHI_VIID_CLK_DIV,
1685                 .mask = 0xf,
1686                 .shift = 28,
1687         },
1688         .hw.init = &(struct clk_init_data){
1689                 .name = "cts_vdac0_sel",
1690                 .ops = &clk_regmap_mux_ro_ops,
1691                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1692                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1693                 .flags = CLK_SET_RATE_PARENT,
1694         },
1695 };
1696
1697 static struct clk_regmap meson8b_cts_vdac0 = {
1698         .data = &(struct clk_regmap_gate_data){
1699                 .offset = HHI_VID_CLK_CNTL2,
1700                 .bit_idx = 4,
1701         },
1702         .hw.init = &(struct clk_init_data){
1703                 .name = "cts_vdac0",
1704                 .ops = &clk_regmap_gate_ro_ops,
1705                 .parent_hws = (const struct clk_hw *[]) {
1706                         &meson8b_cts_vdac0_sel.hw
1707                 },
1708                 .num_parents = 1,
1709                 .flags = CLK_SET_RATE_PARENT,
1710         },
1711 };
1712
1713 static struct clk_regmap meson8b_hdmi_sys_sel = {
1714         .data = &(struct clk_regmap_mux_data){
1715                 .offset = HHI_HDMI_CLK_CNTL,
1716                 .mask = 0x3,
1717                 .shift = 9,
1718                 .flags = CLK_MUX_ROUND_CLOSEST,
1719         },
1720         .hw.init = &(struct clk_init_data){
1721                 .name = "hdmi_sys_sel",
1722                 .ops = &clk_regmap_mux_ro_ops,
1723                 /* FIXME: all other parents are unknown */
1724                 .parent_hws = (const struct clk_hw *[]) {
1725                         &meson8b_xtal.hw
1726                 },
1727                 .num_parents = 1,
1728                 .flags = CLK_SET_RATE_NO_REPARENT,
1729         },
1730 };
1731
1732 static struct clk_regmap meson8b_hdmi_sys_div = {
1733         .data = &(struct clk_regmap_div_data){
1734                 .offset = HHI_HDMI_CLK_CNTL,
1735                 .shift = 0,
1736                 .width = 7,
1737         },
1738         .hw.init = &(struct clk_init_data){
1739                 .name = "hdmi_sys_div",
1740                 .ops = &clk_regmap_divider_ro_ops,
1741                 .parent_hws = (const struct clk_hw *[]) {
1742                         &meson8b_hdmi_sys_sel.hw
1743                 },
1744                 .num_parents = 1,
1745                 .flags = CLK_SET_RATE_PARENT,
1746         },
1747 };
1748
1749 static struct clk_regmap meson8b_hdmi_sys = {
1750         .data = &(struct clk_regmap_gate_data){
1751                 .offset = HHI_HDMI_CLK_CNTL,
1752                 .bit_idx = 8,
1753         },
1754         .hw.init = &(struct clk_init_data) {
1755                 .name = "hdmi_sys",
1756                 .ops = &clk_regmap_gate_ro_ops,
1757                 .parent_hws = (const struct clk_hw *[]) {
1758                         &meson8b_hdmi_sys_div.hw
1759                 },
1760                 .num_parents = 1,
1761                 .flags = CLK_SET_RATE_PARENT,
1762         },
1763 };
1764
1765 /*
1766  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1767  * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
1768  * has mali_0 and no glitch-free mux.
1769  */
1770 static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
1771         &meson8b_xtal.hw,
1772         &meson8b_mpll2.hw,
1773         &meson8b_mpll1.hw,
1774         &meson8b_fclk_div7.hw,
1775         &meson8b_fclk_div4.hw,
1776         &meson8b_fclk_div3.hw,
1777         &meson8b_fclk_div5.hw,
1778 };
1779
1780 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1781
1782 static struct clk_regmap meson8b_mali_0_sel = {
1783         .data = &(struct clk_regmap_mux_data){
1784                 .offset = HHI_MALI_CLK_CNTL,
1785                 .mask = 0x7,
1786                 .shift = 9,
1787                 .table = meson8b_mali_0_1_mux_table,
1788         },
1789         .hw.init = &(struct clk_init_data){
1790                 .name = "mali_0_sel",
1791                 .ops = &clk_regmap_mux_ops,
1792                 .parent_hws = meson8b_mali_0_1_parent_hws,
1793                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
1794                 /*
1795                  * Don't propagate rate changes up because the only changeable
1796                  * parents are mpll1 and mpll2 but we need those for audio and
1797                  * RGMII (Ethernet). We don't want to change the audio or
1798                  * Ethernet clocks when setting the GPU frequency.
1799                  */
1800                 .flags = 0,
1801         },
1802 };
1803
1804 static struct clk_regmap meson8b_mali_0_div = {
1805         .data = &(struct clk_regmap_div_data){
1806                 .offset = HHI_MALI_CLK_CNTL,
1807                 .shift = 0,
1808                 .width = 7,
1809         },
1810         .hw.init = &(struct clk_init_data){
1811                 .name = "mali_0_div",
1812                 .ops = &clk_regmap_divider_ops,
1813                 .parent_hws = (const struct clk_hw *[]) {
1814                         &meson8b_mali_0_sel.hw
1815                 },
1816                 .num_parents = 1,
1817                 .flags = CLK_SET_RATE_PARENT,
1818         },
1819 };
1820
1821 static struct clk_regmap meson8b_mali_0 = {
1822         .data = &(struct clk_regmap_gate_data){
1823                 .offset = HHI_MALI_CLK_CNTL,
1824                 .bit_idx = 8,
1825         },
1826         .hw.init = &(struct clk_init_data){
1827                 .name = "mali_0",
1828                 .ops = &clk_regmap_gate_ops,
1829                 .parent_hws = (const struct clk_hw *[]) {
1830                         &meson8b_mali_0_div.hw
1831                 },
1832                 .num_parents = 1,
1833                 .flags = CLK_SET_RATE_PARENT,
1834         },
1835 };
1836
1837 static struct clk_regmap meson8b_mali_1_sel = {
1838         .data = &(struct clk_regmap_mux_data){
1839                 .offset = HHI_MALI_CLK_CNTL,
1840                 .mask = 0x7,
1841                 .shift = 25,
1842                 .table = meson8b_mali_0_1_mux_table,
1843         },
1844         .hw.init = &(struct clk_init_data){
1845                 .name = "mali_1_sel",
1846                 .ops = &clk_regmap_mux_ops,
1847                 .parent_hws = meson8b_mali_0_1_parent_hws,
1848                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
1849                 /*
1850                  * Don't propagate rate changes up because the only changeable
1851                  * parents are mpll1 and mpll2 but we need those for audio and
1852                  * RGMII (Ethernet). We don't want to change the audio or
1853                  * Ethernet clocks when setting the GPU frequency.
1854                  */
1855                 .flags = 0,
1856         },
1857 };
1858
1859 static struct clk_regmap meson8b_mali_1_div = {
1860         .data = &(struct clk_regmap_div_data){
1861                 .offset = HHI_MALI_CLK_CNTL,
1862                 .shift = 16,
1863                 .width = 7,
1864         },
1865         .hw.init = &(struct clk_init_data){
1866                 .name = "mali_1_div",
1867                 .ops = &clk_regmap_divider_ops,
1868                 .parent_hws = (const struct clk_hw *[]) {
1869                         &meson8b_mali_1_sel.hw
1870                 },
1871                 .num_parents = 1,
1872                 .flags = CLK_SET_RATE_PARENT,
1873         },
1874 };
1875
1876 static struct clk_regmap meson8b_mali_1 = {
1877         .data = &(struct clk_regmap_gate_data){
1878                 .offset = HHI_MALI_CLK_CNTL,
1879                 .bit_idx = 24,
1880         },
1881         .hw.init = &(struct clk_init_data){
1882                 .name = "mali_1",
1883                 .ops = &clk_regmap_gate_ops,
1884                 .parent_hws = (const struct clk_hw *[]) {
1885                         &meson8b_mali_1_div.hw
1886                 },
1887                 .num_parents = 1,
1888                 .flags = CLK_SET_RATE_PARENT,
1889         },
1890 };
1891
1892 static struct clk_regmap meson8b_mali = {
1893         .data = &(struct clk_regmap_mux_data){
1894                 .offset = HHI_MALI_CLK_CNTL,
1895                 .mask = 1,
1896                 .shift = 31,
1897         },
1898         .hw.init = &(struct clk_init_data){
1899                 .name = "mali",
1900                 .ops = &clk_regmap_mux_ops,
1901                 .parent_hws = (const struct clk_hw *[]) {
1902                         &meson8b_mali_0.hw,
1903                         &meson8b_mali_1.hw,
1904                 },
1905                 .num_parents = 2,
1906                 .flags = CLK_SET_RATE_PARENT,
1907         },
1908 };
1909
1910 static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
1911         PLL_PARAMS(182, 3),
1912         { /* sentinel */ },
1913 };
1914
1915 static struct clk_regmap meson8m2_gp_pll_dco = {
1916         .data = &(struct meson_clk_pll_data){
1917                 .en = {
1918                         .reg_off = HHI_GP_PLL_CNTL,
1919                         .shift   = 30,
1920                         .width   = 1,
1921                 },
1922                 .m = {
1923                         .reg_off = HHI_GP_PLL_CNTL,
1924                         .shift   = 0,
1925                         .width   = 9,
1926                 },
1927                 .n = {
1928                         .reg_off = HHI_GP_PLL_CNTL,
1929                         .shift   = 9,
1930                         .width   = 5,
1931                 },
1932                 .l = {
1933                         .reg_off = HHI_GP_PLL_CNTL,
1934                         .shift   = 31,
1935                         .width   = 1,
1936                 },
1937                 .rst = {
1938                         .reg_off = HHI_GP_PLL_CNTL,
1939                         .shift   = 29,
1940                         .width   = 1,
1941                 },
1942                 .table = meson8m2_gp_pll_params_table,
1943         },
1944         .hw.init = &(struct clk_init_data){
1945                 .name = "gp_pll_dco",
1946                 .ops = &meson_clk_pll_ops,
1947                 .parent_hws = (const struct clk_hw *[]) {
1948                         &meson8b_xtal.hw
1949                 },
1950                 .num_parents = 1,
1951         },
1952 };
1953
1954 static struct clk_regmap meson8m2_gp_pll = {
1955         .data = &(struct clk_regmap_div_data){
1956                 .offset = HHI_GP_PLL_CNTL,
1957                 .shift = 16,
1958                 .width = 2,
1959                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1960         },
1961         .hw.init = &(struct clk_init_data){
1962                 .name = "gp_pll",
1963                 .ops = &clk_regmap_divider_ops,
1964                 .parent_hws = (const struct clk_hw *[]) {
1965                         &meson8m2_gp_pll_dco.hw
1966                 },
1967                 .num_parents = 1,
1968                 .flags = CLK_SET_RATE_PARENT,
1969         },
1970 };
1971
1972 static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
1973         &meson8b_fclk_div4.hw,
1974         &meson8b_fclk_div3.hw,
1975         &meson8b_fclk_div5.hw,
1976         &meson8b_fclk_div7.hw,
1977 };
1978
1979 static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
1980         &meson8b_fclk_div4.hw,
1981         &meson8b_fclk_div3.hw,
1982         &meson8b_fclk_div5.hw,
1983         &meson8m2_gp_pll.hw,
1984 };
1985
1986 static struct clk_regmap meson8b_vpu_0_sel = {
1987         .data = &(struct clk_regmap_mux_data){
1988                 .offset = HHI_VPU_CLK_CNTL,
1989                 .mask = 0x3,
1990                 .shift = 9,
1991         },
1992         .hw.init = &(struct clk_init_data){
1993                 .name = "vpu_0_sel",
1994                 .ops = &clk_regmap_mux_ops,
1995                 .parent_hws = meson8b_vpu_0_1_parent_hws,
1996                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
1997                 .flags = CLK_SET_RATE_PARENT,
1998         },
1999 };
2000
2001 static struct clk_regmap meson8m2_vpu_0_sel = {
2002         .data = &(struct clk_regmap_mux_data){
2003                 .offset = HHI_VPU_CLK_CNTL,
2004                 .mask = 0x3,
2005                 .shift = 9,
2006         },
2007         .hw.init = &(struct clk_init_data){
2008                 .name = "vpu_0_sel",
2009                 .ops = &clk_regmap_mux_ops,
2010                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2011                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2012                 .flags = CLK_SET_RATE_PARENT,
2013         },
2014 };
2015
2016 static struct clk_regmap meson8b_vpu_0_div = {
2017         .data = &(struct clk_regmap_div_data){
2018                 .offset = HHI_VPU_CLK_CNTL,
2019                 .shift = 0,
2020                 .width = 7,
2021         },
2022         .hw.init = &(struct clk_init_data){
2023                 .name = "vpu_0_div",
2024                 .ops = &clk_regmap_divider_ops,
2025                 .parent_data = &(const struct clk_parent_data) {
2026                         /*
2027                          * Note:
2028                          * meson8b and meson8m2 have different vpu_0_sels (with
2029                          * different struct clk_hw). We fallback to the global
2030                          * naming string mechanism so vpu_0_div picks up the
2031                          * appropriate one.
2032                          */
2033                         .name = "vpu_0_sel",
2034                         .index = -1,
2035                 },
2036                 .num_parents = 1,
2037                 .flags = CLK_SET_RATE_PARENT,
2038         },
2039 };
2040
2041 static struct clk_regmap meson8b_vpu_0 = {
2042         .data = &(struct clk_regmap_gate_data){
2043                 .offset = HHI_VPU_CLK_CNTL,
2044                 .bit_idx = 8,
2045         },
2046         .hw.init = &(struct clk_init_data) {
2047                 .name = "vpu_0",
2048                 .ops = &clk_regmap_gate_ops,
2049                 .parent_hws = (const struct clk_hw *[]) {
2050                         &meson8b_vpu_0_div.hw
2051                 },
2052                 .num_parents = 1,
2053                 .flags = CLK_SET_RATE_PARENT,
2054         },
2055 };
2056
2057 static struct clk_regmap meson8b_vpu_1_sel = {
2058         .data = &(struct clk_regmap_mux_data){
2059                 .offset = HHI_VPU_CLK_CNTL,
2060                 .mask = 0x3,
2061                 .shift = 25,
2062         },
2063         .hw.init = &(struct clk_init_data){
2064                 .name = "vpu_1_sel",
2065                 .ops = &clk_regmap_mux_ops,
2066                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2067                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2068                 .flags = CLK_SET_RATE_PARENT,
2069         },
2070 };
2071
2072 static struct clk_regmap meson8m2_vpu_1_sel = {
2073         .data = &(struct clk_regmap_mux_data){
2074                 .offset = HHI_VPU_CLK_CNTL,
2075                 .mask = 0x3,
2076                 .shift = 25,
2077         },
2078         .hw.init = &(struct clk_init_data){
2079                 .name = "vpu_1_sel",
2080                 .ops = &clk_regmap_mux_ops,
2081                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2082                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2083                 .flags = CLK_SET_RATE_PARENT,
2084         },
2085 };
2086
2087 static struct clk_regmap meson8b_vpu_1_div = {
2088         .data = &(struct clk_regmap_div_data){
2089                 .offset = HHI_VPU_CLK_CNTL,
2090                 .shift = 16,
2091                 .width = 7,
2092         },
2093         .hw.init = &(struct clk_init_data){
2094                 .name = "vpu_1_div",
2095                 .ops = &clk_regmap_divider_ops,
2096                 .parent_data = &(const struct clk_parent_data) {
2097                         /*
2098                          * Note:
2099                          * meson8b and meson8m2 have different vpu_1_sels (with
2100                          * different struct clk_hw). We fallback to the global
2101                          * naming string mechanism so vpu_1_div picks up the
2102                          * appropriate one.
2103                          */
2104                         .name = "vpu_1_sel",
2105                         .index = -1,
2106                 },
2107                 .num_parents = 1,
2108                 .flags = CLK_SET_RATE_PARENT,
2109         },
2110 };
2111
2112 static struct clk_regmap meson8b_vpu_1 = {
2113         .data = &(struct clk_regmap_gate_data){
2114                 .offset = HHI_VPU_CLK_CNTL,
2115                 .bit_idx = 24,
2116         },
2117         .hw.init = &(struct clk_init_data) {
2118                 .name = "vpu_1",
2119                 .ops = &clk_regmap_gate_ops,
2120                 .parent_hws = (const struct clk_hw *[]) {
2121                         &meson8b_vpu_1_div.hw
2122                 },
2123                 .num_parents = 1,
2124                 .flags = CLK_SET_RATE_PARENT,
2125         },
2126 };
2127
2128 static struct clk_regmap meson8b_vpu = {
2129         .data = &(struct clk_regmap_mux_data){
2130                 .offset = HHI_VPU_CLK_CNTL,
2131                 .mask = 1,
2132                 .shift = 31,
2133         },
2134         .hw.init = &(struct clk_init_data){
2135                 .name = "vpu",
2136                 .ops = &clk_regmap_mux_ops,
2137                 .parent_hws = (const struct clk_hw *[]) {
2138                         &meson8b_vpu_0.hw,
2139                         &meson8b_vpu_1.hw,
2140                 },
2141                 .num_parents = 2,
2142                 .flags = CLK_SET_RATE_NO_REPARENT,
2143         },
2144 };
2145
2146 static const struct clk_hw *meson8b_vdec_parent_hws[] = {
2147         &meson8b_fclk_div4.hw,
2148         &meson8b_fclk_div3.hw,
2149         &meson8b_fclk_div5.hw,
2150         &meson8b_fclk_div7.hw,
2151         &meson8b_mpll2.hw,
2152         &meson8b_mpll1.hw,
2153 };
2154
2155 static struct clk_regmap meson8b_vdec_1_sel = {
2156         .data = &(struct clk_regmap_mux_data){
2157                 .offset = HHI_VDEC_CLK_CNTL,
2158                 .mask = 0x3,
2159                 .shift = 9,
2160                 .flags = CLK_MUX_ROUND_CLOSEST,
2161         },
2162         .hw.init = &(struct clk_init_data){
2163                 .name = "vdec_1_sel",
2164                 .ops = &clk_regmap_mux_ops,
2165                 .parent_hws = meson8b_vdec_parent_hws,
2166                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2167                 .flags = CLK_SET_RATE_PARENT,
2168         },
2169 };
2170
2171 static struct clk_regmap meson8b_vdec_1_1_div = {
2172         .data = &(struct clk_regmap_div_data){
2173                 .offset = HHI_VDEC_CLK_CNTL,
2174                 .shift = 0,
2175                 .width = 7,
2176                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2177         },
2178         .hw.init = &(struct clk_init_data){
2179                 .name = "vdec_1_1_div",
2180                 .ops = &clk_regmap_divider_ops,
2181                 .parent_hws = (const struct clk_hw *[]) {
2182                         &meson8b_vdec_1_sel.hw
2183                 },
2184                 .num_parents = 1,
2185                 .flags = CLK_SET_RATE_PARENT,
2186         },
2187 };
2188
2189 static struct clk_regmap meson8b_vdec_1_1 = {
2190         .data = &(struct clk_regmap_gate_data){
2191                 .offset = HHI_VDEC_CLK_CNTL,
2192                 .bit_idx = 8,
2193         },
2194         .hw.init = &(struct clk_init_data) {
2195                 .name = "vdec_1_1",
2196                 .ops = &clk_regmap_gate_ops,
2197                 .parent_hws = (const struct clk_hw *[]) {
2198                         &meson8b_vdec_1_1_div.hw
2199                 },
2200                 .num_parents = 1,
2201                 .flags = CLK_SET_RATE_PARENT,
2202         },
2203 };
2204
2205 static struct clk_regmap meson8b_vdec_1_2_div = {
2206         .data = &(struct clk_regmap_div_data){
2207                 .offset = HHI_VDEC3_CLK_CNTL,
2208                 .shift = 0,
2209                 .width = 7,
2210                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2211         },
2212         .hw.init = &(struct clk_init_data){
2213                 .name = "vdec_1_2_div",
2214                 .ops = &clk_regmap_divider_ops,
2215                 .parent_hws = (const struct clk_hw *[]) {
2216                         &meson8b_vdec_1_sel.hw
2217                 },
2218                 .num_parents = 1,
2219                 .flags = CLK_SET_RATE_PARENT,
2220         },
2221 };
2222
2223 static struct clk_regmap meson8b_vdec_1_2 = {
2224         .data = &(struct clk_regmap_gate_data){
2225                 .offset = HHI_VDEC3_CLK_CNTL,
2226                 .bit_idx = 8,
2227         },
2228         .hw.init = &(struct clk_init_data) {
2229                 .name = "vdec_1_2",
2230                 .ops = &clk_regmap_gate_ops,
2231                 .parent_hws = (const struct clk_hw *[]) {
2232                         &meson8b_vdec_1_2_div.hw
2233                 },
2234                 .num_parents = 1,
2235                 .flags = CLK_SET_RATE_PARENT,
2236         },
2237 };
2238
2239 static struct clk_regmap meson8b_vdec_1 = {
2240         .data = &(struct clk_regmap_mux_data){
2241                 .offset = HHI_VDEC3_CLK_CNTL,
2242                 .mask = 0x1,
2243                 .shift = 15,
2244                 .flags = CLK_MUX_ROUND_CLOSEST,
2245         },
2246         .hw.init = &(struct clk_init_data){
2247                 .name = "vdec_1",
2248                 .ops = &clk_regmap_mux_ops,
2249                 .parent_hws = (const struct clk_hw *[]) {
2250                         &meson8b_vdec_1_1.hw,
2251                         &meson8b_vdec_1_2.hw,
2252                 },
2253                 .num_parents = 2,
2254                 .flags = CLK_SET_RATE_PARENT,
2255         },
2256 };
2257
2258 static struct clk_regmap meson8b_vdec_hcodec_sel = {
2259         .data = &(struct clk_regmap_mux_data){
2260                 .offset = HHI_VDEC_CLK_CNTL,
2261                 .mask = 0x3,
2262                 .shift = 25,
2263                 .flags = CLK_MUX_ROUND_CLOSEST,
2264         },
2265         .hw.init = &(struct clk_init_data){
2266                 .name = "vdec_hcodec_sel",
2267                 .ops = &clk_regmap_mux_ops,
2268                 .parent_hws = meson8b_vdec_parent_hws,
2269                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2270                 .flags = CLK_SET_RATE_PARENT,
2271         },
2272 };
2273
2274 static struct clk_regmap meson8b_vdec_hcodec_div = {
2275         .data = &(struct clk_regmap_div_data){
2276                 .offset = HHI_VDEC_CLK_CNTL,
2277                 .shift = 16,
2278                 .width = 7,
2279                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2280         },
2281         .hw.init = &(struct clk_init_data){
2282                 .name = "vdec_hcodec_div",
2283                 .ops = &clk_regmap_divider_ops,
2284                 .parent_hws = (const struct clk_hw *[]) {
2285                         &meson8b_vdec_hcodec_sel.hw
2286                 },
2287                 .num_parents = 1,
2288                 .flags = CLK_SET_RATE_PARENT,
2289         },
2290 };
2291
2292 static struct clk_regmap meson8b_vdec_hcodec = {
2293         .data = &(struct clk_regmap_gate_data){
2294                 .offset = HHI_VDEC_CLK_CNTL,
2295                 .bit_idx = 24,
2296         },
2297         .hw.init = &(struct clk_init_data) {
2298                 .name = "vdec_hcodec",
2299                 .ops = &clk_regmap_gate_ops,
2300                 .parent_hws = (const struct clk_hw *[]) {
2301                         &meson8b_vdec_hcodec_div.hw
2302                 },
2303                 .num_parents = 1,
2304                 .flags = CLK_SET_RATE_PARENT,
2305         },
2306 };
2307
2308 static struct clk_regmap meson8b_vdec_2_sel = {
2309         .data = &(struct clk_regmap_mux_data){
2310                 .offset = HHI_VDEC2_CLK_CNTL,
2311                 .mask = 0x3,
2312                 .shift = 9,
2313                 .flags = CLK_MUX_ROUND_CLOSEST,
2314         },
2315         .hw.init = &(struct clk_init_data){
2316                 .name = "vdec_2_sel",
2317                 .ops = &clk_regmap_mux_ops,
2318                 .parent_hws = meson8b_vdec_parent_hws,
2319                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2320                 .flags = CLK_SET_RATE_PARENT,
2321         },
2322 };
2323
2324 static struct clk_regmap meson8b_vdec_2_div = {
2325         .data = &(struct clk_regmap_div_data){
2326                 .offset = HHI_VDEC2_CLK_CNTL,
2327                 .shift = 0,
2328                 .width = 7,
2329                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2330         },
2331         .hw.init = &(struct clk_init_data){
2332                 .name = "vdec_2_div",
2333                 .ops = &clk_regmap_divider_ops,
2334                 .parent_hws = (const struct clk_hw *[]) {
2335                         &meson8b_vdec_2_sel.hw
2336                 },
2337                 .num_parents = 1,
2338                 .flags = CLK_SET_RATE_PARENT,
2339         },
2340 };
2341
2342 static struct clk_regmap meson8b_vdec_2 = {
2343         .data = &(struct clk_regmap_gate_data){
2344                 .offset = HHI_VDEC2_CLK_CNTL,
2345                 .bit_idx = 8,
2346         },
2347         .hw.init = &(struct clk_init_data) {
2348                 .name = "vdec_2",
2349                 .ops = &clk_regmap_gate_ops,
2350                 .parent_hws = (const struct clk_hw *[]) {
2351                         &meson8b_vdec_2_div.hw
2352                 },
2353                 .num_parents = 1,
2354                 .flags = CLK_SET_RATE_PARENT,
2355         },
2356 };
2357
2358 static struct clk_regmap meson8b_vdec_hevc_sel = {
2359         .data = &(struct clk_regmap_mux_data){
2360                 .offset = HHI_VDEC2_CLK_CNTL,
2361                 .mask = 0x3,
2362                 .shift = 25,
2363                 .flags = CLK_MUX_ROUND_CLOSEST,
2364         },
2365         .hw.init = &(struct clk_init_data){
2366                 .name = "vdec_hevc_sel",
2367                 .ops = &clk_regmap_mux_ops,
2368                 .parent_hws = meson8b_vdec_parent_hws,
2369                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2370                 .flags = CLK_SET_RATE_PARENT,
2371         },
2372 };
2373
2374 static struct clk_regmap meson8b_vdec_hevc_div = {
2375         .data = &(struct clk_regmap_div_data){
2376                 .offset = HHI_VDEC2_CLK_CNTL,
2377                 .shift = 16,
2378                 .width = 7,
2379                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2380         },
2381         .hw.init = &(struct clk_init_data){
2382                 .name = "vdec_hevc_div",
2383                 .ops = &clk_regmap_divider_ops,
2384                 .parent_hws = (const struct clk_hw *[]) {
2385                         &meson8b_vdec_hevc_sel.hw
2386                 },
2387                 .num_parents = 1,
2388                 .flags = CLK_SET_RATE_PARENT,
2389         },
2390 };
2391
2392 static struct clk_regmap meson8b_vdec_hevc_en = {
2393         .data = &(struct clk_regmap_gate_data){
2394                 .offset = HHI_VDEC2_CLK_CNTL,
2395                 .bit_idx = 24,
2396         },
2397         .hw.init = &(struct clk_init_data) {
2398                 .name = "vdec_hevc_en",
2399                 .ops = &clk_regmap_gate_ops,
2400                 .parent_hws = (const struct clk_hw *[]) {
2401                         &meson8b_vdec_hevc_div.hw
2402                 },
2403                 .num_parents = 1,
2404                 .flags = CLK_SET_RATE_PARENT,
2405         },
2406 };
2407
2408 static struct clk_regmap meson8b_vdec_hevc = {
2409         .data = &(struct clk_regmap_mux_data){
2410                 .offset = HHI_VDEC2_CLK_CNTL,
2411                 .mask = 0x1,
2412                 .shift = 31,
2413                 .flags = CLK_MUX_ROUND_CLOSEST,
2414         },
2415         .hw.init = &(struct clk_init_data){
2416                 .name = "vdec_hevc",
2417                 .ops = &clk_regmap_mux_ops,
2418                 /* TODO: The second parent is currently unknown */
2419                 .parent_hws = (const struct clk_hw *[]) {
2420                         &meson8b_vdec_hevc_en.hw
2421                 },
2422                 .num_parents = 1,
2423                 .flags = CLK_SET_RATE_PARENT,
2424         },
2425 };
2426
2427 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2428 static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2429         &meson8b_mpll0.hw,
2430         &meson8b_mpll1.hw,
2431         &meson8b_mpll2.hw
2432 };
2433
2434 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2435
2436 static struct clk_regmap meson8b_cts_amclk_sel = {
2437         .data = &(struct clk_regmap_mux_data){
2438                 .offset = HHI_AUD_CLK_CNTL,
2439                 .mask = 0x3,
2440                 .shift = 9,
2441                 .table = meson8b_cts_amclk_mux_table,
2442                 .flags = CLK_MUX_ROUND_CLOSEST,
2443         },
2444         .hw.init = &(struct clk_init_data){
2445                 .name = "cts_amclk_sel",
2446                 .ops = &clk_regmap_mux_ops,
2447                 .parent_hws = meson8b_cts_amclk_parent_hws,
2448                 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2449         },
2450 };
2451
2452 static struct clk_regmap meson8b_cts_amclk_div = {
2453         .data = &(struct clk_regmap_div_data) {
2454                 .offset = HHI_AUD_CLK_CNTL,
2455                 .shift = 0,
2456                 .width = 8,
2457                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2458         },
2459         .hw.init = &(struct clk_init_data){
2460                 .name = "cts_amclk_div",
2461                 .ops = &clk_regmap_divider_ops,
2462                 .parent_hws = (const struct clk_hw *[]) {
2463                         &meson8b_cts_amclk_sel.hw
2464                 },
2465                 .num_parents = 1,
2466                 .flags = CLK_SET_RATE_PARENT,
2467         },
2468 };
2469
2470 static struct clk_regmap meson8b_cts_amclk = {
2471         .data = &(struct clk_regmap_gate_data){
2472                 .offset = HHI_AUD_CLK_CNTL,
2473                 .bit_idx = 8,
2474         },
2475         .hw.init = &(struct clk_init_data){
2476                 .name = "cts_amclk",
2477                 .ops = &clk_regmap_gate_ops,
2478                 .parent_hws = (const struct clk_hw *[]) {
2479                         &meson8b_cts_amclk_div.hw
2480                 },
2481                 .num_parents = 1,
2482                 .flags = CLK_SET_RATE_PARENT,
2483         },
2484 };
2485
2486 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2487 static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2488         &meson8b_mpll0.hw,
2489         &meson8b_mpll1.hw,
2490         &meson8b_mpll2.hw
2491 };
2492
2493 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2494
2495 static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2496         .data = &(struct clk_regmap_mux_data){
2497                 .offset = HHI_AUD_CLK_CNTL2,
2498                 .mask = 0x3,
2499                 .shift = 25,
2500                 .table = meson8b_cts_mclk_i958_mux_table,
2501                 .flags = CLK_MUX_ROUND_CLOSEST,
2502         },
2503         .hw.init = &(struct clk_init_data) {
2504                 .name = "cts_mclk_i958_sel",
2505                 .ops = &clk_regmap_mux_ops,
2506                 .parent_hws = meson8b_cts_mclk_i958_parent_hws,
2507                 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2508         },
2509 };
2510
2511 static struct clk_regmap meson8b_cts_mclk_i958_div = {
2512         .data = &(struct clk_regmap_div_data){
2513                 .offset = HHI_AUD_CLK_CNTL2,
2514                 .shift = 16,
2515                 .width = 8,
2516                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2517         },
2518         .hw.init = &(struct clk_init_data) {
2519                 .name = "cts_mclk_i958_div",
2520                 .ops = &clk_regmap_divider_ops,
2521                 .parent_hws = (const struct clk_hw *[]) {
2522                         &meson8b_cts_mclk_i958_sel.hw
2523                 },
2524                 .num_parents = 1,
2525                 .flags = CLK_SET_RATE_PARENT,
2526         },
2527 };
2528
2529 static struct clk_regmap meson8b_cts_mclk_i958 = {
2530         .data = &(struct clk_regmap_gate_data){
2531                 .offset = HHI_AUD_CLK_CNTL2,
2532                 .bit_idx = 24,
2533         },
2534         .hw.init = &(struct clk_init_data){
2535                 .name = "cts_mclk_i958",
2536                 .ops = &clk_regmap_gate_ops,
2537                 .parent_hws = (const struct clk_hw *[]) {
2538                         &meson8b_cts_mclk_i958_div.hw
2539                 },
2540                 .num_parents = 1,
2541                 .flags = CLK_SET_RATE_PARENT,
2542         },
2543 };
2544
2545 static struct clk_regmap meson8b_cts_i958 = {
2546         .data = &(struct clk_regmap_mux_data){
2547                 .offset = HHI_AUD_CLK_CNTL2,
2548                 .mask = 0x1,
2549                 .shift = 27,
2550                 },
2551         .hw.init = &(struct clk_init_data){
2552                 .name = "cts_i958",
2553                 .ops = &clk_regmap_mux_ops,
2554                 .parent_hws = (const struct clk_hw *[]) {
2555                         &meson8b_cts_amclk.hw,
2556                         &meson8b_cts_mclk_i958.hw
2557                 },
2558                 .num_parents = 2,
2559                 /*
2560                  * The parent is specific to origin of the audio data. Let the
2561                  * consumer choose the appropriate parent.
2562                  */
2563                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2564         },
2565 };
2566
2567 #define MESON_GATE(_name, _reg, _bit) \
2568         MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2569
2570 /* Everything Else (EE) domain gates */
2571
2572 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2573 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2574 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2575 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2576 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2577 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2578 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2579 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2580 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2581 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2582 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2583 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2584 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2585 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2586 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2587 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2588 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2589 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2590 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2591
2592 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2593 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2594 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2595 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
2596 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2597 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2598 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2599 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2600 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2601 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2602 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2603 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2604 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2605 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2606 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2607 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2608 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2609 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2610 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2611 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2612 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2613 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2614 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2615 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2616 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2617
2618 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2619 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2620 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2621 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2622 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2623 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2624 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2625 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2626 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2627 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2628 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2629 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2630 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2631
2632 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2633 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2634 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2635 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2636 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2637 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2638 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2639 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2640 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2641 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2642 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2643 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2644 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2645 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2646 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2647 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2648
2649 /* Always On (AO) domain gates */
2650
2651 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2652 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2653 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2654 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2655
2656 static struct clk_hw_onecell_data meson8_hw_onecell_data = {
2657         .hws = {
2658                 [CLKID_XTAL] = &meson8b_xtal.hw,
2659                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2660                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2661                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2662                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2663                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2664                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2665                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2666                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2667                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2668                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2669                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2670                 [CLKID_CLK81] = &meson8b_clk81.hw,
2671                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2672                 [CLKID_DOS]                 = &meson8b_dos.hw,
2673                 [CLKID_ISA]                 = &meson8b_isa.hw,
2674                 [CLKID_PL301]               = &meson8b_pl301.hw,
2675                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2676                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2677                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2678                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2679                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2680                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2681                 [CLKID_UART0]               = &meson8b_uart0.hw,
2682                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2683                 [CLKID_STREAM]              = &meson8b_stream.hw,
2684                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2685                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2686                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2687                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2688                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2689                 [CLKID_SPI]                 = &meson8b_spi.hw,
2690                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2691                 [CLKID_ETH]                 = &meson8b_eth.hw,
2692                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2693                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2694                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2695                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2696                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2697                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2698                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2699                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2700                 [CLKID_ADC]                 = &meson8b_adc.hw,
2701                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2702                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2703                 [CLKID_UART1]               = &meson8b_uart1.hw,
2704                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2705                 [CLKID_USB0]                = &meson8b_usb0.hw,
2706                 [CLKID_USB1]                = &meson8b_usb1.hw,
2707                 [CLKID_RESET]               = &meson8b_reset.hw,
2708                 [CLKID_NAND]                = &meson8b_nand.hw,
2709                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2710                 [CLKID_USB]                 = &meson8b_usb.hw,
2711                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2712                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2713                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2714                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2715                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2716                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2717                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2718                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2719                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2720                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2721                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2722                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2723                 [CLKID_UART2]               = &meson8b_uart2.hw,
2724                 [CLKID_SANA]                = &meson8b_sana.hw,
2725                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2726                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2727                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2728                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2729                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2730                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2731                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2732                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2733                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2734                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2735                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2736                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2737                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2738                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2739                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2740                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2741                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2742                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2743                 [CLKID_EDP]                 = &meson8b_edp.hw,
2744                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2745                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2746                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2747                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2748                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2749                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2750                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2751                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2752                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2753                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2754                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2755                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2756                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2757                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2758                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2759                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2760                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2761                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2762                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2763                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2764                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2765                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2766                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2767                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2768                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2769                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2770                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2771                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2772                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2773                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2774                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2775                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2776                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2777                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2778                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2779                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2780                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2781                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2782                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2783                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2784                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2785                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2786                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2787                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2788                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2789                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2790                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2791                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2792                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2793                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2794                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2795                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2796                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2797                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2798                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2799                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2800                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2801                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2802                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2803                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2804                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2805                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2806                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2807                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2808                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2809                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2810                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2811                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2812                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2813                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2814                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2815                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2816                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2817                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2818                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2819                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2820                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2821                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2822                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2823                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2824                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2825                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2826                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2827                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2828                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2829                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2830                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2831                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2832                 [CLKID_MALI]                = &meson8b_mali_0.hw,
2833                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
2834                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2835                 [CLKID_VPU]                 = &meson8b_vpu_0.hw,
2836                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2837                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2838                 [CLKID_VDEC_1]              = &meson8b_vdec_1_1.hw,
2839                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2840                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2841                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2842                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2843                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2844                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2845                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2846                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2847                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2848                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2849                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2850                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2851                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2852                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2853                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
2854                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
2855                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
2856                 [CLK_NR_CLKS]               = NULL,
2857         },
2858         .num = CLK_NR_CLKS,
2859 };
2860
2861 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
2862         .hws = {
2863                 [CLKID_XTAL] = &meson8b_xtal.hw,
2864                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2865                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2866                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2867                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2868                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2869                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2870                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2871                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2872                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2873                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2874                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2875                 [CLKID_CLK81] = &meson8b_clk81.hw,
2876                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2877                 [CLKID_DOS]                 = &meson8b_dos.hw,
2878                 [CLKID_ISA]                 = &meson8b_isa.hw,
2879                 [CLKID_PL301]               = &meson8b_pl301.hw,
2880                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2881                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2882                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2883                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2884                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2885                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2886                 [CLKID_UART0]               = &meson8b_uart0.hw,
2887                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2888                 [CLKID_STREAM]              = &meson8b_stream.hw,
2889                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2890                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2891                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2892                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2893                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2894                 [CLKID_SPI]                 = &meson8b_spi.hw,
2895                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2896                 [CLKID_ETH]                 = &meson8b_eth.hw,
2897                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2898                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2899                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2900                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2901                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2902                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2903                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2904                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2905                 [CLKID_ADC]                 = &meson8b_adc.hw,
2906                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2907                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2908                 [CLKID_UART1]               = &meson8b_uart1.hw,
2909                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2910                 [CLKID_USB0]                = &meson8b_usb0.hw,
2911                 [CLKID_USB1]                = &meson8b_usb1.hw,
2912                 [CLKID_RESET]               = &meson8b_reset.hw,
2913                 [CLKID_NAND]                = &meson8b_nand.hw,
2914                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2915                 [CLKID_USB]                 = &meson8b_usb.hw,
2916                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2917                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2918                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2919                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2920                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2921                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2922                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2923                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2924                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2925                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2926                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2927                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2928                 [CLKID_UART2]               = &meson8b_uart2.hw,
2929                 [CLKID_SANA]                = &meson8b_sana.hw,
2930                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2931                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2932                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2933                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2934                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2935                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2936                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2937                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2938                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2939                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2940                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2941                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2942                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2943                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2944                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2945                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2946                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2947                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2948                 [CLKID_EDP]                 = &meson8b_edp.hw,
2949                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2950                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2951                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2952                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2953                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2954                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2955                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2956                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2957                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2958                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2959                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2960                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2961                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2962                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2963                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2964                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2965                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2966                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2967                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2968                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2969                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2970                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2971                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2972                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2973                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2974                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2975                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2976                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2977                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2978                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2979                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2980                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2981                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2982                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2983                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2984                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2985                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2986                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2987                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2988                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2989                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2990                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2991                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2992                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2993                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2994                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2995                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2996                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2997                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2998                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2999                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3000                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3001                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3002                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3003                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3004                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3005                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3006                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3007                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3008                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3009                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3010                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3011                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3012                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3013                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3014                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3015                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3016                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3017                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3018                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3019                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3020                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3021                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3022                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3023                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3024                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3025                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3026                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3027                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3028                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3029                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3030                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3031                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3032                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3033                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3034                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3035                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3036                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3037                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3038                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3039                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3040                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3041                 [CLKID_MALI]                = &meson8b_mali.hw,
3042                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
3043                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3044                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3045                 [CLKID_VPU_1_SEL]           = &meson8b_vpu_1_sel.hw,
3046                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3047                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3048                 [CLKID_VPU]                 = &meson8b_vpu.hw,
3049                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3050                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3051                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3052                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3053                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3054                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3055                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3056                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3057                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3058                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3059                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3060                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3061                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3062                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3063                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3064                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3065                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3066                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3067                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3068                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3069                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3070                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3071                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3072                 [CLK_NR_CLKS]               = NULL,
3073         },
3074         .num = CLK_NR_CLKS,
3075 };
3076
3077 static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
3078         .hws = {
3079                 [CLKID_XTAL] = &meson8b_xtal.hw,
3080                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3081                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3082                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3083                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3084                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3085                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3086                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3087                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3088                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3089                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3090                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3091                 [CLKID_CLK81] = &meson8b_clk81.hw,
3092                 [CLKID_DDR]                 = &meson8b_ddr.hw,
3093                 [CLKID_DOS]                 = &meson8b_dos.hw,
3094                 [CLKID_ISA]                 = &meson8b_isa.hw,
3095                 [CLKID_PL301]               = &meson8b_pl301.hw,
3096                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
3097                 [CLKID_SPICC]               = &meson8b_spicc.hw,
3098                 [CLKID_I2C]                 = &meson8b_i2c.hw,
3099                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
3100                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
3101                 [CLKID_RNG0]                = &meson8b_rng0.hw,
3102                 [CLKID_UART0]               = &meson8b_uart0.hw,
3103                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
3104                 [CLKID_STREAM]              = &meson8b_stream.hw,
3105                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
3106                 [CLKID_SDIO]                = &meson8b_sdio.hw,
3107                 [CLKID_ABUF]                = &meson8b_abuf.hw,
3108                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
3109                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
3110                 [CLKID_SPI]                 = &meson8b_spi.hw,
3111                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
3112                 [CLKID_ETH]                 = &meson8b_eth.hw,
3113                 [CLKID_DEMUX]               = &meson8b_demux.hw,
3114                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
3115                 [CLKID_IEC958]              = &meson8b_iec958.hw,
3116                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
3117                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
3118                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
3119                 [CLKID_MIXER]               = &meson8b_mixer.hw,
3120                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
3121                 [CLKID_ADC]                 = &meson8b_adc.hw,
3122                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
3123                 [CLKID_AIU]                 = &meson8b_aiu.hw,
3124                 [CLKID_UART1]               = &meson8b_uart1.hw,
3125                 [CLKID_G2D]                 = &meson8b_g2d.hw,
3126                 [CLKID_USB0]                = &meson8b_usb0.hw,
3127                 [CLKID_USB1]                = &meson8b_usb1.hw,
3128                 [CLKID_RESET]               = &meson8b_reset.hw,
3129                 [CLKID_NAND]                = &meson8b_nand.hw,
3130                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
3131                 [CLKID_USB]                 = &meson8b_usb.hw,
3132                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
3133                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
3134                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
3135                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
3136                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
3137                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
3138                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
3139                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
3140                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
3141                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
3142                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
3143                 [CLKID_DVIN]                = &meson8b_dvin.hw,
3144                 [CLKID_UART2]               = &meson8b_uart2.hw,
3145                 [CLKID_SANA]                = &meson8b_sana.hw,
3146                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
3147                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3148                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
3149                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
3150                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
3151                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
3152                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
3153                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
3154                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
3155                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
3156                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
3157                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
3158                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
3159                 [CLKID_RNG1]                = &meson8b_rng1.hw,
3160                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
3161                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
3162                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
3163                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
3164                 [CLKID_EDP]                 = &meson8b_edp.hw,
3165                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3166                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3167                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3168                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3169                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3170                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3171                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3172                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3173                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3174                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3175                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3176                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3177                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3178                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3179                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3180                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3181                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3182                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3183                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3184                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3185                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3186                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3187                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3188                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3189                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3190                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3191                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3192                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3193                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3194                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3195                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3196                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3197                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3198                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3199                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3200                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3201                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3202                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3203                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3204                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3205                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3206                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3207                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3208                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3209                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3210                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3211                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3212                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3213                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3214                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3215                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3216                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3217                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3218                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3219                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3220                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3221                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3222                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3223                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3224                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3225                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3226                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3227                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3228                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3229                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3230                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3231                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3232                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3233                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3234                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3235                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3236                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3237                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3238                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3239                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3240                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3241                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3242                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3243                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3244                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3245                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3246                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3247                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3248                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3249                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3250                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3251                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3252                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3253                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3254                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3255                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3256                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3257                 [CLKID_MALI]                = &meson8b_mali.hw,
3258                 [CLKID_GP_PLL_DCO]          = &meson8m2_gp_pll_dco.hw,
3259                 [CLKID_GP_PLL]              = &meson8m2_gp_pll.hw,
3260                 [CLKID_VPU_0_SEL]           = &meson8m2_vpu_0_sel.hw,
3261                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3262                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3263                 [CLKID_VPU_1_SEL]           = &meson8m2_vpu_1_sel.hw,
3264                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3265                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3266                 [CLKID_VPU]                 = &meson8b_vpu.hw,
3267                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3268                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3269                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3270                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3271                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3272                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3273                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3274                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3275                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3276                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3277                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3278                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3279                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3280                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3281                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3282                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3283                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3284                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3285                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3286                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3287                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3288                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3289                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3290                 [CLK_NR_CLKS]               = NULL,
3291         },
3292         .num = CLK_NR_CLKS,
3293 };
3294
3295 static struct clk_regmap *const meson8b_clk_regmaps[] = {
3296         &meson8b_clk81,
3297         &meson8b_ddr,
3298         &meson8b_dos,
3299         &meson8b_isa,
3300         &meson8b_pl301,
3301         &meson8b_periphs,
3302         &meson8b_spicc,
3303         &meson8b_i2c,
3304         &meson8b_sar_adc,
3305         &meson8b_smart_card,
3306         &meson8b_rng0,
3307         &meson8b_uart0,
3308         &meson8b_sdhc,
3309         &meson8b_stream,
3310         &meson8b_async_fifo,
3311         &meson8b_sdio,
3312         &meson8b_abuf,
3313         &meson8b_hiu_iface,
3314         &meson8b_assist_misc,
3315         &meson8b_spi,
3316         &meson8b_i2s_spdif,
3317         &meson8b_eth,
3318         &meson8b_demux,
3319         &meson8b_aiu_glue,
3320         &meson8b_iec958,
3321         &meson8b_i2s_out,
3322         &meson8b_amclk,
3323         &meson8b_aififo2,
3324         &meson8b_mixer,
3325         &meson8b_mixer_iface,
3326         &meson8b_adc,
3327         &meson8b_blkmv,
3328         &meson8b_aiu,
3329         &meson8b_uart1,
3330         &meson8b_g2d,
3331         &meson8b_usb0,
3332         &meson8b_usb1,
3333         &meson8b_reset,
3334         &meson8b_nand,
3335         &meson8b_dos_parser,
3336         &meson8b_usb,
3337         &meson8b_vdin1,
3338         &meson8b_ahb_arb0,
3339         &meson8b_efuse,
3340         &meson8b_boot_rom,
3341         &meson8b_ahb_data_bus,
3342         &meson8b_ahb_ctrl_bus,
3343         &meson8b_hdmi_intr_sync,
3344         &meson8b_hdmi_pclk,
3345         &meson8b_usb1_ddr_bridge,
3346         &meson8b_usb0_ddr_bridge,
3347         &meson8b_mmc_pclk,
3348         &meson8b_dvin,
3349         &meson8b_uart2,
3350         &meson8b_sana,
3351         &meson8b_vpu_intr,
3352         &meson8b_sec_ahb_ahb3_bridge,
3353         &meson8b_clk81_a9,
3354         &meson8b_vclk2_venci0,
3355         &meson8b_vclk2_venci1,
3356         &meson8b_vclk2_vencp0,
3357         &meson8b_vclk2_vencp1,
3358         &meson8b_gclk_venci_int,
3359         &meson8b_gclk_vencp_int,
3360         &meson8b_dac_clk,
3361         &meson8b_aoclk_gate,
3362         &meson8b_iec958_gate,
3363         &meson8b_enc480p,
3364         &meson8b_rng1,
3365         &meson8b_gclk_vencl_int,
3366         &meson8b_vclk2_venclmcc,
3367         &meson8b_vclk2_vencl,
3368         &meson8b_vclk2_other,
3369         &meson8b_edp,
3370         &meson8b_ao_media_cpu,
3371         &meson8b_ao_ahb_sram,
3372         &meson8b_ao_ahb_bus,
3373         &meson8b_ao_iface,
3374         &meson8b_mpeg_clk_div,
3375         &meson8b_mpeg_clk_sel,
3376         &meson8b_mpll0,
3377         &meson8b_mpll1,
3378         &meson8b_mpll2,
3379         &meson8b_mpll0_div,
3380         &meson8b_mpll1_div,
3381         &meson8b_mpll2_div,
3382         &meson8b_fixed_pll,
3383         &meson8b_sys_pll,
3384         &meson8b_cpu_in_sel,
3385         &meson8b_cpu_scale_div,
3386         &meson8b_cpu_scale_out_sel,
3387         &meson8b_cpu_clk,
3388         &meson8b_mpll_prediv,
3389         &meson8b_fclk_div2,
3390         &meson8b_fclk_div3,
3391         &meson8b_fclk_div4,
3392         &meson8b_fclk_div5,
3393         &meson8b_fclk_div7,
3394         &meson8b_nand_clk_sel,
3395         &meson8b_nand_clk_div,
3396         &meson8b_nand_clk_gate,
3397         &meson8b_fixed_pll_dco,
3398         &meson8b_hdmi_pll_dco,
3399         &meson8b_sys_pll_dco,
3400         &meson8b_apb_clk_sel,
3401         &meson8b_apb_clk_gate,
3402         &meson8b_periph_clk_sel,
3403         &meson8b_periph_clk_gate,
3404         &meson8b_axi_clk_sel,
3405         &meson8b_axi_clk_gate,
3406         &meson8b_l2_dram_clk_sel,
3407         &meson8b_l2_dram_clk_gate,
3408         &meson8b_hdmi_pll_lvds_out,
3409         &meson8b_hdmi_pll_hdmi_out,
3410         &meson8b_vid_pll_in_sel,
3411         &meson8b_vid_pll_in_en,
3412         &meson8b_vid_pll_pre_div,
3413         &meson8b_vid_pll_post_div,
3414         &meson8b_vid_pll,
3415         &meson8b_vid_pll_final_div,
3416         &meson8b_vclk_in_sel,
3417         &meson8b_vclk_in_en,
3418         &meson8b_vclk_div1_gate,
3419         &meson8b_vclk_div2_div_gate,
3420         &meson8b_vclk_div4_div_gate,
3421         &meson8b_vclk_div6_div_gate,
3422         &meson8b_vclk_div12_div_gate,
3423         &meson8b_vclk2_in_sel,
3424         &meson8b_vclk2_clk_in_en,
3425         &meson8b_vclk2_div1_gate,
3426         &meson8b_vclk2_div2_div_gate,
3427         &meson8b_vclk2_div4_div_gate,
3428         &meson8b_vclk2_div6_div_gate,
3429         &meson8b_vclk2_div12_div_gate,
3430         &meson8b_cts_enct_sel,
3431         &meson8b_cts_enct,
3432         &meson8b_cts_encp_sel,
3433         &meson8b_cts_encp,
3434         &meson8b_cts_enci_sel,
3435         &meson8b_cts_enci,
3436         &meson8b_hdmi_tx_pixel_sel,
3437         &meson8b_hdmi_tx_pixel,
3438         &meson8b_cts_encl_sel,
3439         &meson8b_cts_encl,
3440         &meson8b_cts_vdac0_sel,
3441         &meson8b_cts_vdac0,
3442         &meson8b_hdmi_sys_sel,
3443         &meson8b_hdmi_sys_div,
3444         &meson8b_hdmi_sys,
3445         &meson8b_mali_0_sel,
3446         &meson8b_mali_0_div,
3447         &meson8b_mali_0,
3448         &meson8b_mali_1_sel,
3449         &meson8b_mali_1_div,
3450         &meson8b_mali_1,
3451         &meson8b_mali,
3452         &meson8m2_gp_pll_dco,
3453         &meson8m2_gp_pll,
3454         &meson8b_vpu_0_sel,
3455         &meson8m2_vpu_0_sel,
3456         &meson8b_vpu_0_div,
3457         &meson8b_vpu_0,
3458         &meson8b_vpu_1_sel,
3459         &meson8m2_vpu_1_sel,
3460         &meson8b_vpu_1_div,
3461         &meson8b_vpu_1,
3462         &meson8b_vpu,
3463         &meson8b_vdec_1_sel,
3464         &meson8b_vdec_1_1_div,
3465         &meson8b_vdec_1_1,
3466         &meson8b_vdec_1_2_div,
3467         &meson8b_vdec_1_2,
3468         &meson8b_vdec_1,
3469         &meson8b_vdec_hcodec_sel,
3470         &meson8b_vdec_hcodec_div,
3471         &meson8b_vdec_hcodec,
3472         &meson8b_vdec_2_sel,
3473         &meson8b_vdec_2_div,
3474         &meson8b_vdec_2,
3475         &meson8b_vdec_hevc_sel,
3476         &meson8b_vdec_hevc_div,
3477         &meson8b_vdec_hevc_en,
3478         &meson8b_vdec_hevc,
3479         &meson8b_cts_amclk,
3480         &meson8b_cts_amclk_sel,
3481         &meson8b_cts_amclk_div,
3482         &meson8b_cts_mclk_i958_sel,
3483         &meson8b_cts_mclk_i958_div,
3484         &meson8b_cts_mclk_i958,
3485         &meson8b_cts_i958,
3486 };
3487
3488 static const struct meson8b_clk_reset_line {
3489         u32 reg;
3490         u8 bit_idx;
3491 } meson8b_clk_reset_bits[] = {
3492         [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
3493                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
3494         },
3495         [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
3496                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
3497         },
3498         [CLKC_RESET_SCU_SOFT_RESET] = {
3499                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
3500         },
3501         [CLKC_RESET_CPU3_SOFT_RESET] = {
3502                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
3503         },
3504         [CLKC_RESET_CPU2_SOFT_RESET] = {
3505                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
3506         },
3507         [CLKC_RESET_CPU1_SOFT_RESET] = {
3508                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
3509         },
3510         [CLKC_RESET_CPU0_SOFT_RESET] = {
3511                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
3512         },
3513         [CLKC_RESET_A5_GLOBAL_RESET] = {
3514                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
3515         },
3516         [CLKC_RESET_A5_AXI_SOFT_RESET] = {
3517                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
3518         },
3519         [CLKC_RESET_A5_ABP_SOFT_RESET] = {
3520                 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
3521         },
3522         [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
3523                 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
3524         },
3525         [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
3526                 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
3527         },
3528         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
3529                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
3530         },
3531         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
3532                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
3533         },
3534         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
3535                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
3536         },
3537         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
3538                 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
3539         },
3540 };
3541
3542 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
3543                                     unsigned long id, bool assert)
3544 {
3545         struct meson8b_clk_reset *meson8b_clk_reset =
3546                 container_of(rcdev, struct meson8b_clk_reset, reset);
3547         unsigned long flags;
3548         const struct meson8b_clk_reset_line *reset;
3549
3550         if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
3551                 return -EINVAL;
3552
3553         reset = &meson8b_clk_reset_bits[id];
3554
3555         spin_lock_irqsave(&meson_clk_lock, flags);
3556
3557         if (assert)
3558                 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3559                                    BIT(reset->bit_idx), BIT(reset->bit_idx));
3560         else
3561                 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3562                                    BIT(reset->bit_idx), 0);
3563
3564         spin_unlock_irqrestore(&meson_clk_lock, flags);
3565
3566         return 0;
3567 }
3568
3569 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
3570                                      unsigned long id)
3571 {
3572         return meson8b_clk_reset_update(rcdev, id, true);
3573 }
3574
3575 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
3576                                        unsigned long id)
3577 {
3578         return meson8b_clk_reset_update(rcdev, id, false);
3579 }
3580
3581 static const struct reset_control_ops meson8b_clk_reset_ops = {
3582         .assert = meson8b_clk_reset_assert,
3583         .deassert = meson8b_clk_reset_deassert,
3584 };
3585
3586 struct meson8b_nb_data {
3587         struct notifier_block nb;
3588         struct clk_hw_onecell_data *onecell_data;
3589 };
3590
3591 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
3592                                        unsigned long event, void *data)
3593 {
3594         struct meson8b_nb_data *nb_data =
3595                 container_of(nb, struct meson8b_nb_data, nb);
3596         struct clk_hw **hws = nb_data->onecell_data->hws;
3597         struct clk_hw *cpu_clk_hw, *parent_clk_hw;
3598         struct clk *cpu_clk, *parent_clk;
3599         int ret;
3600
3601         switch (event) {
3602         case PRE_RATE_CHANGE:
3603                 parent_clk_hw = hws[CLKID_XTAL];
3604                 break;
3605
3606         case POST_RATE_CHANGE:
3607                 parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL];
3608                 break;
3609
3610         default:
3611                 return NOTIFY_DONE;
3612         }
3613
3614         cpu_clk_hw = hws[CLKID_CPUCLK];
3615         cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
3616
3617         parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
3618
3619         ret = clk_set_parent(cpu_clk, parent_clk);
3620         if (ret)
3621                 return notifier_from_errno(ret);
3622
3623         udelay(100);
3624
3625         return NOTIFY_OK;
3626 }
3627
3628 static struct meson8b_nb_data meson8b_cpu_nb_data = {
3629         .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
3630 };
3631
3632 static const struct regmap_config clkc_regmap_config = {
3633         .reg_bits       = 32,
3634         .val_bits       = 32,
3635         .reg_stride     = 4,
3636 };
3637
3638 static void __init meson8b_clkc_init_common(struct device_node *np,
3639                         struct clk_hw_onecell_data *clk_hw_onecell_data)
3640 {
3641         struct meson8b_clk_reset *rstc;
3642         const char *notifier_clk_name;
3643         struct clk *notifier_clk;
3644         void __iomem *clk_base;
3645         struct regmap *map;
3646         int i, ret;
3647
3648         map = syscon_node_to_regmap(of_get_parent(np));
3649         if (IS_ERR(map)) {
3650                 pr_info("failed to get HHI regmap - Trying obsolete regs\n");
3651
3652                 /* Generic clocks, PLLs and some of the reset-bits */
3653                 clk_base = of_iomap(np, 1);
3654                 if (!clk_base) {
3655                         pr_err("%s: Unable to map clk base\n", __func__);
3656                         return;
3657                 }
3658
3659                 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
3660                 if (IS_ERR(map))
3661                         return;
3662         }
3663
3664         rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
3665         if (!rstc)
3666                 return;
3667
3668         /* Reset Controller */
3669         rstc->regmap = map;
3670         rstc->reset.ops = &meson8b_clk_reset_ops;
3671         rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
3672         rstc->reset.of_node = np;
3673         ret = reset_controller_register(&rstc->reset);
3674         if (ret) {
3675                 pr_err("%s: Failed to register clkc reset controller: %d\n",
3676                        __func__, ret);
3677                 return;
3678         }
3679
3680         /* Populate regmap for the regmap backed clocks */
3681         for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3682                 meson8b_clk_regmaps[i]->map = map;
3683
3684         /*
3685          * register all clks
3686          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
3687          */
3688         for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
3689                 /* array might be sparse */
3690                 if (!clk_hw_onecell_data->hws[i])
3691                         continue;
3692
3693                 ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
3694                 if (ret)
3695                         return;
3696         }
3697
3698         meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
3699
3700         /*
3701          * FIXME we shouldn't program the muxes in notifier handlers. The
3702          * tricky programming sequence will be handled by the forthcoming
3703          * coordinated clock rates mechanism once that feature is released.
3704          */
3705         notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
3706         notifier_clk = __clk_lookup(notifier_clk_name);
3707         ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
3708         if (ret) {
3709                 pr_err("%s: failed to register the CPU clock notifier\n",
3710                        __func__);
3711                 return;
3712         }
3713
3714         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
3715                                      clk_hw_onecell_data);
3716         if (ret)
3717                 pr_err("%s: failed to register clock provider\n", __func__);
3718 }
3719
3720 static void __init meson8_clkc_init(struct device_node *np)
3721 {
3722         return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
3723 }
3724
3725 static void __init meson8b_clkc_init(struct device_node *np)
3726 {
3727         return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
3728 }
3729
3730 static void __init meson8m2_clkc_init(struct device_node *np)
3731 {
3732         return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
3733 }
3734
3735 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3736                       meson8_clkc_init);
3737 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3738                       meson8b_clkc_init);
3739 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
3740                       meson8m2_clkc_init);