drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28
  29 struct amd_vce_state {
  30         /* vce clocks */
  31         u32 evclk;
  32         u32 ecclk;
  33         /* gpu clocks */
  34         u32 sclk;
  35         u32 mclk;
  36         u8 clk_idx;
  37         u8 pstate;
  38 };
  39
  40
  41 enum amd_dpm_forced_level {
  42         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  43         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  44         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  45         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  46         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  47         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  48         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  49         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  50         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  51         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  52 };
  53
  54 enum amd_pm_state_type {
  55         /* not used for dpm */
  56         POWER_STATE_TYPE_DEFAULT,
  57         POWER_STATE_TYPE_POWERSAVE,
  58         /* user selectable states */
  59         POWER_STATE_TYPE_BATTERY,
  60         POWER_STATE_TYPE_BALANCED,
  61         POWER_STATE_TYPE_PERFORMANCE,
  62         /* internal states */
  63         POWER_STATE_TYPE_INTERNAL_UVD,
  64         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  65         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  66         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  67         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  68         POWER_STATE_TYPE_INTERNAL_BOOT,
  69         POWER_STATE_TYPE_INTERNAL_THERMAL,
  70         POWER_STATE_TYPE_INTERNAL_ACPI,
  71         POWER_STATE_TYPE_INTERNAL_ULV,
  72         POWER_STATE_TYPE_INTERNAL_3DPERF,
  73 };
  74
  75 #define AMD_MAX_VCE_LEVELS 6
  76
  77 enum amd_vce_level {
  78         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  79         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  80         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  81         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  82         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  83         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  84 };
  85
  86 enum amd_fan_ctrl_mode {
  87         AMD_FAN_CTRL_NONE = 0,
  88         AMD_FAN_CTRL_MANUAL = 1,
  89         AMD_FAN_CTRL_AUTO = 2,
  90 };
  91
  92 enum pp_clock_type {
  93         PP_SCLK,
  94         PP_MCLK,
  95         PP_PCIE,
  96         PP_SOCCLK,
  97         PP_FCLK,
  98         PP_DCEFCLK,
  99         PP_VCLK,
 100         PP_DCLK,
 101         OD_SCLK,
 102         OD_MCLK,
 103         OD_VDDC_CURVE,
 104         OD_RANGE,
 105         OD_VDDGFX_OFFSET,
 106         OD_CCLK,
 107 };
 108
 109 enum amd_pp_sensors {
 110         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 111         AMDGPU_PP_SENSOR_CPU_CLK,
 112         AMDGPU_PP_SENSOR_VDDNB,
 113         AMDGPU_PP_SENSOR_VDDGFX,
 114         AMDGPU_PP_SENSOR_UVD_VCLK,
 115         AMDGPU_PP_SENSOR_UVD_DCLK,
 116         AMDGPU_PP_SENSOR_VCE_ECCLK,
 117         AMDGPU_PP_SENSOR_GPU_LOAD,
 118         AMDGPU_PP_SENSOR_MEM_LOAD,
 119         AMDGPU_PP_SENSOR_GFX_MCLK,
 120         AMDGPU_PP_SENSOR_GPU_TEMP,
 121         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 122         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 123         AMDGPU_PP_SENSOR_MEM_TEMP,
 124         AMDGPU_PP_SENSOR_VCE_POWER,
 125         AMDGPU_PP_SENSOR_UVD_POWER,
 126         AMDGPU_PP_SENSOR_GPU_POWER,
 127         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 128         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 129         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 130         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 131         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 132         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 133         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 134         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 135 };
 136
 137 enum amd_pp_task {
 138         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 139         AMD_PP_TASK_ENABLE_USER_STATE,
 140         AMD_PP_TASK_READJUST_POWER_STATE,
 141         AMD_PP_TASK_COMPLETE_INIT,
 142         AMD_PP_TASK_MAX
 143 };
 144
 145 enum PP_SMC_POWER_PROFILE {
 146         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 147         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 148         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 149         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 150         PP_SMC_POWER_PROFILE_VR           = 0x4,
 151         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 152         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 153         PP_SMC_POWER_PROFILE_COUNT,
 154 };
 155
 156 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 157
 158
 159
 160 enum {
 161         PP_GROUP_UNKNOWN = 0,
 162         PP_GROUP_GFX = 1,
 163         PP_GROUP_SYS,
 164         PP_GROUP_MAX
 165 };
 166
 167 enum PP_OD_DPM_TABLE_COMMAND {
 168         PP_OD_EDIT_SCLK_VDDC_TABLE,
 169         PP_OD_EDIT_MCLK_VDDC_TABLE,
 170         PP_OD_EDIT_CCLK_VDDC_TABLE,
 171         PP_OD_EDIT_VDDC_CURVE,
 172         PP_OD_RESTORE_DEFAULT_TABLE,
 173         PP_OD_COMMIT_DPM_TABLE,
 174         PP_OD_EDIT_VDDGFX_OFFSET
 175 };
 176
 177 struct pp_states_info {
 178         uint32_t nums;
 179         uint32_t states[16];
 180 };
 181
 182 enum PP_HWMON_TEMP {
 183         PP_TEMP_EDGE = 0,
 184         PP_TEMP_JUNCTION,
 185         PP_TEMP_MEM,
 186         PP_TEMP_MAX
 187 };
 188
 189 enum pp_mp1_state {
 190         PP_MP1_STATE_NONE,
 191         PP_MP1_STATE_SHUTDOWN,
 192         PP_MP1_STATE_UNLOAD,
 193         PP_MP1_STATE_RESET,
 194 };
 195
 196 enum pp_df_cstate {
 197         DF_CSTATE_DISALLOW = 0,
 198         DF_CSTATE_ALLOW,
 199 };
 200
 201 /**
 202  * DOC: amdgpu_pp_power
 203  *
 204  * APU power is managed to system-level requirements through the PPT
 205  * (package power tracking) feature. PPT is intended to limit power to the
 206  * requirements of the power source and could be dynamically updated to
 207  * maximize APU performance within the system power budget.
 208  *
 209  * Two types of power measurement can be requested, where supported, with
 210  * :c:type:`enum pp_power_type <pp_power_type>`.
 211  */
 212
 213 /**
 214  * enum pp_power_limit_level - Used to query the power limits
 215  *
 216  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 217  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 218  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 219  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 220  */
 221 enum pp_power_limit_level
 222 {
 223         PP_PWR_LIMIT_MIN = -1,
 224         PP_PWR_LIMIT_CURRENT,
 225         PP_PWR_LIMIT_DEFAULT,
 226         PP_PWR_LIMIT_MAX,
 227 };
 228
 229 /**
 230  * enum pp_power_type - Used to specify the type of the requested power
 231  *
 232  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 233  * moving average of APU power (default ~5000 ms).
 234  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 235  * where supported.
 236  */
 237 enum pp_power_type
 238 {
 239         PP_PWR_TYPE_SUSTAINED,
 240         PP_PWR_TYPE_FAST,
 241 };
 242
 243 #define PP_GROUP_MASK        0xF0000000
 244 #define PP_GROUP_SHIFT       28
 245
 246 #define PP_BLOCK_MASK        0x0FFFFF00
 247 #define PP_BLOCK_SHIFT       8
 248
 249 #define PP_BLOCK_GFX_CG         0x01
 250 #define PP_BLOCK_GFX_MG         0x02
 251 #define PP_BLOCK_GFX_3D         0x04
 252 #define PP_BLOCK_GFX_RLC        0x08
 253 #define PP_BLOCK_GFX_CP         0x10
 254 #define PP_BLOCK_SYS_BIF        0x01
 255 #define PP_BLOCK_SYS_MC         0x02
 256 #define PP_BLOCK_SYS_ROM        0x04
 257 #define PP_BLOCK_SYS_DRM        0x08
 258 #define PP_BLOCK_SYS_HDP        0x10
 259 #define PP_BLOCK_SYS_SDMA       0x20
 260
 261 #define PP_STATE_MASK           0x0000000F
 262 #define PP_STATE_SHIFT          0
 263 #define PP_STATE_SUPPORT_MASK   0x000000F0
 264 #define PP_STATE_SUPPORT_SHIFT  0
 265
 266 #define PP_STATE_CG             0x01
 267 #define PP_STATE_LS             0x02
 268 #define PP_STATE_DS             0x04
 269 #define PP_STATE_SD             0x08
 270 #define PP_STATE_SUPPORT_CG     0x10
 271 #define PP_STATE_SUPPORT_LS     0x20
 272 #define PP_STATE_SUPPORT_DS     0x40
 273 #define PP_STATE_SUPPORT_SD     0x80
 274
 275 #define PP_CG_MSG_ID(group, block, support, state) \
 276                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 277                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 278
 279 #define XGMI_MODE_PSTATE_D3 0
 280 #define XGMI_MODE_PSTATE_D0 1
 281
 282 #define NUM_HBM_INSTANCES 4
 283
 284 struct seq_file;
 285 enum amd_pp_clock_type;
 286 struct amd_pp_simple_clock_info;
 287 struct amd_pp_display_configuration;
 288 struct amd_pp_clock_info;
 289 struct pp_display_clock_request;
 290 struct pp_clock_levels_with_voltage;
 291 struct pp_clock_levels_with_latency;
 292 struct amd_pp_clocks;
 293 struct pp_smu_wm_range_sets;
 294 struct pp_smu_nv_clock_table;
 295 struct dpm_clocks;
 296
 297 struct amd_pm_funcs {
 298 /* export for dpm on ci and si */
 299         int (*pre_set_power_state)(void *handle);
 300         int (*set_power_state)(void *handle);
 301         void (*post_set_power_state)(void *handle);
 302         void (*display_configuration_changed)(void *handle);
 303         void (*print_power_state)(void *handle, void *ps);
 304         bool (*vblank_too_short)(void *handle);
 305         void (*enable_bapm)(void *handle, bool enable);
 306         int (*check_state_equal)(void *handle,
 307                                 void  *cps,
 308                                 void  *rps,
 309                                 bool  *equal);
 310 /* export for sysfs */
 311         void (*set_fan_control_mode)(void *handle, u32 mode);
 312         u32 (*get_fan_control_mode)(void *handle);
 313         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 314         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 315         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 316         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 317         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 318         int (*get_sclk_od)(void *handle);
 319         int (*set_sclk_od)(void *handle, uint32_t value);
 320         int (*get_mclk_od)(void *handle);
 321         int (*set_mclk_od)(void *handle, uint32_t value);
 322         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 323         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 324         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 325         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 326         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 327         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 328         int (*get_pp_table)(void *handle, char **table);
 329         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 330         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 331         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 332 /* export to amdgpu */
 333         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 334         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 335                         enum amd_pm_state_type *user_state);
 336         int (*load_firmware)(void *handle);
 337         int (*wait_for_fw_loading_complete)(void *handle);
 338         int (*set_powergating_by_smu)(void *handle,
 339                                 uint32_t block_type, bool gate);
 340         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 341         int (*set_power_limit)(void *handle, uint32_t n);
 342         int (*get_power_limit)(void *handle, uint32_t *limit,
 343                         enum pp_power_limit_level pp_limit_level,
 344                         enum pp_power_type power_type);
 345         int (*get_power_profile_mode)(void *handle, char *buf);
 346         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 347         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 348         int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
 349         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 350         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 351         int (*gfx_state_change_set)(void *handle, uint32_t state);
 352 /* export to DC */
 353         u32 (*get_sclk)(void *handle, bool low);
 354         u32 (*get_mclk)(void *handle, bool low);
 355         int (*display_configuration_change)(void *handle,
 356                 const struct amd_pp_display_configuration *input);
 357         int (*get_display_power_level)(void *handle,
 358                 struct amd_pp_simple_clock_info *output);
 359         int (*get_current_clocks)(void *handle,
 360                 struct amd_pp_clock_info *clocks);
 361         int (*get_clock_by_type)(void *handle,
 362                 enum amd_pp_clock_type type,
 363                 struct amd_pp_clocks *clocks);
 364         int (*get_clock_by_type_with_latency)(void *handle,
 365                 enum amd_pp_clock_type type,
 366                 struct pp_clock_levels_with_latency *clocks);
 367         int (*get_clock_by_type_with_voltage)(void *handle,
 368                 enum amd_pp_clock_type type,
 369                 struct pp_clock_levels_with_voltage *clocks);
 370         int (*set_watermarks_for_clocks_ranges)(void *handle,
 371                                                 void *clock_ranges);
 372         int (*display_clock_voltage_request)(void *handle,
 373                                 struct pp_display_clock_request *clock);
 374         int (*get_display_mode_validation_clocks)(void *handle,
 375                 struct amd_pp_simple_clock_info *clocks);
 376         int (*notify_smu_enable_pwe)(void *handle);
 377         int (*enable_mgpu_fan_boost)(void *handle);
 378         int (*set_active_display_count)(void *handle, uint32_t count);
 379         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 380         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 381         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 382         int (*get_asic_baco_capability)(void *handle, bool *cap);
 383         int (*get_asic_baco_state)(void *handle, int *state);
 384         int (*set_asic_baco_state)(void *handle, int state);
 385         int (*get_ppfeature_status)(void *handle, char *buf);
 386         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 387         int (*asic_reset_mode_2)(void *handle);
 388         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 389         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 390         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 391         int (*set_watermarks_for_clock_ranges)(void *handle,
 392                                                struct pp_smu_wm_range_sets *ranges);
 393         int (*display_disable_memory_clock_switch)(void *handle,
 394                                                    bool disable_memory_clock_switch);
 395         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 396                                                 struct pp_smu_nv_clock_table *max_clocks);
 397         int (*get_uclk_dpm_states)(void *handle,
 398                                    unsigned int *clock_values_in_khz,
 399                                    unsigned int *num_states);
 400         int (*get_dpm_clock_table)(void *handle,
 401                                    struct dpm_clocks *clock_table);
 402         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 403 };
 404
 405 struct metrics_table_header {
 406         uint16_t                        structure_size;
 407         uint8_t                         format_revision;
 408         uint8_t                         content_revision;
 409 };
 410
 411 /*
 412  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 413  * Use gpu_metrics_v1_1 or later instead.
 414  */
 415 struct gpu_metrics_v1_0 {
 416         struct metrics_table_header     common_header;
 417
 418         /* Driver attached timestamp (in ns) */
 419         uint64_t                        system_clock_counter;
 420
 421         /* Temperature */
 422         uint16_t                        temperature_edge;
 423         uint16_t                        temperature_hotspot;
 424         uint16_t                        temperature_mem;
 425         uint16_t                        temperature_vrgfx;
 426         uint16_t                        temperature_vrsoc;
 427         uint16_t                        temperature_vrmem;
 428
 429         /* Utilization */
 430         uint16_t                        average_gfx_activity;
 431         uint16_t                        average_umc_activity; // memory controller
 432         uint16_t                        average_mm_activity; // UVD or VCN
 433
 434         /* Power/Energy */
 435         uint16_t                        average_socket_power;
 436         uint32_t                        energy_accumulator;
 437
 438         /* Average clocks */
 439         uint16_t                        average_gfxclk_frequency;
 440         uint16_t                        average_socclk_frequency;
 441         uint16_t                        average_uclk_frequency;
 442         uint16_t                        average_vclk0_frequency;
 443         uint16_t                        average_dclk0_frequency;
 444         uint16_t                        average_vclk1_frequency;
 445         uint16_t                        average_dclk1_frequency;
 446
 447         /* Current clocks */
 448         uint16_t                        current_gfxclk;
 449         uint16_t                        current_socclk;
 450         uint16_t                        current_uclk;
 451         uint16_t                        current_vclk0;
 452         uint16_t                        current_dclk0;
 453         uint16_t                        current_vclk1;
 454         uint16_t                        current_dclk1;
 455
 456         /* Throttle status */
 457         uint32_t                        throttle_status;
 458
 459         /* Fans */
 460         uint16_t                        current_fan_speed;
 461
 462         /* Link width/speed */
 463         uint8_t                         pcie_link_width;
 464         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 465 };
 466
 467 struct gpu_metrics_v1_1 {
 468         struct metrics_table_header     common_header;
 469
 470         /* Temperature */
 471         uint16_t                        temperature_edge;
 472         uint16_t                        temperature_hotspot;
 473         uint16_t                        temperature_mem;
 474         uint16_t                        temperature_vrgfx;
 475         uint16_t                        temperature_vrsoc;
 476         uint16_t                        temperature_vrmem;
 477
 478         /* Utilization */
 479         uint16_t                        average_gfx_activity;
 480         uint16_t                        average_umc_activity; // memory controller
 481         uint16_t                        average_mm_activity; // UVD or VCN
 482
 483         /* Power/Energy */
 484         uint16_t                        average_socket_power;
 485         uint64_t                        energy_accumulator;
 486
 487         /* Driver attached timestamp (in ns) */
 488         uint64_t                        system_clock_counter;
 489
 490         /* Average clocks */
 491         uint16_t                        average_gfxclk_frequency;
 492         uint16_t                        average_socclk_frequency;
 493         uint16_t                        average_uclk_frequency;
 494         uint16_t                        average_vclk0_frequency;
 495         uint16_t                        average_dclk0_frequency;
 496         uint16_t                        average_vclk1_frequency;
 497         uint16_t                        average_dclk1_frequency;
 498
 499         /* Current clocks */
 500         uint16_t                        current_gfxclk;
 501         uint16_t                        current_socclk;
 502         uint16_t                        current_uclk;
 503         uint16_t                        current_vclk0;
 504         uint16_t                        current_dclk0;
 505         uint16_t                        current_vclk1;
 506         uint16_t                        current_dclk1;
 507
 508         /* Throttle status */
 509         uint32_t                        throttle_status;
 510
 511         /* Fans */
 512         uint16_t                        current_fan_speed;
 513
 514         /* Link width/speed */
 515         uint16_t                        pcie_link_width;
 516         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 517
 518         uint16_t                        padding;
 519
 520         uint32_t                        gfx_activity_acc;
 521         uint32_t                        mem_activity_acc;
 522
 523         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 524 };
 525
 526 struct gpu_metrics_v1_2 {
 527         struct metrics_table_header     common_header;
 528
 529         /* Temperature */
 530         uint16_t                        temperature_edge;
 531         uint16_t                        temperature_hotspot;
 532         uint16_t                        temperature_mem;
 533         uint16_t                        temperature_vrgfx;
 534         uint16_t                        temperature_vrsoc;
 535         uint16_t                        temperature_vrmem;
 536
 537         /* Utilization */
 538         uint16_t                        average_gfx_activity;
 539         uint16_t                        average_umc_activity; // memory controller
 540         uint16_t                        average_mm_activity; // UVD or VCN
 541
 542         /* Power/Energy */
 543         uint16_t                        average_socket_power;
 544         uint64_t                        energy_accumulator;
 545
 546         /* Driver attached timestamp (in ns) */
 547         uint64_t                        system_clock_counter;
 548
 549         /* Average clocks */
 550         uint16_t                        average_gfxclk_frequency;
 551         uint16_t                        average_socclk_frequency;
 552         uint16_t                        average_uclk_frequency;
 553         uint16_t                        average_vclk0_frequency;
 554         uint16_t                        average_dclk0_frequency;
 555         uint16_t                        average_vclk1_frequency;
 556         uint16_t                        average_dclk1_frequency;
 557
 558         /* Current clocks */
 559         uint16_t                        current_gfxclk;
 560         uint16_t                        current_socclk;
 561         uint16_t                        current_uclk;
 562         uint16_t                        current_vclk0;
 563         uint16_t                        current_dclk0;
 564         uint16_t                        current_vclk1;
 565         uint16_t                        current_dclk1;
 566
 567         /* Throttle status (ASIC dependent) */
 568         uint32_t                        throttle_status;
 569
 570         /* Fans */
 571         uint16_t                        current_fan_speed;
 572
 573         /* Link width/speed */
 574         uint16_t                        pcie_link_width;
 575         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 576
 577         uint16_t                        padding;
 578
 579         uint32_t                        gfx_activity_acc;
 580         uint32_t                        mem_activity_acc;
 581
 582         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 583
 584         /* PMFW attached timestamp (10ns resolution) */
 585         uint64_t                        firmware_timestamp;
 586 };
 587
 588 struct gpu_metrics_v1_3 {
 589         struct metrics_table_header     common_header;
 590
 591         /* Temperature */
 592         uint16_t                        temperature_edge;
 593         uint16_t                        temperature_hotspot;
 594         uint16_t                        temperature_mem;
 595         uint16_t                        temperature_vrgfx;
 596         uint16_t                        temperature_vrsoc;
 597         uint16_t                        temperature_vrmem;
 598
 599         /* Utilization */
 600         uint16_t                        average_gfx_activity;
 601         uint16_t                        average_umc_activity; // memory controller
 602         uint16_t                        average_mm_activity; // UVD or VCN
 603
 604         /* Power/Energy */
 605         uint16_t                        average_socket_power;
 606         uint64_t                        energy_accumulator;
 607
 608         /* Driver attached timestamp (in ns) */
 609         uint64_t                        system_clock_counter;
 610
 611         /* Average clocks */
 612         uint16_t                        average_gfxclk_frequency;
 613         uint16_t                        average_socclk_frequency;
 614         uint16_t                        average_uclk_frequency;
 615         uint16_t                        average_vclk0_frequency;
 616         uint16_t                        average_dclk0_frequency;
 617         uint16_t                        average_vclk1_frequency;
 618         uint16_t                        average_dclk1_frequency;
 619
 620         /* Current clocks */
 621         uint16_t                        current_gfxclk;
 622         uint16_t                        current_socclk;
 623         uint16_t                        current_uclk;
 624         uint16_t                        current_vclk0;
 625         uint16_t                        current_dclk0;
 626         uint16_t                        current_vclk1;
 627         uint16_t                        current_dclk1;
 628
 629         /* Throttle status */
 630         uint32_t                        throttle_status;
 631
 632         /* Fans */
 633         uint16_t                        current_fan_speed;
 634
 635         /* Link width/speed */
 636         uint16_t                        pcie_link_width;
 637         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 638
 639         uint16_t                        padding;
 640
 641         uint32_t                        gfx_activity_acc;
 642         uint32_t                        mem_activity_acc;
 643
 644         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 645
 646         /* PMFW attached timestamp (10ns resolution) */
 647         uint64_t                        firmware_timestamp;
 648
 649         /* Voltage (mV) */
 650         uint16_t                        voltage_soc;
 651         uint16_t                        voltage_gfx;
 652         uint16_t                        voltage_mem;
 653
 654         uint16_t                        padding1;
 655
 656         /* Throttle status (ASIC independent) */
 657         uint64_t                        indep_throttle_status;
 658 };
 659
 660 /*
 661  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 662  * Use gpu_metrics_v2_1 or later instead.
 663  */
 664 struct gpu_metrics_v2_0 {
 665         struct metrics_table_header     common_header;
 666
 667         /* Driver attached timestamp (in ns) */
 668         uint64_t                        system_clock_counter;
 669
 670         /* Temperature */
 671         uint16_t                        temperature_gfx; // gfx temperature on APUs
 672         uint16_t                        temperature_soc; // soc temperature on APUs
 673         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 674         uint16_t                        temperature_l3[2];
 675
 676         /* Utilization */
 677         uint16_t                        average_gfx_activity;
 678         uint16_t                        average_mm_activity; // UVD or VCN
 679
 680         /* Power/Energy */
 681         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 682         uint16_t                        average_cpu_power;
 683         uint16_t                        average_soc_power;
 684         uint16_t                        average_gfx_power;
 685         uint16_t                        average_core_power[8]; // CPU core power on APUs
 686
 687         /* Average clocks */
 688         uint16_t                        average_gfxclk_frequency;
 689         uint16_t                        average_socclk_frequency;
 690         uint16_t                        average_uclk_frequency;
 691         uint16_t                        average_fclk_frequency;
 692         uint16_t                        average_vclk_frequency;
 693         uint16_t                        average_dclk_frequency;
 694
 695         /* Current clocks */
 696         uint16_t                        current_gfxclk;
 697         uint16_t                        current_socclk;
 698         uint16_t                        current_uclk;
 699         uint16_t                        current_fclk;
 700         uint16_t                        current_vclk;
 701         uint16_t                        current_dclk;
 702         uint16_t                        current_coreclk[8]; // CPU core clocks
 703         uint16_t                        current_l3clk[2];
 704
 705         /* Throttle status */
 706         uint32_t                        throttle_status;
 707
 708         /* Fans */
 709         uint16_t                        fan_pwm;
 710
 711         uint16_t                        padding;
 712 };
 713
 714 struct gpu_metrics_v2_1 {
 715         struct metrics_table_header     common_header;
 716
 717         /* Temperature */
 718         uint16_t                        temperature_gfx; // gfx temperature on APUs
 719         uint16_t                        temperature_soc; // soc temperature on APUs
 720         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 721         uint16_t                        temperature_l3[2];
 722
 723         /* Utilization */
 724         uint16_t                        average_gfx_activity;
 725         uint16_t                        average_mm_activity; // UVD or VCN
 726
 727         /* Driver attached timestamp (in ns) */
 728         uint64_t                        system_clock_counter;
 729
 730         /* Power/Energy */
 731         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 732         uint16_t                        average_cpu_power;
 733         uint16_t                        average_soc_power;
 734         uint16_t                        average_gfx_power;
 735         uint16_t                        average_core_power[8]; // CPU core power on APUs
 736
 737         /* Average clocks */
 738         uint16_t                        average_gfxclk_frequency;
 739         uint16_t                        average_socclk_frequency;
 740         uint16_t                        average_uclk_frequency;
 741         uint16_t                        average_fclk_frequency;
 742         uint16_t                        average_vclk_frequency;
 743         uint16_t                        average_dclk_frequency;
 744
 745         /* Current clocks */
 746         uint16_t                        current_gfxclk;
 747         uint16_t                        current_socclk;
 748         uint16_t                        current_uclk;
 749         uint16_t                        current_fclk;
 750         uint16_t                        current_vclk;
 751         uint16_t                        current_dclk;
 752         uint16_t                        current_coreclk[8]; // CPU core clocks
 753         uint16_t                        current_l3clk[2];
 754
 755         /* Throttle status */
 756         uint32_t                        throttle_status;
 757
 758         /* Fans */
 759         uint16_t                        fan_pwm;
 760
 761         uint16_t                        padding[3];
 762 };
 763
 764 struct gpu_metrics_v2_2 {
 765         struct metrics_table_header     common_header;
 766
 767         /* Temperature */
 768         uint16_t                        temperature_gfx; // gfx temperature on APUs
 769         uint16_t                        temperature_soc; // soc temperature on APUs
 770         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 771         uint16_t                        temperature_l3[2];
 772
 773         /* Utilization */
 774         uint16_t                        average_gfx_activity;
 775         uint16_t                        average_mm_activity; // UVD or VCN
 776
 777         /* Driver attached timestamp (in ns) */
 778         uint64_t                        system_clock_counter;
 779
 780         /* Power/Energy */
 781         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 782         uint16_t                        average_cpu_power;
 783         uint16_t                        average_soc_power;
 784         uint16_t                        average_gfx_power;
 785         uint16_t                        average_core_power[8]; // CPU core power on APUs
 786
 787         /* Average clocks */
 788         uint16_t                        average_gfxclk_frequency;
 789         uint16_t                        average_socclk_frequency;
 790         uint16_t                        average_uclk_frequency;
 791         uint16_t                        average_fclk_frequency;
 792         uint16_t                        average_vclk_frequency;
 793         uint16_t                        average_dclk_frequency;
 794
 795         /* Current clocks */
 796         uint16_t                        current_gfxclk;
 797         uint16_t                        current_socclk;
 798         uint16_t                        current_uclk;
 799         uint16_t                        current_fclk;
 800         uint16_t                        current_vclk;
 801         uint16_t                        current_dclk;
 802         uint16_t                        current_coreclk[8]; // CPU core clocks
 803         uint16_t                        current_l3clk[2];
 804
 805         /* Throttle status (ASIC dependent) */
 806         uint32_t                        throttle_status;
 807
 808         /* Fans */
 809         uint16_t                        fan_pwm;
 810
 811         uint16_t                        padding[3];
 812
 813         /* Throttle status (ASIC independent) */
 814         uint64_t                        indep_throttle_status;
 815 };
 816
 817 #endif