drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_0.h"
  26
  27 #include "nbio/nbio_7_0_default.h"
  28 #include "nbio/nbio_7_0_offset.h"
  29 #include "nbio/nbio_7_0_sh_mask.h"
  30 #include "vega10_enum.h"
  31
  32 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c
  33
  34 #define smnCPM_CONTROL                                                                                  0x11180460
  35 #define smnPCIE_CNTL2                                                                                   0x11180070
  36
  37 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
  38 {
  39         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
  40
  41         tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  42         tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  43
  44         return tmp;
  45 }
  46
  47 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
  48 {
  49         if (enable)
  50                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
  51                         BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
  52         else
  53                 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
  54 }
  55
  56 static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
  57 {
  58         WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
  59 }
  60
  61 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
  62 {
  63         return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
  64 }
  65
  66 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  67                                           bool use_doorbell, int doorbell_index)
  68 {
  69         u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
  70                         SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
  71
  72         u32 doorbell_range = RREG32(reg);
  73
  74         if (use_doorbell) {
  75                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
  76                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
  77         } else
  78                 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
  79
  80         WREG32(reg, doorbell_range);
  81 }
  82
  83 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
  84                                                bool enable)
  85 {
  86         WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
  87 }
  88
  89 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
  90                                                         bool enable)
  91 {
  92
  93 }
  94
  95 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
  96                                         bool use_doorbell, int doorbell_index)
  97 {
  98         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
  99
 100         if (use_doorbell) {
 101                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
 102                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
 103         } else
 104                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
 105
 106         WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 107 }
 108
 109 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
 110 {
 111         uint32_t data;
 112
 113         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 114         data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
 115
 116         return data;
 117 }
 118
 119 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
 120                                        uint32_t data)
 121 {
 122         WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
 123         WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
 124 }
 125
 126 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 127                                                        bool enable)
 128 {
 129         uint32_t def, data;
 130
 131         /* NBIF_MGCG_CTRL_LCLK */
 132         def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
 133
 134         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 135                 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 136         else
 137                 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
 138
 139         if (def != data)
 140                 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
 141
 142         /* SYSHUB_MGCG_CTRL_SOCCLK */
 143         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
 144
 145         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 146                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 147         else
 148                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
 149
 150         if (def != data)
 151                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
 152
 153         /* SYSHUB_MGCG_CTRL_SHUBCLK */
 154         def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
 155
 156         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
 157                 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 158         else
 159                 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
 160
 161         if (def != data)
 162                 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
 163 }
 164
 165 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 166                                                       bool enable)
 167 {
 168         uint32_t def, data;
 169
 170         def = data = RREG32_PCIE(smnPCIE_CNTL2);
 171         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
 172                 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 173                          PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 174                          PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 175         } else {
 176                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
 177                           PCIE_CNTL2__MST_MEM_LS_EN_MASK |
 178                           PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
 179         }
 180
 181         if (def != data)
 182                 WREG32_PCIE(smnPCIE_CNTL2, data);
 183 }
 184
 185 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
 186                                             u32 *flags)
 187 {
 188         int data;
 189
 190         /* AMD_CG_SUPPORT_BIF_MGCG */
 191         data = RREG32_PCIE(smnCPM_CONTROL);
 192         if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
 193                 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
 194
 195         /* AMD_CG_SUPPORT_BIF_LS */
 196         data = RREG32_PCIE(smnPCIE_CNTL2);
 197         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
 198                 *flags |= AMD_CG_SUPPORT_BIF_LS;
 199 }
 200
 201 static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
 202 {
 203         u32 interrupt_cntl;
 204
 205         /* setup interrupt control */
 206         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);
 207         interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
 208         /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 209          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 210          */
 211         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
 212         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 213         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
 214         WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 215 }
 216
 217 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 218 {
 219         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
 220 }
 221
 222 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 223 {
 224         return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
 225 }
 226
 227 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
 228 {
 229         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
 230 }
 231
 232 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
 233 {
 234         return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
 235 }
 236
 237 const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
 238         .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
 239         .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
 240         .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
 241         .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
 242         .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
 243         .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
 244         .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
 245         .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
 246         .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
 247         .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
 248         .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 249         .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 250 };
 251
 252 static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
 253 {
 254         if (is_virtual_machine())       /* passthrough mode exclus sriov mod */
 255                 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 256 }
 257
 258 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
 259 {
 260
 261 }
 262
 263 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
 264         .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
 265         .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
 266         .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
 267         .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
 268         .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
 269         .get_rev_id = nbio_v7_0_get_rev_id,
 270         .mc_access_enable = nbio_v7_0_mc_access_enable,
 271         .hdp_flush = nbio_v7_0_hdp_flush,
 272         .get_memsize = nbio_v7_0_get_memsize,
 273         .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
 274         .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
 275         .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
 276         .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
 277         .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
 278         .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
 279         .get_clockgating_state = nbio_v7_0_get_clockgating_state,
 280         .ih_control = nbio_v7_0_ih_control,
 281         .init_registers = nbio_v7_0_init_registers,
 282         .detect_hw_virt = nbio_v7_0_detect_hw_virt,
 283 };