drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "gmc_v8_0.h"
  27 #include "amdgpu_ucode.h"
  28
  29 #include "gmc/gmc_8_1_d.h"
  30 #include "gmc/gmc_8_1_sh_mask.h"
  31
  32 #include "bif/bif_5_0_d.h"
  33 #include "bif/bif_5_0_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "dce/dce_10_0_d.h"
  39 #include "dce/dce_10_0_sh_mask.h"
  40
  41 #include "vid.h"
  42 #include "vi.h"
  43
  44 #include "amdgpu_atombios.h"
  45
  46
  47 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
  48 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  49 static int gmc_v8_0_wait_for_idle(void *handle);
  50
  51 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
  52 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
  53 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
  54 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
  55
  56 static const u32 golden_settings_tonga_a11[] =
  57 {
  58         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  59         mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
  60         mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
  61         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  62         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  63         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  64         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  65 };
  66
  67 static const u32 tonga_mgcg_cgcg_init[] =
  68 {
  69         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  70 };
  71
  72 static const u32 golden_settings_fiji_a10[] =
  73 {
  74         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  75         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  76         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  77         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  78 };
  79
  80 static const u32 fiji_mgcg_cgcg_init[] =
  81 {
  82         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
  83 };
  84
  85 static const u32 golden_settings_polaris11_a11[] =
  86 {
  87         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  88         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  89         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  90         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
  91 };
  92
  93 static const u32 golden_settings_polaris10_a11[] =
  94 {
  95         mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
  96         mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  97         mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  98         mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
  99         mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 100 };
 101
 102 static const u32 cz_mgcg_cgcg_init[] =
 103 {
 104         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 105 };
 106
 107 static const u32 stoney_mgcg_cgcg_init[] =
 108 {
 109         mmATC_MISC_CG, 0xffffffff, 0x000c0200,
 110         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 111 };
 112
 113 static const u32 golden_settings_stoney_common[] =
 114 {
 115         mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
 116         mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
 117 };
 118
 119 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 120 {
 121         switch (adev->asic_type) {
 122         case CHIP_FIJI:
 123                 amdgpu_device_program_register_sequence(adev,
 124                                                         fiji_mgcg_cgcg_init,
 125                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 126                 amdgpu_device_program_register_sequence(adev,
 127                                                         golden_settings_fiji_a10,
 128                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 129                 break;
 130         case CHIP_TONGA:
 131                 amdgpu_device_program_register_sequence(adev,
 132                                                         tonga_mgcg_cgcg_init,
 133                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 134                 amdgpu_device_program_register_sequence(adev,
 135                                                         golden_settings_tonga_a11,
 136                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 137                 break;
 138         case CHIP_POLARIS11:
 139         case CHIP_POLARIS12:
 140                 amdgpu_device_program_register_sequence(adev,
 141                                                         golden_settings_polaris11_a11,
 142                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 143                 break;
 144         case CHIP_POLARIS10:
 145                 amdgpu_device_program_register_sequence(adev,
 146                                                         golden_settings_polaris10_a11,
 147                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 148                 break;
 149         case CHIP_CARRIZO:
 150                 amdgpu_device_program_register_sequence(adev,
 151                                                         cz_mgcg_cgcg_init,
 152                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 153                 break;
 154         case CHIP_STONEY:
 155                 amdgpu_device_program_register_sequence(adev,
 156                                                         stoney_mgcg_cgcg_init,
 157                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 158                 amdgpu_device_program_register_sequence(adev,
 159                                                         golden_settings_stoney_common,
 160                                                         ARRAY_SIZE(golden_settings_stoney_common));
 161                 break;
 162         default:
 163                 break;
 164         }
 165 }
 166
 167 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
 168 {
 169         u32 blackout;
 170
 171         gmc_v8_0_wait_for_idle(adev);
 172
 173         blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 174         if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
 175                 /* Block CPU access */
 176                 WREG32(mmBIF_FB_EN, 0);
 177                 /* blackout the MC */
 178                 blackout = REG_SET_FIELD(blackout,
 179                                          MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
 180                 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
 181         }
 182         /* wait for the MC to settle */
 183         udelay(100);
 184 }
 185
 186 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
 187 {
 188         u32 tmp;
 189
 190         /* unblackout the MC */
 191         tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
 192         tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
 193         WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
 194         /* allow CPU access */
 195         tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
 196         tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
 197         WREG32(mmBIF_FB_EN, tmp);
 198 }
 199
 200 /**
 201  * gmc_v8_0_init_microcode - load ucode images from disk
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Use the firmware interface to load the ucode images into
 206  * the driver (not loaded into hw).
 207  * Returns 0 on success, error on failure.
 208  */
 209 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 210 {
 211         const char *chip_name;
 212         char fw_name[30];
 213         int err;
 214
 215         DRM_DEBUG("\n");
 216
 217         switch (adev->asic_type) {
 218         case CHIP_TONGA:
 219                 chip_name = "tonga";
 220                 break;
 221         case CHIP_POLARIS11:
 222                 chip_name = "polaris11";
 223                 break;
 224         case CHIP_POLARIS10:
 225                 chip_name = "polaris10";
 226                 break;
 227         case CHIP_POLARIS12:
 228                 chip_name = "polaris12";
 229                 break;
 230         case CHIP_FIJI:
 231         case CHIP_CARRIZO:
 232         case CHIP_STONEY:
 233                 return 0;
 234         default: BUG();
 235         }
 236
 237         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 238         err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
 239         if (err)
 240                 goto out;
 241         err = amdgpu_ucode_validate(adev->mc.fw);
 242
 243 out:
 244         if (err) {
 245                 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
 246                 release_firmware(adev->mc.fw);
 247                 adev->mc.fw = NULL;
 248         }
 249         return err;
 250 }
 251
 252 /**
 253  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
 254  *
 255  * @adev: amdgpu_device pointer
 256  *
 257  * Load the GDDR MC ucode into the hw (CIK).
 258  * Returns 0 on success, error on failure.
 259  */
 260 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
 261 {
 262         const struct mc_firmware_header_v1_0 *hdr;
 263         const __le32 *fw_data = NULL;
 264         const __le32 *io_mc_regs = NULL;
 265         u32 running;
 266         int i, ucode_size, regs_size;
 267
 268         /* Skip MC ucode loading on SR-IOV capable boards.
 269          * vbios does this for us in asic_init in that case.
 270          * Skip MC ucode loading on VF, because hypervisor will do that
 271          * for this adaptor.
 272          */
 273         if (amdgpu_sriov_bios(adev))
 274                 return 0;
 275
 276         if (!adev->mc.fw)
 277                 return -EINVAL;
 278
 279         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 280         amdgpu_ucode_print_mc_hdr(&hdr->header);
 281
 282         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 283         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 284         io_mc_regs = (const __le32 *)
 285                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 286         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 287         fw_data = (const __le32 *)
 288                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 289
 290         running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
 291
 292         if (running == 0) {
 293                 /* reset the engine and set to writable */
 294                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 295                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 296
 297                 /* load mc io regs */
 298                 for (i = 0; i < regs_size; i++) {
 299                         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 300                         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 301                 }
 302                 /* load the MC ucode */
 303                 for (i = 0; i < ucode_size; i++)
 304                         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 305
 306                 /* put the engine back into the active state */
 307                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 308                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 309                 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 310
 311                 /* wait for training to complete */
 312                 for (i = 0; i < adev->usec_timeout; i++) {
 313                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 314                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
 315                                 break;
 316                         udelay(1);
 317                 }
 318                 for (i = 0; i < adev->usec_timeout; i++) {
 319                         if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
 320                                           MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
 321                                 break;
 322                         udelay(1);
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
 330 {
 331         const struct mc_firmware_header_v1_0 *hdr;
 332         const __le32 *fw_data = NULL;
 333         const __le32 *io_mc_regs = NULL;
 334         u32 data, vbios_version;
 335         int i, ucode_size, regs_size;
 336
 337         /* Skip MC ucode loading on SR-IOV capable boards.
 338          * vbios does this for us in asic_init in that case.
 339          * Skip MC ucode loading on VF, because hypervisor will do that
 340          * for this adaptor.
 341          */
 342         if (amdgpu_sriov_bios(adev))
 343                 return 0;
 344
 345         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
 346         data = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
 347         vbios_version = data & 0xf;
 348
 349         if (vbios_version == 0)
 350                 return 0;
 351
 352         if (!adev->mc.fw)
 353                 return -EINVAL;
 354
 355         hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;
 356         amdgpu_ucode_print_mc_hdr(&hdr->header);
 357
 358         adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);
 359         regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
 360         io_mc_regs = (const __le32 *)
 361                 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
 362         ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 363         fw_data = (const __le32 *)
 364                 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 365
 366         data = RREG32(mmMC_SEQ_MISC0);
 367         data &= ~(0x40);
 368         WREG32(mmMC_SEQ_MISC0, data);
 369
 370         /* load mc io regs */
 371         for (i = 0; i < regs_size; i++) {
 372                 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
 373                 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
 374         }
 375
 376         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 377         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
 378
 379         /* load the MC ucode */
 380         for (i = 0; i < ucode_size; i++)
 381                 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
 382
 383         /* put the engine back into the active state */
 384         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
 385         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
 386         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
 387
 388         /* wait for training to complete */
 389         for (i = 0; i < adev->usec_timeout; i++) {
 390                 data = RREG32(mmMC_SEQ_MISC0);
 391                 if (data & 0x80)
 392                         break;
 393                 udelay(1);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
 400                                        struct amdgpu_mc *mc)
 401 {
 402         u64 base = 0;
 403
 404         if (!amdgpu_sriov_vf(adev))
 405                 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
 406         base <<= 24;
 407
 408         amdgpu_device_vram_location(adev, &adev->mc, base);
 409         amdgpu_device_gart_location(adev, mc);
 410 }
 411
 412 /**
 413  * gmc_v8_0_mc_program - program the GPU memory controller
 414  *
 415  * @adev: amdgpu_device pointer
 416  *
 417  * Set the location of vram, gart, and AGP in the GPU's
 418  * physical address space (CIK).
 419  */
 420 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
 421 {
 422         u32 tmp;
 423         int i, j;
 424
 425         /* Initialize HDP */
 426         for (i = 0, j = 0; i < 32; i++, j += 0x6) {
 427                 WREG32((0xb05 + j), 0x00000000);
 428                 WREG32((0xb06 + j), 0x00000000);
 429                 WREG32((0xb07 + j), 0x00000000);
 430                 WREG32((0xb08 + j), 0x00000000);
 431                 WREG32((0xb09 + j), 0x00000000);
 432         }
 433         WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
 434
 435         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 436                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 437         }
 438         if (adev->mode_info.num_crtc) {
 439                 /* Lockout access through VGA aperture*/
 440                 tmp = RREG32(mmVGA_HDP_CONTROL);
 441                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 442                 WREG32(mmVGA_HDP_CONTROL, tmp);
 443
 444                 /* disable VGA render */
 445                 tmp = RREG32(mmVGA_RENDER_CONTROL);
 446                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 447                 WREG32(mmVGA_RENDER_CONTROL, tmp);
 448         }
 449         /* Update configuration */
 450         WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 451                adev->mc.vram_start >> 12);
 452         WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 453                adev->mc.vram_end >> 12);
 454         WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
 455                adev->vram_scratch.gpu_addr >> 12);
 456
 457         if (amdgpu_sriov_vf(adev)) {
 458                 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;
 459                 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);
 460                 WREG32(mmMC_VM_FB_LOCATION, tmp);
 461                 /* XXX double check these! */
 462                 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));
 463                 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
 464                 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 465         }
 466
 467         WREG32(mmMC_VM_AGP_BASE, 0);
 468         WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
 469         WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
 470         if (gmc_v8_0_wait_for_idle((void *)adev)) {
 471                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 472         }
 473
 474         WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
 475
 476         tmp = RREG32(mmHDP_MISC_CNTL);
 477         tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
 478         WREG32(mmHDP_MISC_CNTL, tmp);
 479
 480         tmp = RREG32(mmHDP_HOST_PATH_CNTL);
 481         WREG32(mmHDP_HOST_PATH_CNTL, tmp);
 482 }
 483
 484 /**
 485  * gmc_v8_0_mc_init - initialize the memory controller driver params
 486  *
 487  * @adev: amdgpu_device pointer
 488  *
 489  * Look up the amount of vram, vram width, and decide how to place
 490  * vram and gart within the GPU's physical address space (CIK).
 491  * Returns 0 for success.
 492  */
 493 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 494 {
 495         int r;
 496
 497         adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev);
 498         if (!adev->mc.vram_width) {
 499                 u32 tmp;
 500                 int chansize, numchan;
 501
 502                 /* Get VRAM informations */
 503                 tmp = RREG32(mmMC_ARB_RAMCFG);
 504                 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
 505                         chansize = 64;
 506                 } else {
 507                         chansize = 32;
 508                 }
 509                 tmp = RREG32(mmMC_SHARED_CHMAP);
 510                 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
 511                 case 0:
 512                 default:
 513                         numchan = 1;
 514                         break;
 515                 case 1:
 516                         numchan = 2;
 517                         break;
 518                 case 2:
 519                         numchan = 4;
 520                         break;
 521                 case 3:
 522                         numchan = 8;
 523                         break;
 524                 case 4:
 525                         numchan = 3;
 526                         break;
 527                 case 5:
 528                         numchan = 6;
 529                         break;
 530                 case 6:
 531                         numchan = 10;
 532                         break;
 533                 case 7:
 534                         numchan = 12;
 535                         break;
 536                 case 8:
 537                         numchan = 16;
 538                         break;
 539                 }
 540                 adev->mc.vram_width = numchan * chansize;
 541         }
 542         /* size in MB on si */
 543         adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 544         adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
 545
 546         if (!(adev->flags & AMD_IS_APU)) {
 547                 r = amdgpu_device_resize_fb_bar(adev);
 548                 if (r)
 549                         return r;
 550         }
 551         adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
 552         adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
 553
 554 #ifdef CONFIG_X86_64
 555         if (adev->flags & AMD_IS_APU) {
 556                 adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
 557                 adev->mc.aper_size = adev->mc.real_vram_size;
 558         }
 559 #endif
 560
 561         /* In case the PCI BAR is larger than the actual amount of vram */
 562         adev->mc.visible_vram_size = adev->mc.aper_size;
 563         if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
 564                 adev->mc.visible_vram_size = adev->mc.real_vram_size;
 565
 566         /* set the gart size */
 567         if (amdgpu_gart_size == -1) {
 568                 switch (adev->asic_type) {
 569                 case CHIP_POLARIS11: /* all engines support GPUVM */
 570                 case CHIP_POLARIS10: /* all engines support GPUVM */
 571                 case CHIP_POLARIS12: /* all engines support GPUVM */
 572                 default:
 573                         adev->mc.gart_size = 256ULL << 20;
 574                         break;
 575                 case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
 576                 case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
 577                 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
 578                 case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
 579                         adev->mc.gart_size = 1024ULL << 20;
 580                         break;
 581                 }
 582         } else {
 583                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 584         }
 585
 586         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 587
 588         return 0;
 589 }
 590
 591 /*
 592  * GART
 593  * VMID 0 is the physical GPU addresses as used by the kernel.
 594  * VMIDs 1-15 are used for userspace clients and are handled
 595  * by the amdgpu vm/hsa code.
 596  */
 597
 598 /**
 599  * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
 600  *
 601  * @adev: amdgpu_device pointer
 602  * @vmid: vm instance to flush
 603  *
 604  * Flush the TLB for the requested page table (CIK).
 605  */
 606 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
 607                                         uint32_t vmid)
 608 {
 609         /* flush hdp cache */
 610         WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 611
 612         /* bits 0-15 are the VM contexts0-15 */
 613         WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 614 }
 615
 616 /**
 617  * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
 618  *
 619  * @adev: amdgpu_device pointer
 620  * @cpu_pt_addr: cpu address of the page table
 621  * @gpu_page_idx: entry in the page table to update
 622  * @addr: dst addr to write into pte/pde
 623  * @flags: access flags
 624  *
 625  * Update the page tables using the CPU.
 626  */
 627 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 628                                      void *cpu_pt_addr,
 629                                      uint32_t gpu_page_idx,
 630                                      uint64_t addr,
 631                                      uint64_t flags)
 632 {
 633         void __iomem *ptr = (void *)cpu_pt_addr;
 634         uint64_t value;
 635
 636         /*
 637          * PTE format on VI:
 638          * 63:40 reserved
 639          * 39:12 4k physical page base address
 640          * 11:7 fragment
 641          * 6 write
 642          * 5 read
 643          * 4 exe
 644          * 3 reserved
 645          * 2 snooped
 646          * 1 system
 647          * 0 valid
 648          *
 649          * PDE format on VI:
 650          * 63:59 block fragment size
 651          * 58:40 reserved
 652          * 39:1 physical base address of PTE
 653          * bits 5:1 must be 0.
 654          * 0 valid
 655          */
 656         value = addr & 0x000000FFFFFFF000ULL;
 657         value |= flags;
 658         writeq(value, ptr + (gpu_page_idx * 8));
 659
 660         return 0;
 661 }
 662
 663 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev,
 664                                           uint32_t flags)
 665 {
 666         uint64_t pte_flag = 0;
 667
 668         if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
 669                 pte_flag |= AMDGPU_PTE_EXECUTABLE;
 670         if (flags & AMDGPU_VM_PAGE_READABLE)
 671                 pte_flag |= AMDGPU_PTE_READABLE;
 672         if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 673                 pte_flag |= AMDGPU_PTE_WRITEABLE;
 674         if (flags & AMDGPU_VM_PAGE_PRT)
 675                 pte_flag |= AMDGPU_PTE_PRT;
 676
 677         return pte_flag;
 678 }
 679
 680 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
 681                                 uint64_t *addr, uint64_t *flags)
 682 {
 683         BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
 684 }
 685
 686 /**
 687  * gmc_v8_0_set_fault_enable_default - update VM fault handling
 688  *
 689  * @adev: amdgpu_device pointer
 690  * @value: true redirects VM faults to the default page
 691  */
 692 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
 693                                               bool value)
 694 {
 695         u32 tmp;
 696
 697         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 698         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 699                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 700         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 701                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 702         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 703                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 704         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 705                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 706         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 707                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 708         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 709                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 710         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 711                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 712         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 713 }
 714
 715 /**
 716  * gmc_v8_0_set_prt - set PRT VM fault
 717  *
 718  * @adev: amdgpu_device pointer
 719  * @enable: enable/disable VM fault handling for PRT
 720 */
 721 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
 722 {
 723         u32 tmp;
 724
 725         if (enable && !adev->mc.prt_warning) {
 726                 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
 727                 adev->mc.prt_warning = true;
 728         }
 729
 730         tmp = RREG32(mmVM_PRT_CNTL);
 731         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 732                             CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 733         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 734                             CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 735         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 736                             TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
 737         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 738                             TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
 739         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 740                             L2_CACHE_STORE_INVALID_ENTRIES, enable);
 741         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 742                             L1_TLB_STORE_INVALID_ENTRIES, enable);
 743         tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
 744                             MASK_PDE0_FAULT, enable);
 745         WREG32(mmVM_PRT_CNTL, tmp);
 746
 747         if (enable) {
 748                 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
 749                 uint32_t high = adev->vm_manager.max_pfn;
 750
 751                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
 752                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
 753                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
 754                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
 755                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
 756                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
 757                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
 758                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
 759         } else {
 760                 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
 761                 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
 762                 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
 763                 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
 764                 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
 765                 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
 766                 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
 767                 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
 768         }
 769 }
 770
 771 /**
 772  * gmc_v8_0_gart_enable - gart enable
 773  *
 774  * @adev: amdgpu_device pointer
 775  *
 776  * This sets up the TLBs, programs the page tables for VMID0,
 777  * sets up the hw for VMIDs 1-15 which are allocated on
 778  * demand, and sets up the global locations for the LDS, GDS,
 779  * and GPUVM for FSA64 clients (CIK).
 780  * Returns 0 for success, errors for failure.
 781  */
 782 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 783 {
 784         int r, i;
 785         u32 tmp, field;
 786
 787         if (adev->gart.robj == NULL) {
 788                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 789                 return -EINVAL;
 790         }
 791         r = amdgpu_gart_table_vram_pin(adev);
 792         if (r)
 793                 return r;
 794         /* Setup TLB control */
 795         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 796         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 797         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
 798         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 799         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
 800         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 801         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 802         /* Setup L2 cache */
 803         tmp = RREG32(mmVM_L2_CNTL);
 804         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 805         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 806         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
 807         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
 808         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
 809         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 810         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 811         WREG32(mmVM_L2_CNTL, tmp);
 812         tmp = RREG32(mmVM_L2_CNTL2);
 813         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 814         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 815         WREG32(mmVM_L2_CNTL2, tmp);
 816
 817         field = adev->vm_manager.fragment_size;
 818         tmp = RREG32(mmVM_L2_CNTL3);
 819         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
 820         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
 821         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
 822         WREG32(mmVM_L2_CNTL3, tmp);
 823         /* XXX: set to enable PTE/PDE in system memory */
 824         tmp = RREG32(mmVM_L2_CNTL4);
 825         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
 826         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
 827         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
 828         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
 829         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
 830         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
 831         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
 832         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
 833         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
 834         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
 835         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
 836         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
 837         WREG32(mmVM_L2_CNTL4, tmp);
 838         /* setup context0 */
 839         WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);
 840         WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
 841         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
 842         WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 843                         (u32)(adev->dummy_page.addr >> 12));
 844         WREG32(mmVM_CONTEXT0_CNTL2, 0);
 845         tmp = RREG32(mmVM_CONTEXT0_CNTL);
 846         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 847         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 848         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 849         WREG32(mmVM_CONTEXT0_CNTL, tmp);
 850
 851         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
 852         WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
 853         WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
 854
 855         /* empty context1-15 */
 856         /* FIXME start with 4G, once using 2 level pt switch to full
 857          * vm size space
 858          */
 859         /* set vm size, must be a multiple of 4 */
 860         WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
 861         WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
 862         for (i = 1; i < 16; i++) {
 863                 if (i < 8)
 864                         WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
 865                                adev->gart.table_addr >> 12);
 866                 else
 867                         WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
 868                                adev->gart.table_addr >> 12);
 869         }
 870
 871         /* enable context1-15 */
 872         WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
 873                (u32)(adev->dummy_page.addr >> 12));
 874         WREG32(mmVM_CONTEXT1_CNTL2, 4);
 875         tmp = RREG32(mmVM_CONTEXT1_CNTL);
 876         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 877         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
 878         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 879         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 880         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 881         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 882         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 883         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 884         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 885         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
 886                             adev->vm_manager.block_size - 9);
 887         WREG32(mmVM_CONTEXT1_CNTL, tmp);
 888         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
 889                 gmc_v8_0_set_fault_enable_default(adev, false);
 890         else
 891                 gmc_v8_0_set_fault_enable_default(adev, true);
 892
 893         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
 894         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 895                  (unsigned)(adev->mc.gart_size >> 20),
 896                  (unsigned long long)adev->gart.table_addr);
 897         adev->gart.ready = true;
 898         return 0;
 899 }
 900
 901 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 902 {
 903         int r;
 904
 905         if (adev->gart.robj) {
 906                 WARN(1, "R600 PCIE GART already initialized\n");
 907                 return 0;
 908         }
 909         /* Initialize common gart structure */
 910         r = amdgpu_gart_init(adev);
 911         if (r)
 912                 return r;
 913         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
 914         adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
 915         return amdgpu_gart_table_vram_alloc(adev);
 916 }
 917
 918 /**
 919  * gmc_v8_0_gart_disable - gart disable
 920  *
 921  * @adev: amdgpu_device pointer
 922  *
 923  * This disables all VM page table (CIK).
 924  */
 925 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
 926 {
 927         u32 tmp;
 928
 929         /* Disable all tables */
 930         WREG32(mmVM_CONTEXT0_CNTL, 0);
 931         WREG32(mmVM_CONTEXT1_CNTL, 0);
 932         /* Setup TLB control */
 933         tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
 934         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 935         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
 936         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
 937         WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
 938         /* Setup L2 cache */
 939         tmp = RREG32(mmVM_L2_CNTL);
 940         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 941         WREG32(mmVM_L2_CNTL, tmp);
 942         WREG32(mmVM_L2_CNTL2, 0);
 943         amdgpu_gart_table_vram_unpin(adev);
 944 }
 945
 946 /**
 947  * gmc_v8_0_gart_fini - vm fini callback
 948  *
 949  * @adev: amdgpu_device pointer
 950  *
 951  * Tears down the driver GART/VM setup (CIK).
 952  */
 953 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev)
 954 {
 955         amdgpu_gart_table_vram_free(adev);
 956         amdgpu_gart_fini(adev);
 957 }
 958
 959 /**
 960  * gmc_v8_0_vm_decode_fault - print human readable fault info
 961  *
 962  * @adev: amdgpu_device pointer
 963  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
 964  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
 965  *
 966  * Print human readable fault information (CIK).
 967  */
 968 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev,
 969                                      u32 status, u32 addr, u32 mc_client)
 970 {
 971         u32 mc_id;
 972         u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
 973         u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 974                                         PROTECTIONS);
 975         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
 976                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
 977
 978         mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 979                               MEMORY_CLIENT_ID);
 980
 981         dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
 982                protections, vmid, addr,
 983                REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
 984                              MEMORY_CLIENT_RW) ?
 985                "write" : "read", block, mc_client, mc_id);
 986 }
 987
 988 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
 989 {
 990         switch (mc_seq_vram_type) {
 991         case MC_SEQ_MISC0__MT__GDDR1:
 992                 return AMDGPU_VRAM_TYPE_GDDR1;
 993         case MC_SEQ_MISC0__MT__DDR2:
 994                 return AMDGPU_VRAM_TYPE_DDR2;
 995         case MC_SEQ_MISC0__MT__GDDR3:
 996                 return AMDGPU_VRAM_TYPE_GDDR3;
 997         case MC_SEQ_MISC0__MT__GDDR4:
 998                 return AMDGPU_VRAM_TYPE_GDDR4;
 999         case MC_SEQ_MISC0__MT__GDDR5:
1000                 return AMDGPU_VRAM_TYPE_GDDR5;
1001         case MC_SEQ_MISC0__MT__HBM:
1002                 return AMDGPU_VRAM_TYPE_HBM;
1003         case MC_SEQ_MISC0__MT__DDR3:
1004                 return AMDGPU_VRAM_TYPE_DDR3;
1005         default:
1006                 return AMDGPU_VRAM_TYPE_UNKNOWN;
1007         }
1008 }
1009
1010 static int gmc_v8_0_early_init(void *handle)
1011 {
1012         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013
1014         gmc_v8_0_set_gart_funcs(adev);
1015         gmc_v8_0_set_irq_funcs(adev);
1016
1017         adev->mc.shared_aperture_start = 0x2000000000000000ULL;
1018         adev->mc.shared_aperture_end =
1019                 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
1020         adev->mc.private_aperture_start =
1021                 adev->mc.shared_aperture_end + 1;
1022         adev->mc.private_aperture_end =
1023                 adev->mc.private_aperture_start + (4ULL << 30) - 1;
1024
1025         return 0;
1026 }
1027
1028 static int gmc_v8_0_late_init(void *handle)
1029 {
1030         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031
1032         if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1033                 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
1034         else
1035                 return 0;
1036 }
1037
1038 #define mmMC_SEQ_MISC0_FIJI 0xA71
1039
1040 static int gmc_v8_0_sw_init(void *handle)
1041 {
1042         int r;
1043         int dma_bits;
1044         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045
1046         if (adev->flags & AMD_IS_APU) {
1047                 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1048         } else {
1049                 u32 tmp;
1050
1051                 if (adev->asic_type == CHIP_FIJI)
1052                         tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1053                 else
1054                         tmp = RREG32(mmMC_SEQ_MISC0);
1055                 tmp &= MC_SEQ_MISC0__MT__MASK;
1056                 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1057         }
1058
1059         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
1060         if (r)
1061                 return r;
1062
1063         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
1064         if (r)
1065                 return r;
1066
1067         /* Adjust VM size here.
1068          * Currently set to 4GB ((1 << 20) 4k pages).
1069          * Max GPUVM size for cayman and SI is 40 bits.
1070          */
1071         amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1072
1073         /* Set the internal MC address mask
1074          * This is the max address of the GPU's
1075          * internal address space.
1076          */
1077         adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1078
1079         adev->mc.stolen_size = 256 * 1024;
1080
1081         /* set DMA mask + need_dma32 flags.
1082          * PCIE - can handle 40-bits.
1083          * IGP - can handle 40-bits
1084          * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1085          */
1086         adev->need_dma32 = false;
1087         dma_bits = adev->need_dma32 ? 32 : 40;
1088         r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1089         if (r) {
1090                 adev->need_dma32 = true;
1091                 dma_bits = 32;
1092                 pr_warn("amdgpu: No suitable DMA available\n");
1093         }
1094         r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
1095         if (r) {
1096                 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
1097                 pr_warn("amdgpu: No coherent DMA available\n");
1098         }
1099
1100         r = gmc_v8_0_init_microcode(adev);
1101         if (r) {
1102                 DRM_ERROR("Failed to load mc firmware!\n");
1103                 return r;
1104         }
1105
1106         r = gmc_v8_0_mc_init(adev);
1107         if (r)
1108                 return r;
1109
1110         /* Memory manager */
1111         r = amdgpu_bo_init(adev);
1112         if (r)
1113                 return r;
1114
1115         r = gmc_v8_0_gart_init(adev);
1116         if (r)
1117                 return r;
1118
1119         /*
1120          * number of VMs
1121          * VMID 0 is reserved for System
1122          * amdgpu graphics/compute will use VMIDs 1-7
1123          * amdkfd will use VMIDs 8-15
1124          */
1125         adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
1126         amdgpu_vm_manager_init(adev);
1127
1128         /* base offset of vram pages */
1129         if (adev->flags & AMD_IS_APU) {
1130                 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1131
1132                 tmp <<= 22;
1133                 adev->vm_manager.vram_base_offset = tmp;
1134         } else {
1135                 adev->vm_manager.vram_base_offset = 0;
1136         }
1137
1138         return 0;
1139 }
1140
1141 static int gmc_v8_0_sw_fini(void *handle)
1142 {
1143         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1144
1145         amdgpu_gem_force_release(adev);
1146         amdgpu_vm_manager_fini(adev);
1147         gmc_v8_0_gart_fini(adev);
1148         amdgpu_bo_fini(adev);
1149         release_firmware(adev->mc.fw);
1150         adev->mc.fw = NULL;
1151
1152         return 0;
1153 }
1154
1155 static int gmc_v8_0_hw_init(void *handle)
1156 {
1157         int r;
1158         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1159
1160         gmc_v8_0_init_golden_registers(adev);
1161
1162         gmc_v8_0_mc_program(adev);
1163
1164         if (adev->asic_type == CHIP_TONGA) {
1165                 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1166                 if (r) {
1167                         DRM_ERROR("Failed to load MC firmware!\n");
1168                         return r;
1169                 }
1170         } else if (adev->asic_type == CHIP_POLARIS11 ||
1171                         adev->asic_type == CHIP_POLARIS10 ||
1172                         adev->asic_type == CHIP_POLARIS12) {
1173                 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1174                 if (r) {
1175                         DRM_ERROR("Failed to load MC firmware!\n");
1176                         return r;
1177                 }
1178         }
1179
1180         r = gmc_v8_0_gart_enable(adev);
1181         if (r)
1182                 return r;
1183
1184         return r;
1185 }
1186
1187 static int gmc_v8_0_hw_fini(void *handle)
1188 {
1189         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190
1191         amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1192         gmc_v8_0_gart_disable(adev);
1193
1194         return 0;
1195 }
1196
1197 static int gmc_v8_0_suspend(void *handle)
1198 {
1199         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200
1201         gmc_v8_0_hw_fini(adev);
1202
1203         return 0;
1204 }
1205
1206 static int gmc_v8_0_resume(void *handle)
1207 {
1208         int r;
1209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1210
1211         r = gmc_v8_0_hw_init(adev);
1212         if (r)
1213                 return r;
1214
1215         amdgpu_vmid_reset_all(adev);
1216
1217         return 0;
1218 }
1219
1220 static bool gmc_v8_0_is_idle(void *handle)
1221 {
1222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1223         u32 tmp = RREG32(mmSRBM_STATUS);
1224
1225         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1226                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1227                 return false;
1228
1229         return true;
1230 }
1231
1232 static int gmc_v8_0_wait_for_idle(void *handle)
1233 {
1234         unsigned i;
1235         u32 tmp;
1236         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1237
1238         for (i = 0; i < adev->usec_timeout; i++) {
1239                 /* read MC_STATUS */
1240                 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1241                                                SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1242                                                SRBM_STATUS__MCC_BUSY_MASK |
1243                                                SRBM_STATUS__MCD_BUSY_MASK |
1244                                                SRBM_STATUS__VMC_BUSY_MASK |
1245                                                SRBM_STATUS__VMC1_BUSY_MASK);
1246                 if (!tmp)
1247                         return 0;
1248                 udelay(1);
1249         }
1250         return -ETIMEDOUT;
1251
1252 }
1253
1254 static bool gmc_v8_0_check_soft_reset(void *handle)
1255 {
1256         u32 srbm_soft_reset = 0;
1257         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1258         u32 tmp = RREG32(mmSRBM_STATUS);
1259
1260         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1261                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1262                                                 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1263
1264         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1265                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1266                 if (!(adev->flags & AMD_IS_APU))
1267                         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1268                                                         SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1269         }
1270         if (srbm_soft_reset) {
1271                 adev->mc.srbm_soft_reset = srbm_soft_reset;
1272                 return true;
1273         } else {
1274                 adev->mc.srbm_soft_reset = 0;
1275                 return false;
1276         }
1277 }
1278
1279 static int gmc_v8_0_pre_soft_reset(void *handle)
1280 {
1281         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1282
1283         if (!adev->mc.srbm_soft_reset)
1284                 return 0;
1285
1286         gmc_v8_0_mc_stop(adev);
1287         if (gmc_v8_0_wait_for_idle(adev)) {
1288                 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1289         }
1290
1291         return 0;
1292 }
1293
1294 static int gmc_v8_0_soft_reset(void *handle)
1295 {
1296         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297         u32 srbm_soft_reset;
1298
1299         if (!adev->mc.srbm_soft_reset)
1300                 return 0;
1301         srbm_soft_reset = adev->mc.srbm_soft_reset;
1302
1303         if (srbm_soft_reset) {
1304                 u32 tmp;
1305
1306                 tmp = RREG32(mmSRBM_SOFT_RESET);
1307                 tmp |= srbm_soft_reset;
1308                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1309                 WREG32(mmSRBM_SOFT_RESET, tmp);
1310                 tmp = RREG32(mmSRBM_SOFT_RESET);
1311
1312                 udelay(50);
1313
1314                 tmp &= ~srbm_soft_reset;
1315                 WREG32(mmSRBM_SOFT_RESET, tmp);
1316                 tmp = RREG32(mmSRBM_SOFT_RESET);
1317
1318                 /* Wait a little for things to settle down */
1319                 udelay(50);
1320         }
1321
1322         return 0;
1323 }
1324
1325 static int gmc_v8_0_post_soft_reset(void *handle)
1326 {
1327         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329         if (!adev->mc.srbm_soft_reset)
1330                 return 0;
1331
1332         gmc_v8_0_mc_resume(adev);
1333         return 0;
1334 }
1335
1336 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1337                                              struct amdgpu_irq_src *src,
1338                                              unsigned type,
1339                                              enum amdgpu_interrupt_state state)
1340 {
1341         u32 tmp;
1342         u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1343                     VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1344                     VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1345                     VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1346                     VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1347                     VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1348                     VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1349
1350         switch (state) {
1351         case AMDGPU_IRQ_STATE_DISABLE:
1352                 /* system context */
1353                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1354                 tmp &= ~bits;
1355                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1356                 /* VMs */
1357                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1358                 tmp &= ~bits;
1359                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1360                 break;
1361         case AMDGPU_IRQ_STATE_ENABLE:
1362                 /* system context */
1363                 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1364                 tmp |= bits;
1365                 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1366                 /* VMs */
1367                 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1368                 tmp |= bits;
1369                 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1370                 break;
1371         default:
1372                 break;
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1379                                       struct amdgpu_irq_src *source,
1380                                       struct amdgpu_iv_entry *entry)
1381 {
1382         u32 addr, status, mc_client;
1383
1384         if (amdgpu_sriov_vf(adev)) {
1385                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1386                         entry->src_id, entry->src_data[0]);
1387                 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1388                 return 0;
1389         }
1390
1391         addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1392         status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1393         mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1394         /* reset addr and status */
1395         WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1396
1397         if (!addr && !status)
1398                 return 0;
1399
1400         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1401                 gmc_v8_0_set_fault_enable_default(adev, false);
1402
1403         if (printk_ratelimit()) {
1404                 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1405                         entry->src_id, entry->src_data[0]);
1406                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1407                         addr);
1408                 dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1409                         status);
1410                 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client);
1411         }
1412
1413         return 0;
1414 }
1415
1416 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1417                                                      bool enable)
1418 {
1419         uint32_t data;
1420
1421         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1422                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1423                 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1424                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1425
1426                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1427                 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1428                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1429
1430                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1431                 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1432                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1433
1434                 data = RREG32(mmMC_XPB_CLK_GAT);
1435                 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1436                 WREG32(mmMC_XPB_CLK_GAT, data);
1437
1438                 data = RREG32(mmATC_MISC_CG);
1439                 data |= ATC_MISC_CG__ENABLE_MASK;
1440                 WREG32(mmATC_MISC_CG, data);
1441
1442                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1443                 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1444                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1445
1446                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1447                 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1448                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1449
1450                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1451                 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1452                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1453
1454                 data = RREG32(mmVM_L2_CG);
1455                 data |= VM_L2_CG__ENABLE_MASK;
1456                 WREG32(mmVM_L2_CG, data);
1457         } else {
1458                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1459                 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1460                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1461
1462                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1463                 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1464                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1465
1466                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1467                 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1468                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1469
1470                 data = RREG32(mmMC_XPB_CLK_GAT);
1471                 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1472                 WREG32(mmMC_XPB_CLK_GAT, data);
1473
1474                 data = RREG32(mmATC_MISC_CG);
1475                 data &= ~ATC_MISC_CG__ENABLE_MASK;
1476                 WREG32(mmATC_MISC_CG, data);
1477
1478                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1479                 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1480                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1481
1482                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1483                 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1484                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1485
1486                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1487                 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1488                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1489
1490                 data = RREG32(mmVM_L2_CG);
1491                 data &= ~VM_L2_CG__ENABLE_MASK;
1492                 WREG32(mmVM_L2_CG, data);
1493         }
1494 }
1495
1496 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1497                                        bool enable)
1498 {
1499         uint32_t data;
1500
1501         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1502                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1503                 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1504                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1505
1506                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1507                 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1508                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1509
1510                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1511                 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1512                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1513
1514                 data = RREG32(mmMC_XPB_CLK_GAT);
1515                 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1516                 WREG32(mmMC_XPB_CLK_GAT, data);
1517
1518                 data = RREG32(mmATC_MISC_CG);
1519                 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1520                 WREG32(mmATC_MISC_CG, data);
1521
1522                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1523                 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1524                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1525
1526                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1527                 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1528                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1529
1530                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1531                 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1532                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1533
1534                 data = RREG32(mmVM_L2_CG);
1535                 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1536                 WREG32(mmVM_L2_CG, data);
1537         } else {
1538                 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1539                 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1540                 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1541
1542                 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1543                 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1544                 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1545
1546                 data = RREG32(mmMC_HUB_MISC_VM_CG);
1547                 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1548                 WREG32(mmMC_HUB_MISC_VM_CG, data);
1549
1550                 data = RREG32(mmMC_XPB_CLK_GAT);
1551                 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1552                 WREG32(mmMC_XPB_CLK_GAT, data);
1553
1554                 data = RREG32(mmATC_MISC_CG);
1555                 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1556                 WREG32(mmATC_MISC_CG, data);
1557
1558                 data = RREG32(mmMC_CITF_MISC_WR_CG);
1559                 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1560                 WREG32(mmMC_CITF_MISC_WR_CG, data);
1561
1562                 data = RREG32(mmMC_CITF_MISC_RD_CG);
1563                 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1564                 WREG32(mmMC_CITF_MISC_RD_CG, data);
1565
1566                 data = RREG32(mmMC_CITF_MISC_VM_CG);
1567                 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1568                 WREG32(mmMC_CITF_MISC_VM_CG, data);
1569
1570                 data = RREG32(mmVM_L2_CG);
1571                 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1572                 WREG32(mmVM_L2_CG, data);
1573         }
1574 }
1575
1576 static int gmc_v8_0_set_clockgating_state(void *handle,
1577                                           enum amd_clockgating_state state)
1578 {
1579         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1580
1581         if (amdgpu_sriov_vf(adev))
1582                 return 0;
1583
1584         switch (adev->asic_type) {
1585         case CHIP_FIJI:
1586                 fiji_update_mc_medium_grain_clock_gating(adev,
1587                                 state == AMD_CG_STATE_GATE);
1588                 fiji_update_mc_light_sleep(adev,
1589                                 state == AMD_CG_STATE_GATE);
1590                 break;
1591         default:
1592                 break;
1593         }
1594         return 0;
1595 }
1596
1597 static int gmc_v8_0_set_powergating_state(void *handle,
1598                                           enum amd_powergating_state state)
1599 {
1600         return 0;
1601 }
1602
1603 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags)
1604 {
1605         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1606         int data;
1607
1608         if (amdgpu_sriov_vf(adev))
1609                 *flags = 0;
1610
1611         /* AMD_CG_SUPPORT_MC_MGCG */
1612         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1613         if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1614                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1615
1616         /* AMD_CG_SUPPORT_MC_LS */
1617         if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1618                 *flags |= AMD_CG_SUPPORT_MC_LS;
1619 }
1620
1621 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1622         .name = "gmc_v8_0",
1623         .early_init = gmc_v8_0_early_init,
1624         .late_init = gmc_v8_0_late_init,
1625         .sw_init = gmc_v8_0_sw_init,
1626         .sw_fini = gmc_v8_0_sw_fini,
1627         .hw_init = gmc_v8_0_hw_init,
1628         .hw_fini = gmc_v8_0_hw_fini,
1629         .suspend = gmc_v8_0_suspend,
1630         .resume = gmc_v8_0_resume,
1631         .is_idle = gmc_v8_0_is_idle,
1632         .wait_for_idle = gmc_v8_0_wait_for_idle,
1633         .check_soft_reset = gmc_v8_0_check_soft_reset,
1634         .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1635         .soft_reset = gmc_v8_0_soft_reset,
1636         .post_soft_reset = gmc_v8_0_post_soft_reset,
1637         .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1638         .set_powergating_state = gmc_v8_0_set_powergating_state,
1639         .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1640 };
1641
1642 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = {
1643         .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb,
1644         .set_pte_pde = gmc_v8_0_gart_set_pte_pde,
1645         .set_prt = gmc_v8_0_set_prt,
1646         .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags,
1647         .get_vm_pde = gmc_v8_0_get_vm_pde
1648 };
1649
1650 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1651         .set = gmc_v8_0_vm_fault_interrupt_state,
1652         .process = gmc_v8_0_process_interrupt,
1653 };
1654
1655 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev)
1656 {
1657         if (adev->gart.gart_funcs == NULL)
1658                 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs;
1659 }
1660
1661 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1662 {
1663         adev->mc.vm_fault.num_types = 1;
1664         adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1665 }
1666
1667 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1668 {
1669         .type = AMD_IP_BLOCK_TYPE_GMC,
1670         .major = 8,
1671         .minor = 0,
1672         .rev = 0,
1673         .funcs = &gmc_v8_0_ip_funcs,
1674 };
1675
1676 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1677 {
1678         .type = AMD_IP_BLOCK_TYPE_GMC,
1679         .major = 8,
1680         .minor = 1,
1681         .rev = 0,
1682         .funcs = &gmc_v8_0_ip_funcs,
1683 };
1684
1685 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1686 {
1687         .type = AMD_IP_BLOCK_TYPE_GMC,
1688         .major = 8,
1689         .minor = 5,
1690         .rev = 0,
1691         .funcs = &gmc_v8_0_ip_funcs,
1692 };