drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  81                                     struct device_attribute *attr,
  82                                     char *buf)
  83 {
  84         struct drm_device *ddev = dev_get_drvdata(dev);
  85         struct amdgpu_device *adev = ddev->dev_private;
  86         enum amd_pm_state_type pm;
  87
  88         if (adev->powerplay.pp_funcs->get_current_power_state)
  89                 pm = amdgpu_dpm_get_current_power_state(adev);
  90         else
  91                 pm = adev->pm.dpm.user_state;
  92
  93         return snprintf(buf, PAGE_SIZE, "%s\n",
  94                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  95                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  96 }
  97
  98 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  99                                     struct device_attribute *attr,
 100                                     const char *buf,
 101                                     size_t count)
 102 {
 103         struct drm_device *ddev = dev_get_drvdata(dev);
 104         struct amdgpu_device *adev = ddev->dev_private;
 105         enum amd_pm_state_type  state;
 106
 107         if (strncmp("battery", buf, strlen("battery")) == 0)
 108                 state = POWER_STATE_TYPE_BATTERY;
 109         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 110                 state = POWER_STATE_TYPE_BALANCED;
 111         else if (strncmp("performance", buf, strlen("performance")) == 0)
 112                 state = POWER_STATE_TYPE_PERFORMANCE;
 113         else {
 114                 count = -EINVAL;
 115                 goto fail;
 116         }
 117
 118         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 119                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
 120         } else {
 121                 mutex_lock(&adev->pm.mutex);
 122                 adev->pm.dpm.user_state = state;
 123                 mutex_unlock(&adev->pm.mutex);
 124
 125                 /* Can't set dpm state when the card is off */
 126                 if (!(adev->flags & AMD_IS_PX) ||
 127                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 128                         amdgpu_pm_compute_clocks(adev);
 129         }
 130 fail:
 131         return count;
 132 }
 133
 134 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 135                                                 struct device_attribute *attr,
 136                                                                 char *buf)
 137 {
 138         struct drm_device *ddev = dev_get_drvdata(dev);
 139         struct amdgpu_device *adev = ddev->dev_private;
 140         enum amd_dpm_forced_level level = 0xff;
 141
 142         if  ((adev->flags & AMD_IS_PX) &&
 143              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 144                 return snprintf(buf, PAGE_SIZE, "off\n");
 145
 146         if (adev->powerplay.pp_funcs->get_performance_level)
 147                 level = amdgpu_dpm_get_performance_level(adev);
 148         else
 149                 level = adev->pm.dpm.forced_level;
 150
 151         return snprintf(buf, PAGE_SIZE, "%s\n",
 152                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 153                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 154                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 155                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 156                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 157                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 158                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 159                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 160                         "unknown");
 161 }
 162
 163 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 164                                                        struct device_attribute *attr,
 165                                                        const char *buf,
 166                                                        size_t count)
 167 {
 168         struct drm_device *ddev = dev_get_drvdata(dev);
 169         struct amdgpu_device *adev = ddev->dev_private;
 170         enum amd_dpm_forced_level level;
 171         enum amd_dpm_forced_level current_level = 0xff;
 172         int ret = 0;
 173
 174         /* Can't force performance level when the card is off */
 175         if  ((adev->flags & AMD_IS_PX) &&
 176              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 177                 return -EINVAL;
 178
 179         if (adev->powerplay.pp_funcs->get_performance_level)
 180                 current_level = amdgpu_dpm_get_performance_level(adev);
 181
 182         if (strncmp("low", buf, strlen("low")) == 0) {
 183                 level = AMD_DPM_FORCED_LEVEL_LOW;
 184         } else if (strncmp("high", buf, strlen("high")) == 0) {
 185                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 186         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 187                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 188         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 189                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 190         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 191                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 192         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 193                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 194         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 195                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 196         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 197                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 198         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 199                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 200         }  else {
 201                 count = -EINVAL;
 202                 goto fail;
 203         }
 204
 205         if (current_level == level)
 206                 return count;
 207
 208         if (adev->powerplay.pp_funcs->force_performance_level) {
 209                 mutex_lock(&adev->pm.mutex);
 210                 if (adev->pm.dpm.thermal_active) {
 211                         count = -EINVAL;
 212                         mutex_unlock(&adev->pm.mutex);
 213                         goto fail;
 214                 }
 215                 ret = amdgpu_dpm_force_performance_level(adev, level);
 216                 if (ret)
 217                         count = -EINVAL;
 218                 else
 219                         adev->pm.dpm.forced_level = level;
 220                 mutex_unlock(&adev->pm.mutex);
 221         }
 222
 223 fail:
 224         return count;
 225 }
 226
 227 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 228                 struct device_attribute *attr,
 229                 char *buf)
 230 {
 231         struct drm_device *ddev = dev_get_drvdata(dev);
 232         struct amdgpu_device *adev = ddev->dev_private;
 233         struct pp_states_info data;
 234         int i, buf_len;
 235
 236         if (adev->powerplay.pp_funcs->get_pp_num_states)
 237                 amdgpu_dpm_get_pp_num_states(adev, &data);
 238
 239         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 240         for (i = 0; i < data.nums; i++)
 241                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 242                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 243                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 244                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 245                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 246
 247         return buf_len;
 248 }
 249
 250 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 251                 struct device_attribute *attr,
 252                 char *buf)
 253 {
 254         struct drm_device *ddev = dev_get_drvdata(dev);
 255         struct amdgpu_device *adev = ddev->dev_private;
 256         struct pp_states_info data;
 257         enum amd_pm_state_type pm = 0;
 258         int i = 0;
 259
 260         if (adev->powerplay.pp_funcs->get_current_power_state
 261                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 262                 pm = amdgpu_dpm_get_current_power_state(adev);
 263                 amdgpu_dpm_get_pp_num_states(adev, &data);
 264
 265                 for (i = 0; i < data.nums; i++) {
 266                         if (pm == data.states[i])
 267                                 break;
 268                 }
 269
 270                 if (i == data.nums)
 271                         i = -EINVAL;
 272         }
 273
 274         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 275 }
 276
 277 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 278                 struct device_attribute *attr,
 279                 char *buf)
 280 {
 281         struct drm_device *ddev = dev_get_drvdata(dev);
 282         struct amdgpu_device *adev = ddev->dev_private;
 283
 284         if (adev->pp_force_state_enabled)
 285                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 286         else
 287                 return snprintf(buf, PAGE_SIZE, "\n");
 288 }
 289
 290 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 291                 struct device_attribute *attr,
 292                 const char *buf,
 293                 size_t count)
 294 {
 295         struct drm_device *ddev = dev_get_drvdata(dev);
 296         struct amdgpu_device *adev = ddev->dev_private;
 297         enum amd_pm_state_type state = 0;
 298         unsigned long idx;
 299         int ret;
 300
 301         if (strlen(buf) == 1)
 302                 adev->pp_force_state_enabled = false;
 303         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 304                         adev->powerplay.pp_funcs->get_pp_num_states) {
 305                 struct pp_states_info data;
 306
 307                 ret = kstrtoul(buf, 0, &idx);
 308                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 309                         count = -EINVAL;
 310                         goto fail;
 311                 }
 312
 313                 amdgpu_dpm_get_pp_num_states(adev, &data);
 314                 state = data.states[idx];
 315                 /* only set user selected power states */
 316                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 317                     state != POWER_STATE_TYPE_DEFAULT) {
 318                         amdgpu_dpm_dispatch_task(adev,
 319                                         AMD_PP_TASK_ENABLE_USER_STATE, &state, NULL);
 320                         adev->pp_force_state_enabled = true;
 321                 }
 322         }
 323 fail:
 324         return count;
 325 }
 326
 327 static ssize_t amdgpu_get_pp_table(struct device *dev,
 328                 struct device_attribute *attr,
 329                 char *buf)
 330 {
 331         struct drm_device *ddev = dev_get_drvdata(dev);
 332         struct amdgpu_device *adev = ddev->dev_private;
 333         char *table = NULL;
 334         int size;
 335
 336         if (adev->powerplay.pp_funcs->get_pp_table)
 337                 size = amdgpu_dpm_get_pp_table(adev, &table);
 338         else
 339                 return 0;
 340
 341         if (size >= PAGE_SIZE)
 342                 size = PAGE_SIZE - 1;
 343
 344         memcpy(buf, table, size);
 345
 346         return size;
 347 }
 348
 349 static ssize_t amdgpu_set_pp_table(struct device *dev,
 350                 struct device_attribute *attr,
 351                 const char *buf,
 352                 size_t count)
 353 {
 354         struct drm_device *ddev = dev_get_drvdata(dev);
 355         struct amdgpu_device *adev = ddev->dev_private;
 356
 357         if (adev->powerplay.pp_funcs->set_pp_table)
 358                 amdgpu_dpm_set_pp_table(adev, buf, count);
 359
 360         return count;
 361 }
 362
 363 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 364                 struct device_attribute *attr,
 365                 char *buf)
 366 {
 367         struct drm_device *ddev = dev_get_drvdata(dev);
 368         struct amdgpu_device *adev = ddev->dev_private;
 369
 370         if (adev->powerplay.pp_funcs->print_clock_levels)
 371                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 372         else
 373                 return snprintf(buf, PAGE_SIZE, "\n");
 374 }
 375
 376 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 377                 struct device_attribute *attr,
 378                 const char *buf,
 379                 size_t count)
 380 {
 381         struct drm_device *ddev = dev_get_drvdata(dev);
 382         struct amdgpu_device *adev = ddev->dev_private;
 383         int ret;
 384         long level;
 385         uint32_t i, mask = 0;
 386         char sub_str[2];
 387
 388         for (i = 0; i < strlen(buf); i++) {
 389                 if (*(buf + i) == '\n')
 390                         continue;
 391                 sub_str[0] = *(buf + i);
 392                 sub_str[1] = '\0';
 393                 ret = kstrtol(sub_str, 0, &level);
 394
 395                 if (ret) {
 396                         count = -EINVAL;
 397                         goto fail;
 398                 }
 399                 mask |= 1 << level;
 400         }
 401
 402         if (adev->powerplay.pp_funcs->force_clock_level)
 403                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 404
 405 fail:
 406         return count;
 407 }
 408
 409 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 410                 struct device_attribute *attr,
 411                 char *buf)
 412 {
 413         struct drm_device *ddev = dev_get_drvdata(dev);
 414         struct amdgpu_device *adev = ddev->dev_private;
 415
 416         if (adev->powerplay.pp_funcs->print_clock_levels)
 417                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 418         else
 419                 return snprintf(buf, PAGE_SIZE, "\n");
 420 }
 421
 422 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 423                 struct device_attribute *attr,
 424                 const char *buf,
 425                 size_t count)
 426 {
 427         struct drm_device *ddev = dev_get_drvdata(dev);
 428         struct amdgpu_device *adev = ddev->dev_private;
 429         int ret;
 430         long level;
 431         uint32_t i, mask = 0;
 432         char sub_str[2];
 433
 434         for (i = 0; i < strlen(buf); i++) {
 435                 if (*(buf + i) == '\n')
 436                         continue;
 437                 sub_str[0] = *(buf + i);
 438                 sub_str[1] = '\0';
 439                 ret = kstrtol(sub_str, 0, &level);
 440
 441                 if (ret) {
 442                         count = -EINVAL;
 443                         goto fail;
 444                 }
 445                 mask |= 1 << level;
 446         }
 447         if (adev->powerplay.pp_funcs->force_clock_level)
 448                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 449
 450 fail:
 451         return count;
 452 }
 453
 454 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 455                 struct device_attribute *attr,
 456                 char *buf)
 457 {
 458         struct drm_device *ddev = dev_get_drvdata(dev);
 459         struct amdgpu_device *adev = ddev->dev_private;
 460
 461         if (adev->powerplay.pp_funcs->print_clock_levels)
 462                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 463         else
 464                 return snprintf(buf, PAGE_SIZE, "\n");
 465 }
 466
 467 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 468                 struct device_attribute *attr,
 469                 const char *buf,
 470                 size_t count)
 471 {
 472         struct drm_device *ddev = dev_get_drvdata(dev);
 473         struct amdgpu_device *adev = ddev->dev_private;
 474         int ret;
 475         long level;
 476         uint32_t i, mask = 0;
 477         char sub_str[2];
 478
 479         for (i = 0; i < strlen(buf); i++) {
 480                 if (*(buf + i) == '\n')
 481                         continue;
 482                 sub_str[0] = *(buf + i);
 483                 sub_str[1] = '\0';
 484                 ret = kstrtol(sub_str, 0, &level);
 485
 486                 if (ret) {
 487                         count = -EINVAL;
 488                         goto fail;
 489                 }
 490                 mask |= 1 << level;
 491         }
 492         if (adev->powerplay.pp_funcs->force_clock_level)
 493                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 494
 495 fail:
 496         return count;
 497 }
 498
 499 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 500                 struct device_attribute *attr,
 501                 char *buf)
 502 {
 503         struct drm_device *ddev = dev_get_drvdata(dev);
 504         struct amdgpu_device *adev = ddev->dev_private;
 505         uint32_t value = 0;
 506
 507         if (adev->powerplay.pp_funcs->get_sclk_od)
 508                 value = amdgpu_dpm_get_sclk_od(adev);
 509
 510         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 511 }
 512
 513 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 514                 struct device_attribute *attr,
 515                 const char *buf,
 516                 size_t count)
 517 {
 518         struct drm_device *ddev = dev_get_drvdata(dev);
 519         struct amdgpu_device *adev = ddev->dev_private;
 520         int ret;
 521         long int value;
 522
 523         ret = kstrtol(buf, 0, &value);
 524
 525         if (ret) {
 526                 count = -EINVAL;
 527                 goto fail;
 528         }
 529         if (adev->powerplay.pp_funcs->set_sclk_od)
 530                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 531
 532         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 533                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
 534         } else {
 535                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 536                 amdgpu_pm_compute_clocks(adev);
 537         }
 538
 539 fail:
 540         return count;
 541 }
 542
 543 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 544                 struct device_attribute *attr,
 545                 char *buf)
 546 {
 547         struct drm_device *ddev = dev_get_drvdata(dev);
 548         struct amdgpu_device *adev = ddev->dev_private;
 549         uint32_t value = 0;
 550
 551         if (adev->powerplay.pp_funcs->get_mclk_od)
 552                 value = amdgpu_dpm_get_mclk_od(adev);
 553
 554         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 555 }
 556
 557 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 558                 struct device_attribute *attr,
 559                 const char *buf,
 560                 size_t count)
 561 {
 562         struct drm_device *ddev = dev_get_drvdata(dev);
 563         struct amdgpu_device *adev = ddev->dev_private;
 564         int ret;
 565         long int value;
 566
 567         ret = kstrtol(buf, 0, &value);
 568
 569         if (ret) {
 570                 count = -EINVAL;
 571                 goto fail;
 572         }
 573         if (adev->powerplay.pp_funcs->set_mclk_od)
 574                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 575
 576         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 577                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
 578         } else {
 579                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 580                 amdgpu_pm_compute_clocks(adev);
 581         }
 582
 583 fail:
 584         return count;
 585 }
 586
 587 static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
 588                 char *buf, struct amd_pp_profile *query)
 589 {
 590         struct drm_device *ddev = dev_get_drvdata(dev);
 591         struct amdgpu_device *adev = ddev->dev_private;
 592         int ret = 0xff;
 593
 594         if (adev->powerplay.pp_funcs->get_power_profile_state)
 595                 ret = amdgpu_dpm_get_power_profile_state(
 596                                 adev, query);
 597
 598         if (ret)
 599                 return ret;
 600
 601         return snprintf(buf, PAGE_SIZE,
 602                         "%d %d %d %d %d\n",
 603                         query->min_sclk / 100,
 604                         query->min_mclk / 100,
 605                         query->activity_threshold,
 606                         query->up_hyst,
 607                         query->down_hyst);
 608 }
 609
 610 static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev,
 611                 struct device_attribute *attr,
 612                 char *buf)
 613 {
 614         struct amd_pp_profile query = {0};
 615
 616         query.type = AMD_PP_GFX_PROFILE;
 617
 618         return amdgpu_get_pp_power_profile(dev, buf, &query);
 619 }
 620
 621 static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev,
 622                 struct device_attribute *attr,
 623                 char *buf)
 624 {
 625         struct amd_pp_profile query = {0};
 626
 627         query.type = AMD_PP_COMPUTE_PROFILE;
 628
 629         return amdgpu_get_pp_power_profile(dev, buf, &query);
 630 }
 631
 632 static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
 633                 const char *buf,
 634                 size_t count,
 635                 struct amd_pp_profile *request)
 636 {
 637         struct drm_device *ddev = dev_get_drvdata(dev);
 638         struct amdgpu_device *adev = ddev->dev_private;
 639         uint32_t loop = 0;
 640         char *sub_str, buf_cpy[128], *tmp_str;
 641         const char delimiter[3] = {' ', '\n', '\0'};
 642         long int value;
 643         int ret = 0xff;
 644
 645         if (strncmp("reset", buf, strlen("reset")) == 0) {
 646                 if (adev->powerplay.pp_funcs->reset_power_profile_state)
 647                         ret = amdgpu_dpm_reset_power_profile_state(
 648                                         adev, request);
 649                 if (ret) {
 650                         count = -EINVAL;
 651                         goto fail;
 652                 }
 653                 return count;
 654         }
 655
 656         if (strncmp("set", buf, strlen("set")) == 0) {
 657                 if (adev->powerplay.pp_funcs->set_power_profile_state)
 658                         ret = amdgpu_dpm_set_power_profile_state(
 659                                         adev, request);
 660
 661                 if (ret) {
 662                         count = -EINVAL;
 663                         goto fail;
 664                 }
 665                 return count;
 666         }
 667
 668         if (count + 1 >= 128) {
 669                 count = -EINVAL;
 670                 goto fail;
 671         }
 672
 673         memcpy(buf_cpy, buf, count + 1);
 674         tmp_str = buf_cpy;
 675
 676         while (tmp_str[0]) {
 677                 sub_str = strsep(&tmp_str, delimiter);
 678                 ret = kstrtol(sub_str, 0, &value);
 679                 if (ret) {
 680                         count = -EINVAL;
 681                         goto fail;
 682                 }
 683
 684                 switch (loop) {
 685                 case 0:
 686                         /* input unit MHz convert to dpm table unit 10KHz*/
 687                         request->min_sclk = (uint32_t)value * 100;
 688                         break;
 689                 case 1:
 690                         /* input unit MHz convert to dpm table unit 10KHz*/
 691                         request->min_mclk = (uint32_t)value * 100;
 692                         break;
 693                 case 2:
 694                         request->activity_threshold = (uint16_t)value;
 695                         break;
 696                 case 3:
 697                         request->up_hyst = (uint8_t)value;
 698                         break;
 699                 case 4:
 700                         request->down_hyst = (uint8_t)value;
 701                         break;
 702                 default:
 703                         break;
 704                 }
 705
 706                 loop++;
 707         }
 708         if (adev->powerplay.pp_funcs->set_power_profile_state)
 709                 ret = amdgpu_dpm_set_power_profile_state(adev, request);
 710
 711         if (ret)
 712                 count = -EINVAL;
 713
 714 fail:
 715         return count;
 716 }
 717
 718 static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev,
 719                 struct device_attribute *attr,
 720                 const char *buf,
 721                 size_t count)
 722 {
 723         struct amd_pp_profile request = {0};
 724
 725         request.type = AMD_PP_GFX_PROFILE;
 726
 727         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 728 }
 729
 730 static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev,
 731                 struct device_attribute *attr,
 732                 const char *buf,
 733                 size_t count)
 734 {
 735         struct amd_pp_profile request = {0};
 736
 737         request.type = AMD_PP_COMPUTE_PROFILE;
 738
 739         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 740 }
 741
 742 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 743 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 744                    amdgpu_get_dpm_forced_performance_level,
 745                    amdgpu_set_dpm_forced_performance_level);
 746 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 747 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 748 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 749                 amdgpu_get_pp_force_state,
 750                 amdgpu_set_pp_force_state);
 751 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 752                 amdgpu_get_pp_table,
 753                 amdgpu_set_pp_table);
 754 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 755                 amdgpu_get_pp_dpm_sclk,
 756                 amdgpu_set_pp_dpm_sclk);
 757 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 758                 amdgpu_get_pp_dpm_mclk,
 759                 amdgpu_set_pp_dpm_mclk);
 760 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 761                 amdgpu_get_pp_dpm_pcie,
 762                 amdgpu_set_pp_dpm_pcie);
 763 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 764                 amdgpu_get_pp_sclk_od,
 765                 amdgpu_set_pp_sclk_od);
 766 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 767                 amdgpu_get_pp_mclk_od,
 768                 amdgpu_set_pp_mclk_od);
 769 static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
 770                 amdgpu_get_pp_gfx_power_profile,
 771                 amdgpu_set_pp_gfx_power_profile);
 772 static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
 773                 amdgpu_get_pp_compute_power_profile,
 774                 amdgpu_set_pp_compute_power_profile);
 775
 776 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 777                                       struct device_attribute *attr,
 778                                       char *buf)
 779 {
 780         struct amdgpu_device *adev = dev_get_drvdata(dev);
 781         struct drm_device *ddev = adev->ddev;
 782         int temp;
 783
 784         /* Can't get temperature when the card is off */
 785         if  ((adev->flags & AMD_IS_PX) &&
 786              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 787                 return -EINVAL;
 788
 789         if (!adev->powerplay.pp_funcs->get_temperature)
 790                 temp = 0;
 791         else
 792                 temp = amdgpu_dpm_get_temperature(adev);
 793
 794         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 795 }
 796
 797 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 798                                              struct device_attribute *attr,
 799                                              char *buf)
 800 {
 801         struct amdgpu_device *adev = dev_get_drvdata(dev);
 802         int hyst = to_sensor_dev_attr(attr)->index;
 803         int temp;
 804
 805         if (hyst)
 806                 temp = adev->pm.dpm.thermal.min_temp;
 807         else
 808                 temp = adev->pm.dpm.thermal.max_temp;
 809
 810         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 811 }
 812
 813 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 814                                             struct device_attribute *attr,
 815                                             char *buf)
 816 {
 817         struct amdgpu_device *adev = dev_get_drvdata(dev);
 818         u32 pwm_mode = 0;
 819
 820         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 821                 return -EINVAL;
 822
 823         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 824
 825         return sprintf(buf, "%i\n", pwm_mode);
 826 }
 827
 828 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 829                                             struct device_attribute *attr,
 830                                             const char *buf,
 831                                             size_t count)
 832 {
 833         struct amdgpu_device *adev = dev_get_drvdata(dev);
 834         int err;
 835         int value;
 836
 837         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 838                 return -EINVAL;
 839
 840         err = kstrtoint(buf, 10, &value);
 841         if (err)
 842                 return err;
 843
 844         amdgpu_dpm_set_fan_control_mode(adev, value);
 845
 846         return count;
 847 }
 848
 849 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 850                                          struct device_attribute *attr,
 851                                          char *buf)
 852 {
 853         return sprintf(buf, "%i\n", 0);
 854 }
 855
 856 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 857                                          struct device_attribute *attr,
 858                                          char *buf)
 859 {
 860         return sprintf(buf, "%i\n", 255);
 861 }
 862
 863 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 864                                      struct device_attribute *attr,
 865                                      const char *buf, size_t count)
 866 {
 867         struct amdgpu_device *adev = dev_get_drvdata(dev);
 868         int err;
 869         u32 value;
 870
 871         err = kstrtou32(buf, 10, &value);
 872         if (err)
 873                 return err;
 874
 875         value = (value * 100) / 255;
 876
 877         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
 878                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 879                 if (err)
 880                         return err;
 881         }
 882
 883         return count;
 884 }
 885
 886 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 887                                      struct device_attribute *attr,
 888                                      char *buf)
 889 {
 890         struct amdgpu_device *adev = dev_get_drvdata(dev);
 891         int err;
 892         u32 speed = 0;
 893
 894         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
 895                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 896                 if (err)
 897                         return err;
 898         }
 899
 900         speed = (speed * 255) / 100;
 901
 902         return sprintf(buf, "%i\n", speed);
 903 }
 904
 905 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 906                                            struct device_attribute *attr,
 907                                            char *buf)
 908 {
 909         struct amdgpu_device *adev = dev_get_drvdata(dev);
 910         int err;
 911         u32 speed = 0;
 912
 913         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
 914                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 915                 if (err)
 916                         return err;
 917         }
 918
 919         return sprintf(buf, "%i\n", speed);
 920 }
 921
 922 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 923 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 924 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 925 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 926 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 927 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 928 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 929 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
 930
 931 static struct attribute *hwmon_attributes[] = {
 932         &sensor_dev_attr_temp1_input.dev_attr.attr,
 933         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 934         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 935         &sensor_dev_attr_pwm1.dev_attr.attr,
 936         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 937         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 938         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 939         &sensor_dev_attr_fan1_input.dev_attr.attr,
 940         NULL
 941 };
 942
 943 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 944                                         struct attribute *attr, int index)
 945 {
 946         struct device *dev = kobj_to_dev(kobj);
 947         struct amdgpu_device *adev = dev_get_drvdata(dev);
 948         umode_t effective_mode = attr->mode;
 949
 950         /* no skipping for powerplay */
 951         if (adev->powerplay.cgs_device)
 952                 return effective_mode;
 953
 954         /* Skip limit attributes if DPM is not enabled */
 955         if (!adev->pm.dpm_enabled &&
 956             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 957              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 958              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 959              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 960              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 961              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 962                 return 0;
 963
 964         /* Skip fan attributes if fan is not present */
 965         if (adev->pm.no_fan &&
 966             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 967              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 968              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 969              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 970                 return 0;
 971
 972         /* mask fan attributes if we have no bindings for this asic to expose */
 973         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
 974              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 975             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
 976              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 977                 effective_mode &= ~S_IRUGO;
 978
 979         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
 980              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 981             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
 982              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 983                 effective_mode &= ~S_IWUSR;
 984
 985         /* hide max/min values if we can't both query and manage the fan */
 986         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
 987              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
 988             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 989              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 990                 return 0;
 991
 992         /* requires powerplay */
 993         if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
 994                 return 0;
 995
 996         return effective_mode;
 997 }
 998
 999 static const struct attribute_group hwmon_attrgroup = {
1000         .attrs = hwmon_attributes,
1001         .is_visible = hwmon_attributes_visible,
1002 };
1003
1004 static const struct attribute_group *hwmon_groups[] = {
1005         &hwmon_attrgroup,
1006         NULL
1007 };
1008
1009 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1010 {
1011         struct amdgpu_device *adev =
1012                 container_of(work, struct amdgpu_device,
1013                              pm.dpm.thermal.work);
1014         /* switch to the thermal state */
1015         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1016
1017         if (!adev->pm.dpm_enabled)
1018                 return;
1019
1020         if (adev->powerplay.pp_funcs->get_temperature) {
1021                 int temp = amdgpu_dpm_get_temperature(adev);
1022
1023                 if (temp < adev->pm.dpm.thermal.min_temp)
1024                         /* switch back the user state */
1025                         dpm_state = adev->pm.dpm.user_state;
1026         } else {
1027                 if (adev->pm.dpm.thermal.high_to_low)
1028                         /* switch back the user state */
1029                         dpm_state = adev->pm.dpm.user_state;
1030         }
1031         mutex_lock(&adev->pm.mutex);
1032         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1033                 adev->pm.dpm.thermal_active = true;
1034         else
1035                 adev->pm.dpm.thermal_active = false;
1036         adev->pm.dpm.state = dpm_state;
1037         mutex_unlock(&adev->pm.mutex);
1038
1039         amdgpu_pm_compute_clocks(adev);
1040 }
1041
1042 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1043                                                      enum amd_pm_state_type dpm_state)
1044 {
1045         int i;
1046         struct amdgpu_ps *ps;
1047         u32 ui_class;
1048         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1049                 true : false;
1050
1051         /* check if the vblank period is too short to adjust the mclk */
1052         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1053                 if (amdgpu_dpm_vblank_too_short(adev))
1054                         single_display = false;
1055         }
1056
1057         /* certain older asics have a separare 3D performance state,
1058          * so try that first if the user selected performance
1059          */
1060         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1061                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1062         /* balanced states don't exist at the moment */
1063         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1064                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1065
1066 restart_search:
1067         /* Pick the best power state based on current conditions */
1068         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1069                 ps = &adev->pm.dpm.ps[i];
1070                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1071                 switch (dpm_state) {
1072                 /* user states */
1073                 case POWER_STATE_TYPE_BATTERY:
1074                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1075                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1076                                         if (single_display)
1077                                                 return ps;
1078                                 } else
1079                                         return ps;
1080                         }
1081                         break;
1082                 case POWER_STATE_TYPE_BALANCED:
1083                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1084                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1085                                         if (single_display)
1086                                                 return ps;
1087                                 } else
1088                                         return ps;
1089                         }
1090                         break;
1091                 case POWER_STATE_TYPE_PERFORMANCE:
1092                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1093                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1094                                         if (single_display)
1095                                                 return ps;
1096                                 } else
1097                                         return ps;
1098                         }
1099                         break;
1100                 /* internal states */
1101                 case POWER_STATE_TYPE_INTERNAL_UVD:
1102                         if (adev->pm.dpm.uvd_ps)
1103                                 return adev->pm.dpm.uvd_ps;
1104                         else
1105                                 break;
1106                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1107                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1108                                 return ps;
1109                         break;
1110                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1111                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1112                                 return ps;
1113                         break;
1114                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1115                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1116                                 return ps;
1117                         break;
1118                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1119                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1120                                 return ps;
1121                         break;
1122                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1123                         return adev->pm.dpm.boot_ps;
1124                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1125                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1126                                 return ps;
1127                         break;
1128                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1129                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1130                                 return ps;
1131                         break;
1132                 case POWER_STATE_TYPE_INTERNAL_ULV:
1133                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1134                                 return ps;
1135                         break;
1136                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1137                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1138                                 return ps;
1139                         break;
1140                 default:
1141                         break;
1142                 }
1143         }
1144         /* use a fallback state if we didn't match */
1145         switch (dpm_state) {
1146         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1147                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1148                 goto restart_search;
1149         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1150         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1151         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1152                 if (adev->pm.dpm.uvd_ps) {
1153                         return adev->pm.dpm.uvd_ps;
1154                 } else {
1155                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1156                         goto restart_search;
1157                 }
1158         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1159                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1160                 goto restart_search;
1161         case POWER_STATE_TYPE_INTERNAL_ACPI:
1162                 dpm_state = POWER_STATE_TYPE_BATTERY;
1163                 goto restart_search;
1164         case POWER_STATE_TYPE_BATTERY:
1165         case POWER_STATE_TYPE_BALANCED:
1166         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1167                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1168                 goto restart_search;
1169         default:
1170                 break;
1171         }
1172
1173         return NULL;
1174 }
1175
1176 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1177 {
1178         struct amdgpu_ps *ps;
1179         enum amd_pm_state_type dpm_state;
1180         int ret;
1181         bool equal = false;
1182
1183         /* if dpm init failed */
1184         if (!adev->pm.dpm_enabled)
1185                 return;
1186
1187         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1188                 /* add other state override checks here */
1189                 if ((!adev->pm.dpm.thermal_active) &&
1190                     (!adev->pm.dpm.uvd_active))
1191                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1192         }
1193         dpm_state = adev->pm.dpm.state;
1194
1195         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1196         if (ps)
1197                 adev->pm.dpm.requested_ps = ps;
1198         else
1199                 return;
1200
1201         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1202                 printk("switching from power state:\n");
1203                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1204                 printk("switching to power state:\n");
1205                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1206         }
1207
1208         /* update whether vce is active */
1209         ps->vce_active = adev->pm.dpm.vce_active;
1210         if (adev->powerplay.pp_funcs->display_configuration_changed)
1211                 amdgpu_dpm_display_configuration_changed(adev);
1212
1213         ret = amdgpu_dpm_pre_set_power_state(adev);
1214         if (ret)
1215                 return;
1216
1217         if (adev->powerplay.pp_funcs->check_state_equal) {
1218                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1219                         equal = false;
1220         }
1221
1222         if (equal)
1223                 return;
1224
1225         amdgpu_dpm_set_power_state(adev);
1226         amdgpu_dpm_post_set_power_state(adev);
1227
1228         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1229         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1230
1231         if (adev->powerplay.pp_funcs->force_performance_level) {
1232                 if (adev->pm.dpm.thermal_active) {
1233                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1234                         /* force low perf level for thermal */
1235                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1236                         /* save the user's level */
1237                         adev->pm.dpm.forced_level = level;
1238                 } else {
1239                         /* otherwise, user selected level */
1240                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1241                 }
1242         }
1243 }
1244
1245 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1246 {
1247         if (adev->powerplay.pp_funcs->powergate_uvd) {
1248                 /* enable/disable UVD */
1249                 mutex_lock(&adev->pm.mutex);
1250                 amdgpu_dpm_powergate_uvd(adev, !enable);
1251                 mutex_unlock(&adev->pm.mutex);
1252         } else {
1253                 if (enable) {
1254                         mutex_lock(&adev->pm.mutex);
1255                         adev->pm.dpm.uvd_active = true;
1256                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1257                         mutex_unlock(&adev->pm.mutex);
1258                 } else {
1259                         mutex_lock(&adev->pm.mutex);
1260                         adev->pm.dpm.uvd_active = false;
1261                         mutex_unlock(&adev->pm.mutex);
1262                 }
1263                 amdgpu_pm_compute_clocks(adev);
1264         }
1265 }
1266
1267 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1268 {
1269         if (adev->powerplay.pp_funcs->powergate_vce) {
1270                 /* enable/disable VCE */
1271                 mutex_lock(&adev->pm.mutex);
1272                 amdgpu_dpm_powergate_vce(adev, !enable);
1273                 mutex_unlock(&adev->pm.mutex);
1274         } else {
1275                 if (enable) {
1276                         mutex_lock(&adev->pm.mutex);
1277                         adev->pm.dpm.vce_active = true;
1278                         /* XXX select vce level based on ring/task */
1279                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1280                         mutex_unlock(&adev->pm.mutex);
1281                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1282                                                                AMD_CG_STATE_UNGATE);
1283                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1284                                                                AMD_PG_STATE_UNGATE);
1285                         amdgpu_pm_compute_clocks(adev);
1286                 } else {
1287                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1288                                                                AMD_PG_STATE_GATE);
1289                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1290                                                                AMD_CG_STATE_GATE);
1291                         mutex_lock(&adev->pm.mutex);
1292                         adev->pm.dpm.vce_active = false;
1293                         mutex_unlock(&adev->pm.mutex);
1294                         amdgpu_pm_compute_clocks(adev);
1295                 }
1296
1297         }
1298 }
1299
1300 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1301 {
1302         int i;
1303
1304         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1305                 return;
1306
1307         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1308                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1309
1310 }
1311
1312 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1313 {
1314         int ret;
1315
1316         if (adev->pm.sysfs_initialized)
1317                 return 0;
1318
1319         if (adev->pm.dpm_enabled == 0)
1320                 return 0;
1321
1322         if (adev->powerplay.pp_funcs->get_temperature == NULL)
1323                 return 0;
1324
1325         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1326                                                                    DRIVER_NAME, adev,
1327                                                                    hwmon_groups);
1328         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1329                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1330                 dev_err(adev->dev,
1331                         "Unable to register hwmon device: %d\n", ret);
1332                 return ret;
1333         }
1334
1335         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1336         if (ret) {
1337                 DRM_ERROR("failed to create device file for dpm state\n");
1338                 return ret;
1339         }
1340         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1341         if (ret) {
1342                 DRM_ERROR("failed to create device file for dpm state\n");
1343                 return ret;
1344         }
1345
1346
1347         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1348         if (ret) {
1349                 DRM_ERROR("failed to create device file pp_num_states\n");
1350                 return ret;
1351         }
1352         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1353         if (ret) {
1354                 DRM_ERROR("failed to create device file pp_cur_state\n");
1355                 return ret;
1356         }
1357         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1358         if (ret) {
1359                 DRM_ERROR("failed to create device file pp_force_state\n");
1360                 return ret;
1361         }
1362         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1363         if (ret) {
1364                 DRM_ERROR("failed to create device file pp_table\n");
1365                 return ret;
1366         }
1367
1368         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1369         if (ret) {
1370                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1371                 return ret;
1372         }
1373         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1374         if (ret) {
1375                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1376                 return ret;
1377         }
1378         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1379         if (ret) {
1380                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1381                 return ret;
1382         }
1383         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1384         if (ret) {
1385                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1386                 return ret;
1387         }
1388         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1389         if (ret) {
1390                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1391                 return ret;
1392         }
1393         ret = device_create_file(adev->dev,
1394                         &dev_attr_pp_gfx_power_profile);
1395         if (ret) {
1396                 DRM_ERROR("failed to create device file "
1397                                 "pp_gfx_power_profile\n");
1398                 return ret;
1399         }
1400         ret = device_create_file(adev->dev,
1401                         &dev_attr_pp_compute_power_profile);
1402         if (ret) {
1403                 DRM_ERROR("failed to create device file "
1404                                 "pp_compute_power_profile\n");
1405                 return ret;
1406         }
1407
1408         ret = amdgpu_debugfs_pm_init(adev);
1409         if (ret) {
1410                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1411                 return ret;
1412         }
1413
1414         adev->pm.sysfs_initialized = true;
1415
1416         return 0;
1417 }
1418
1419 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1420 {
1421         if (adev->pm.dpm_enabled == 0)
1422                 return;
1423
1424         if (adev->pm.int_hwmon_dev)
1425                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1426         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1427         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1428
1429         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1430         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1431         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1432         device_remove_file(adev->dev, &dev_attr_pp_table);
1433
1434         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1435         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1436         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1437         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1438         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1439         device_remove_file(adev->dev,
1440                         &dev_attr_pp_gfx_power_profile);
1441         device_remove_file(adev->dev,
1442                         &dev_attr_pp_compute_power_profile);
1443 }
1444
1445 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1446 {
1447         struct drm_device *ddev = adev->ddev;
1448         struct drm_crtc *crtc;
1449         struct amdgpu_crtc *amdgpu_crtc;
1450         int i = 0;
1451
1452         if (!adev->pm.dpm_enabled)
1453                 return;
1454
1455         if (adev->mode_info.num_crtc)
1456                 amdgpu_display_bandwidth_update(adev);
1457
1458         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1459                 struct amdgpu_ring *ring = adev->rings[i];
1460                 if (ring && ring->ready)
1461                         amdgpu_fence_wait_empty(ring);
1462         }
1463
1464         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1465                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1466         } else {
1467                 mutex_lock(&adev->pm.mutex);
1468                 adev->pm.dpm.new_active_crtcs = 0;
1469                 adev->pm.dpm.new_active_crtc_count = 0;
1470                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1471                         list_for_each_entry(crtc,
1472                                             &ddev->mode_config.crtc_list, head) {
1473                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1474                                 if (amdgpu_crtc->enabled) {
1475                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1476                                         adev->pm.dpm.new_active_crtc_count++;
1477                                 }
1478                         }
1479                 }
1480                 /* update battery/ac status */
1481                 if (power_supply_is_system_supplied() > 0)
1482                         adev->pm.dpm.ac_power = true;
1483                 else
1484                         adev->pm.dpm.ac_power = false;
1485
1486                 amdgpu_dpm_change_power_state_locked(adev);
1487
1488                 mutex_unlock(&adev->pm.mutex);
1489         }
1490 }
1491
1492 /*
1493  * Debugfs info
1494  */
1495 #if defined(CONFIG_DEBUG_FS)
1496
1497 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1498 {
1499         uint32_t value;
1500         struct pp_gpu_power query = {0};
1501         int size;
1502
1503         /* sanity check PP is enabled */
1504         if (!(adev->powerplay.pp_funcs &&
1505               adev->powerplay.pp_funcs->read_sensor))
1506               return -EINVAL;
1507
1508         /* GPU Clocks */
1509         size = sizeof(value);
1510         seq_printf(m, "GFX Clocks and Power:\n");
1511         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1512                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1513         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1514                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1515         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1516                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1517         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1518                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1519         size = sizeof(query);
1520         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1521                 seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1522                                 query.vddc_power & 0xff);
1523                 seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1524                                 query.vddci_power & 0xff);
1525                 seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1526                                 query.max_gpu_power & 0xff);
1527                 seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1528                                 query.average_gpu_power & 0xff);
1529         }
1530         size = sizeof(value);
1531         seq_printf(m, "\n");
1532
1533         /* GPU Temp */
1534         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1535                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1536
1537         /* GPU Load */
1538         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1539                 seq_printf(m, "GPU Load: %u %%\n", value);
1540         seq_printf(m, "\n");
1541
1542         /* UVD clocks */
1543         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1544                 if (!value) {
1545                         seq_printf(m, "UVD: Disabled\n");
1546                 } else {
1547                         seq_printf(m, "UVD: Enabled\n");
1548                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1549                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1550                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1551                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1552                 }
1553         }
1554         seq_printf(m, "\n");
1555
1556         /* VCE clocks */
1557         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1558                 if (!value) {
1559                         seq_printf(m, "VCE: Disabled\n");
1560                 } else {
1561                         seq_printf(m, "VCE: Enabled\n");
1562                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1563                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1564                 }
1565         }
1566
1567         return 0;
1568 }
1569
1570 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1571 {
1572         int i;
1573
1574         for (i = 0; clocks[i].flag; i++)
1575                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1576                            (flags & clocks[i].flag) ? "On" : "Off");
1577 }
1578
1579 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1580 {
1581         struct drm_info_node *node = (struct drm_info_node *) m->private;
1582         struct drm_device *dev = node->minor->dev;
1583         struct amdgpu_device *adev = dev->dev_private;
1584         struct drm_device *ddev = adev->ddev;
1585         u32 flags = 0;
1586
1587         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1588         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1589         amdgpu_parse_cg_state(m, flags);
1590         seq_printf(m, "\n");
1591
1592         if (!adev->pm.dpm_enabled) {
1593                 seq_printf(m, "dpm not enabled\n");
1594                 return 0;
1595         }
1596         if  ((adev->flags & AMD_IS_PX) &&
1597              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1598                 seq_printf(m, "PX asic powered off\n");
1599         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1600                 mutex_lock(&adev->pm.mutex);
1601                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1602                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1603                 else
1604                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1605                 mutex_unlock(&adev->pm.mutex);
1606         } else {
1607                 return amdgpu_debugfs_pm_info_pp(m, adev);
1608         }
1609
1610         return 0;
1611 }
1612
1613 static const struct drm_info_list amdgpu_pm_info_list[] = {
1614         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1615 };
1616 #endif
1617
1618 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1619 {
1620 #if defined(CONFIG_DEBUG_FS)
1621         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1622 #else
1623         return 0;
1624 #endif
1625 }