drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  81                                     struct device_attribute *attr,
  82                                     char *buf)
  83 {
  84         struct drm_device *ddev = dev_get_drvdata(dev);
  85         struct amdgpu_device *adev = ddev->dev_private;
  86         enum amd_pm_state_type pm;
  87
  88         if (adev->powerplay.pp_funcs->get_current_power_state)
  89                 pm = amdgpu_dpm_get_current_power_state(adev);
  90         else
  91                 pm = adev->pm.dpm.user_state;
  92
  93         return snprintf(buf, PAGE_SIZE, "%s\n",
  94                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  95                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  96 }
  97
  98 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  99                                     struct device_attribute *attr,
 100                                     const char *buf,
 101                                     size_t count)
 102 {
 103         struct drm_device *ddev = dev_get_drvdata(dev);
 104         struct amdgpu_device *adev = ddev->dev_private;
 105         enum amd_pm_state_type  state;
 106
 107         if (strncmp("battery", buf, strlen("battery")) == 0)
 108                 state = POWER_STATE_TYPE_BATTERY;
 109         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 110                 state = POWER_STATE_TYPE_BALANCED;
 111         else if (strncmp("performance", buf, strlen("performance")) == 0)
 112                 state = POWER_STATE_TYPE_PERFORMANCE;
 113         else {
 114                 count = -EINVAL;
 115                 goto fail;
 116         }
 117
 118         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 119                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 120         } else {
 121                 mutex_lock(&adev->pm.mutex);
 122                 adev->pm.dpm.user_state = state;
 123                 mutex_unlock(&adev->pm.mutex);
 124
 125                 /* Can't set dpm state when the card is off */
 126                 if (!(adev->flags & AMD_IS_PX) ||
 127                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 128                         amdgpu_pm_compute_clocks(adev);
 129         }
 130 fail:
 131         return count;
 132 }
 133
 134
 135 /**
 136  * DOC: power_dpm_force_performance_level
 137  *
 138  * The amdgpu driver provides a sysfs API for adjusting certain power
 139  * related parameters.  The file power_dpm_force_performance_level is
 140  * used for this.  It accepts the following arguments:
 141  * - auto
 142  * - low
 143  * - high
 144  * - manual
 145  * - GPU fan
 146  * - profile_standard
 147  * - profile_min_sclk
 148  * - profile_min_mclk
 149  * - profile_peak
 150  *
 151  * auto
 152  *
 153  * When auto is selected, the driver will attempt to dynamically select
 154  * the optimal power profile for current conditions in the driver.
 155  *
 156  * low
 157  *
 158  * When low is selected, the clocks are forced to the lowest power state.
 159  *
 160  * high
 161  *
 162  * When high is selected, the clocks are forced to the highest power state.
 163  *
 164  * manual
 165  *
 166  * When manual is selected, the user can manually adjust which power states
 167  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 168  * and pp_dpm_pcie files and adjust the power state transition heuristics
 169  * via the pp_power_profile_mode sysfs file.
 170  *
 171  * profile_standard
 172  * profile_min_sclk
 173  * profile_min_mclk
 174  * profile_peak
 175  *
 176  * When the profiling modes are selected, clock and power gating are
 177  * disabled and the clocks are set for different profiling cases. This
 178  * mode is recommended for profiling specific work loads where you do
 179  * not want clock or power gating for clock fluctuation to interfere
 180  * with your results. profile_standard sets the clocks to a fixed clock
 181  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 182  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 183  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 184  *
 185  */
 186
 187 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 188                                                 struct device_attribute *attr,
 189                                                                 char *buf)
 190 {
 191         struct drm_device *ddev = dev_get_drvdata(dev);
 192         struct amdgpu_device *adev = ddev->dev_private;
 193         enum amd_dpm_forced_level level = 0xff;
 194
 195         if  ((adev->flags & AMD_IS_PX) &&
 196              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 197                 return snprintf(buf, PAGE_SIZE, "off\n");
 198
 199         if (adev->powerplay.pp_funcs->get_performance_level)
 200                 level = amdgpu_dpm_get_performance_level(adev);
 201         else
 202                 level = adev->pm.dpm.forced_level;
 203
 204         return snprintf(buf, PAGE_SIZE, "%s\n",
 205                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 206                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 207                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 208                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 209                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 210                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 211                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 212                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 213                         "unknown");
 214 }
 215
 216 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 217                                                        struct device_attribute *attr,
 218                                                        const char *buf,
 219                                                        size_t count)
 220 {
 221         struct drm_device *ddev = dev_get_drvdata(dev);
 222         struct amdgpu_device *adev = ddev->dev_private;
 223         enum amd_dpm_forced_level level;
 224         enum amd_dpm_forced_level current_level = 0xff;
 225         int ret = 0;
 226
 227         /* Can't force performance level when the card is off */
 228         if  ((adev->flags & AMD_IS_PX) &&
 229              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 230                 return -EINVAL;
 231
 232         if (adev->powerplay.pp_funcs->get_performance_level)
 233                 current_level = amdgpu_dpm_get_performance_level(adev);
 234
 235         if (strncmp("low", buf, strlen("low")) == 0) {
 236                 level = AMD_DPM_FORCED_LEVEL_LOW;
 237         } else if (strncmp("high", buf, strlen("high")) == 0) {
 238                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 239         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 240                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 241         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 242                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 243         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 244                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 245         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 246                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 247         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 248                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 249         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 250                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 251         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 252                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 253         }  else {
 254                 count = -EINVAL;
 255                 goto fail;
 256         }
 257
 258         if (current_level == level)
 259                 return count;
 260
 261         if (adev->powerplay.pp_funcs->force_performance_level) {
 262                 mutex_lock(&adev->pm.mutex);
 263                 if (adev->pm.dpm.thermal_active) {
 264                         count = -EINVAL;
 265                         mutex_unlock(&adev->pm.mutex);
 266                         goto fail;
 267                 }
 268                 ret = amdgpu_dpm_force_performance_level(adev, level);
 269                 if (ret)
 270                         count = -EINVAL;
 271                 else
 272                         adev->pm.dpm.forced_level = level;
 273                 mutex_unlock(&adev->pm.mutex);
 274         }
 275
 276 fail:
 277         return count;
 278 }
 279
 280 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 281                 struct device_attribute *attr,
 282                 char *buf)
 283 {
 284         struct drm_device *ddev = dev_get_drvdata(dev);
 285         struct amdgpu_device *adev = ddev->dev_private;
 286         struct pp_states_info data;
 287         int i, buf_len;
 288
 289         if (adev->powerplay.pp_funcs->get_pp_num_states)
 290                 amdgpu_dpm_get_pp_num_states(adev, &data);
 291
 292         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 293         for (i = 0; i < data.nums; i++)
 294                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 295                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 296                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 297                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 298                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 299
 300         return buf_len;
 301 }
 302
 303 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 304                 struct device_attribute *attr,
 305                 char *buf)
 306 {
 307         struct drm_device *ddev = dev_get_drvdata(dev);
 308         struct amdgpu_device *adev = ddev->dev_private;
 309         struct pp_states_info data;
 310         enum amd_pm_state_type pm = 0;
 311         int i = 0;
 312
 313         if (adev->powerplay.pp_funcs->get_current_power_state
 314                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 315                 pm = amdgpu_dpm_get_current_power_state(adev);
 316                 amdgpu_dpm_get_pp_num_states(adev, &data);
 317
 318                 for (i = 0; i < data.nums; i++) {
 319                         if (pm == data.states[i])
 320                                 break;
 321                 }
 322
 323                 if (i == data.nums)
 324                         i = -EINVAL;
 325         }
 326
 327         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 328 }
 329
 330 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 331                 struct device_attribute *attr,
 332                 char *buf)
 333 {
 334         struct drm_device *ddev = dev_get_drvdata(dev);
 335         struct amdgpu_device *adev = ddev->dev_private;
 336
 337         if (adev->pp_force_state_enabled)
 338                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 339         else
 340                 return snprintf(buf, PAGE_SIZE, "\n");
 341 }
 342
 343 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 344                 struct device_attribute *attr,
 345                 const char *buf,
 346                 size_t count)
 347 {
 348         struct drm_device *ddev = dev_get_drvdata(dev);
 349         struct amdgpu_device *adev = ddev->dev_private;
 350         enum amd_pm_state_type state = 0;
 351         unsigned long idx;
 352         int ret;
 353
 354         if (strlen(buf) == 1)
 355                 adev->pp_force_state_enabled = false;
 356         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 357                         adev->powerplay.pp_funcs->get_pp_num_states) {
 358                 struct pp_states_info data;
 359
 360                 ret = kstrtoul(buf, 0, &idx);
 361                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 362                         count = -EINVAL;
 363                         goto fail;
 364                 }
 365
 366                 amdgpu_dpm_get_pp_num_states(adev, &data);
 367                 state = data.states[idx];
 368                 /* only set user selected power states */
 369                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 370                     state != POWER_STATE_TYPE_DEFAULT) {
 371                         amdgpu_dpm_dispatch_task(adev,
 372                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 373                         adev->pp_force_state_enabled = true;
 374                 }
 375         }
 376 fail:
 377         return count;
 378 }
 379
 380 static ssize_t amdgpu_get_pp_table(struct device *dev,
 381                 struct device_attribute *attr,
 382                 char *buf)
 383 {
 384         struct drm_device *ddev = dev_get_drvdata(dev);
 385         struct amdgpu_device *adev = ddev->dev_private;
 386         char *table = NULL;
 387         int size;
 388
 389         if (adev->powerplay.pp_funcs->get_pp_table)
 390                 size = amdgpu_dpm_get_pp_table(adev, &table);
 391         else
 392                 return 0;
 393
 394         if (size >= PAGE_SIZE)
 395                 size = PAGE_SIZE - 1;
 396
 397         memcpy(buf, table, size);
 398
 399         return size;
 400 }
 401
 402 static ssize_t amdgpu_set_pp_table(struct device *dev,
 403                 struct device_attribute *attr,
 404                 const char *buf,
 405                 size_t count)
 406 {
 407         struct drm_device *ddev = dev_get_drvdata(dev);
 408         struct amdgpu_device *adev = ddev->dev_private;
 409
 410         if (adev->powerplay.pp_funcs->set_pp_table)
 411                 amdgpu_dpm_set_pp_table(adev, buf, count);
 412
 413         return count;
 414 }
 415
 416 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 417                 struct device_attribute *attr,
 418                 const char *buf,
 419                 size_t count)
 420 {
 421         struct drm_device *ddev = dev_get_drvdata(dev);
 422         struct amdgpu_device *adev = ddev->dev_private;
 423         int ret;
 424         uint32_t parameter_size = 0;
 425         long parameter[64];
 426         char buf_cpy[128];
 427         char *tmp_str;
 428         char *sub_str;
 429         const char delimiter[3] = {' ', '\n', '\0'};
 430         uint32_t type;
 431
 432         if (count > 127)
 433                 return -EINVAL;
 434
 435         if (*buf == 's')
 436                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 437         else if (*buf == 'm')
 438                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 439         else if(*buf == 'r')
 440                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 441         else if (*buf == 'c')
 442                 type = PP_OD_COMMIT_DPM_TABLE;
 443         else
 444                 return -EINVAL;
 445
 446         memcpy(buf_cpy, buf, count+1);
 447
 448         tmp_str = buf_cpy;
 449
 450         while (isspace(*++tmp_str));
 451
 452         while (tmp_str[0]) {
 453                 sub_str = strsep(&tmp_str, delimiter);
 454                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 455                 if (ret)
 456                         return -EINVAL;
 457                 parameter_size++;
 458
 459                 while (isspace(*tmp_str))
 460                         tmp_str++;
 461         }
 462
 463         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 464                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 465                                                 parameter, parameter_size);
 466
 467         if (ret)
 468                 return -EINVAL;
 469
 470         if (type == PP_OD_COMMIT_DPM_TABLE) {
 471                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 472                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 473                         return count;
 474                 } else {
 475                         return -EINVAL;
 476                 }
 477         }
 478
 479         return count;
 480 }
 481
 482 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 483                 struct device_attribute *attr,
 484                 char *buf)
 485 {
 486         struct drm_device *ddev = dev_get_drvdata(dev);
 487         struct amdgpu_device *adev = ddev->dev_private;
 488         uint32_t size = 0;
 489
 490         if (adev->powerplay.pp_funcs->print_clock_levels) {
 491                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 492                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 493                 return size;
 494         } else {
 495                 return snprintf(buf, PAGE_SIZE, "\n");
 496         }
 497
 498 }
 499
 500 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 501                 struct device_attribute *attr,
 502                 char *buf)
 503 {
 504         struct drm_device *ddev = dev_get_drvdata(dev);
 505         struct amdgpu_device *adev = ddev->dev_private;
 506
 507         if (adev->powerplay.pp_funcs->print_clock_levels)
 508                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 509         else
 510                 return snprintf(buf, PAGE_SIZE, "\n");
 511 }
 512
 513 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 514                 struct device_attribute *attr,
 515                 const char *buf,
 516                 size_t count)
 517 {
 518         struct drm_device *ddev = dev_get_drvdata(dev);
 519         struct amdgpu_device *adev = ddev->dev_private;
 520         int ret;
 521         long level;
 522         uint32_t i, mask = 0;
 523         char sub_str[2];
 524
 525         for (i = 0; i < strlen(buf); i++) {
 526                 if (*(buf + i) == '\n')
 527                         continue;
 528                 sub_str[0] = *(buf + i);
 529                 sub_str[1] = '\0';
 530                 ret = kstrtol(sub_str, 0, &level);
 531
 532                 if (ret) {
 533                         count = -EINVAL;
 534                         goto fail;
 535                 }
 536                 mask |= 1 << level;
 537         }
 538
 539         if (adev->powerplay.pp_funcs->force_clock_level)
 540                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 541
 542 fail:
 543         return count;
 544 }
 545
 546 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 547                 struct device_attribute *attr,
 548                 char *buf)
 549 {
 550         struct drm_device *ddev = dev_get_drvdata(dev);
 551         struct amdgpu_device *adev = ddev->dev_private;
 552
 553         if (adev->powerplay.pp_funcs->print_clock_levels)
 554                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 555         else
 556                 return snprintf(buf, PAGE_SIZE, "\n");
 557 }
 558
 559 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 560                 struct device_attribute *attr,
 561                 const char *buf,
 562                 size_t count)
 563 {
 564         struct drm_device *ddev = dev_get_drvdata(dev);
 565         struct amdgpu_device *adev = ddev->dev_private;
 566         int ret;
 567         long level;
 568         uint32_t i, mask = 0;
 569         char sub_str[2];
 570
 571         for (i = 0; i < strlen(buf); i++) {
 572                 if (*(buf + i) == '\n')
 573                         continue;
 574                 sub_str[0] = *(buf + i);
 575                 sub_str[1] = '\0';
 576                 ret = kstrtol(sub_str, 0, &level);
 577
 578                 if (ret) {
 579                         count = -EINVAL;
 580                         goto fail;
 581                 }
 582                 mask |= 1 << level;
 583         }
 584         if (adev->powerplay.pp_funcs->force_clock_level)
 585                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 586
 587 fail:
 588         return count;
 589 }
 590
 591 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 592                 struct device_attribute *attr,
 593                 char *buf)
 594 {
 595         struct drm_device *ddev = dev_get_drvdata(dev);
 596         struct amdgpu_device *adev = ddev->dev_private;
 597
 598         if (adev->powerplay.pp_funcs->print_clock_levels)
 599                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 600         else
 601                 return snprintf(buf, PAGE_SIZE, "\n");
 602 }
 603
 604 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 605                 struct device_attribute *attr,
 606                 const char *buf,
 607                 size_t count)
 608 {
 609         struct drm_device *ddev = dev_get_drvdata(dev);
 610         struct amdgpu_device *adev = ddev->dev_private;
 611         int ret;
 612         long level;
 613         uint32_t i, mask = 0;
 614         char sub_str[2];
 615
 616         for (i = 0; i < strlen(buf); i++) {
 617                 if (*(buf + i) == '\n')
 618                         continue;
 619                 sub_str[0] = *(buf + i);
 620                 sub_str[1] = '\0';
 621                 ret = kstrtol(sub_str, 0, &level);
 622
 623                 if (ret) {
 624                         count = -EINVAL;
 625                         goto fail;
 626                 }
 627                 mask |= 1 << level;
 628         }
 629         if (adev->powerplay.pp_funcs->force_clock_level)
 630                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 631
 632 fail:
 633         return count;
 634 }
 635
 636 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 637                 struct device_attribute *attr,
 638                 char *buf)
 639 {
 640         struct drm_device *ddev = dev_get_drvdata(dev);
 641         struct amdgpu_device *adev = ddev->dev_private;
 642         uint32_t value = 0;
 643
 644         if (adev->powerplay.pp_funcs->get_sclk_od)
 645                 value = amdgpu_dpm_get_sclk_od(adev);
 646
 647         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 648 }
 649
 650 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 651                 struct device_attribute *attr,
 652                 const char *buf,
 653                 size_t count)
 654 {
 655         struct drm_device *ddev = dev_get_drvdata(dev);
 656         struct amdgpu_device *adev = ddev->dev_private;
 657         int ret;
 658         long int value;
 659
 660         ret = kstrtol(buf, 0, &value);
 661
 662         if (ret) {
 663                 count = -EINVAL;
 664                 goto fail;
 665         }
 666         if (adev->powerplay.pp_funcs->set_sclk_od)
 667                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 668
 669         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 670                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 671         } else {
 672                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 673                 amdgpu_pm_compute_clocks(adev);
 674         }
 675
 676 fail:
 677         return count;
 678 }
 679
 680 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 681                 struct device_attribute *attr,
 682                 char *buf)
 683 {
 684         struct drm_device *ddev = dev_get_drvdata(dev);
 685         struct amdgpu_device *adev = ddev->dev_private;
 686         uint32_t value = 0;
 687
 688         if (adev->powerplay.pp_funcs->get_mclk_od)
 689                 value = amdgpu_dpm_get_mclk_od(adev);
 690
 691         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 692 }
 693
 694 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 695                 struct device_attribute *attr,
 696                 const char *buf,
 697                 size_t count)
 698 {
 699         struct drm_device *ddev = dev_get_drvdata(dev);
 700         struct amdgpu_device *adev = ddev->dev_private;
 701         int ret;
 702         long int value;
 703
 704         ret = kstrtol(buf, 0, &value);
 705
 706         if (ret) {
 707                 count = -EINVAL;
 708                 goto fail;
 709         }
 710         if (adev->powerplay.pp_funcs->set_mclk_od)
 711                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 712
 713         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 714                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 715         } else {
 716                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 717                 amdgpu_pm_compute_clocks(adev);
 718         }
 719
 720 fail:
 721         return count;
 722 }
 723
 724 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 725                 struct device_attribute *attr,
 726                 char *buf)
 727 {
 728         struct drm_device *ddev = dev_get_drvdata(dev);
 729         struct amdgpu_device *adev = ddev->dev_private;
 730
 731         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 732                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 733
 734         return snprintf(buf, PAGE_SIZE, "\n");
 735 }
 736
 737
 738 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 739                 struct device_attribute *attr,
 740                 const char *buf,
 741                 size_t count)
 742 {
 743         int ret = 0xff;
 744         struct drm_device *ddev = dev_get_drvdata(dev);
 745         struct amdgpu_device *adev = ddev->dev_private;
 746         uint32_t parameter_size = 0;
 747         long parameter[64];
 748         char *sub_str, buf_cpy[128];
 749         char *tmp_str;
 750         uint32_t i = 0;
 751         char tmp[2];
 752         long int profile_mode = 0;
 753         const char delimiter[3] = {' ', '\n', '\0'};
 754
 755         tmp[0] = *(buf);
 756         tmp[1] = '\0';
 757         ret = kstrtol(tmp, 0, &profile_mode);
 758         if (ret)
 759                 goto fail;
 760
 761         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 762                 if (count < 2 || count > 127)
 763                         return -EINVAL;
 764                 while (isspace(*++buf))
 765                         i++;
 766                 memcpy(buf_cpy, buf, count-i);
 767                 tmp_str = buf_cpy;
 768                 while (tmp_str[0]) {
 769                         sub_str = strsep(&tmp_str, delimiter);
 770                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 771                         if (ret) {
 772                                 count = -EINVAL;
 773                                 goto fail;
 774                         }
 775                         parameter_size++;
 776                         while (isspace(*tmp_str))
 777                                 tmp_str++;
 778                 }
 779         }
 780         parameter[parameter_size] = profile_mode;
 781         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 782                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 783
 784         if (!ret)
 785                 return count;
 786 fail:
 787         return -EINVAL;
 788 }
 789
 790 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 791 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 792                    amdgpu_get_dpm_forced_performance_level,
 793                    amdgpu_set_dpm_forced_performance_level);
 794 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 795 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 796 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 797                 amdgpu_get_pp_force_state,
 798                 amdgpu_set_pp_force_state);
 799 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 800                 amdgpu_get_pp_table,
 801                 amdgpu_set_pp_table);
 802 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 803                 amdgpu_get_pp_dpm_sclk,
 804                 amdgpu_set_pp_dpm_sclk);
 805 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 806                 amdgpu_get_pp_dpm_mclk,
 807                 amdgpu_set_pp_dpm_mclk);
 808 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 809                 amdgpu_get_pp_dpm_pcie,
 810                 amdgpu_set_pp_dpm_pcie);
 811 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 812                 amdgpu_get_pp_sclk_od,
 813                 amdgpu_set_pp_sclk_od);
 814 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 815                 amdgpu_get_pp_mclk_od,
 816                 amdgpu_set_pp_mclk_od);
 817 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 818                 amdgpu_get_pp_power_profile_mode,
 819                 amdgpu_set_pp_power_profile_mode);
 820 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 821                 amdgpu_get_pp_od_clk_voltage,
 822                 amdgpu_set_pp_od_clk_voltage);
 823
 824 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 825                                       struct device_attribute *attr,
 826                                       char *buf)
 827 {
 828         struct amdgpu_device *adev = dev_get_drvdata(dev);
 829         struct drm_device *ddev = adev->ddev;
 830         int r, temp, size = sizeof(temp);
 831
 832         /* Can't get temperature when the card is off */
 833         if  ((adev->flags & AMD_IS_PX) &&
 834              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 835                 return -EINVAL;
 836
 837         /* sanity check PP is enabled */
 838         if (!(adev->powerplay.pp_funcs &&
 839               adev->powerplay.pp_funcs->read_sensor))
 840                 return -EINVAL;
 841
 842         /* get the temperature */
 843         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 844                                    (void *)&temp, &size);
 845         if (r)
 846                 return r;
 847
 848         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 849 }
 850
 851 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 852                                              struct device_attribute *attr,
 853                                              char *buf)
 854 {
 855         struct amdgpu_device *adev = dev_get_drvdata(dev);
 856         int hyst = to_sensor_dev_attr(attr)->index;
 857         int temp;
 858
 859         if (hyst)
 860                 temp = adev->pm.dpm.thermal.min_temp;
 861         else
 862                 temp = adev->pm.dpm.thermal.max_temp;
 863
 864         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 865 }
 866
 867 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 868                                             struct device_attribute *attr,
 869                                             char *buf)
 870 {
 871         struct amdgpu_device *adev = dev_get_drvdata(dev);
 872         u32 pwm_mode = 0;
 873
 874         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 875                 return -EINVAL;
 876
 877         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 878
 879         return sprintf(buf, "%i\n", pwm_mode);
 880 }
 881
 882 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 883                                             struct device_attribute *attr,
 884                                             const char *buf,
 885                                             size_t count)
 886 {
 887         struct amdgpu_device *adev = dev_get_drvdata(dev);
 888         int err;
 889         int value;
 890
 891         /* Can't adjust fan when the card is off */
 892         if  ((adev->flags & AMD_IS_PX) &&
 893              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 894                 return -EINVAL;
 895
 896         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 897                 return -EINVAL;
 898
 899         err = kstrtoint(buf, 10, &value);
 900         if (err)
 901                 return err;
 902
 903         amdgpu_dpm_set_fan_control_mode(adev, value);
 904
 905         return count;
 906 }
 907
 908 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 909                                          struct device_attribute *attr,
 910                                          char *buf)
 911 {
 912         return sprintf(buf, "%i\n", 0);
 913 }
 914
 915 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 916                                          struct device_attribute *attr,
 917                                          char *buf)
 918 {
 919         return sprintf(buf, "%i\n", 255);
 920 }
 921
 922 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 923                                      struct device_attribute *attr,
 924                                      const char *buf, size_t count)
 925 {
 926         struct amdgpu_device *adev = dev_get_drvdata(dev);
 927         int err;
 928         u32 value;
 929
 930         /* Can't adjust fan when the card is off */
 931         if  ((adev->flags & AMD_IS_PX) &&
 932              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 933                 return -EINVAL;
 934
 935         err = kstrtou32(buf, 10, &value);
 936         if (err)
 937                 return err;
 938
 939         value = (value * 100) / 255;
 940
 941         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
 942                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 943                 if (err)
 944                         return err;
 945         }
 946
 947         return count;
 948 }
 949
 950 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 951                                      struct device_attribute *attr,
 952                                      char *buf)
 953 {
 954         struct amdgpu_device *adev = dev_get_drvdata(dev);
 955         int err;
 956         u32 speed = 0;
 957
 958         /* Can't adjust fan when the card is off */
 959         if  ((adev->flags & AMD_IS_PX) &&
 960              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 961                 return -EINVAL;
 962
 963         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
 964                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 965                 if (err)
 966                         return err;
 967         }
 968
 969         speed = (speed * 255) / 100;
 970
 971         return sprintf(buf, "%i\n", speed);
 972 }
 973
 974 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 975                                            struct device_attribute *attr,
 976                                            char *buf)
 977 {
 978         struct amdgpu_device *adev = dev_get_drvdata(dev);
 979         int err;
 980         u32 speed = 0;
 981
 982         /* Can't adjust fan when the card is off */
 983         if  ((adev->flags & AMD_IS_PX) &&
 984              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 985                 return -EINVAL;
 986
 987         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
 988                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 989                 if (err)
 990                         return err;
 991         }
 992
 993         return sprintf(buf, "%i\n", speed);
 994 }
 995
 996 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
 997                                         struct device_attribute *attr,
 998                                         char *buf)
 999 {
1000         struct amdgpu_device *adev = dev_get_drvdata(dev);
1001         struct drm_device *ddev = adev->ddev;
1002         u32 vddgfx;
1003         int r, size = sizeof(vddgfx);
1004
1005         /* Can't get voltage when the card is off */
1006         if  ((adev->flags & AMD_IS_PX) &&
1007              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1008                 return -EINVAL;
1009
1010         /* sanity check PP is enabled */
1011         if (!(adev->powerplay.pp_funcs &&
1012               adev->powerplay.pp_funcs->read_sensor))
1013               return -EINVAL;
1014
1015         /* get the voltage */
1016         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1017                                    (void *)&vddgfx, &size);
1018         if (r)
1019                 return r;
1020
1021         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1022 }
1023
1024 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1025                                               struct device_attribute *attr,
1026                                               char *buf)
1027 {
1028         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1029 }
1030
1031 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1032                                        struct device_attribute *attr,
1033                                        char *buf)
1034 {
1035         struct amdgpu_device *adev = dev_get_drvdata(dev);
1036         struct drm_device *ddev = adev->ddev;
1037         u32 vddnb;
1038         int r, size = sizeof(vddnb);
1039
1040         /* only APUs have vddnb */
1041         if  (adev->flags & AMD_IS_APU)
1042                 return -EINVAL;
1043
1044         /* Can't get voltage when the card is off */
1045         if  ((adev->flags & AMD_IS_PX) &&
1046              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1047                 return -EINVAL;
1048
1049         /* sanity check PP is enabled */
1050         if (!(adev->powerplay.pp_funcs &&
1051               adev->powerplay.pp_funcs->read_sensor))
1052               return -EINVAL;
1053
1054         /* get the voltage */
1055         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1056                                    (void *)&vddnb, &size);
1057         if (r)
1058                 return r;
1059
1060         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1061 }
1062
1063 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1064                                               struct device_attribute *attr,
1065                                               char *buf)
1066 {
1067         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1068 }
1069
1070 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1071                                            struct device_attribute *attr,
1072                                            char *buf)
1073 {
1074         struct amdgpu_device *adev = dev_get_drvdata(dev);
1075         struct drm_device *ddev = adev->ddev;
1076         u32 query = 0;
1077         int r, size = sizeof(u32);
1078         unsigned uw;
1079
1080         /* Can't get power when the card is off */
1081         if  ((adev->flags & AMD_IS_PX) &&
1082              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1083                 return -EINVAL;
1084
1085         /* sanity check PP is enabled */
1086         if (!(adev->powerplay.pp_funcs &&
1087               adev->powerplay.pp_funcs->read_sensor))
1088               return -EINVAL;
1089
1090         /* get the voltage */
1091         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1092                                    (void *)&query, &size);
1093         if (r)
1094                 return r;
1095
1096         /* convert to microwatts */
1097         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1098
1099         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1100 }
1101
1102 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1103                                          struct device_attribute *attr,
1104                                          char *buf)
1105 {
1106         return sprintf(buf, "%i\n", 0);
1107 }
1108
1109 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1110                                          struct device_attribute *attr,
1111                                          char *buf)
1112 {
1113         struct amdgpu_device *adev = dev_get_drvdata(dev);
1114         uint32_t limit = 0;
1115
1116         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1117                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1118                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1119         } else {
1120                 return snprintf(buf, PAGE_SIZE, "\n");
1121         }
1122 }
1123
1124 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1125                                          struct device_attribute *attr,
1126                                          char *buf)
1127 {
1128         struct amdgpu_device *adev = dev_get_drvdata(dev);
1129         uint32_t limit = 0;
1130
1131         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1132                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1133                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1134         } else {
1135                 return snprintf(buf, PAGE_SIZE, "\n");
1136         }
1137 }
1138
1139
1140 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1141                 struct device_attribute *attr,
1142                 const char *buf,
1143                 size_t count)
1144 {
1145         struct amdgpu_device *adev = dev_get_drvdata(dev);
1146         int err;
1147         u32 value;
1148
1149         err = kstrtou32(buf, 10, &value);
1150         if (err)
1151                 return err;
1152
1153         value = value / 1000000; /* convert to Watt */
1154         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1155                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1156                 if (err)
1157                         return err;
1158         } else {
1159                 return -EINVAL;
1160         }
1161
1162         return count;
1163 }
1164
1165
1166 /**
1167  * DOC: hwmon
1168  *
1169  * The amdgpu driver exposes the following sensor interfaces:
1170  * - GPU temperature (via the on-die sensor)
1171  * - GPU voltage
1172  * - Northbridge voltage (APUs only)
1173  * - GPU power
1174  * - GPU fan
1175  *
1176  * hwmon interfaces for GPU temperature:
1177  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1178  * - temp1_crit: temperature critical max value in millidegrees Celsius
1179  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1180  *
1181  * hwmon interfaces for GPU voltage:
1182  * - in0_input: the voltage on the GPU in millivolts
1183  * - in1_input: the voltage on the Northbridge in millivolts
1184  *
1185  * hwmon interfaces for GPU power:
1186  * - power1_average: average power used by the GPU in microWatts
1187  * - power1_cap_min: minimum cap supported in microWatts
1188  * - power1_cap_max: maximum cap supported in microWatts
1189  * - power1_cap: selected power cap in microWatts
1190  *
1191  * hwmon interfaces for GPU fan:
1192  * - pwm1: pulse width modulation fan level (0-255)
1193  * - pwm1_enable: pulse width modulation fan control method
1194  *                0: no fan speed control
1195  *                1: manual fan speed control using pwm interface
1196  *                2: automatic fan speed control
1197  * - pwm1_min: pulse width modulation fan control minimum level (0)
1198  * - pwm1_max: pulse width modulation fan control maximum level (255)
1199  * - fan1_input: fan speed in RPM
1200  *
1201  * You can use hwmon tools like sensors to view this information on your system.
1202  *
1203  */
1204
1205 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1206 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1207 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1208 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1209 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1210 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1211 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1212 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1213 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1214 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1215 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1216 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1217 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1218 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1219 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1220 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1221
1222 static struct attribute *hwmon_attributes[] = {
1223         &sensor_dev_attr_temp1_input.dev_attr.attr,
1224         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1225         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1226         &sensor_dev_attr_pwm1.dev_attr.attr,
1227         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1228         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1229         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1230         &sensor_dev_attr_fan1_input.dev_attr.attr,
1231         &sensor_dev_attr_in0_input.dev_attr.attr,
1232         &sensor_dev_attr_in0_label.dev_attr.attr,
1233         &sensor_dev_attr_in1_input.dev_attr.attr,
1234         &sensor_dev_attr_in1_label.dev_attr.attr,
1235         &sensor_dev_attr_power1_average.dev_attr.attr,
1236         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1237         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1238         &sensor_dev_attr_power1_cap.dev_attr.attr,
1239         NULL
1240 };
1241
1242 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1243                                         struct attribute *attr, int index)
1244 {
1245         struct device *dev = kobj_to_dev(kobj);
1246         struct amdgpu_device *adev = dev_get_drvdata(dev);
1247         umode_t effective_mode = attr->mode;
1248
1249         /* handle non-powerplay limitations */
1250         if (!adev->powerplay.pp_handle) {
1251                 /* Skip fan attributes if fan is not present */
1252                 if (adev->pm.no_fan &&
1253                     (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1254                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1255                      attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1256                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1257                         return 0;
1258                 /* requires powerplay */
1259                 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1260                         return 0;
1261         }
1262
1263         /* Skip limit attributes if DPM is not enabled */
1264         if (!adev->pm.dpm_enabled &&
1265             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1266              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1267              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1268              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1269              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1270              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1271                 return 0;
1272
1273         /* mask fan attributes if we have no bindings for this asic to expose */
1274         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1275              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1276             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1277              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1278                 effective_mode &= ~S_IRUGO;
1279
1280         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1281              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1282             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1283              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1284                 effective_mode &= ~S_IWUSR;
1285
1286         if ((adev->flags & AMD_IS_APU) &&
1287             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1288              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1289              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1290                 return 0;
1291
1292         /* hide max/min values if we can't both query and manage the fan */
1293         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1294              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1295             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1296              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1297                 return 0;
1298
1299         /* only APUs have vddnb */
1300         if (!(adev->flags & AMD_IS_APU) &&
1301             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1302              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1303                 return 0;
1304
1305         return effective_mode;
1306 }
1307
1308 static const struct attribute_group hwmon_attrgroup = {
1309         .attrs = hwmon_attributes,
1310         .is_visible = hwmon_attributes_visible,
1311 };
1312
1313 static const struct attribute_group *hwmon_groups[] = {
1314         &hwmon_attrgroup,
1315         NULL
1316 };
1317
1318 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1319 {
1320         struct amdgpu_device *adev =
1321                 container_of(work, struct amdgpu_device,
1322                              pm.dpm.thermal.work);
1323         /* switch to the thermal state */
1324         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1325         int temp, size = sizeof(temp);
1326
1327         if (!adev->pm.dpm_enabled)
1328                 return;
1329
1330         if (adev->powerplay.pp_funcs &&
1331             adev->powerplay.pp_funcs->read_sensor &&
1332             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1333                                     (void *)&temp, &size)) {
1334                 if (temp < adev->pm.dpm.thermal.min_temp)
1335                         /* switch back the user state */
1336                         dpm_state = adev->pm.dpm.user_state;
1337         } else {
1338                 if (adev->pm.dpm.thermal.high_to_low)
1339                         /* switch back the user state */
1340                         dpm_state = adev->pm.dpm.user_state;
1341         }
1342         mutex_lock(&adev->pm.mutex);
1343         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1344                 adev->pm.dpm.thermal_active = true;
1345         else
1346                 adev->pm.dpm.thermal_active = false;
1347         adev->pm.dpm.state = dpm_state;
1348         mutex_unlock(&adev->pm.mutex);
1349
1350         amdgpu_pm_compute_clocks(adev);
1351 }
1352
1353 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1354                                                      enum amd_pm_state_type dpm_state)
1355 {
1356         int i;
1357         struct amdgpu_ps *ps;
1358         u32 ui_class;
1359         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1360                 true : false;
1361
1362         /* check if the vblank period is too short to adjust the mclk */
1363         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1364                 if (amdgpu_dpm_vblank_too_short(adev))
1365                         single_display = false;
1366         }
1367
1368         /* certain older asics have a separare 3D performance state,
1369          * so try that first if the user selected performance
1370          */
1371         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1372                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1373         /* balanced states don't exist at the moment */
1374         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1375                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1376
1377 restart_search:
1378         /* Pick the best power state based on current conditions */
1379         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1380                 ps = &adev->pm.dpm.ps[i];
1381                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1382                 switch (dpm_state) {
1383                 /* user states */
1384                 case POWER_STATE_TYPE_BATTERY:
1385                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1386                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1387                                         if (single_display)
1388                                                 return ps;
1389                                 } else
1390                                         return ps;
1391                         }
1392                         break;
1393                 case POWER_STATE_TYPE_BALANCED:
1394                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1395                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1396                                         if (single_display)
1397                                                 return ps;
1398                                 } else
1399                                         return ps;
1400                         }
1401                         break;
1402                 case POWER_STATE_TYPE_PERFORMANCE:
1403                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1404                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1405                                         if (single_display)
1406                                                 return ps;
1407                                 } else
1408                                         return ps;
1409                         }
1410                         break;
1411                 /* internal states */
1412                 case POWER_STATE_TYPE_INTERNAL_UVD:
1413                         if (adev->pm.dpm.uvd_ps)
1414                                 return adev->pm.dpm.uvd_ps;
1415                         else
1416                                 break;
1417                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1418                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1419                                 return ps;
1420                         break;
1421                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1422                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1423                                 return ps;
1424                         break;
1425                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1426                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1427                                 return ps;
1428                         break;
1429                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1430                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1431                                 return ps;
1432                         break;
1433                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1434                         return adev->pm.dpm.boot_ps;
1435                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1436                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1437                                 return ps;
1438                         break;
1439                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1440                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1441                                 return ps;
1442                         break;
1443                 case POWER_STATE_TYPE_INTERNAL_ULV:
1444                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1445                                 return ps;
1446                         break;
1447                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1448                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1449                                 return ps;
1450                         break;
1451                 default:
1452                         break;
1453                 }
1454         }
1455         /* use a fallback state if we didn't match */
1456         switch (dpm_state) {
1457         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1458                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1459                 goto restart_search;
1460         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1461         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1462         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1463                 if (adev->pm.dpm.uvd_ps) {
1464                         return adev->pm.dpm.uvd_ps;
1465                 } else {
1466                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1467                         goto restart_search;
1468                 }
1469         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1470                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1471                 goto restart_search;
1472         case POWER_STATE_TYPE_INTERNAL_ACPI:
1473                 dpm_state = POWER_STATE_TYPE_BATTERY;
1474                 goto restart_search;
1475         case POWER_STATE_TYPE_BATTERY:
1476         case POWER_STATE_TYPE_BALANCED:
1477         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1478                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1479                 goto restart_search;
1480         default:
1481                 break;
1482         }
1483
1484         return NULL;
1485 }
1486
1487 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1488 {
1489         struct amdgpu_ps *ps;
1490         enum amd_pm_state_type dpm_state;
1491         int ret;
1492         bool equal = false;
1493
1494         /* if dpm init failed */
1495         if (!adev->pm.dpm_enabled)
1496                 return;
1497
1498         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1499                 /* add other state override checks here */
1500                 if ((!adev->pm.dpm.thermal_active) &&
1501                     (!adev->pm.dpm.uvd_active))
1502                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1503         }
1504         dpm_state = adev->pm.dpm.state;
1505
1506         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1507         if (ps)
1508                 adev->pm.dpm.requested_ps = ps;
1509         else
1510                 return;
1511
1512         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1513                 printk("switching from power state:\n");
1514                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1515                 printk("switching to power state:\n");
1516                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1517         }
1518
1519         /* update whether vce is active */
1520         ps->vce_active = adev->pm.dpm.vce_active;
1521         if (adev->powerplay.pp_funcs->display_configuration_changed)
1522                 amdgpu_dpm_display_configuration_changed(adev);
1523
1524         ret = amdgpu_dpm_pre_set_power_state(adev);
1525         if (ret)
1526                 return;
1527
1528         if (adev->powerplay.pp_funcs->check_state_equal) {
1529                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1530                         equal = false;
1531         }
1532
1533         if (equal)
1534                 return;
1535
1536         amdgpu_dpm_set_power_state(adev);
1537         amdgpu_dpm_post_set_power_state(adev);
1538
1539         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1540         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1541
1542         if (adev->powerplay.pp_funcs->force_performance_level) {
1543                 if (adev->pm.dpm.thermal_active) {
1544                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1545                         /* force low perf level for thermal */
1546                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1547                         /* save the user's level */
1548                         adev->pm.dpm.forced_level = level;
1549                 } else {
1550                         /* otherwise, user selected level */
1551                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1552                 }
1553         }
1554 }
1555
1556 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1557 {
1558         if (adev->powerplay.pp_funcs->powergate_uvd) {
1559                 /* enable/disable UVD */
1560                 mutex_lock(&adev->pm.mutex);
1561                 amdgpu_dpm_powergate_uvd(adev, !enable);
1562                 mutex_unlock(&adev->pm.mutex);
1563         } else {
1564                 if (enable) {
1565                         mutex_lock(&adev->pm.mutex);
1566                         adev->pm.dpm.uvd_active = true;
1567                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1568                         mutex_unlock(&adev->pm.mutex);
1569                 } else {
1570                         mutex_lock(&adev->pm.mutex);
1571                         adev->pm.dpm.uvd_active = false;
1572                         mutex_unlock(&adev->pm.mutex);
1573                 }
1574                 amdgpu_pm_compute_clocks(adev);
1575         }
1576 }
1577
1578 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1579 {
1580         if (adev->powerplay.pp_funcs->powergate_vce) {
1581                 /* enable/disable VCE */
1582                 mutex_lock(&adev->pm.mutex);
1583                 amdgpu_dpm_powergate_vce(adev, !enable);
1584                 mutex_unlock(&adev->pm.mutex);
1585         } else {
1586                 if (enable) {
1587                         mutex_lock(&adev->pm.mutex);
1588                         adev->pm.dpm.vce_active = true;
1589                         /* XXX select vce level based on ring/task */
1590                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1591                         mutex_unlock(&adev->pm.mutex);
1592                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1593                                                                AMD_CG_STATE_UNGATE);
1594                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1595                                                                AMD_PG_STATE_UNGATE);
1596                         amdgpu_pm_compute_clocks(adev);
1597                 } else {
1598                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1599                                                                AMD_PG_STATE_GATE);
1600                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1601                                                                AMD_CG_STATE_GATE);
1602                         mutex_lock(&adev->pm.mutex);
1603                         adev->pm.dpm.vce_active = false;
1604                         mutex_unlock(&adev->pm.mutex);
1605                         amdgpu_pm_compute_clocks(adev);
1606                 }
1607
1608         }
1609 }
1610
1611 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1612 {
1613         int i;
1614
1615         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1616                 return;
1617
1618         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1619                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1620
1621 }
1622
1623 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1624 {
1625         int ret;
1626
1627         if (adev->pm.sysfs_initialized)
1628                 return 0;
1629
1630         if (adev->pm.dpm_enabled == 0)
1631                 return 0;
1632
1633         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1634                                                                    DRIVER_NAME, adev,
1635                                                                    hwmon_groups);
1636         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1637                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1638                 dev_err(adev->dev,
1639                         "Unable to register hwmon device: %d\n", ret);
1640                 return ret;
1641         }
1642
1643         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1644         if (ret) {
1645                 DRM_ERROR("failed to create device file for dpm state\n");
1646                 return ret;
1647         }
1648         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1649         if (ret) {
1650                 DRM_ERROR("failed to create device file for dpm state\n");
1651                 return ret;
1652         }
1653
1654
1655         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1656         if (ret) {
1657                 DRM_ERROR("failed to create device file pp_num_states\n");
1658                 return ret;
1659         }
1660         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1661         if (ret) {
1662                 DRM_ERROR("failed to create device file pp_cur_state\n");
1663                 return ret;
1664         }
1665         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1666         if (ret) {
1667                 DRM_ERROR("failed to create device file pp_force_state\n");
1668                 return ret;
1669         }
1670         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1671         if (ret) {
1672                 DRM_ERROR("failed to create device file pp_table\n");
1673                 return ret;
1674         }
1675
1676         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1677         if (ret) {
1678                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1679                 return ret;
1680         }
1681         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1682         if (ret) {
1683                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1684                 return ret;
1685         }
1686         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1687         if (ret) {
1688                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1689                 return ret;
1690         }
1691         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1692         if (ret) {
1693                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1694                 return ret;
1695         }
1696         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1697         if (ret) {
1698                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1699                 return ret;
1700         }
1701         ret = device_create_file(adev->dev,
1702                         &dev_attr_pp_power_profile_mode);
1703         if (ret) {
1704                 DRM_ERROR("failed to create device file "
1705                                 "pp_power_profile_mode\n");
1706                 return ret;
1707         }
1708         ret = device_create_file(adev->dev,
1709                         &dev_attr_pp_od_clk_voltage);
1710         if (ret) {
1711                 DRM_ERROR("failed to create device file "
1712                                 "pp_od_clk_voltage\n");
1713                 return ret;
1714         }
1715         ret = amdgpu_debugfs_pm_init(adev);
1716         if (ret) {
1717                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1718                 return ret;
1719         }
1720
1721         adev->pm.sysfs_initialized = true;
1722
1723         return 0;
1724 }
1725
1726 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1727 {
1728         if (adev->pm.dpm_enabled == 0)
1729                 return;
1730
1731         if (adev->pm.int_hwmon_dev)
1732                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1733         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1734         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1735
1736         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1737         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1738         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1739         device_remove_file(adev->dev, &dev_attr_pp_table);
1740
1741         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1742         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1743         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1744         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1745         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1746         device_remove_file(adev->dev,
1747                         &dev_attr_pp_power_profile_mode);
1748         device_remove_file(adev->dev,
1749                         &dev_attr_pp_od_clk_voltage);
1750 }
1751
1752 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1753 {
1754         int i = 0;
1755
1756         if (!adev->pm.dpm_enabled)
1757                 return;
1758
1759         if (adev->mode_info.num_crtc)
1760                 amdgpu_display_bandwidth_update(adev);
1761
1762         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1763                 struct amdgpu_ring *ring = adev->rings[i];
1764                 if (ring && ring->ready)
1765                         amdgpu_fence_wait_empty(ring);
1766         }
1767
1768         if (!amdgpu_device_has_dc_support(adev)) {
1769                 mutex_lock(&adev->pm.mutex);
1770                 amdgpu_dpm_get_active_displays(adev);
1771                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1772                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1773                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1774                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1775                 if (adev->pm.pm_display_cfg.vrefresh > 120)
1776                         adev->pm.pm_display_cfg.min_vblank_time = 0;
1777                 if (adev->powerplay.pp_funcs->display_configuration_change)
1778                         adev->powerplay.pp_funcs->display_configuration_change(
1779                                                         adev->powerplay.pp_handle,
1780                                                         &adev->pm.pm_display_cfg);
1781                 mutex_unlock(&adev->pm.mutex);
1782         }
1783
1784         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1785                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1786         } else {
1787                 mutex_lock(&adev->pm.mutex);
1788                 /* update battery/ac status */
1789                 if (power_supply_is_system_supplied() > 0)
1790                         adev->pm.dpm.ac_power = true;
1791                 else
1792                         adev->pm.dpm.ac_power = false;
1793
1794                 amdgpu_dpm_change_power_state_locked(adev);
1795
1796                 mutex_unlock(&adev->pm.mutex);
1797         }
1798 }
1799
1800 /*
1801  * Debugfs info
1802  */
1803 #if defined(CONFIG_DEBUG_FS)
1804
1805 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1806 {
1807         uint32_t value;
1808         uint32_t query = 0;
1809         int size;
1810
1811         /* sanity check PP is enabled */
1812         if (!(adev->powerplay.pp_funcs &&
1813               adev->powerplay.pp_funcs->read_sensor))
1814               return -EINVAL;
1815
1816         /* GPU Clocks */
1817         size = sizeof(value);
1818         seq_printf(m, "GFX Clocks and Power:\n");
1819         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1820                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1821         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1822                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1823         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1824                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1825         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1826                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1827         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1828                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1829         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1830                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1831         size = sizeof(uint32_t);
1832         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1833                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1834         size = sizeof(value);
1835         seq_printf(m, "\n");
1836
1837         /* GPU Temp */
1838         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1839                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1840
1841         /* GPU Load */
1842         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1843                 seq_printf(m, "GPU Load: %u %%\n", value);
1844         seq_printf(m, "\n");
1845
1846         /* UVD clocks */
1847         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1848                 if (!value) {
1849                         seq_printf(m, "UVD: Disabled\n");
1850                 } else {
1851                         seq_printf(m, "UVD: Enabled\n");
1852                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1853                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1854                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1855                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1856                 }
1857         }
1858         seq_printf(m, "\n");
1859
1860         /* VCE clocks */
1861         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1862                 if (!value) {
1863                         seq_printf(m, "VCE: Disabled\n");
1864                 } else {
1865                         seq_printf(m, "VCE: Enabled\n");
1866                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1867                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1868                 }
1869         }
1870
1871         return 0;
1872 }
1873
1874 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1875 {
1876         int i;
1877
1878         for (i = 0; clocks[i].flag; i++)
1879                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1880                            (flags & clocks[i].flag) ? "On" : "Off");
1881 }
1882
1883 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1884 {
1885         struct drm_info_node *node = (struct drm_info_node *) m->private;
1886         struct drm_device *dev = node->minor->dev;
1887         struct amdgpu_device *adev = dev->dev_private;
1888         struct drm_device *ddev = adev->ddev;
1889         u32 flags = 0;
1890
1891         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1892         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1893         amdgpu_parse_cg_state(m, flags);
1894         seq_printf(m, "\n");
1895
1896         if (!adev->pm.dpm_enabled) {
1897                 seq_printf(m, "dpm not enabled\n");
1898                 return 0;
1899         }
1900         if  ((adev->flags & AMD_IS_PX) &&
1901              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1902                 seq_printf(m, "PX asic powered off\n");
1903         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1904                 mutex_lock(&adev->pm.mutex);
1905                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1906                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1907                 else
1908                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1909                 mutex_unlock(&adev->pm.mutex);
1910         } else {
1911                 return amdgpu_debugfs_pm_info_pp(m, adev);
1912         }
1913
1914         return 0;
1915 }
1916
1917 static const struct drm_info_list amdgpu_pm_info_list[] = {
1918         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1919 };
1920 #endif
1921
1922 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1923 {
1924 #if defined(CONFIG_DEBUG_FS)
1925         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1926 #else
1927         return 0;
1928 #endif
1929 }