drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/debugfs.h>
  34 #include <linux/highmem.h>
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/errno.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-mapping.h>
  40 #include <linux/slab.h>
  41 #include <linux/bitmap.h>
  42 #if defined(CONFIG_X86)
  43 #include <asm/pat.h>
  44 #endif
  45 #include <linux/sched.h>
  46 #include <linux/sched/mm.h>
  47 #include <linux/sched/task.h>
  48 #include <linux/delay.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <rdma/ib_addr.h>
  51 #include <rdma/ib_cache.h>
  52 #include <linux/mlx5/port.h>
  53 #include <linux/mlx5/vport.h>
  54 #include <linux/mlx5/fs.h>
  55 #include <linux/mlx5/eswitch.h>
  56 #include <linux/list.h>
  57 #include <rdma/ib_smi.h>
  58 #include <rdma/ib_umem.h>
  59 #include <linux/in.h>
  60 #include <linux/etherdevice.h>
  61 #include "mlx5_ib.h"
  62 #include "ib_rep.h"
  63 #include "cmd.h"
  64 #include "srq.h"
  65 #include <linux/mlx5/fs_helpers.h>
  66 #include <linux/mlx5/accel.h>
  67 #include <rdma/uverbs_std_types.h>
  68 #include <rdma/mlx5_user_ioctl_verbs.h>
  69 #include <rdma/mlx5_user_ioctl_cmds.h>
  70
  71 #define UVERBS_MODULE_NAME mlx5_ib
  72 #include <rdma/uverbs_named_ioctl.h>
  73
  74 #define DRIVER_NAME "mlx5_ib"
  75 #define DRIVER_VERSION "5.0-0"
  76
  77 MODULE_AUTHOR("Eli Cohen <[email protected]>");
  78 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  79 MODULE_LICENSE("Dual BSD/GPL");
  80
  81 static char mlx5_version[] =
  82         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  83         DRIVER_VERSION "\n";
  84
  85 struct mlx5_ib_event_work {
  86         struct work_struct      work;
  87         union {
  88                 struct mlx5_ib_dev            *dev;
  89                 struct mlx5_ib_multiport_info *mpi;
  90         };
  91         bool                    is_slave;
  92         unsigned int            event;
  93         void                    *param;
  94 };
  95
  96 enum {
  97         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  98 };
  99
 100 static struct workqueue_struct *mlx5_ib_event_wq;
 101 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
 102 static LIST_HEAD(mlx5_ib_dev_list);
 103 /*
 104  * This mutex should be held when accessing either of the above lists
 105  */
 106 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
 107
 108 /* We can't use an array for xlt_emergency_page because dma_map_single
 109  * doesn't work on kernel modules memory
 110  */
 111 static unsigned long xlt_emergency_page;
 112 static struct mutex xlt_emergency_page_mutex;
 113
 114 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
 115 {
 116         struct mlx5_ib_dev *dev;
 117
 118         mutex_lock(&mlx5_ib_multiport_mutex);
 119         dev = mpi->ibdev;
 120         mutex_unlock(&mlx5_ib_multiport_mutex);
 121         return dev;
 122 }
 123
 124 static enum rdma_link_layer
 125 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
 126 {
 127         switch (port_type_cap) {
 128         case MLX5_CAP_PORT_TYPE_IB:
 129                 return IB_LINK_LAYER_INFINIBAND;
 130         case MLX5_CAP_PORT_TYPE_ETH:
 131                 return IB_LINK_LAYER_ETHERNET;
 132         default:
 133                 return IB_LINK_LAYER_UNSPECIFIED;
 134         }
 135 }
 136
 137 static enum rdma_link_layer
 138 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
 139 {
 140         struct mlx5_ib_dev *dev = to_mdev(device);
 141         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
 142
 143         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
 144 }
 145
 146 static int get_port_state(struct ib_device *ibdev,
 147                           u8 port_num,
 148                           enum ib_port_state *state)
 149 {
 150         struct ib_port_attr attr;
 151         int ret;
 152
 153         memset(&attr, 0, sizeof(attr));
 154         ret = ibdev->ops.query_port(ibdev, port_num, &attr);
 155         if (!ret)
 156                 *state = attr.state;
 157         return ret;
 158 }
 159
 160 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
 161                                            struct net_device *ndev,
 162                                            u8 *port_num)
 163 {
 164         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
 165         struct net_device *rep_ndev;
 166         struct mlx5_ib_port *port;
 167         int i;
 168
 169         for (i = 0; i < dev->num_ports; i++) {
 170                 port  = &dev->port[i];
 171                 if (!port->rep)
 172                         continue;
 173
 174                 read_lock(&port->roce.netdev_lock);
 175                 rep_ndev = mlx5_ib_get_rep_netdev(esw,
 176                                                   port->rep->vport);
 177                 if (rep_ndev == ndev) {
 178                         read_unlock(&port->roce.netdev_lock);
 179                         *port_num = i + 1;
 180                         return &port->roce;
 181                 }
 182                 read_unlock(&port->roce.netdev_lock);
 183         }
 184
 185         return NULL;
 186 }
 187
 188 static int mlx5_netdev_event(struct notifier_block *this,
 189                              unsigned long event, void *ptr)
 190 {
 191         struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
 192         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 193         u8 port_num = roce->native_port_num;
 194         struct mlx5_core_dev *mdev;
 195         struct mlx5_ib_dev *ibdev;
 196
 197         ibdev = roce->dev;
 198         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 199         if (!mdev)
 200                 return NOTIFY_DONE;
 201
 202         switch (event) {
 203         case NETDEV_REGISTER:
 204                 /* Should already be registered during the load */
 205                 if (ibdev->is_rep)
 206                         break;
 207                 write_lock(&roce->netdev_lock);
 208                 if (ndev->dev.parent == mdev->device)
 209                         roce->netdev = ndev;
 210                 write_unlock(&roce->netdev_lock);
 211                 break;
 212
 213         case NETDEV_UNREGISTER:
 214                 /* In case of reps, ib device goes away before the netdevs */
 215                 write_lock(&roce->netdev_lock);
 216                 if (roce->netdev == ndev)
 217                         roce->netdev = NULL;
 218                 write_unlock(&roce->netdev_lock);
 219                 break;
 220
 221         case NETDEV_CHANGE:
 222         case NETDEV_UP:
 223         case NETDEV_DOWN: {
 224                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
 225                 struct net_device *upper = NULL;
 226
 227                 if (lag_ndev) {
 228                         upper = netdev_master_upper_dev_get(lag_ndev);
 229                         dev_put(lag_ndev);
 230                 }
 231
 232                 if (ibdev->is_rep)
 233                         roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
 234                 if (!roce)
 235                         return NOTIFY_DONE;
 236                 if ((upper == ndev || (!upper && ndev == roce->netdev))
 237                     && ibdev->ib_active) {
 238                         struct ib_event ibev = { };
 239                         enum ib_port_state port_state;
 240
 241                         if (get_port_state(&ibdev->ib_dev, port_num,
 242                                            &port_state))
 243                                 goto done;
 244
 245                         if (roce->last_port_state == port_state)
 246                                 goto done;
 247
 248                         roce->last_port_state = port_state;
 249                         ibev.device = &ibdev->ib_dev;
 250                         if (port_state == IB_PORT_DOWN)
 251                                 ibev.event = IB_EVENT_PORT_ERR;
 252                         else if (port_state == IB_PORT_ACTIVE)
 253                                 ibev.event = IB_EVENT_PORT_ACTIVE;
 254                         else
 255                                 goto done;
 256
 257                         ibev.element.port_num = port_num;
 258                         ib_dispatch_event(&ibev);
 259                 }
 260                 break;
 261         }
 262
 263         default:
 264                 break;
 265         }
 266 done:
 267         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 268         return NOTIFY_DONE;
 269 }
 270
 271 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 272                                              u8 port_num)
 273 {
 274         struct mlx5_ib_dev *ibdev = to_mdev(device);
 275         struct net_device *ndev;
 276         struct mlx5_core_dev *mdev;
 277
 278         mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
 279         if (!mdev)
 280                 return NULL;
 281
 282         ndev = mlx5_lag_get_roce_netdev(mdev);
 283         if (ndev)
 284                 goto out;
 285
 286         /* Ensure ndev does not disappear before we invoke dev_hold()
 287          */
 288         read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
 289         ndev = ibdev->port[port_num - 1].roce.netdev;
 290         if (ndev)
 291                 dev_hold(ndev);
 292         read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
 293
 294 out:
 295         mlx5_ib_put_native_port_mdev(ibdev, port_num);
 296         return ndev;
 297 }
 298
 299 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
 300                                                    u8 ib_port_num,
 301                                                    u8 *native_port_num)
 302 {
 303         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 304                                                           ib_port_num);
 305         struct mlx5_core_dev *mdev = NULL;
 306         struct mlx5_ib_multiport_info *mpi;
 307         struct mlx5_ib_port *port;
 308
 309         if (!mlx5_core_mp_enabled(ibdev->mdev) ||
 310             ll != IB_LINK_LAYER_ETHERNET) {
 311                 if (native_port_num)
 312                         *native_port_num = ib_port_num;
 313                 return ibdev->mdev;
 314         }
 315
 316         if (native_port_num)
 317                 *native_port_num = 1;
 318
 319         port = &ibdev->port[ib_port_num - 1];
 320         if (!port)
 321                 return NULL;
 322
 323         spin_lock(&port->mp.mpi_lock);
 324         mpi = ibdev->port[ib_port_num - 1].mp.mpi;
 325         if (mpi && !mpi->unaffiliate) {
 326                 mdev = mpi->mdev;
 327                 /* If it's the master no need to refcount, it'll exist
 328                  * as long as the ib_dev exists.
 329                  */
 330                 if (!mpi->is_master)
 331                         mpi->mdev_refcnt++;
 332         }
 333         spin_unlock(&port->mp.mpi_lock);
 334
 335         return mdev;
 336 }
 337
 338 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
 339 {
 340         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
 341                                                           port_num);
 342         struct mlx5_ib_multiport_info *mpi;
 343         struct mlx5_ib_port *port;
 344
 345         if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
 346                 return;
 347
 348         port = &ibdev->port[port_num - 1];
 349
 350         spin_lock(&port->mp.mpi_lock);
 351         mpi = ibdev->port[port_num - 1].mp.mpi;
 352         if (mpi->is_master)
 353                 goto out;
 354
 355         mpi->mdev_refcnt--;
 356         if (mpi->unaffiliate)
 357                 complete(&mpi->unref_comp);
 358 out:
 359         spin_unlock(&port->mp.mpi_lock);
 360 }
 361
 362 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 363                                            u8 *active_width)
 364 {
 365         switch (eth_proto_oper) {
 366         case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
 367         case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
 368         case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
 369         case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
 370                 *active_width = IB_WIDTH_1X;
 371                 *active_speed = IB_SPEED_SDR;
 372                 break;
 373         case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
 374         case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
 375         case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
 376         case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
 377         case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
 378         case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
 379         case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
 380                 *active_width = IB_WIDTH_1X;
 381                 *active_speed = IB_SPEED_QDR;
 382                 break;
 383         case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
 384         case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
 385         case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
 386                 *active_width = IB_WIDTH_1X;
 387                 *active_speed = IB_SPEED_EDR;
 388                 break;
 389         case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
 390         case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
 391         case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
 392         case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
 393                 *active_width = IB_WIDTH_4X;
 394                 *active_speed = IB_SPEED_QDR;
 395                 break;
 396         case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
 397         case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
 398         case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
 399                 *active_width = IB_WIDTH_1X;
 400                 *active_speed = IB_SPEED_HDR;
 401                 break;
 402         case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
 403                 *active_width = IB_WIDTH_4X;
 404                 *active_speed = IB_SPEED_FDR;
 405                 break;
 406         case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
 407         case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
 408         case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
 409         case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
 410                 *active_width = IB_WIDTH_4X;
 411                 *active_speed = IB_SPEED_EDR;
 412                 break;
 413         default:
 414                 return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 421                                         u8 *active_width)
 422 {
 423         switch (eth_proto_oper) {
 424         case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
 425         case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
 426                 *active_width = IB_WIDTH_1X;
 427                 *active_speed = IB_SPEED_SDR;
 428                 break;
 429         case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
 430                 *active_width = IB_WIDTH_1X;
 431                 *active_speed = IB_SPEED_DDR;
 432                 break;
 433         case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
 434                 *active_width = IB_WIDTH_1X;
 435                 *active_speed = IB_SPEED_QDR;
 436                 break;
 437         case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
 438                 *active_width = IB_WIDTH_4X;
 439                 *active_speed = IB_SPEED_QDR;
 440                 break;
 441         case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
 442                 *active_width = IB_WIDTH_1X;
 443                 *active_speed = IB_SPEED_EDR;
 444                 break;
 445         case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
 446                 *active_width = IB_WIDTH_2X;
 447                 *active_speed = IB_SPEED_EDR;
 448                 break;
 449         case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
 450                 *active_width = IB_WIDTH_1X;
 451                 *active_speed = IB_SPEED_HDR;
 452                 break;
 453         case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
 454                 *active_width = IB_WIDTH_4X;
 455                 *active_speed = IB_SPEED_EDR;
 456                 break;
 457         case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
 458                 *active_width = IB_WIDTH_2X;
 459                 *active_speed = IB_SPEED_HDR;
 460                 break;
 461         case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
 462                 *active_width = IB_WIDTH_4X;
 463                 *active_speed = IB_SPEED_HDR;
 464                 break;
 465         default:
 466                 return -EINVAL;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
 473                                     u8 *active_width, bool ext)
 474 {
 475         return ext ?
 476                 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
 477                                              active_width) :
 478                 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
 479                                                 active_width);
 480 }
 481
 482 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 483                                 struct ib_port_attr *props)
 484 {
 485         struct mlx5_ib_dev *dev = to_mdev(device);
 486         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 487         struct mlx5_core_dev *mdev;
 488         struct net_device *ndev, *upper;
 489         enum ib_mtu ndev_ib_mtu;
 490         bool put_mdev = true;
 491         u16 qkey_viol_cntr;
 492         u32 eth_prot_oper;
 493         u8 mdev_port_num;
 494         bool ext;
 495         int err;
 496
 497         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
 498         if (!mdev) {
 499                 /* This means the port isn't affiliated yet. Get the
 500                  * info for the master port instead.
 501                  */
 502                 put_mdev = false;
 503                 mdev = dev->mdev;
 504                 mdev_port_num = 1;
 505                 port_num = 1;
 506         }
 507
 508         /* Possible bad flows are checked before filling out props so in case
 509          * of an error it will still be zeroed out.
 510          * Use native port in case of reps
 511          */
 512         if (dev->is_rep)
 513                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 514                                            1);
 515         else
 516                 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
 517                                            mdev_port_num);
 518         if (err)
 519                 goto out;
 520         ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet);
 521         eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
 522
 523         props->active_width     = IB_WIDTH_4X;
 524         props->active_speed     = IB_SPEED_QDR;
 525
 526         translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
 527                                  &props->active_width, ext);
 528
 529         props->port_cap_flags |= IB_PORT_CM_SUP;
 530         props->ip_gids = true;
 531
 532         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 533                                                 roce_address_table_size);
 534         props->max_mtu          = IB_MTU_4096;
 535         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 536         props->pkey_tbl_len     = 1;
 537         props->state            = IB_PORT_DOWN;
 538         props->phys_state       = 3;
 539
 540         mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
 541         props->qkey_viol_cntr = qkey_viol_cntr;
 542
 543         /* If this is a stub query for an unaffiliated port stop here */
 544         if (!put_mdev)
 545                 goto out;
 546
 547         ndev = mlx5_ib_get_netdev(device, port_num);
 548         if (!ndev)
 549                 goto out;
 550
 551         if (dev->lag_active) {
 552                 rcu_read_lock();
 553                 upper = netdev_master_upper_dev_get_rcu(ndev);
 554                 if (upper) {
 555                         dev_put(ndev);
 556                         ndev = upper;
 557                         dev_hold(ndev);
 558                 }
 559                 rcu_read_unlock();
 560         }
 561
 562         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 563                 props->state      = IB_PORT_ACTIVE;
 564                 props->phys_state = 5;
 565         }
 566
 567         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 568
 569         dev_put(ndev);
 570
 571         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 572 out:
 573         if (put_mdev)
 574                 mlx5_ib_put_native_port_mdev(dev, port_num);
 575         return err;
 576 }
 577
 578 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
 579                          unsigned int index, const union ib_gid *gid,
 580                          const struct ib_gid_attr *attr)
 581 {
 582         enum ib_gid_type gid_type = IB_GID_TYPE_IB;
 583         u16 vlan_id = 0xffff;
 584         u8 roce_version = 0;
 585         u8 roce_l3_type = 0;
 586         u8 mac[ETH_ALEN];
 587         int ret;
 588
 589         if (gid) {
 590                 gid_type = attr->gid_type;
 591                 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
 592                 if (ret)
 593                         return ret;
 594         }
 595
 596         switch (gid_type) {
 597         case IB_GID_TYPE_IB:
 598                 roce_version = MLX5_ROCE_VERSION_1;
 599                 break;
 600         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 601                 roce_version = MLX5_ROCE_VERSION_2;
 602                 if (ipv6_addr_v4mapped((void *)gid))
 603                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
 604                 else
 605                         roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
 606                 break;
 607
 608         default:
 609                 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
 610         }
 611
 612         return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
 613                                       roce_l3_type, gid->raw, mac,
 614                                       vlan_id < VLAN_CFI_MASK, vlan_id,
 615                                       port_num);
 616 }
 617
 618 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
 619                            __always_unused void **context)
 620 {
 621         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 622                              attr->index, &attr->gid, attr);
 623 }
 624
 625 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
 626                            __always_unused void **context)
 627 {
 628         return set_roce_addr(to_mdev(attr->device), attr->port_num,
 629                              attr->index, NULL, NULL);
 630 }
 631
 632 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
 633                                const struct ib_gid_attr *attr)
 634 {
 635         if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 636                 return 0;
 637
 638         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 639 }
 640
 641 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 642 {
 643         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 644                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 645         return 0;
 646 }
 647
 648 enum {
 649         MLX5_VPORT_ACCESS_METHOD_MAD,
 650         MLX5_VPORT_ACCESS_METHOD_HCA,
 651         MLX5_VPORT_ACCESS_METHOD_NIC,
 652 };
 653
 654 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 655 {
 656         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 657                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 658
 659         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 660             IB_LINK_LAYER_ETHERNET)
 661                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 662
 663         return MLX5_VPORT_ACCESS_METHOD_HCA;
 664 }
 665
 666 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 667                             u8 atomic_size_qp,
 668                             struct ib_device_attr *props)
 669 {
 670         u8 tmp;
 671         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 672         u8 atomic_req_8B_endianness_mode =
 673                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
 674
 675         /* Check if HW supports 8 bytes standard atomic operations and capable
 676          * of host endianness respond
 677          */
 678         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 679         if (((atomic_operations & tmp) == tmp) &&
 680             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 681             (atomic_req_8B_endianness_mode)) {
 682                 props->atomic_cap = IB_ATOMIC_HCA;
 683         } else {
 684                 props->atomic_cap = IB_ATOMIC_NONE;
 685         }
 686 }
 687
 688 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
 689                                struct ib_device_attr *props)
 690 {
 691         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 692
 693         get_atomic_caps(dev, atomic_size_qp, props);
 694 }
 695
 696 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
 697                                struct ib_device_attr *props)
 698 {
 699         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
 700
 701         get_atomic_caps(dev, atomic_size_qp, props);
 702 }
 703
 704 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
 705 {
 706         struct ib_device_attr props = {};
 707
 708         get_atomic_caps_dc(dev, &props);
 709         return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
 710 }
 711 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 712                                         __be64 *sys_image_guid)
 713 {
 714         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 715         struct mlx5_core_dev *mdev = dev->mdev;
 716         u64 tmp;
 717         int err;
 718
 719         switch (mlx5_get_vport_access_method(ibdev)) {
 720         case MLX5_VPORT_ACCESS_METHOD_MAD:
 721                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 722                                                             sys_image_guid);
 723
 724         case MLX5_VPORT_ACCESS_METHOD_HCA:
 725                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 726                 break;
 727
 728         case MLX5_VPORT_ACCESS_METHOD_NIC:
 729                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         if (!err)
 737                 *sys_image_guid = cpu_to_be64(tmp);
 738
 739         return err;
 740
 741 }
 742
 743 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 744                                 u16 *max_pkeys)
 745 {
 746         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 747         struct mlx5_core_dev *mdev = dev->mdev;
 748
 749         switch (mlx5_get_vport_access_method(ibdev)) {
 750         case MLX5_VPORT_ACCESS_METHOD_MAD:
 751                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 752
 753         case MLX5_VPORT_ACCESS_METHOD_HCA:
 754         case MLX5_VPORT_ACCESS_METHOD_NIC:
 755                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 756                                                 pkey_table_size));
 757                 return 0;
 758
 759         default:
 760                 return -EINVAL;
 761         }
 762 }
 763
 764 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 765                                 u32 *vendor_id)
 766 {
 767         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 768
 769         switch (mlx5_get_vport_access_method(ibdev)) {
 770         case MLX5_VPORT_ACCESS_METHOD_MAD:
 771                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 772
 773         case MLX5_VPORT_ACCESS_METHOD_HCA:
 774         case MLX5_VPORT_ACCESS_METHOD_NIC:
 775                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 776
 777         default:
 778                 return -EINVAL;
 779         }
 780 }
 781
 782 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 783                                 __be64 *node_guid)
 784 {
 785         u64 tmp;
 786         int err;
 787
 788         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 789         case MLX5_VPORT_ACCESS_METHOD_MAD:
 790                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 791
 792         case MLX5_VPORT_ACCESS_METHOD_HCA:
 793                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 794                 break;
 795
 796         case MLX5_VPORT_ACCESS_METHOD_NIC:
 797                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 798                 break;
 799
 800         default:
 801                 return -EINVAL;
 802         }
 803
 804         if (!err)
 805                 *node_guid = cpu_to_be64(tmp);
 806
 807         return err;
 808 }
 809
 810 struct mlx5_reg_node_desc {
 811         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 812 };
 813
 814 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 815 {
 816         struct mlx5_reg_node_desc in;
 817
 818         if (mlx5_use_mad_ifc(dev))
 819                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 820
 821         memset(&in, 0, sizeof(in));
 822
 823         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 824                                     sizeof(struct mlx5_reg_node_desc),
 825                                     MLX5_REG_NODE_DESC, 0, 0);
 826 }
 827
 828 static int mlx5_ib_query_device(struct ib_device *ibdev,
 829                                 struct ib_device_attr *props,
 830                                 struct ib_udata *uhw)
 831 {
 832         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 833         struct mlx5_core_dev *mdev = dev->mdev;
 834         int err = -ENOMEM;
 835         int max_sq_desc;
 836         int max_rq_sg;
 837         int max_sq_sg;
 838         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 839         bool raw_support = !mlx5_core_mp_enabled(mdev);
 840         struct mlx5_ib_query_device_resp resp = {};
 841         size_t resp_len;
 842         u64 max_tso;
 843
 844         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 845         if (uhw->outlen && uhw->outlen < resp_len)
 846                 return -EINVAL;
 847         else
 848                 resp.response_length = resp_len;
 849
 850         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 851                 return -EINVAL;
 852
 853         memset(props, 0, sizeof(*props));
 854         err = mlx5_query_system_image_guid(ibdev,
 855                                            &props->sys_image_guid);
 856         if (err)
 857                 return err;
 858
 859         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 860         if (err)
 861                 return err;
 862
 863         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 864         if (err)
 865                 return err;
 866
 867         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 868                 (fw_rev_min(dev->mdev) << 16) |
 869                 fw_rev_sub(dev->mdev);
 870         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 871                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 872                 IB_DEVICE_SYS_IMAGE_GUID                |
 873                 IB_DEVICE_RC_RNR_NAK_GEN;
 874
 875         if (MLX5_CAP_GEN(mdev, pkv))
 876                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 877         if (MLX5_CAP_GEN(mdev, qkv))
 878                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 879         if (MLX5_CAP_GEN(mdev, apm))
 880                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 881         if (MLX5_CAP_GEN(mdev, xrc))
 882                 props->device_cap_flags |= IB_DEVICE_XRC;
 883         if (MLX5_CAP_GEN(mdev, imaicl)) {
 884                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 885                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 886                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 887                 /* We support 'Gappy' memory registration too */
 888                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 889         }
 890         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 891         if (MLX5_CAP_GEN(mdev, sho)) {
 892                 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
 893                 /* At this stage no support for signature handover */
 894                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 895                                       IB_PROT_T10DIF_TYPE_2 |
 896                                       IB_PROT_T10DIF_TYPE_3;
 897                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 898                                        IB_GUARD_T10DIF_CSUM;
 899         }
 900         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 901                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 902
 903         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
 904                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 905                         /* Legacy bit to support old userspace libraries */
 906                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 907                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 908                 }
 909
 910                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 911                         props->raw_packet_caps |=
 912                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 913
 914                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 915                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 916                         if (max_tso) {
 917                                 resp.tso_caps.max_tso = 1 << max_tso;
 918                                 resp.tso_caps.supported_qpts |=
 919                                         1 << IB_QPT_RAW_PACKET;
 920                                 resp.response_length += sizeof(resp.tso_caps);
 921                         }
 922                 }
 923
 924                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 925                         resp.rss_caps.rx_hash_function =
 926                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 927                         resp.rss_caps.rx_hash_fields_mask =
 928                                                 MLX5_RX_HASH_SRC_IPV4 |
 929                                                 MLX5_RX_HASH_DST_IPV4 |
 930                                                 MLX5_RX_HASH_SRC_IPV6 |
 931                                                 MLX5_RX_HASH_DST_IPV6 |
 932                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 933                                                 MLX5_RX_HASH_DST_PORT_TCP |
 934                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 935                                                 MLX5_RX_HASH_DST_PORT_UDP |
 936                                                 MLX5_RX_HASH_INNER;
 937                         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
 938                             MLX5_ACCEL_IPSEC_CAP_DEVICE)
 939                                 resp.rss_caps.rx_hash_fields_mask |=
 940                                         MLX5_RX_HASH_IPSEC_SPI;
 941                         resp.response_length += sizeof(resp.rss_caps);
 942                 }
 943         } else {
 944                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 945                         resp.response_length += sizeof(resp.tso_caps);
 946                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 947                         resp.response_length += sizeof(resp.rss_caps);
 948         }
 949
 950         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 951                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 952                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 953         }
 954
 955         if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
 956             MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
 957             raw_support)
 958                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
 959
 960         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
 961             MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
 962                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 963
 964         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 965             MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
 966             raw_support) {
 967                 /* Legacy bit to support old userspace libraries */
 968                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 969                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 970         }
 971
 972         if (MLX5_CAP_DEV_MEM(mdev, memic)) {
 973                 props->max_dm_size =
 974                         MLX5_CAP_DEV_MEM(mdev, max_memic_size);
 975         }
 976
 977         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 978                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 979
 980         if (MLX5_CAP_GEN(mdev, end_pad))
 981                 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
 982
 983         props->vendor_part_id      = mdev->pdev->device;
 984         props->hw_ver              = mdev->pdev->revision;
 985
 986         props->max_mr_size         = ~0ull;
 987         props->page_size_cap       = ~(min_page_size - 1);
 988         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 989         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 990         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 991                      sizeof(struct mlx5_wqe_data_seg);
 992         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 993         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 994                      sizeof(struct mlx5_wqe_raddr_seg)) /
 995                 sizeof(struct mlx5_wqe_data_seg);
 996         props->max_send_sge = max_sq_sg;
 997         props->max_recv_sge = max_rq_sg;
 998         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 999         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
1000         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
1001         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
1002         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
1003         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
1004         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
1005         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
1006         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
1007         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
1008         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
1009         props->max_srq_sge         = max_rq_sg - 1;
1010         props->max_fast_reg_page_list_len =
1011                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
1012         props->max_pi_fast_reg_page_list_len =
1013                 props->max_fast_reg_page_list_len / 2;
1014         get_atomic_caps_qp(dev, props);
1015         props->masked_atomic_cap   = IB_ATOMIC_NONE;
1016         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
1017         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
1018         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1019                                            props->max_mcast_grp;
1020         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
1021         props->max_ah = INT_MAX;
1022         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
1023         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
1024
1025         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1026                 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
1027                         props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
1028                 props->odp_caps = dev->odp_caps;
1029         }
1030
1031         if (MLX5_CAP_GEN(mdev, cd))
1032                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1033
1034         if (!mlx5_core_is_pf(mdev))
1035                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1036
1037         if (mlx5_ib_port_link_layer(ibdev, 1) ==
1038             IB_LINK_LAYER_ETHERNET && raw_support) {
1039                 props->rss_caps.max_rwq_indirection_tables =
1040                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1041                 props->rss_caps.max_rwq_indirection_table_size =
1042                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1043                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1044                 props->max_wq_type_rq =
1045                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1046         }
1047
1048         if (MLX5_CAP_GEN(mdev, tag_matching)) {
1049                 props->tm_caps.max_num_tags =
1050                         (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1051                 props->tm_caps.max_ops =
1052                         1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1053                 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1054         }
1055
1056         if (MLX5_CAP_GEN(mdev, tag_matching) &&
1057             MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1058                 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1059                 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1060         }
1061
1062         if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1063                 props->cq_caps.max_cq_moderation_count =
1064                                                 MLX5_MAX_CQ_COUNT;
1065                 props->cq_caps.max_cq_moderation_period =
1066                                                 MLX5_MAX_CQ_PERIOD;
1067         }
1068
1069         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
1070                 resp.response_length += sizeof(resp.cqe_comp_caps);
1071
1072                 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1073                         resp.cqe_comp_caps.max_num =
1074                                 MLX5_CAP_GEN(dev->mdev,
1075                                              cqe_compression_max_num);
1076
1077                         resp.cqe_comp_caps.supported_format =
1078                                 MLX5_IB_CQE_RES_FORMAT_HASH |
1079                                 MLX5_IB_CQE_RES_FORMAT_CSUM;
1080
1081                         if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1082                                 resp.cqe_comp_caps.supported_format |=
1083                                         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1084                 }
1085         }
1086
1087         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
1088             raw_support) {
1089                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1090                     MLX5_CAP_GEN(mdev, qos)) {
1091                         resp.packet_pacing_caps.qp_rate_limit_max =
1092                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1093                         resp.packet_pacing_caps.qp_rate_limit_min =
1094                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1095                         resp.packet_pacing_caps.supported_qpts |=
1096                                 1 << IB_QPT_RAW_PACKET;
1097                         if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1098                             MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1099                                 resp.packet_pacing_caps.cap_flags |=
1100                                         MLX5_IB_PP_SUPPORT_BURST;
1101                 }
1102                 resp.response_length += sizeof(resp.packet_pacing_caps);
1103         }
1104
1105         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
1106                         uhw->outlen)) {
1107                 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1108                         resp.mlx5_ib_support_multi_pkt_send_wqes =
1109                                 MLX5_IB_ALLOW_MPW;
1110
1111                 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1112                         resp.mlx5_ib_support_multi_pkt_send_wqes |=
1113                                 MLX5_IB_SUPPORT_EMPW;
1114
1115                 resp.response_length +=
1116                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1117         }
1118
1119         if (field_avail(typeof(resp), flags, uhw->outlen)) {
1120                 resp.response_length += sizeof(resp.flags);
1121
1122                 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1123                         resp.flags |=
1124                                 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1125
1126                 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1127                         resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1128                 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1129                         resp.flags |=
1130                                 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1131
1132                 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1133         }
1134
1135         if (field_avail(typeof(resp), sw_parsing_caps,
1136                         uhw->outlen)) {
1137                 resp.response_length += sizeof(resp.sw_parsing_caps);
1138                 if (MLX5_CAP_ETH(mdev, swp)) {
1139                         resp.sw_parsing_caps.sw_parsing_offloads |=
1140                                 MLX5_IB_SW_PARSING;
1141
1142                         if (MLX5_CAP_ETH(mdev, swp_csum))
1143                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1144                                         MLX5_IB_SW_PARSING_CSUM;
1145
1146                         if (MLX5_CAP_ETH(mdev, swp_lso))
1147                                 resp.sw_parsing_caps.sw_parsing_offloads |=
1148                                         MLX5_IB_SW_PARSING_LSO;
1149
1150                         if (resp.sw_parsing_caps.sw_parsing_offloads)
1151                                 resp.sw_parsing_caps.supported_qpts =
1152                                         BIT(IB_QPT_RAW_PACKET);
1153                 }
1154         }
1155
1156         if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1157             raw_support) {
1158                 resp.response_length += sizeof(resp.striding_rq_caps);
1159                 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1160                         resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1161                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1162                         resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1163                                 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1164                         resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1165                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1166                         resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1167                                 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1168                         resp.striding_rq_caps.supported_qpts =
1169                                 BIT(IB_QPT_RAW_PACKET);
1170                 }
1171         }
1172
1173         if (field_avail(typeof(resp), tunnel_offloads_caps,
1174                         uhw->outlen)) {
1175                 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1176                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1177                         resp.tunnel_offloads_caps |=
1178                                 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1179                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1180                         resp.tunnel_offloads_caps |=
1181                                 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1182                 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1183                         resp.tunnel_offloads_caps |=
1184                                 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1185                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1186                     MLX5_FLEX_PROTO_CW_MPLS_GRE)
1187                         resp.tunnel_offloads_caps |=
1188                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1189                 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1190                     MLX5_FLEX_PROTO_CW_MPLS_UDP)
1191                         resp.tunnel_offloads_caps |=
1192                                 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1193         }
1194
1195         if (uhw->outlen) {
1196                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1197
1198                 if (err)
1199                         return err;
1200         }
1201
1202         return 0;
1203 }
1204
1205 enum mlx5_ib_width {
1206         MLX5_IB_WIDTH_1X        = 1 << 0,
1207         MLX5_IB_WIDTH_2X        = 1 << 1,
1208         MLX5_IB_WIDTH_4X        = 1 << 2,
1209         MLX5_IB_WIDTH_8X        = 1 << 3,
1210         MLX5_IB_WIDTH_12X       = 1 << 4
1211 };
1212
1213 static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1214                                   u8 *ib_width)
1215 {
1216         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1217
1218         if (active_width & MLX5_IB_WIDTH_1X)
1219                 *ib_width = IB_WIDTH_1X;
1220         else if (active_width & MLX5_IB_WIDTH_2X)
1221                 *ib_width = IB_WIDTH_2X;
1222         else if (active_width & MLX5_IB_WIDTH_4X)
1223                 *ib_width = IB_WIDTH_4X;
1224         else if (active_width & MLX5_IB_WIDTH_8X)
1225                 *ib_width = IB_WIDTH_8X;
1226         else if (active_width & MLX5_IB_WIDTH_12X)
1227                 *ib_width = IB_WIDTH_12X;
1228         else {
1229                 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1230                             (int)active_width);
1231                 *ib_width = IB_WIDTH_4X;
1232         }
1233
1234         return;
1235 }
1236
1237 static int mlx5_mtu_to_ib_mtu(int mtu)
1238 {
1239         switch (mtu) {
1240         case 256: return 1;
1241         case 512: return 2;
1242         case 1024: return 3;
1243         case 2048: return 4;
1244         case 4096: return 5;
1245         default:
1246                 pr_warn("invalid mtu\n");
1247                 return -1;
1248         }
1249 }
1250
1251 enum ib_max_vl_num {
1252         __IB_MAX_VL_0           = 1,
1253         __IB_MAX_VL_0_1         = 2,
1254         __IB_MAX_VL_0_3         = 3,
1255         __IB_MAX_VL_0_7         = 4,
1256         __IB_MAX_VL_0_14        = 5,
1257 };
1258
1259 enum mlx5_vl_hw_cap {
1260         MLX5_VL_HW_0    = 1,
1261         MLX5_VL_HW_0_1  = 2,
1262         MLX5_VL_HW_0_2  = 3,
1263         MLX5_VL_HW_0_3  = 4,
1264         MLX5_VL_HW_0_4  = 5,
1265         MLX5_VL_HW_0_5  = 6,
1266         MLX5_VL_HW_0_6  = 7,
1267         MLX5_VL_HW_0_7  = 8,
1268         MLX5_VL_HW_0_14 = 15
1269 };
1270
1271 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1272                                 u8 *max_vl_num)
1273 {
1274         switch (vl_hw_cap) {
1275         case MLX5_VL_HW_0:
1276                 *max_vl_num = __IB_MAX_VL_0;
1277                 break;
1278         case MLX5_VL_HW_0_1:
1279                 *max_vl_num = __IB_MAX_VL_0_1;
1280                 break;
1281         case MLX5_VL_HW_0_3:
1282                 *max_vl_num = __IB_MAX_VL_0_3;
1283                 break;
1284         case MLX5_VL_HW_0_7:
1285                 *max_vl_num = __IB_MAX_VL_0_7;
1286                 break;
1287         case MLX5_VL_HW_0_14:
1288                 *max_vl_num = __IB_MAX_VL_0_14;
1289                 break;
1290
1291         default:
1292                 return -EINVAL;
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1299                                struct ib_port_attr *props)
1300 {
1301         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1302         struct mlx5_core_dev *mdev = dev->mdev;
1303         struct mlx5_hca_vport_context *rep;
1304         u16 max_mtu;
1305         u16 oper_mtu;
1306         int err;
1307         u8 ib_link_width_oper;
1308         u8 vl_hw_cap;
1309
1310         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1311         if (!rep) {
1312                 err = -ENOMEM;
1313                 goto out;
1314         }
1315
1316         /* props being zeroed by the caller, avoid zeroing it here */
1317
1318         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1319         if (err)
1320                 goto out;
1321
1322         props->lid              = rep->lid;
1323         props->lmc              = rep->lmc;
1324         props->sm_lid           = rep->sm_lid;
1325         props->sm_sl            = rep->sm_sl;
1326         props->state            = rep->vport_state;
1327         props->phys_state       = rep->port_physical_state;
1328         props->port_cap_flags   = rep->cap_mask1;
1329         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1330         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1331         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1332         props->bad_pkey_cntr    = rep->pkey_violation_counter;
1333         props->qkey_viol_cntr   = rep->qkey_violation_counter;
1334         props->subnet_timeout   = rep->subnet_timeout;
1335         props->init_type_reply  = rep->init_type_reply;
1336
1337         if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1338                 props->port_cap_flags2 = rep->cap_mask2;
1339
1340         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1341         if (err)
1342                 goto out;
1343
1344         translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1345
1346         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1347         if (err)
1348                 goto out;
1349
1350         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1351
1352         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1353
1354         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1355
1356         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1357
1358         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1359         if (err)
1360                 goto out;
1361
1362         err = translate_max_vl_num(ibdev, vl_hw_cap,
1363                                    &props->max_vl_num);
1364 out:
1365         kfree(rep);
1366         return err;
1367 }
1368
1369 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1370                        struct ib_port_attr *props)
1371 {
1372         unsigned int count;
1373         int ret;
1374
1375         switch (mlx5_get_vport_access_method(ibdev)) {
1376         case MLX5_VPORT_ACCESS_METHOD_MAD:
1377                 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1378                 break;
1379
1380         case MLX5_VPORT_ACCESS_METHOD_HCA:
1381                 ret = mlx5_query_hca_port(ibdev, port, props);
1382                 break;
1383
1384         case MLX5_VPORT_ACCESS_METHOD_NIC:
1385                 ret = mlx5_query_port_roce(ibdev, port, props);
1386                 break;
1387
1388         default:
1389                 ret = -EINVAL;
1390         }
1391
1392         if (!ret && props) {
1393                 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1394                 struct mlx5_core_dev *mdev;
1395                 bool put_mdev = true;
1396
1397                 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1398                 if (!mdev) {
1399                         /* If the port isn't affiliated yet query the master.
1400                          * The master and slave will have the same values.
1401                          */
1402                         mdev = dev->mdev;
1403                         port = 1;
1404                         put_mdev = false;
1405                 }
1406                 count = mlx5_core_reserved_gids_count(mdev);
1407                 if (put_mdev)
1408                         mlx5_ib_put_native_port_mdev(dev, port);
1409                 props->gid_tbl_len -= count;
1410         }
1411         return ret;
1412 }
1413
1414 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1415                                   struct ib_port_attr *props)
1416 {
1417         int ret;
1418
1419         /* Only link layer == ethernet is valid for representors
1420          * and we always use port 1
1421          */
1422         ret = mlx5_query_port_roce(ibdev, port, props);
1423         if (ret || !props)
1424                 return ret;
1425
1426         /* We don't support GIDS */
1427         props->gid_tbl_len = 0;
1428
1429         return ret;
1430 }
1431
1432 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1433                              union ib_gid *gid)
1434 {
1435         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1436         struct mlx5_core_dev *mdev = dev->mdev;
1437
1438         switch (mlx5_get_vport_access_method(ibdev)) {
1439         case MLX5_VPORT_ACCESS_METHOD_MAD:
1440                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1441
1442         case MLX5_VPORT_ACCESS_METHOD_HCA:
1443                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1444
1445         default:
1446                 return -EINVAL;
1447         }
1448
1449 }
1450
1451 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1452                                    u16 index, u16 *pkey)
1453 {
1454         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1455         struct mlx5_core_dev *mdev;
1456         bool put_mdev = true;
1457         u8 mdev_port_num;
1458         int err;
1459
1460         mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1461         if (!mdev) {
1462                 /* The port isn't affiliated yet, get the PKey from the master
1463                  * port. For RoCE the PKey tables will be the same.
1464                  */
1465                 put_mdev = false;
1466                 mdev = dev->mdev;
1467                 mdev_port_num = 1;
1468         }
1469
1470         err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1471                                         index, pkey);
1472         if (put_mdev)
1473                 mlx5_ib_put_native_port_mdev(dev, port);
1474
1475         return err;
1476 }
1477
1478 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1479                               u16 *pkey)
1480 {
1481         switch (mlx5_get_vport_access_method(ibdev)) {
1482         case MLX5_VPORT_ACCESS_METHOD_MAD:
1483                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1484
1485         case MLX5_VPORT_ACCESS_METHOD_HCA:
1486         case MLX5_VPORT_ACCESS_METHOD_NIC:
1487                 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1488         default:
1489                 return -EINVAL;
1490         }
1491 }
1492
1493 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1494                                  struct ib_device_modify *props)
1495 {
1496         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1497         struct mlx5_reg_node_desc in;
1498         struct mlx5_reg_node_desc out;
1499         int err;
1500
1501         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1502                 return -EOPNOTSUPP;
1503
1504         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1505                 return 0;
1506
1507         /*
1508          * If possible, pass node desc to FW, so it can generate
1509          * a 144 trap.  If cmd fails, just ignore.
1510          */
1511         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1512         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1513                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1514         if (err)
1515                 return err;
1516
1517         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1518
1519         return err;
1520 }
1521
1522 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1523                                 u32 value)
1524 {
1525         struct mlx5_hca_vport_context ctx = {};
1526         struct mlx5_core_dev *mdev;
1527         u8 mdev_port_num;
1528         int err;
1529
1530         mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1531         if (!mdev)
1532                 return -ENODEV;
1533
1534         err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1535         if (err)
1536                 goto out;
1537
1538         if (~ctx.cap_mask1_perm & mask) {
1539                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1540                              mask, ctx.cap_mask1_perm);
1541                 err = -EINVAL;
1542                 goto out;
1543         }
1544
1545         ctx.cap_mask1 = value;
1546         ctx.cap_mask1_perm = mask;
1547         err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1548                                                  0, &ctx);
1549
1550 out:
1551         mlx5_ib_put_native_port_mdev(dev, port_num);
1552
1553         return err;
1554 }
1555
1556 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1557                                struct ib_port_modify *props)
1558 {
1559         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1560         struct ib_port_attr attr;
1561         u32 tmp;
1562         int err;
1563         u32 change_mask;
1564         u32 value;
1565         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1566                       IB_LINK_LAYER_INFINIBAND);
1567
1568         /* CM layer calls ib_modify_port() regardless of the link layer. For
1569          * Ethernet ports, qkey violation and Port capabilities are meaningless.
1570          */
1571         if (!is_ib)
1572                 return 0;
1573
1574         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1575                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1576                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1577                 return set_port_caps_atomic(dev, port, change_mask, value);
1578         }
1579
1580         mutex_lock(&dev->cap_mask_mutex);
1581
1582         err = ib_query_port(ibdev, port, &attr);
1583         if (err)
1584                 goto out;
1585
1586         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1587                 ~props->clr_port_cap_mask;
1588
1589         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1590
1591 out:
1592         mutex_unlock(&dev->cap_mask_mutex);
1593         return err;
1594 }
1595
1596 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1597 {
1598         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1599                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1600 }
1601
1602 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1603 {
1604         /* Large page with non 4k uar support might limit the dynamic size */
1605         if (uars_per_sys_page == 1  && PAGE_SIZE > 4096)
1606                 return MLX5_MIN_DYN_BFREGS;
1607
1608         return MLX5_MAX_DYN_BFREGS;
1609 }
1610
1611 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1612                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1613                              struct mlx5_bfreg_info *bfregi)
1614 {
1615         int uars_per_sys_page;
1616         int bfregs_per_sys_page;
1617         int ref_bfregs = req->total_num_bfregs;
1618
1619         if (req->total_num_bfregs == 0)
1620                 return -EINVAL;
1621
1622         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1623         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1624
1625         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1626                 return -ENOMEM;
1627
1628         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1629         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1630         /* This holds the required static allocation asked by the user */
1631         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1632         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1633                 return -EINVAL;
1634
1635         bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1636         bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1637         bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1638         bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1639
1640         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1641                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1642                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1643                     req->total_num_bfregs, bfregi->total_num_bfregs,
1644                     bfregi->num_sys_pages);
1645
1646         return 0;
1647 }
1648
1649 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1650 {
1651         struct mlx5_bfreg_info *bfregi;
1652         int err;
1653         int i;
1654
1655         bfregi = &context->bfregi;
1656         for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1657                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1658                 if (err)
1659                         goto error;
1660
1661                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1662         }
1663
1664         for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1665                 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1666
1667         return 0;
1668
1669 error:
1670         for (--i; i >= 0; i--)
1671                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1672                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1673
1674         return err;
1675 }
1676
1677 static void deallocate_uars(struct mlx5_ib_dev *dev,
1678                             struct mlx5_ib_ucontext *context)
1679 {
1680         struct mlx5_bfreg_info *bfregi;
1681         int i;
1682
1683         bfregi = &context->bfregi;
1684         for (i = 0; i < bfregi->num_sys_pages; i++)
1685                 if (i < bfregi->num_static_sys_pages ||
1686                     bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1687                         mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1688 }
1689
1690 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1691 {
1692         int err = 0;
1693
1694         mutex_lock(&dev->lb.mutex);
1695         if (td)
1696                 dev->lb.user_td++;
1697         if (qp)
1698                 dev->lb.qps++;
1699
1700         if (dev->lb.user_td == 2 ||
1701             dev->lb.qps == 1) {
1702                 if (!dev->lb.enabled) {
1703                         err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1704                         dev->lb.enabled = true;
1705                 }
1706         }
1707
1708         mutex_unlock(&dev->lb.mutex);
1709
1710         return err;
1711 }
1712
1713 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1714 {
1715         mutex_lock(&dev->lb.mutex);
1716         if (td)
1717                 dev->lb.user_td--;
1718         if (qp)
1719                 dev->lb.qps--;
1720
1721         if (dev->lb.user_td == 1 &&
1722             dev->lb.qps == 0) {
1723                 if (dev->lb.enabled) {
1724                         mlx5_nic_vport_update_local_lb(dev->mdev, false);
1725                         dev->lb.enabled = false;
1726                 }
1727         }
1728
1729         mutex_unlock(&dev->lb.mutex);
1730 }
1731
1732 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1733                                           u16 uid)
1734 {
1735         int err;
1736
1737         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1738                 return 0;
1739
1740         err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1741         if (err)
1742                 return err;
1743
1744         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1745             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1746              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1747                 return err;
1748
1749         return mlx5_ib_enable_lb(dev, true, false);
1750 }
1751
1752 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1753                                              u16 uid)
1754 {
1755         if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1756                 return;
1757
1758         mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1759
1760         if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1761             (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1762              !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1763                 return;
1764
1765         mlx5_ib_disable_lb(dev, true, false);
1766 }
1767
1768 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1769                                   struct ib_udata *udata)
1770 {
1771         struct ib_device *ibdev = uctx->device;
1772         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1773         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1774         struct mlx5_ib_alloc_ucontext_resp resp = {};
1775         struct mlx5_core_dev *mdev = dev->mdev;
1776         struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1777         struct mlx5_bfreg_info *bfregi;
1778         int ver;
1779         int err;
1780         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1781                                      max_cqe_version);
1782         u32 dump_fill_mkey;
1783         bool lib_uar_4k;
1784
1785         if (!dev->ib_active)
1786                 return -EAGAIN;
1787
1788         if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1789                 ver = 0;
1790         else if (udata->inlen >= min_req_v2)
1791                 ver = 2;
1792         else
1793                 return -EINVAL;
1794
1795         err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1796         if (err)
1797                 return err;
1798
1799         if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1800                 return -EOPNOTSUPP;
1801
1802         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1803                 return -EOPNOTSUPP;
1804
1805         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1806                                     MLX5_NON_FP_BFREGS_PER_UAR);
1807         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1808                 return -EINVAL;
1809
1810         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1811         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1812                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1813         resp.cache_line_size = cache_line_size();
1814         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1815         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1816         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1817         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1818         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1819         resp.cqe_version = min_t(__u8,
1820                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1821                                  req.max_cqe_version);
1822         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1823                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1824         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1825                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1826         resp.response_length = min(offsetof(typeof(resp), response_length) +
1827                                    sizeof(resp.response_length), udata->outlen);
1828
1829         if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1830                 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1831                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1832                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1833                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1834                 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1835                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1836                 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1837                         resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1838                 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1839         }
1840
1841         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1842         bfregi = &context->bfregi;
1843
1844         /* updates req->total_num_bfregs */
1845         err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1846         if (err)
1847                 goto out_ctx;
1848
1849         mutex_init(&bfregi->lock);
1850         bfregi->lib_uar_4k = lib_uar_4k;
1851         bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1852                                 GFP_KERNEL);
1853         if (!bfregi->count) {
1854                 err = -ENOMEM;
1855                 goto out_ctx;
1856         }
1857
1858         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1859                                     sizeof(*bfregi->sys_pages),
1860                                     GFP_KERNEL);
1861         if (!bfregi->sys_pages) {
1862                 err = -ENOMEM;
1863                 goto out_count;
1864         }
1865
1866         err = allocate_uars(dev, context);
1867         if (err)
1868                 goto out_sys_pages;
1869
1870         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1871                 err = mlx5_ib_devx_create(dev, true);
1872                 if (err < 0)
1873                         goto out_uars;
1874                 context->devx_uid = err;
1875         }
1876
1877         err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1878                                              context->devx_uid);
1879         if (err)
1880                 goto out_devx;
1881
1882         if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1883                 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1884                 if (err)
1885                         goto out_mdev;
1886         }
1887
1888         INIT_LIST_HEAD(&context->db_page_list);
1889         mutex_init(&context->db_page_mutex);
1890
1891         resp.tot_bfregs = req.total_num_bfregs;
1892         resp.num_ports = dev->num_ports;
1893
1894         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1895                 resp.response_length += sizeof(resp.cqe_version);
1896
1897         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1898                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1899                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1900                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1901         }
1902
1903         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1904                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1905                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1906                         resp.eth_min_inline++;
1907                 }
1908                 resp.response_length += sizeof(resp.eth_min_inline);
1909         }
1910
1911         if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1912                 if (mdev->clock_info)
1913                         resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1914                 resp.response_length += sizeof(resp.clock_info_versions);
1915         }
1916
1917         /*
1918          * We don't want to expose information from the PCI bar that is located
1919          * after 4096 bytes, so if the arch only supports larger pages, let's
1920          * pretend we don't support reading the HCA's core clock. This is also
1921          * forced by mmap function.
1922          */
1923         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1924                 if (PAGE_SIZE <= 4096) {
1925                         resp.comp_mask |=
1926                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1927                         resp.hca_core_clock_offset =
1928                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1929                 }
1930                 resp.response_length += sizeof(resp.hca_core_clock_offset);
1931         }
1932
1933         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1934                 resp.response_length += sizeof(resp.log_uar_size);
1935
1936         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1937                 resp.response_length += sizeof(resp.num_uars_per_page);
1938
1939         if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1940                 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1941                 resp.response_length += sizeof(resp.num_dyn_bfregs);
1942         }
1943
1944         if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1945                 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1946                         resp.dump_fill_mkey = dump_fill_mkey;
1947                         resp.comp_mask |=
1948                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1949                 }
1950                 resp.response_length += sizeof(resp.dump_fill_mkey);
1951         }
1952
1953         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1954         if (err)
1955                 goto out_mdev;
1956
1957         bfregi->ver = ver;
1958         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1959         context->cqe_version = resp.cqe_version;
1960         context->lib_caps = req.lib_caps;
1961         print_lib_caps(dev, context->lib_caps);
1962
1963         if (dev->lag_active) {
1964                 u8 port = mlx5_core_native_port_num(dev->mdev) - 1;
1965
1966                 atomic_set(&context->tx_port_affinity,
1967                            atomic_add_return(
1968                                    1, &dev->port[port].roce.tx_port_affinity));
1969         }
1970
1971         return 0;
1972
1973 out_mdev:
1974         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1975 out_devx:
1976         if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1977                 mlx5_ib_devx_destroy(dev, context->devx_uid);
1978
1979 out_uars:
1980         deallocate_uars(dev, context);
1981
1982 out_sys_pages:
1983         kfree(bfregi->sys_pages);
1984
1985 out_count:
1986         kfree(bfregi->count);
1987
1988 out_ctx:
1989         return err;
1990 }
1991
1992 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1993 {
1994         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1995         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1996         struct mlx5_bfreg_info *bfregi;
1997
1998         bfregi = &context->bfregi;
1999         mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2000
2001         if (context->devx_uid)
2002                 mlx5_ib_devx_destroy(dev, context->devx_uid);
2003
2004         deallocate_uars(dev, context);
2005         kfree(bfregi->sys_pages);
2006         kfree(bfregi->count);
2007 }
2008
2009 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2010                                  int uar_idx)
2011 {
2012         int fw_uars_per_page;
2013
2014         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2015
2016         return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2017 }
2018
2019 static int get_command(unsigned long offset)
2020 {
2021         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2022 }
2023
2024 static int get_arg(unsigned long offset)
2025 {
2026         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2027 }
2028
2029 static int get_index(unsigned long offset)
2030 {
2031         return get_arg(offset);
2032 }
2033
2034 /* Index resides in an extra byte to enable larger values than 255 */
2035 static int get_extended_index(unsigned long offset)
2036 {
2037         return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2038 }
2039
2040
2041 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2042 {
2043 }
2044
2045 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2046 {
2047         switch (cmd) {
2048         case MLX5_IB_MMAP_WC_PAGE:
2049                 return "WC";
2050         case MLX5_IB_MMAP_REGULAR_PAGE:
2051                 return "best effort WC";
2052         case MLX5_IB_MMAP_NC_PAGE:
2053                 return "NC";
2054         case MLX5_IB_MMAP_DEVICE_MEM:
2055                 return "Device Memory";
2056         default:
2057                 return NULL;
2058         }
2059 }
2060
2061 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2062                                         struct vm_area_struct *vma,
2063                                         struct mlx5_ib_ucontext *context)
2064 {
2065         if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2066             !(vma->vm_flags & VM_SHARED))
2067                 return -EINVAL;
2068
2069         if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2070                 return -EOPNOTSUPP;
2071
2072         if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2073                 return -EPERM;
2074         vma->vm_flags &= ~VM_MAYWRITE;
2075
2076         if (!dev->mdev->clock_info)
2077                 return -EOPNOTSUPP;
2078
2079         return vm_insert_page(vma, vma->vm_start,
2080                               virt_to_page(dev->mdev->clock_info));
2081 }
2082
2083 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2084                     struct vm_area_struct *vma,
2085                     struct mlx5_ib_ucontext *context)
2086 {
2087         struct mlx5_bfreg_info *bfregi = &context->bfregi;
2088         int err;
2089         unsigned long idx;
2090         phys_addr_t pfn;
2091         pgprot_t prot;
2092         u32 bfreg_dyn_idx = 0;
2093         u32 uar_index;
2094         int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2095         int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2096                                 bfregi->num_static_sys_pages;
2097
2098         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2099                 return -EINVAL;
2100
2101         if (dyn_uar)
2102                 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2103         else
2104                 idx = get_index(vma->vm_pgoff);
2105
2106         if (idx >= max_valid_idx) {
2107                 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2108                              idx, max_valid_idx);
2109                 return -EINVAL;
2110         }
2111
2112         switch (cmd) {
2113         case MLX5_IB_MMAP_WC_PAGE:
2114         case MLX5_IB_MMAP_ALLOC_WC:
2115 /* Some architectures don't support WC memory */
2116 #if defined(CONFIG_X86)
2117                 if (!pat_enabled())
2118                         return -EPERM;
2119 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2120                         return -EPERM;
2121 #endif
2122         /* fall through */
2123         case MLX5_IB_MMAP_REGULAR_PAGE:
2124                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2125                 prot = pgprot_writecombine(vma->vm_page_prot);
2126                 break;
2127         case MLX5_IB_MMAP_NC_PAGE:
2128                 prot = pgprot_noncached(vma->vm_page_prot);
2129                 break;
2130         default:
2131                 return -EINVAL;
2132         }
2133
2134         if (dyn_uar) {
2135                 int uars_per_page;
2136
2137                 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2138                 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2139                 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2140                         mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2141                                      bfreg_dyn_idx, bfregi->total_num_bfregs);
2142                         return -EINVAL;
2143                 }
2144
2145                 mutex_lock(&bfregi->lock);
2146                 /* Fail if uar already allocated, first bfreg index of each
2147                  * page holds its count.
2148                  */
2149                 if (bfregi->count[bfreg_dyn_idx]) {
2150                         mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2151                         mutex_unlock(&bfregi->lock);
2152                         return -EINVAL;
2153                 }
2154
2155                 bfregi->count[bfreg_dyn_idx]++;
2156                 mutex_unlock(&bfregi->lock);
2157
2158                 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2159                 if (err) {
2160                         mlx5_ib_warn(dev, "UAR alloc failed\n");
2161                         goto free_bfreg;
2162                 }
2163         } else {
2164                 uar_index = bfregi->sys_pages[idx];
2165         }
2166
2167         pfn = uar_index2pfn(dev, uar_index);
2168         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2169
2170         err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2171                                 prot);
2172         if (err) {
2173                 mlx5_ib_err(dev,
2174                             "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2175                             err, mmap_cmd2str(cmd));
2176                 goto err;
2177         }
2178
2179         if (dyn_uar)
2180                 bfregi->sys_pages[idx] = uar_index;
2181         return 0;
2182
2183 err:
2184         if (!dyn_uar)
2185                 return err;
2186
2187         mlx5_cmd_free_uar(dev->mdev, idx);
2188
2189 free_bfreg:
2190         mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2191
2192         return err;
2193 }
2194
2195 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2196 {
2197         struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2198         struct mlx5_ib_dev *dev = to_mdev(context->device);
2199         u16 page_idx = get_extended_index(vma->vm_pgoff);
2200         size_t map_size = vma->vm_end - vma->vm_start;
2201         u32 npages = map_size >> PAGE_SHIFT;
2202         phys_addr_t pfn;
2203
2204         if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2205             page_idx + npages)
2206                 return -EINVAL;
2207
2208         pfn = ((dev->mdev->bar_addr +
2209               MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2210               PAGE_SHIFT) +
2211               page_idx;
2212         return rdma_user_mmap_io(context, vma, pfn, map_size,
2213                                  pgprot_writecombine(vma->vm_page_prot));
2214 }
2215
2216 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2217 {
2218         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2219         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2220         unsigned long command;
2221         phys_addr_t pfn;
2222
2223         command = get_command(vma->vm_pgoff);
2224         switch (command) {
2225         case MLX5_IB_MMAP_WC_PAGE:
2226         case MLX5_IB_MMAP_NC_PAGE:
2227         case MLX5_IB_MMAP_REGULAR_PAGE:
2228         case MLX5_IB_MMAP_ALLOC_WC:
2229                 return uar_mmap(dev, command, vma, context);
2230
2231         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2232                 return -ENOSYS;
2233
2234         case MLX5_IB_MMAP_CORE_CLOCK:
2235                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2236                         return -EINVAL;
2237
2238                 if (vma->vm_flags & VM_WRITE)
2239                         return -EPERM;
2240                 vma->vm_flags &= ~VM_MAYWRITE;
2241
2242                 /* Don't expose to user-space information it shouldn't have */
2243                 if (PAGE_SIZE > 4096)
2244                         return -EOPNOTSUPP;
2245
2246                 pfn = (dev->mdev->iseg_base +
2247                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2248                         PAGE_SHIFT;
2249                 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2250                                          PAGE_SIZE,
2251                                          pgprot_noncached(vma->vm_page_prot));
2252         case MLX5_IB_MMAP_CLOCK_INFO:
2253                 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2254
2255         case MLX5_IB_MMAP_DEVICE_MEM:
2256                 return dm_mmap(ibcontext, vma);
2257
2258         default:
2259                 return -EINVAL;
2260         }
2261
2262         return 0;
2263 }
2264
2265 static inline int check_dm_type_support(struct mlx5_ib_dev *dev,
2266                                         u32 type)
2267 {
2268         switch (type) {
2269         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2270                 if (!MLX5_CAP_DEV_MEM(dev->mdev, memic))
2271                         return -EOPNOTSUPP;
2272                 break;
2273         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2274         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2275                 if (!capable(CAP_SYS_RAWIO) ||
2276                     !capable(CAP_NET_RAW))
2277                         return -EPERM;
2278
2279                 if (!(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
2280                       MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, sw_owner)))
2281                         return -EOPNOTSUPP;
2282                 break;
2283         }
2284
2285         return 0;
2286 }
2287
2288 static int handle_alloc_dm_memic(struct ib_ucontext *ctx,
2289                                  struct mlx5_ib_dm *dm,
2290                                  struct ib_dm_alloc_attr *attr,
2291                                  struct uverbs_attr_bundle *attrs)
2292 {
2293         struct mlx5_dm *dm_db = &to_mdev(ctx->device)->dm;
2294         u64 start_offset;
2295         u32 page_idx;
2296         int err;
2297
2298         dm->size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2299
2300         err = mlx5_cmd_alloc_memic(dm_db, &dm->dev_addr,
2301                                    dm->size, attr->alignment);
2302         if (err)
2303                 return err;
2304
2305         page_idx = (dm->dev_addr - pci_resource_start(dm_db->dev->pdev, 0) -
2306                     MLX5_CAP64_DEV_MEM(dm_db->dev, memic_bar_start_addr)) >>
2307                     PAGE_SHIFT;
2308
2309         err = uverbs_copy_to(attrs,
2310                              MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2311                              &page_idx, sizeof(page_idx));
2312         if (err)
2313                 goto err_dealloc;
2314
2315         start_offset = dm->dev_addr & ~PAGE_MASK;
2316         err = uverbs_copy_to(attrs,
2317                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2318                              &start_offset, sizeof(start_offset));
2319         if (err)
2320                 goto err_dealloc;
2321
2322         bitmap_set(to_mucontext(ctx)->dm_pages, page_idx,
2323                    DIV_ROUND_UP(dm->size, PAGE_SIZE));
2324
2325         return 0;
2326
2327 err_dealloc:
2328         mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2329
2330         return err;
2331 }
2332
2333 static int handle_alloc_dm_sw_icm(struct ib_ucontext *ctx,
2334                                   struct mlx5_ib_dm *dm,
2335                                   struct ib_dm_alloc_attr *attr,
2336                                   struct uverbs_attr_bundle *attrs,
2337                                   int type)
2338 {
2339         struct mlx5_core_dev *dev = to_mdev(ctx->device)->mdev;
2340         u64 act_size;
2341         int err;
2342
2343         /* Allocation size must a multiple of the basic block size
2344          * and a power of 2.
2345          */
2346         act_size = round_up(attr->length, MLX5_SW_ICM_BLOCK_SIZE(dev));
2347         act_size = roundup_pow_of_two(act_size);
2348
2349         dm->size = act_size;
2350         err = mlx5_dm_sw_icm_alloc(dev, type, act_size,
2351                                    to_mucontext(ctx)->devx_uid, &dm->dev_addr,
2352                                    &dm->icm_dm.obj_id);
2353         if (err)
2354                 return err;
2355
2356         err = uverbs_copy_to(attrs,
2357                              MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2358                              &dm->dev_addr, sizeof(dm->dev_addr));
2359         if (err)
2360                 mlx5_dm_sw_icm_dealloc(dev, type, dm->size,
2361                                        to_mucontext(ctx)->devx_uid, dm->dev_addr,
2362                                        dm->icm_dm.obj_id);
2363
2364         return err;
2365 }
2366
2367 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2368                                struct ib_ucontext *context,
2369                                struct ib_dm_alloc_attr *attr,
2370                                struct uverbs_attr_bundle *attrs)
2371 {
2372         struct mlx5_ib_dm *dm;
2373         enum mlx5_ib_uapi_dm_type type;
2374         int err;
2375
2376         err = uverbs_get_const_default(&type, attrs,
2377                                        MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
2378                                        MLX5_IB_UAPI_DM_TYPE_MEMIC);
2379         if (err)
2380                 return ERR_PTR(err);
2381
2382         mlx5_ib_dbg(to_mdev(ibdev), "alloc_dm req: dm_type=%d user_length=0x%llx log_alignment=%d\n",
2383                     type, attr->length, attr->alignment);
2384
2385         err = check_dm_type_support(to_mdev(ibdev), type);
2386         if (err)
2387                 return ERR_PTR(err);
2388
2389         dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2390         if (!dm)
2391                 return ERR_PTR(-ENOMEM);
2392
2393         dm->type = type;
2394
2395         switch (type) {
2396         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2397                 err = handle_alloc_dm_memic(context, dm,
2398                                             attr,
2399                                             attrs);
2400                 break;
2401         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2402                 err = handle_alloc_dm_sw_icm(context, dm,
2403                                              attr, attrs,
2404                                              MLX5_SW_ICM_TYPE_STEERING);
2405                 break;
2406         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2407                 err = handle_alloc_dm_sw_icm(context, dm,
2408                                              attr, attrs,
2409                                              MLX5_SW_ICM_TYPE_HEADER_MODIFY);
2410                 break;
2411         default:
2412                 err = -EOPNOTSUPP;
2413         }
2414
2415         if (err)
2416                 goto err_free;
2417
2418         return &dm->ibdm;
2419
2420 err_free:
2421         kfree(dm);
2422         return ERR_PTR(err);
2423 }
2424
2425 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs)
2426 {
2427         struct mlx5_ib_ucontext *ctx = rdma_udata_to_drv_context(
2428                 &attrs->driver_udata, struct mlx5_ib_ucontext, ibucontext);
2429         struct mlx5_core_dev *dev = to_mdev(ibdm->device)->mdev;
2430         struct mlx5_dm *dm_db = &to_mdev(ibdm->device)->dm;
2431         struct mlx5_ib_dm *dm = to_mdm(ibdm);
2432         u32 page_idx;
2433         int ret;
2434
2435         switch (dm->type) {
2436         case MLX5_IB_UAPI_DM_TYPE_MEMIC:
2437                 ret = mlx5_cmd_dealloc_memic(dm_db, dm->dev_addr, dm->size);
2438                 if (ret)
2439                         return ret;
2440
2441                 page_idx = (dm->dev_addr - pci_resource_start(dev->pdev, 0) -
2442                             MLX5_CAP64_DEV_MEM(dev, memic_bar_start_addr)) >>
2443                             PAGE_SHIFT;
2444                 bitmap_clear(ctx->dm_pages, page_idx,
2445                              DIV_ROUND_UP(dm->size, PAGE_SIZE));
2446                 break;
2447         case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
2448                 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_STEERING,
2449                                              dm->size, ctx->devx_uid, dm->dev_addr,
2450                                              dm->icm_dm.obj_id);
2451                 if (ret)
2452                         return ret;
2453                 break;
2454         case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
2455                 ret = mlx5_dm_sw_icm_dealloc(dev, MLX5_SW_ICM_TYPE_HEADER_MODIFY,
2456                                              dm->size, ctx->devx_uid, dm->dev_addr,
2457                                              dm->icm_dm.obj_id);
2458                 if (ret)
2459                         return ret;
2460                 break;
2461         default:
2462                 return -EOPNOTSUPP;
2463         }
2464
2465         kfree(dm);
2466
2467         return 0;
2468 }
2469
2470 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2471 {
2472         struct mlx5_ib_pd *pd = to_mpd(ibpd);
2473         struct ib_device *ibdev = ibpd->device;
2474         struct mlx5_ib_alloc_pd_resp resp;
2475         int err;
2476         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2477         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)]   = {};
2478         u16 uid = 0;
2479         struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2480                 udata, struct mlx5_ib_ucontext, ibucontext);
2481
2482         uid = context ? context->devx_uid : 0;
2483         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2484         MLX5_SET(alloc_pd_in, in, uid, uid);
2485         err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2486                             out, sizeof(out));
2487         if (err)
2488                 return err;
2489
2490         pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2491         pd->uid = uid;
2492         if (udata) {
2493                 resp.pdn = pd->pdn;
2494                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2495                         mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2496                         return -EFAULT;
2497                 }
2498         }
2499
2500         return 0;
2501 }
2502
2503 static void mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2504 {
2505         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2506         struct mlx5_ib_pd *mpd = to_mpd(pd);
2507
2508         mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2509 }
2510
2511 enum {
2512         MATCH_CRITERIA_ENABLE_OUTER_BIT,
2513         MATCH_CRITERIA_ENABLE_MISC_BIT,
2514         MATCH_CRITERIA_ENABLE_INNER_BIT,
2515         MATCH_CRITERIA_ENABLE_MISC2_BIT
2516 };
2517
2518 #define HEADER_IS_ZERO(match_criteria, headers)                            \
2519         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2520                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
2521
2522 static u8 get_match_criteria_enable(u32 *match_criteria)
2523 {
2524         u8 match_criteria_enable;
2525
2526         match_criteria_enable =
2527                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2528                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2529         match_criteria_enable |=
2530                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2531                 MATCH_CRITERIA_ENABLE_MISC_BIT;
2532         match_criteria_enable |=
2533                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2534                 MATCH_CRITERIA_ENABLE_INNER_BIT;
2535         match_criteria_enable |=
2536                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2537                 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2538
2539         return match_criteria_enable;
2540 }
2541
2542 static int set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2543 {
2544         u8 entry_mask;
2545         u8 entry_val;
2546         int err = 0;
2547
2548         if (!mask)
2549                 goto out;
2550
2551         entry_mask = MLX5_GET(fte_match_set_lyr_2_4, outer_c,
2552                               ip_protocol);
2553         entry_val = MLX5_GET(fte_match_set_lyr_2_4, outer_v,
2554                              ip_protocol);
2555         if (!entry_mask) {
2556                 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2557                 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2558                 goto out;
2559         }
2560         /* Don't override existing ip protocol */
2561         if (mask != entry_mask || val != entry_val)
2562                 err = -EINVAL;
2563 out:
2564         return err;
2565 }
2566
2567 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2568                            bool inner)
2569 {
2570         if (inner) {
2571                 MLX5_SET(fte_match_set_misc,
2572                          misc_c, inner_ipv6_flow_label, mask);
2573                 MLX5_SET(fte_match_set_misc,
2574                          misc_v, inner_ipv6_flow_label, val);
2575         } else {
2576                 MLX5_SET(fte_match_set_misc,
2577                          misc_c, outer_ipv6_flow_label, mask);
2578                 MLX5_SET(fte_match_set_misc,
2579                          misc_v, outer_ipv6_flow_label, val);
2580         }
2581 }
2582
2583 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2584 {
2585         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2586         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2587         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2588         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2589 }
2590
2591 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2592 {
2593         if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2594             !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2595                 return -EOPNOTSUPP;
2596
2597         if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2598             !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2599                 return -EOPNOTSUPP;
2600
2601         if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2602             !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2603                 return -EOPNOTSUPP;
2604
2605         if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2606             !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2607                 return -EOPNOTSUPP;
2608
2609         return 0;
2610 }
2611
2612 #define LAST_ETH_FIELD vlan_tag
2613 #define LAST_IB_FIELD sl
2614 #define LAST_IPV4_FIELD tos
2615 #define LAST_IPV6_FIELD traffic_class
2616 #define LAST_TCP_UDP_FIELD src_port
2617 #define LAST_TUNNEL_FIELD tunnel_id
2618 #define LAST_FLOW_TAG_FIELD tag_id
2619 #define LAST_DROP_FIELD size
2620 #define LAST_COUNTERS_FIELD counters
2621
2622 /* Field is the last supported field */
2623 #define FIELDS_NOT_SUPPORTED(filter, field)\
2624         memchr_inv((void *)&filter.field  +\
2625                    sizeof(filter.field), 0,\
2626                    sizeof(filter) -\
2627                    offsetof(typeof(filter), field) -\
2628                    sizeof(filter.field))
2629
2630 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2631                            bool is_egress,
2632                            struct mlx5_flow_act *action)
2633 {
2634
2635         switch (maction->ib_action.type) {
2636         case IB_FLOW_ACTION_ESP:
2637                 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2638                                       MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2639                         return -EINVAL;
2640                 /* Currently only AES_GCM keymat is supported by the driver */
2641                 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2642                 action->action |= is_egress ?
2643                         MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2644                         MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2645                 return 0;
2646         case IB_FLOW_ACTION_UNSPECIFIED:
2647                 if (maction->flow_action_raw.sub_type ==
2648                     MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2649                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2650                                 return -EINVAL;
2651                         action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2652                         action->modify_hdr =
2653                                 maction->flow_action_raw.modify_hdr;
2654                         return 0;
2655                 }
2656                 if (maction->flow_action_raw.sub_type ==
2657                     MLX5_IB_FLOW_ACTION_DECAP) {
2658                         if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2659                                 return -EINVAL;
2660                         action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2661                         return 0;
2662                 }
2663                 if (maction->flow_action_raw.sub_type ==
2664                     MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2665                         if (action->action &
2666                             MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2667                                 return -EINVAL;
2668                         action->action |=
2669                                 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2670                         action->pkt_reformat =
2671                                 maction->flow_action_raw.pkt_reformat;
2672                         return 0;
2673                 }
2674                 /* fall through */
2675         default:
2676                 return -EOPNOTSUPP;
2677         }
2678 }
2679
2680 static int parse_flow_attr(struct mlx5_core_dev *mdev,
2681                            struct mlx5_flow_spec *spec,
2682                            const union ib_flow_spec *ib_spec,
2683                            const struct ib_flow_attr *flow_attr,
2684                            struct mlx5_flow_act *action, u32 prev_type)
2685 {
2686         struct mlx5_flow_context *flow_context = &spec->flow_context;
2687         u32 *match_c = spec->match_criteria;
2688         u32 *match_v = spec->match_value;
2689         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2690                                            misc_parameters);
2691         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2692                                            misc_parameters);
2693         void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2694                                             misc_parameters_2);
2695         void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2696                                             misc_parameters_2);
2697         void *headers_c;
2698         void *headers_v;
2699         int match_ipv;
2700         int ret;
2701
2702         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2703                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2704                                          inner_headers);
2705                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2706                                          inner_headers);
2707                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2708                                         ft_field_support.inner_ip_version);
2709         } else {
2710                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2711                                          outer_headers);
2712                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2713                                          outer_headers);
2714                 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2715                                         ft_field_support.outer_ip_version);
2716         }
2717
2718         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2719         case IB_FLOW_SPEC_ETH:
2720                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2721                         return -EOPNOTSUPP;
2722
2723                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2724                                              dmac_47_16),
2725                                 ib_spec->eth.mask.dst_mac);
2726                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2727                                              dmac_47_16),
2728                                 ib_spec->eth.val.dst_mac);
2729
2730                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2731                                              smac_47_16),
2732                                 ib_spec->eth.mask.src_mac);
2733                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2734                                              smac_47_16),
2735                                 ib_spec->eth.val.src_mac);
2736
2737                 if (ib_spec->eth.mask.vlan_tag) {
2738                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2739                                  cvlan_tag, 1);
2740                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2741                                  cvlan_tag, 1);
2742
2743                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2744                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2745                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2746                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2747
2748                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2749                                  first_cfi,
2750                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2751                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2752                                  first_cfi,
2753                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2754
2755                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2756                                  first_prio,
2757                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2758                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2759                                  first_prio,
2760                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2761                 }
2762                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2763                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
2764                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2765                          ethertype, ntohs(ib_spec->eth.val.ether_type));
2766                 break;
2767         case IB_FLOW_SPEC_IPV4:
2768                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2769                         return -EOPNOTSUPP;
2770
2771                 if (match_ipv) {
2772                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2773                                  ip_version, 0xf);
2774                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2775                                  ip_version, MLX5_FS_IPV4_VERSION);
2776                 } else {
2777                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2778                                  ethertype, 0xffff);
2779                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2780                                  ethertype, ETH_P_IP);
2781                 }
2782
2783                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2784                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2785                        &ib_spec->ipv4.mask.src_ip,
2786                        sizeof(ib_spec->ipv4.mask.src_ip));
2787                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2788                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
2789                        &ib_spec->ipv4.val.src_ip,
2790                        sizeof(ib_spec->ipv4.val.src_ip));
2791                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2792                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2793                        &ib_spec->ipv4.mask.dst_ip,
2794                        sizeof(ib_spec->ipv4.mask.dst_ip));
2795                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2796                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2797                        &ib_spec->ipv4.val.dst_ip,
2798                        sizeof(ib_spec->ipv4.val.dst_ip));
2799
2800                 set_tos(headers_c, headers_v,
2801                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2802
2803                 if (set_proto(headers_c, headers_v,
2804                               ib_spec->ipv4.mask.proto,
2805                               ib_spec->ipv4.val.proto))
2806                         return -EINVAL;
2807                 break;
2808         case IB_FLOW_SPEC_IPV6:
2809                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2810                         return -EOPNOTSUPP;
2811
2812                 if (match_ipv) {
2813                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2814                                  ip_version, 0xf);
2815                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2816                                  ip_version, MLX5_FS_IPV6_VERSION);
2817                 } else {
2818                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2819                                  ethertype, 0xffff);
2820                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2821                                  ethertype, ETH_P_IPV6);
2822                 }
2823
2824                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2825                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2826                        &ib_spec->ipv6.mask.src_ip,
2827                        sizeof(ib_spec->ipv6.mask.src_ip));
2828                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2829                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
2830                        &ib_spec->ipv6.val.src_ip,
2831                        sizeof(ib_spec->ipv6.val.src_ip));
2832                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2833                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2834                        &ib_spec->ipv6.mask.dst_ip,
2835                        sizeof(ib_spec->ipv6.mask.dst_ip));
2836                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2837                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2838                        &ib_spec->ipv6.val.dst_ip,
2839                        sizeof(ib_spec->ipv6.val.dst_ip));
2840
2841                 set_tos(headers_c, headers_v,
2842                         ib_spec->ipv6.mask.traffic_class,
2843                         ib_spec->ipv6.val.traffic_class);
2844
2845                 if (set_proto(headers_c, headers_v,
2846                               ib_spec->ipv6.mask.next_hdr,
2847                               ib_spec->ipv6.val.next_hdr))
2848                         return -EINVAL;
2849
2850                 set_flow_label(misc_params_c, misc_params_v,
2851                                ntohl(ib_spec->ipv6.mask.flow_label),
2852                                ntohl(ib_spec->ipv6.val.flow_label),
2853                                ib_spec->type & IB_FLOW_SPEC_INNER);
2854                 break;
2855         case IB_FLOW_SPEC_ESP:
2856                 if (ib_spec->esp.mask.seq)
2857                         return -EOPNOTSUPP;
2858
2859                 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2860                          ntohl(ib_spec->esp.mask.spi));
2861                 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2862                          ntohl(ib_spec->esp.val.spi));
2863                 break;
2864         case IB_FLOW_SPEC_TCP:
2865                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2866                                          LAST_TCP_UDP_FIELD))
2867                         return -EOPNOTSUPP;
2868
2869                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_TCP))
2870                         return -EINVAL;
2871
2872                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2873                          ntohs(ib_spec->tcp_udp.mask.src_port));
2874                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2875                          ntohs(ib_spec->tcp_udp.val.src_port));
2876
2877                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2878                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2879                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2880                          ntohs(ib_spec->tcp_udp.val.dst_port));
2881                 break;
2882         case IB_FLOW_SPEC_UDP:
2883                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2884                                          LAST_TCP_UDP_FIELD))
2885                         return -EOPNOTSUPP;
2886
2887                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_UDP))
2888                         return -EINVAL;
2889
2890                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2891                          ntohs(ib_spec->tcp_udp.mask.src_port));
2892                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2893                          ntohs(ib_spec->tcp_udp.val.src_port));
2894
2895                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2896                          ntohs(ib_spec->tcp_udp.mask.dst_port));
2897                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2898                          ntohs(ib_spec->tcp_udp.val.dst_port));
2899                 break;
2900         case IB_FLOW_SPEC_GRE:
2901                 if (ib_spec->gre.mask.c_ks_res0_ver)
2902                         return -EOPNOTSUPP;
2903
2904                 if (set_proto(headers_c, headers_v, 0xff, IPPROTO_GRE))
2905                         return -EINVAL;
2906
2907                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2908                          0xff);
2909                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2910                          IPPROTO_GRE);
2911
2912                 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2913                          ntohs(ib_spec->gre.mask.protocol));
2914                 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2915                          ntohs(ib_spec->gre.val.protocol));
2916
2917                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2918                                     gre_key.nvgre.hi),
2919                        &ib_spec->gre.mask.key,
2920                        sizeof(ib_spec->gre.mask.key));
2921                 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2922                                     gre_key.nvgre.hi),
2923                        &ib_spec->gre.val.key,
2924                        sizeof(ib_spec->gre.val.key));
2925                 break;
2926         case IB_FLOW_SPEC_MPLS:
2927                 switch (prev_type) {
2928                 case IB_FLOW_SPEC_UDP:
2929                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2930                                                    ft_field_support.outer_first_mpls_over_udp),
2931                                                    &ib_spec->mpls.mask.tag))
2932                                 return -EOPNOTSUPP;
2933
2934                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2935                                             outer_first_mpls_over_udp),
2936                                &ib_spec->mpls.val.tag,
2937                                sizeof(ib_spec->mpls.val.tag));
2938                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2939                                             outer_first_mpls_over_udp),
2940                                &ib_spec->mpls.mask.tag,
2941                                sizeof(ib_spec->mpls.mask.tag));
2942                         break;
2943                 case IB_FLOW_SPEC_GRE:
2944                         if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2945                                                    ft_field_support.outer_first_mpls_over_gre),
2946                                                    &ib_spec->mpls.mask.tag))
2947                                 return -EOPNOTSUPP;
2948
2949                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2950                                             outer_first_mpls_over_gre),
2951                                &ib_spec->mpls.val.tag,
2952                                sizeof(ib_spec->mpls.val.tag));
2953                         memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2954                                             outer_first_mpls_over_gre),
2955                                &ib_spec->mpls.mask.tag,
2956                                sizeof(ib_spec->mpls.mask.tag));
2957                         break;
2958                 default:
2959                         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2960                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2961                                                            ft_field_support.inner_first_mpls),
2962                                                            &ib_spec->mpls.mask.tag))
2963                                         return -EOPNOTSUPP;
2964
2965                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2966                                                     inner_first_mpls),
2967                                        &ib_spec->mpls.val.tag,
2968                                        sizeof(ib_spec->mpls.val.tag));
2969                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2970                                                     inner_first_mpls),
2971                                        &ib_spec->mpls.mask.tag,
2972                                        sizeof(ib_spec->mpls.mask.tag));
2973                         } else {
2974                                 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2975                                                            ft_field_support.outer_first_mpls),
2976                                                            &ib_spec->mpls.mask.tag))
2977                                         return -EOPNOTSUPP;
2978
2979                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2980                                                     outer_first_mpls),
2981                                        &ib_spec->mpls.val.tag,
2982                                        sizeof(ib_spec->mpls.val.tag));
2983                                 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2984                                                     outer_first_mpls),
2985                                        &ib_spec->mpls.mask.tag,
2986                                        sizeof(ib_spec->mpls.mask.tag));
2987                         }
2988                 }
2989                 break;
2990         case IB_FLOW_SPEC_VXLAN_TUNNEL:
2991                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2992                                          LAST_TUNNEL_FIELD))
2993                         return -EOPNOTSUPP;
2994
2995                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2996                          ntohl(ib_spec->tunnel.mask.tunnel_id));
2997                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2998                          ntohl(ib_spec->tunnel.val.tunnel_id));
2999                 break;
3000         case IB_FLOW_SPEC_ACTION_TAG:
3001                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
3002                                          LAST_FLOW_TAG_FIELD))
3003                         return -EOPNOTSUPP;
3004                 if (ib_spec->flow_tag.tag_id >= BIT(24))
3005                         return -EINVAL;
3006
3007                 flow_context->flow_tag = ib_spec->flow_tag.tag_id;
3008                 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
3009                 break;
3010         case IB_FLOW_SPEC_ACTION_DROP:
3011                 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
3012                                          LAST_DROP_FIELD))
3013                         return -EOPNOTSUPP;
3014                 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3015                 break;
3016         case IB_FLOW_SPEC_ACTION_HANDLE:
3017                 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
3018                         flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
3019                 if (ret)
3020                         return ret;
3021                 break;
3022         case IB_FLOW_SPEC_ACTION_COUNT:
3023                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
3024                                          LAST_COUNTERS_FIELD))
3025                         return -EOPNOTSUPP;
3026
3027                 /* for now support only one counters spec per flow */
3028                 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
3029                         return -EINVAL;
3030
3031                 action->counters = ib_spec->flow_count.counters;
3032                 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3033                 break;
3034         default:
3035                 return -EINVAL;
3036         }
3037
3038         return 0;
3039 }
3040
3041 /* If a flow could catch both multicast and unicast packets,
3042  * it won't fall into the multicast flow steering table and this rule
3043  * could steal other multicast packets.
3044  */
3045 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
3046 {
3047         union ib_flow_spec *flow_spec;
3048
3049         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
3050             ib_attr->num_of_specs < 1)
3051                 return false;
3052
3053         flow_spec = (union ib_flow_spec *)(ib_attr + 1);
3054         if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
3055                 struct ib_flow_spec_ipv4 *ipv4_spec;
3056
3057                 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
3058                 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
3059                         return true;
3060
3061                 return false;
3062         }
3063
3064         if (flow_spec->type == IB_FLOW_SPEC_ETH) {
3065                 struct ib_flow_spec_eth *eth_spec;
3066
3067                 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
3068                 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
3069                        is_multicast_ether_addr(eth_spec->val.dst_mac);
3070         }
3071
3072         return false;
3073 }
3074
3075 enum valid_spec {
3076         VALID_SPEC_INVALID,
3077         VALID_SPEC_VALID,
3078         VALID_SPEC_NA,
3079 };
3080
3081 static enum valid_spec
3082 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
3083                      const struct mlx5_flow_spec *spec,
3084                      const struct mlx5_flow_act *flow_act,
3085                      bool egress)
3086 {
3087         const u32 *match_c = spec->match_criteria;
3088         bool is_crypto =
3089                 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
3090                                      MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
3091         bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
3092         bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
3093
3094         /*
3095          * Currently only crypto is supported in egress, when regular egress
3096          * rules would be supported, always return VALID_SPEC_NA.
3097          */
3098         if (!is_crypto)
3099                 return VALID_SPEC_NA;
3100
3101         return is_crypto && is_ipsec &&
3102                 (!egress || (!is_drop &&
3103                              !(spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG))) ?
3104                 VALID_SPEC_VALID : VALID_SPEC_INVALID;
3105 }
3106
3107 static bool is_valid_spec(struct mlx5_core_dev *mdev,
3108                           const struct mlx5_flow_spec *spec,
3109                           const struct mlx5_flow_act *flow_act,
3110                           bool egress)
3111 {
3112         /* We curretly only support ipsec egress flow */
3113         return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
3114 }
3115
3116 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
3117                                const struct ib_flow_attr *flow_attr,
3118                                bool check_inner)
3119 {
3120         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
3121         int match_ipv = check_inner ?
3122                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3123                                         ft_field_support.inner_ip_version) :
3124                         MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3125                                         ft_field_support.outer_ip_version);
3126         int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
3127         bool ipv4_spec_valid, ipv6_spec_valid;
3128         unsigned int ip_spec_type = 0;
3129         bool has_ethertype = false;
3130         unsigned int spec_index;
3131         bool mask_valid = true;
3132         u16 eth_type = 0;
3133         bool type_valid;
3134
3135         /* Validate that ethertype is correct */
3136         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3137                 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
3138                     ib_spec->eth.mask.ether_type) {
3139                         mask_valid = (ib_spec->eth.mask.ether_type ==
3140                                       htons(0xffff));
3141                         has_ethertype = true;
3142                         eth_type = ntohs(ib_spec->eth.val.ether_type);
3143                 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
3144                            (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
3145                         ip_spec_type = ib_spec->type;
3146                 }
3147                 ib_spec = (void *)ib_spec + ib_spec->size;
3148         }
3149
3150         type_valid = (!has_ethertype) || (!ip_spec_type);
3151         if (!type_valid && mask_valid) {
3152                 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
3153                         (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
3154                 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
3155                         (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
3156
3157                 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
3158                              (((eth_type == ETH_P_MPLS_UC) ||
3159                                (eth_type == ETH_P_MPLS_MC)) && match_ipv);
3160         }
3161
3162         return type_valid;
3163 }
3164
3165 static bool is_valid_attr(struct mlx5_core_dev *mdev,
3166                           const struct ib_flow_attr *flow_attr)
3167 {
3168         return is_valid_ethertype(mdev, flow_attr, false) &&
3169                is_valid_ethertype(mdev, flow_attr, true);
3170 }
3171
3172 static void put_flow_table(struct mlx5_ib_dev *dev,
3173                            struct mlx5_ib_flow_prio *prio, bool ft_added)
3174 {
3175         prio->refcount -= !!ft_added;
3176         if (!prio->refcount) {
3177                 mlx5_destroy_flow_table(prio->flow_table);
3178                 prio->flow_table = NULL;
3179         }
3180 }
3181
3182 static void counters_clear_description(struct ib_counters *counters)
3183 {
3184         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3185
3186         mutex_lock(&mcounters->mcntrs_mutex);
3187         kfree(mcounters->counters_data);
3188         mcounters->counters_data = NULL;
3189         mcounters->cntrs_max_index = 0;
3190         mutex_unlock(&mcounters->mcntrs_mutex);
3191 }
3192
3193 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
3194 {
3195         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
3196                                                           struct mlx5_ib_flow_handler,
3197                                                           ibflow);
3198         struct mlx5_ib_flow_handler *iter, *tmp;
3199         struct mlx5_ib_dev *dev = handler->dev;
3200
3201         mutex_lock(&dev->flow_db->lock);
3202
3203         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3204                 mlx5_del_flow_rules(iter->rule);
3205                 put_flow_table(dev, iter->prio, true);
3206                 list_del(&iter->list);
3207                 kfree(iter);
3208         }
3209
3210         mlx5_del_flow_rules(handler->rule);
3211         put_flow_table(dev, handler->prio, true);
3212         if (handler->ibcounters &&
3213             atomic_read(&handler->ibcounters->usecnt) == 1)
3214                 counters_clear_description(handler->ibcounters);
3215
3216         mutex_unlock(&dev->flow_db->lock);
3217         if (handler->flow_matcher)
3218                 atomic_dec(&handler->flow_matcher->usecnt);
3219         kfree(handler);
3220
3221         return 0;
3222 }
3223
3224 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3225 {
3226         priority *= 2;
3227         if (!dont_trap)
3228                 priority++;
3229         return priority;
3230 }
3231
3232 enum flow_table_type {
3233         MLX5_IB_FT_RX,
3234         MLX5_IB_FT_TX
3235 };
3236
3237 #define MLX5_FS_MAX_TYPES        6
3238 #define MLX5_FS_MAX_ENTRIES      BIT(16)
3239
3240 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3241                                            struct mlx5_ib_flow_prio *prio,
3242                                            int priority,
3243                                            int num_entries, int num_groups,
3244                                            u32 flags)
3245 {
3246         struct mlx5_flow_table *ft;
3247
3248         ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3249                                                  num_entries,
3250                                                  num_groups,
3251                                                  0, flags);
3252         if (IS_ERR(ft))
3253                 return ERR_CAST(ft);
3254
3255         prio->flow_table = ft;
3256         prio->refcount = 0;
3257         return prio;
3258 }
3259
3260 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3261                                                 struct ib_flow_attr *flow_attr,
3262                                                 enum flow_table_type ft_type)
3263 {
3264         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3265         struct mlx5_flow_namespace *ns = NULL;
3266         struct mlx5_ib_flow_prio *prio;
3267         struct mlx5_flow_table *ft;
3268         int max_table_size;
3269         int num_entries;
3270         int num_groups;
3271         bool esw_encap;
3272         u32 flags = 0;
3273         int priority;
3274
3275         max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3276                                                        log_max_ft_size));
3277         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3278                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3279         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3280                 enum mlx5_flow_namespace_type fn_type;
3281
3282                 if (flow_is_multicast_only(flow_attr) &&
3283                     !dont_trap)
3284                         priority = MLX5_IB_FLOW_MCAST_PRIO;
3285                 else
3286                         priority = ib_prio_to_core_prio(flow_attr->priority,
3287                                                         dont_trap);
3288                 if (ft_type == MLX5_IB_FT_RX) {
3289                         fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3290                         prio = &dev->flow_db->prios[priority];
3291                         if (!dev->is_rep && !esw_encap &&
3292                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3293                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3294                         if (!dev->is_rep && !esw_encap &&
3295                             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3296                                         reformat_l3_tunnel_to_l2))
3297                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3298                 } else {
3299                         max_table_size =
3300                                 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3301                                                               log_max_ft_size));
3302                         fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3303                         prio = &dev->flow_db->egress_prios[priority];
3304                         if (!dev->is_rep && !esw_encap &&
3305                             MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3306                                 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3307                 }
3308                 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3309                 num_entries = MLX5_FS_MAX_ENTRIES;
3310                 num_groups = MLX5_FS_MAX_TYPES;
3311         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3312                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3313                 ns = mlx5_get_flow_namespace(dev->mdev,
3314                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
3315                 build_leftovers_ft_param(&priority,
3316                                          &num_entries,
3317                                          &num_groups);
3318                 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3319         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3320                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3321                                         allow_sniffer_and_nic_rx_shared_tir))
3322                         return ERR_PTR(-ENOTSUPP);
3323
3324                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3325                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3326                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3327
3328                 prio = &dev->flow_db->sniffer[ft_type];
3329                 priority = 0;
3330                 num_entries = 1;
3331                 num_groups = 1;
3332         }
3333
3334         if (!ns)
3335                 return ERR_PTR(-ENOTSUPP);
3336
3337         max_table_size = min_t(int, num_entries, max_table_size);
3338
3339         ft = prio->flow_table;
3340         if (!ft)
3341                 return _get_prio(ns, prio, priority, max_table_size, num_groups,
3342                                  flags);
3343
3344         return prio;
3345 }
3346
3347 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3348                             struct mlx5_flow_spec *spec,
3349                             u32 underlay_qpn)
3350 {
3351         void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3352                                            spec->match_criteria,
3353                                            misc_parameters);
3354         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3355                                            misc_parameters);
3356
3357         if (underlay_qpn &&
3358             MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3359                                       ft_field_support.bth_dst_qp)) {
3360                 MLX5_SET(fte_match_set_misc,
3361                          misc_params_v, bth_dst_qp, underlay_qpn);
3362                 MLX5_SET(fte_match_set_misc,
3363                          misc_params_c, bth_dst_qp, 0xffffff);
3364         }
3365 }
3366
3367 static int read_flow_counters(struct ib_device *ibdev,
3368                               struct mlx5_read_counters_attr *read_attr)
3369 {
3370         struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3371         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3372
3373         return mlx5_fc_query(dev->mdev, fc,
3374                              &read_attr->out[IB_COUNTER_PACKETS],
3375                              &read_attr->out[IB_COUNTER_BYTES]);
3376 }
3377
3378 /* flow counters currently expose two counters packets and bytes */
3379 #define FLOW_COUNTERS_NUM 2
3380 static int counters_set_description(struct ib_counters *counters,
3381                                     enum mlx5_ib_counters_type counters_type,
3382                                     struct mlx5_ib_flow_counters_desc *desc_data,
3383                                     u32 ncounters)
3384 {
3385         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3386         u32 cntrs_max_index = 0;
3387         int i;
3388
3389         if (counters_type != MLX5_IB_COUNTERS_FLOW)
3390                 return -EINVAL;
3391
3392         /* init the fields for the object */
3393         mcounters->type = counters_type;
3394         mcounters->read_counters = read_flow_counters;
3395         mcounters->counters_num = FLOW_COUNTERS_NUM;
3396         mcounters->ncounters = ncounters;
3397         /* each counter entry have both description and index pair */
3398         for (i = 0; i < ncounters; i++) {
3399                 if (desc_data[i].description > IB_COUNTER_BYTES)
3400                         return -EINVAL;
3401
3402                 if (cntrs_max_index <= desc_data[i].index)
3403                         cntrs_max_index = desc_data[i].index + 1;
3404         }
3405
3406         mutex_lock(&mcounters->mcntrs_mutex);
3407         mcounters->counters_data = desc_data;
3408         mcounters->cntrs_max_index = cntrs_max_index;
3409         mutex_unlock(&mcounters->mcntrs_mutex);
3410
3411         return 0;
3412 }
3413
3414 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3415 static int flow_counters_set_data(struct ib_counters *ibcounters,
3416                                   struct mlx5_ib_create_flow *ucmd)
3417 {
3418         struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3419         struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3420         struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3421         bool hw_hndl = false;
3422         int ret = 0;
3423
3424         if (ucmd && ucmd->ncounters_data != 0) {
3425                 cntrs_data = ucmd->data;
3426                 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3427                         return -EINVAL;
3428
3429                 desc_data = kcalloc(cntrs_data->ncounters,
3430                                     sizeof(*desc_data),
3431                                     GFP_KERNEL);
3432                 if (!desc_data)
3433                         return  -ENOMEM;
3434
3435                 if (copy_from_user(desc_data,
3436                                    u64_to_user_ptr(cntrs_data->counters_data),
3437                                    sizeof(*desc_data) * cntrs_data->ncounters)) {
3438                         ret = -EFAULT;
3439                         goto free;
3440                 }
3441         }
3442
3443         if (!mcounters->hw_cntrs_hndl) {
3444                 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3445                         to_mdev(ibcounters->device)->mdev, false);
3446                 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3447                         ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3448                         goto free;
3449                 }
3450                 hw_hndl = true;
3451         }
3452
3453         if (desc_data) {
3454                 /* counters already bound to at least one flow */
3455                 if (mcounters->cntrs_max_index) {
3456                         ret = -EINVAL;
3457                         goto free_hndl;
3458                 }
3459
3460                 ret = counters_set_description(ibcounters,
3461                                                MLX5_IB_COUNTERS_FLOW,
3462                                                desc_data,
3463                                                cntrs_data->ncounters);
3464                 if (ret)
3465                         goto free_hndl;
3466
3467         } else if (!mcounters->cntrs_max_index) {
3468                 /* counters not bound yet, must have udata passed */
3469                 ret = -EINVAL;
3470                 goto free_hndl;
3471         }
3472
3473         return 0;
3474
3475 free_hndl:
3476         if (hw_hndl) {
3477                 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3478                                 mcounters->hw_cntrs_hndl);
3479                 mcounters->hw_cntrs_hndl = NULL;
3480         }
3481 free:
3482         kfree(desc_data);
3483         return ret;
3484 }
3485
3486 static void mlx5_ib_set_rule_source_port(struct mlx5_ib_dev *dev,
3487                                          struct mlx5_flow_spec *spec,
3488                                          struct mlx5_eswitch_rep *rep)
3489 {
3490         struct mlx5_eswitch *esw = dev->mdev->priv.eswitch;
3491         void *misc;
3492
3493         if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
3494                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3495                                     misc_parameters_2);
3496
3497                 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
3498                          mlx5_eswitch_get_vport_metadata_for_match(esw,
3499                                                                    rep->vport));
3500                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3501                                     misc_parameters_2);
3502
3503                 MLX5_SET_TO_ONES(fte_match_set_misc2, misc, metadata_reg_c_0);
3504         } else {
3505                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3506                                     misc_parameters);
3507
3508                 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport);
3509
3510                 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3511                                     misc_parameters);
3512
3513                 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3514         }
3515 }
3516
3517 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3518                                                       struct mlx5_ib_flow_prio *ft_prio,
3519                                                       const struct ib_flow_attr *flow_attr,
3520                                                       struct mlx5_flow_destination *dst,
3521                                                       u32 underlay_qpn,
3522                                                       struct mlx5_ib_create_flow *ucmd)
3523 {
3524         struct mlx5_flow_table  *ft = ft_prio->flow_table;
3525         struct mlx5_ib_flow_handler *handler;
3526         struct mlx5_flow_act flow_act = {};
3527         struct mlx5_flow_spec *spec;
3528         struct mlx5_flow_destination dest_arr[2] = {};
3529         struct mlx5_flow_destination *rule_dst = dest_arr;
3530         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3531         unsigned int spec_index;
3532         u32 prev_type = 0;
3533         int err = 0;
3534         int dest_num = 0;
3535         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3536
3537         if (!is_valid_attr(dev->mdev, flow_attr))
3538                 return ERR_PTR(-EINVAL);
3539
3540         if (dev->is_rep && is_egress)
3541                 return ERR_PTR(-EINVAL);
3542
3543         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3544         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3545         if (!handler || !spec) {
3546                 err = -ENOMEM;
3547                 goto free;
3548         }
3549
3550         INIT_LIST_HEAD(&handler->list);
3551         if (dst) {
3552                 memcpy(&dest_arr[0], dst, sizeof(*dst));
3553                 dest_num++;
3554         }
3555
3556         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3557                 err = parse_flow_attr(dev->mdev, spec,
3558                                       ib_flow, flow_attr, &flow_act,
3559                                       prev_type);
3560                 if (err < 0)
3561                         goto free;
3562
3563                 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3564                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3565         }
3566
3567         if (!flow_is_multicast_only(flow_attr))
3568                 set_underlay_qp(dev, spec, underlay_qpn);
3569
3570         if (dev->is_rep) {
3571                 struct mlx5_eswitch_rep *rep;
3572
3573                 rep = dev->port[flow_attr->port - 1].rep;
3574                 if (!rep) {
3575                         err = -EINVAL;
3576                         goto free;
3577                 }
3578
3579                 mlx5_ib_set_rule_source_port(dev, spec, rep);
3580         }
3581
3582         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3583
3584         if (is_egress &&
3585             !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3586                 err = -EINVAL;
3587                 goto free;
3588         }
3589
3590         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3591                 struct mlx5_ib_mcounters *mcounters;
3592
3593                 err = flow_counters_set_data(flow_act.counters, ucmd);
3594                 if (err)
3595                         goto free;
3596
3597                 mcounters = to_mcounters(flow_act.counters);
3598                 handler->ibcounters = flow_act.counters;
3599                 dest_arr[dest_num].type =
3600                         MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3601                 dest_arr[dest_num].counter_id =
3602                         mlx5_fc_id(mcounters->hw_cntrs_hndl);
3603                 dest_num++;
3604         }
3605
3606         if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3607                 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3608                         rule_dst = NULL;
3609                         dest_num = 0;
3610                 }
3611         } else {
3612                 if (is_egress)
3613                         flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3614                 else
3615                         flow_act.action |=
3616                                 dest_num ?  MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3617                                         MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3618         }
3619
3620         if ((spec->flow_context.flags & FLOW_CONTEXT_HAS_TAG)  &&
3621             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3622              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3623                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3624                              spec->flow_context.flow_tag, flow_attr->type);
3625                 err = -EINVAL;
3626                 goto free;
3627         }
3628         handler->rule = mlx5_add_flow_rules(ft, spec,
3629                                             &flow_act,
3630                                             rule_dst, dest_num);
3631
3632         if (IS_ERR(handler->rule)) {
3633                 err = PTR_ERR(handler->rule);
3634                 goto free;
3635         }
3636
3637         ft_prio->refcount++;
3638         handler->prio = ft_prio;
3639         handler->dev = dev;
3640
3641         ft_prio->flow_table = ft;
3642 free:
3643         if (err && handler) {
3644                 if (handler->ibcounters &&
3645                     atomic_read(&handler->ibcounters->usecnt) == 1)
3646                         counters_clear_description(handler->ibcounters);
3647                 kfree(handler);
3648         }
3649         kvfree(spec);
3650         return err ? ERR_PTR(err) : handler;
3651 }
3652
3653 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3654                                                      struct mlx5_ib_flow_prio *ft_prio,
3655                                                      const struct ib_flow_attr *flow_attr,
3656                                                      struct mlx5_flow_destination *dst)
3657 {
3658         return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3659 }
3660
3661 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3662                                                           struct mlx5_ib_flow_prio *ft_prio,
3663                                                           struct ib_flow_attr *flow_attr,
3664                                                           struct mlx5_flow_destination *dst)
3665 {
3666         struct mlx5_ib_flow_handler *handler_dst = NULL;
3667         struct mlx5_ib_flow_handler *handler = NULL;
3668
3669         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3670         if (!IS_ERR(handler)) {
3671                 handler_dst = create_flow_rule(dev, ft_prio,
3672                                                flow_attr, dst);
3673                 if (IS_ERR(handler_dst)) {
3674                         mlx5_del_flow_rules(handler->rule);
3675                         ft_prio->refcount--;
3676                         kfree(handler);
3677                         handler = handler_dst;
3678                 } else {
3679                         list_add(&handler_dst->list, &handler->list);
3680                 }
3681         }
3682
3683         return handler;
3684 }
3685 enum {
3686         LEFTOVERS_MC,
3687         LEFTOVERS_UC,
3688 };
3689
3690 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3691                                                           struct mlx5_ib_flow_prio *ft_prio,
3692                                                           struct ib_flow_attr *flow_attr,
3693                                                           struct mlx5_flow_destination *dst)
3694 {
3695         struct mlx5_ib_flow_handler *handler_ucast = NULL;
3696         struct mlx5_ib_flow_handler *handler = NULL;
3697
3698         static struct {
3699                 struct ib_flow_attr     flow_attr;
3700                 struct ib_flow_spec_eth eth_flow;
3701         } leftovers_specs[] = {
3702                 [LEFTOVERS_MC] = {
3703                         .flow_attr = {
3704                                 .num_of_specs = 1,
3705                                 .size = sizeof(leftovers_specs[0])
3706                         },
3707                         .eth_flow = {
3708                                 .type = IB_FLOW_SPEC_ETH,
3709                                 .size = sizeof(struct ib_flow_spec_eth),
3710                                 .mask = {.dst_mac = {0x1} },
3711                                 .val =  {.dst_mac = {0x1} }
3712                         }
3713                 },
3714                 [LEFTOVERS_UC] = {
3715                         .flow_attr = {
3716                                 .num_of_specs = 1,
3717                                 .size = sizeof(leftovers_specs[0])
3718                         },
3719                         .eth_flow = {
3720                                 .type = IB_FLOW_SPEC_ETH,
3721                                 .size = sizeof(struct ib_flow_spec_eth),
3722                                 .mask = {.dst_mac = {0x1} },
3723                                 .val = {.dst_mac = {} }
3724                         }
3725                 }
3726         };
3727
3728         handler = create_flow_rule(dev, ft_prio,
3729                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
3730                                    dst);
3731         if (!IS_ERR(handler) &&
3732             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3733                 handler_ucast = create_flow_rule(dev, ft_prio,
3734                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
3735                                                  dst);
3736                 if (IS_ERR(handler_ucast)) {
3737                         mlx5_del_flow_rules(handler->rule);
3738                         ft_prio->refcount--;
3739                         kfree(handler);
3740                         handler = handler_ucast;
3741                 } else {
3742                         list_add(&handler_ucast->list, &handler->list);
3743                 }
3744         }
3745
3746         return handler;
3747 }
3748
3749 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3750                                                         struct mlx5_ib_flow_prio *ft_rx,
3751                                                         struct mlx5_ib_flow_prio *ft_tx,
3752                                                         struct mlx5_flow_destination *dst)
3753 {
3754         struct mlx5_ib_flow_handler *handler_rx;
3755         struct mlx5_ib_flow_handler *handler_tx;
3756         int err;
3757         static const struct ib_flow_attr flow_attr  = {
3758                 .num_of_specs = 0,
3759                 .size = sizeof(flow_attr)
3760         };
3761
3762         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3763         if (IS_ERR(handler_rx)) {
3764                 err = PTR_ERR(handler_rx);
3765                 goto err;
3766         }
3767
3768         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3769         if (IS_ERR(handler_tx)) {
3770                 err = PTR_ERR(handler_tx);
3771                 goto err_tx;
3772         }
3773
3774         list_add(&handler_tx->list, &handler_rx->list);
3775
3776         return handler_rx;
3777
3778 err_tx:
3779         mlx5_del_flow_rules(handler_rx->rule);
3780         ft_rx->refcount--;
3781         kfree(handler_rx);
3782 err:
3783         return ERR_PTR(err);
3784 }
3785
3786 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3787                                            struct ib_flow_attr *flow_attr,
3788                                            int domain,
3789                                            struct ib_udata *udata)
3790 {
3791         struct mlx5_ib_dev *dev = to_mdev(qp->device);
3792         struct mlx5_ib_qp *mqp = to_mqp(qp);
3793         struct mlx5_ib_flow_handler *handler = NULL;
3794         struct mlx5_flow_destination *dst = NULL;
3795         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3796         struct mlx5_ib_flow_prio *ft_prio;
3797         bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3798         struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3799         size_t min_ucmd_sz, required_ucmd_sz;
3800         int err;
3801         int underlay_qpn;
3802
3803         if (udata && udata->inlen) {
3804                 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3805                                 sizeof(ucmd_hdr.reserved);
3806                 if (udata->inlen < min_ucmd_sz)
3807                         return ERR_PTR(-EOPNOTSUPP);
3808
3809                 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3810                 if (err)
3811                         return ERR_PTR(err);
3812
3813                 /* currently supports only one counters data */
3814                 if (ucmd_hdr.ncounters_data > 1)
3815                         return ERR_PTR(-EINVAL);
3816
3817                 required_ucmd_sz = min_ucmd_sz +
3818                         sizeof(struct mlx5_ib_flow_counters_data) *
3819                         ucmd_hdr.ncounters_data;
3820                 if (udata->inlen > required_ucmd_sz &&
3821                     !ib_is_udata_cleared(udata, required_ucmd_sz,
3822                                          udata->inlen - required_ucmd_sz))
3823                         return ERR_PTR(-EOPNOTSUPP);
3824
3825                 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3826                 if (!ucmd)
3827                         return ERR_PTR(-ENOMEM);
3828
3829                 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3830                 if (err)
3831                         goto free_ucmd;
3832         }
3833
3834         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3835                 err = -ENOMEM;
3836                 goto free_ucmd;
3837         }
3838
3839         if (domain != IB_FLOW_DOMAIN_USER ||
3840             flow_attr->port > dev->num_ports ||
3841             (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3842                                   IB_FLOW_ATTR_FLAGS_EGRESS))) {
3843                 err = -EINVAL;
3844                 goto free_ucmd;
3845         }
3846
3847         if (is_egress &&
3848             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3849              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3850                 err = -EINVAL;
3851                 goto free_ucmd;
3852         }
3853
3854         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3855         if (!dst) {
3856                 err = -ENOMEM;
3857                 goto free_ucmd;
3858         }
3859
3860         mutex_lock(&dev->flow_db->lock);
3861
3862         ft_prio = get_flow_table(dev, flow_attr,
3863                                  is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3864         if (IS_ERR(ft_prio)) {
3865                 err = PTR_ERR(ft_prio);
3866                 goto unlock;
3867         }
3868         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3869                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3870                 if (IS_ERR(ft_prio_tx)) {
3871                         err = PTR_ERR(ft_prio_tx);
3872                         ft_prio_tx = NULL;
3873                         goto destroy_ft;
3874                 }
3875         }
3876
3877         if (is_egress) {
3878                 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3879         } else {
3880                 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3881                 if (mqp->flags & MLX5_IB_QP_RSS)
3882                         dst->tir_num = mqp->rss_qp.tirn;
3883                 else
3884                         dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3885         }
3886
3887         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3888                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
3889                         handler = create_dont_trap_rule(dev, ft_prio,
3890                                                         flow_attr, dst);
3891                 } else {
3892                         underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3893                                         mqp->underlay_qpn : 0;
3894                         handler = _create_flow_rule(dev, ft_prio, flow_attr,
3895                                                     dst, underlay_qpn, ucmd);
3896                 }
3897         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3898                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3899                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3900                                                 dst);
3901         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3902                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3903         } else {
3904                 err = -EINVAL;
3905                 goto destroy_ft;
3906         }
3907
3908         if (IS_ERR(handler)) {
3909                 err = PTR_ERR(handler);
3910                 handler = NULL;
3911                 goto destroy_ft;
3912         }
3913
3914         mutex_unlock(&dev->flow_db->lock);
3915         kfree(dst);
3916         kfree(ucmd);
3917
3918         return &handler->ibflow;
3919
3920 destroy_ft:
3921         put_flow_table(dev, ft_prio, false);
3922         if (ft_prio_tx)
3923                 put_flow_table(dev, ft_prio_tx, false);
3924 unlock:
3925         mutex_unlock(&dev->flow_db->lock);
3926         kfree(dst);
3927 free_ucmd:
3928         kfree(ucmd);
3929         return ERR_PTR(err);
3930 }
3931
3932 static struct mlx5_ib_flow_prio *
3933 _get_flow_table(struct mlx5_ib_dev *dev,
3934                 struct mlx5_ib_flow_matcher *fs_matcher,
3935                 bool mcast)
3936 {
3937         struct mlx5_flow_namespace *ns = NULL;
3938         struct mlx5_ib_flow_prio *prio = NULL;
3939         int max_table_size = 0;
3940         bool esw_encap;
3941         u32 flags = 0;
3942         int priority;
3943
3944         if (mcast)
3945                 priority = MLX5_IB_FLOW_MCAST_PRIO;
3946         else
3947                 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3948
3949         esw_encap = mlx5_eswitch_get_encap_mode(dev->mdev) !=
3950                 DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3951         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3952                 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3953                                         log_max_ft_size));
3954                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap) && !esw_encap)
3955                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3956                 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3957                                               reformat_l3_tunnel_to_l2) &&
3958                     !esw_encap)
3959                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3960         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS) {
3961                 max_table_size = BIT(
3962                         MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, log_max_ft_size));
3963                 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat) && !esw_encap)
3964                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3965         } else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3966                 max_table_size = BIT(
3967                         MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, log_max_ft_size));
3968                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, decap) && esw_encap)
3969                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3970                 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev->mdev, reformat_l3_tunnel_to_l2) &&
3971                     esw_encap)
3972                         flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3973                 priority = FDB_BYPASS_PATH;
3974         }
3975
3976         max_table_size = min_t(int, max_table_size, MLX5_FS_MAX_ENTRIES);
3977
3978         ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3979         if (!ns)
3980                 return ERR_PTR(-ENOTSUPP);
3981
3982         if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3983                 prio = &dev->flow_db->prios[priority];
3984         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_EGRESS)
3985                 prio = &dev->flow_db->egress_prios[priority];
3986         else if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_FDB)
3987                 prio = &dev->flow_db->fdb;
3988
3989         if (!prio)
3990                 return ERR_PTR(-EINVAL);
3991
3992         if (prio->flow_table)
3993                 return prio;
3994
3995         return _get_prio(ns, prio, priority, max_table_size,
3996                          MLX5_FS_MAX_TYPES, flags);
3997 }
3998
3999 static struct mlx5_ib_flow_handler *
4000 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
4001                       struct mlx5_ib_flow_prio *ft_prio,
4002                       struct mlx5_flow_destination *dst,
4003                       struct mlx5_ib_flow_matcher  *fs_matcher,
4004                       struct mlx5_flow_context *flow_context,
4005                       struct mlx5_flow_act *flow_act,
4006                       void *cmd_in, int inlen,
4007                       int dst_num)
4008 {
4009         struct mlx5_ib_flow_handler *handler;
4010         struct mlx5_flow_spec *spec;
4011         struct mlx5_flow_table *ft = ft_prio->flow_table;
4012         int err = 0;
4013
4014         spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
4015         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
4016         if (!handler || !spec) {
4017                 err = -ENOMEM;
4018                 goto free;
4019         }
4020
4021         INIT_LIST_HEAD(&handler->list);
4022
4023         memcpy(spec->match_value, cmd_in, inlen);
4024         memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
4025                fs_matcher->mask_len);
4026         spec->match_criteria_enable = fs_matcher->match_criteria_enable;
4027         spec->flow_context = *flow_context;
4028
4029         handler->rule = mlx5_add_flow_rules(ft, spec,
4030                                             flow_act, dst, dst_num);
4031
4032         if (IS_ERR(handler->rule)) {
4033                 err = PTR_ERR(handler->rule);
4034                 goto free;
4035         }
4036
4037         ft_prio->refcount++;
4038         handler->prio = ft_prio;
4039         handler->dev = dev;
4040         ft_prio->flow_table = ft;
4041
4042 free:
4043         if (err)
4044                 kfree(handler);
4045         kvfree(spec);
4046         return err ? ERR_PTR(err) : handler;
4047 }
4048
4049 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
4050                                 void *match_v)
4051 {
4052         void *match_c;
4053         void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
4054         void *dmac, *dmac_mask;
4055         void *ipv4, *ipv4_mask;
4056
4057         if (!(fs_matcher->match_criteria_enable &
4058               (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
4059                 return false;
4060
4061         match_c = fs_matcher->matcher_mask.match_params;
4062         match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
4063                                            outer_headers);
4064         match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
4065                                            outer_headers);
4066
4067         dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4068                             dmac_47_16);
4069         dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4070                                  dmac_47_16);
4071
4072         if (is_multicast_ether_addr(dmac) &&
4073             is_multicast_ether_addr(dmac_mask))
4074                 return true;
4075
4076         ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
4077                             dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4078
4079         ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
4080                                  dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4081
4082         if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
4083             ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
4084                 return true;
4085
4086         return false;
4087 }
4088
4089 struct mlx5_ib_flow_handler *
4090 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
4091                         struct mlx5_ib_flow_matcher *fs_matcher,
4092                         struct mlx5_flow_context *flow_context,
4093                         struct mlx5_flow_act *flow_act,
4094                         u32 counter_id,
4095                         void *cmd_in, int inlen, int dest_id,
4096                         int dest_type)
4097 {
4098         struct mlx5_flow_destination *dst;
4099         struct mlx5_ib_flow_prio *ft_prio;
4100         struct mlx5_ib_flow_handler *handler;
4101         int dst_num = 0;
4102         bool mcast;
4103         int err;
4104
4105         if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
4106                 return ERR_PTR(-EOPNOTSUPP);
4107
4108         if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
4109                 return ERR_PTR(-ENOMEM);
4110
4111         dst = kcalloc(2, sizeof(*dst), GFP_KERNEL);
4112         if (!dst)
4113                 return ERR_PTR(-ENOMEM);
4114
4115         mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
4116         mutex_lock(&dev->flow_db->lock);
4117
4118         ft_prio = _get_flow_table(dev, fs_matcher, mcast);
4119         if (IS_ERR(ft_prio)) {
4120                 err = PTR_ERR(ft_prio);
4121                 goto unlock;
4122         }
4123
4124         if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
4125                 dst[dst_num].type = dest_type;
4126                 dst[dst_num].tir_num = dest_id;
4127                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4128         } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
4129                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
4130                 dst[dst_num].ft_num = dest_id;
4131                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4132         } else {
4133                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_PORT;
4134                 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
4135         }
4136
4137         dst_num++;
4138
4139         if (flow_act->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
4140                 dst[dst_num].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
4141                 dst[dst_num].counter_id = counter_id;
4142                 dst_num++;
4143         }
4144
4145         handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher,
4146                                         flow_context, flow_act,
4147                                         cmd_in, inlen, dst_num);
4148
4149         if (IS_ERR(handler)) {
4150                 err = PTR_ERR(handler);
4151                 goto destroy_ft;
4152         }
4153
4154         mutex_unlock(&dev->flow_db->lock);
4155         atomic_inc(&fs_matcher->usecnt);
4156         handler->flow_matcher = fs_matcher;
4157
4158         kfree(dst);
4159
4160         return handler;
4161
4162 destroy_ft:
4163         put_flow_table(dev, ft_prio, false);
4164 unlock:
4165         mutex_unlock(&dev->flow_db->lock);
4166         kfree(dst);
4167
4168         return ERR_PTR(err);
4169 }
4170
4171 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
4172 {
4173         u32 flags = 0;
4174
4175         if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
4176                 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
4177
4178         return flags;
4179 }
4180
4181 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED      MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
4182 static struct ib_flow_action *
4183 mlx5_ib_create_flow_action_esp(struct ib_device *device,
4184                                const struct ib_flow_action_attrs_esp *attr,
4185                                struct uverbs_attr_bundle *attrs)
4186 {
4187         struct mlx5_ib_dev *mdev = to_mdev(device);
4188         struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
4189         struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
4190         struct mlx5_ib_flow_action *action;
4191         u64 action_flags;
4192         u64 flags;
4193         int err = 0;
4194
4195         err = uverbs_get_flags64(
4196                 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
4197                 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
4198         if (err)
4199                 return ERR_PTR(err);
4200
4201         flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
4202
4203         /* We current only support a subset of the standard features. Only a
4204          * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4205          * (with overlap). Full offload mode isn't supported.
4206          */
4207         if (!attr->keymat || attr->replay || attr->encap ||
4208             attr->spi || attr->seq || attr->tfc_pad ||
4209             attr->hard_limit_pkts ||
4210             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4211                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
4212                 return ERR_PTR(-EOPNOTSUPP);
4213
4214         if (attr->keymat->protocol !=
4215             IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
4216                 return ERR_PTR(-EOPNOTSUPP);
4217
4218         aes_gcm = &attr->keymat->keymat.aes_gcm;
4219
4220         if (aes_gcm->icv_len != 16 ||
4221             aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
4222                 return ERR_PTR(-EOPNOTSUPP);
4223
4224         action = kmalloc(sizeof(*action), GFP_KERNEL);
4225         if (!action)
4226                 return ERR_PTR(-ENOMEM);
4227
4228         action->esp_aes_gcm.ib_flags = attr->flags;
4229         memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
4230                sizeof(accel_attrs.keymat.aes_gcm.aes_key));
4231         accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
4232         memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
4233                sizeof(accel_attrs.keymat.aes_gcm.salt));
4234         memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
4235                sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
4236         accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
4237         accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
4238         accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
4239
4240         accel_attrs.esn = attr->esn;
4241         if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
4242                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
4243         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4244                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4245
4246         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
4247                 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
4248
4249         action->esp_aes_gcm.ctx =
4250                 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
4251         if (IS_ERR(action->esp_aes_gcm.ctx)) {
4252                 err = PTR_ERR(action->esp_aes_gcm.ctx);
4253                 goto err_parse;
4254         }
4255
4256         action->esp_aes_gcm.ib_flags = attr->flags;
4257
4258         return &action->ib_action;
4259
4260 err_parse:
4261         kfree(action);
4262         return ERR_PTR(err);
4263 }
4264
4265 static int
4266 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
4267                                const struct ib_flow_action_attrs_esp *attr,
4268                                struct uverbs_attr_bundle *attrs)
4269 {
4270         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4271         struct mlx5_accel_esp_xfrm_attrs accel_attrs;
4272         int err = 0;
4273
4274         if (attr->keymat || attr->replay || attr->encap ||
4275             attr->spi || attr->seq || attr->tfc_pad ||
4276             attr->hard_limit_pkts ||
4277             (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4278                              IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
4279                              IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
4280                 return -EOPNOTSUPP;
4281
4282         /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4283          * be modified.
4284          */
4285         if (!(maction->esp_aes_gcm.ib_flags &
4286               IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
4287             attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
4288                            IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
4289                 return -EINVAL;
4290
4291         memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
4292                sizeof(accel_attrs));
4293
4294         accel_attrs.esn = attr->esn;
4295         if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4296                 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4297         else
4298                 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4299
4300         err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4301                                          &accel_attrs);
4302         if (err)
4303                 return err;
4304
4305         maction->esp_aes_gcm.ib_flags &=
4306                 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4307         maction->esp_aes_gcm.ib_flags |=
4308                 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4309
4310         return 0;
4311 }
4312
4313 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4314 {
4315         struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4316
4317         switch (action->type) {
4318         case IB_FLOW_ACTION_ESP:
4319                 /*
4320                  * We only support aes_gcm by now, so we implicitly know this is
4321                  * the underline crypto.
4322                  */
4323                 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4324                 break;
4325         case IB_FLOW_ACTION_UNSPECIFIED:
4326                 mlx5_ib_destroy_flow_action_raw(maction);
4327                 break;
4328         default:
4329                 WARN_ON(true);
4330                 break;
4331         }
4332
4333         kfree(maction);
4334         return 0;
4335 }
4336
4337 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4338 {
4339         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4340         struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4341         int err;
4342         u16 uid;
4343
4344         uid = ibqp->pd ?
4345                 to_mpd(ibqp->pd)->uid : 0;
4346
4347         if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4348                 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4349                 return -EOPNOTSUPP;
4350         }
4351
4352         err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4353         if (err)
4354                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4355                              ibqp->qp_num, gid->raw);
4356
4357         return err;
4358 }
4359
4360 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4361 {
4362         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4363         int err;
4364         u16 uid;
4365
4366         uid = ibqp->pd ?
4367                 to_mpd(ibqp->pd)->uid : 0;
4368         err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4369         if (err)
4370                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4371                              ibqp->qp_num, gid->raw);
4372
4373         return err;
4374 }
4375
4376 static int init_node_data(struct mlx5_ib_dev *dev)
4377 {
4378         int err;
4379
4380         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4381         if (err)
4382                 return err;
4383
4384         dev->mdev->rev_id = dev->mdev->pdev->revision;
4385
4386         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4387 }
4388
4389 static ssize_t fw_pages_show(struct device *device,
4390                              struct device_attribute *attr, char *buf)
4391 {
4392         struct mlx5_ib_dev *dev =
4393                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4394
4395         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4396 }
4397 static DEVICE_ATTR_RO(fw_pages);
4398
4399 static ssize_t reg_pages_show(struct device *device,
4400                               struct device_attribute *attr, char *buf)
4401 {
4402         struct mlx5_ib_dev *dev =
4403                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4404
4405         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4406 }
4407 static DEVICE_ATTR_RO(reg_pages);
4408
4409 static ssize_t hca_type_show(struct device *device,
4410                              struct device_attribute *attr, char *buf)
4411 {
4412         struct mlx5_ib_dev *dev =
4413                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4414
4415         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4416 }
4417 static DEVICE_ATTR_RO(hca_type);
4418
4419 static ssize_t hw_rev_show(struct device *device,
4420                            struct device_attribute *attr, char *buf)
4421 {
4422         struct mlx5_ib_dev *dev =
4423                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4424
4425         return sprintf(buf, "%x\n", dev->mdev->rev_id);
4426 }
4427 static DEVICE_ATTR_RO(hw_rev);
4428
4429 static ssize_t board_id_show(struct device *device,
4430                              struct device_attribute *attr, char *buf)
4431 {
4432         struct mlx5_ib_dev *dev =
4433                 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
4434
4435         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4436                        dev->mdev->board_id);
4437 }
4438 static DEVICE_ATTR_RO(board_id);
4439
4440 static struct attribute *mlx5_class_attributes[] = {
4441         &dev_attr_hw_rev.attr,
4442         &dev_attr_hca_type.attr,
4443         &dev_attr_board_id.attr,
4444         &dev_attr_fw_pages.attr,
4445         &dev_attr_reg_pages.attr,
4446         NULL,
4447 };
4448
4449 static const struct attribute_group mlx5_attr_group = {
4450         .attrs = mlx5_class_attributes,
4451 };
4452
4453 static void pkey_change_handler(struct work_struct *work)
4454 {
4455         struct mlx5_ib_port_resources *ports =
4456                 container_of(work, struct mlx5_ib_port_resources,
4457                              pkey_change_work);
4458
4459         mutex_lock(&ports->devr->mutex);
4460         mlx5_ib_gsi_pkey_change(ports->gsi);
4461         mutex_unlock(&ports->devr->mutex);
4462 }
4463
4464 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4465 {
4466         struct mlx5_ib_qp *mqp;
4467         struct mlx5_ib_cq *send_mcq, *recv_mcq;
4468         struct mlx5_core_cq *mcq;
4469         struct list_head cq_armed_list;
4470         unsigned long flags_qp;
4471         unsigned long flags_cq;
4472         unsigned long flags;
4473
4474         INIT_LIST_HEAD(&cq_armed_list);
4475
4476         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4477         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4478         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4479                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4480                 if (mqp->sq.tail != mqp->sq.head) {
4481                         send_mcq = to_mcq(mqp->ibqp.send_cq);
4482                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
4483                         if (send_mcq->mcq.comp &&
4484                             mqp->ibqp.send_cq->comp_handler) {
4485                                 if (!send_mcq->mcq.reset_notify_added) {
4486                                         send_mcq->mcq.reset_notify_added = 1;
4487                                         list_add_tail(&send_mcq->mcq.reset_notify,
4488                                                       &cq_armed_list);
4489                                 }
4490                         }
4491                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4492                 }
4493                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4494                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4495                 /* no handling is needed for SRQ */
4496                 if (!mqp->ibqp.srq) {
4497                         if (mqp->rq.tail != mqp->rq.head) {
4498                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4499                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4500                                 if (recv_mcq->mcq.comp &&
4501                                     mqp->ibqp.recv_cq->comp_handler) {
4502                                         if (!recv_mcq->mcq.reset_notify_added) {
4503                                                 recv_mcq->mcq.reset_notify_added = 1;
4504                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
4505                                                               &cq_armed_list);
4506                                         }
4507                                 }
4508                                 spin_unlock_irqrestore(&recv_mcq->lock,
4509                                                        flags_cq);
4510                         }
4511                 }
4512                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4513         }
4514         /*At that point all inflight post send were put to be executed as of we
4515          * lock/unlock above locks Now need to arm all involved CQs.
4516          */
4517         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4518                 mcq->comp(mcq, NULL);
4519         }
4520         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4521 }
4522
4523 static void delay_drop_handler(struct work_struct *work)
4524 {
4525         int err;
4526         struct mlx5_ib_delay_drop *delay_drop =
4527                 container_of(work, struct mlx5_ib_delay_drop,
4528                              delay_drop_work);
4529
4530         atomic_inc(&delay_drop->events_cnt);
4531
4532         mutex_lock(&delay_drop->lock);
4533         err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4534                                        delay_drop->timeout);
4535         if (err) {
4536                 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4537                              delay_drop->timeout);
4538                 delay_drop->activate = false;
4539         }
4540         mutex_unlock(&delay_drop->lock);
4541 }
4542
4543 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4544                                  struct ib_event *ibev)
4545 {
4546         u8 port = (eqe->data.port.port >> 4) & 0xf;
4547
4548         switch (eqe->sub_type) {
4549         case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
4550                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4551                                             IB_LINK_LAYER_ETHERNET)
4552                         schedule_work(&ibdev->delay_drop.delay_drop_work);
4553                 break;
4554         default: /* do nothing */
4555                 return;
4556         }
4557 }
4558
4559 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
4560                               struct ib_event *ibev)
4561 {
4562         u8 port = (eqe->data.port.port >> 4) & 0xf;
4563
4564         ibev->element.port_num = port;
4565
4566         switch (eqe->sub_type) {
4567         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
4568         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
4569         case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
4570                 /* In RoCE, port up/down events are handled in
4571                  * mlx5_netdev_event().
4572                  */
4573                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4574                                             IB_LINK_LAYER_ETHERNET)
4575                         return -EINVAL;
4576
4577                 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
4578                                 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4579                 break;
4580
4581         case MLX5_PORT_CHANGE_SUBTYPE_LID:
4582                 ibev->event = IB_EVENT_LID_CHANGE;
4583                 break;
4584
4585         case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
4586                 ibev->event = IB_EVENT_PKEY_CHANGE;
4587                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4588                 break;
4589
4590         case MLX5_PORT_CHANGE_SUBTYPE_GUID:
4591                 ibev->event = IB_EVENT_GID_CHANGE;
4592                 break;
4593
4594         case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
4595                 ibev->event = IB_EVENT_CLIENT_REREGISTER;
4596                 break;
4597         default:
4598                 return -EINVAL;
4599         }
4600
4601         return 0;
4602 }
4603
4604 static void mlx5_ib_handle_event(struct work_struct *_work)
4605 {
4606         struct mlx5_ib_event_work *work =
4607                 container_of(_work, struct mlx5_ib_event_work, work);
4608         struct mlx5_ib_dev *ibdev;
4609         struct ib_event ibev;
4610         bool fatal = false;
4611
4612         if (work->is_slave) {
4613                 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
4614                 if (!ibdev)
4615                         goto out;
4616         } else {
4617                 ibdev = work->dev;
4618         }
4619
4620         switch (work->event) {
4621         case MLX5_DEV_EVENT_SYS_ERROR:
4622                 ibev.event = IB_EVENT_DEVICE_FATAL;
4623                 mlx5_ib_handle_internal_error(ibdev);
4624                 ibev.element.port_num  = (u8)(unsigned long)work->param;
4625                 fatal = true;
4626                 break;
4627         case MLX5_EVENT_TYPE_PORT_CHANGE:
4628                 if (handle_port_change(ibdev, work->param, &ibev))
4629                         goto out;
4630                 break;
4631         case MLX5_EVENT_TYPE_GENERAL_EVENT:
4632                 handle_general_event(ibdev, work->param, &ibev);
4633                 /* fall through */
4634         default:
4635                 goto out;
4636         }
4637
4638         ibev.device = &ibdev->ib_dev;
4639
4640         if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
4641                 mlx5_ib_warn(ibdev, "warning: event on port %d\n",  ibev.element.port_num);
4642                 goto out;
4643         }
4644
4645         if (ibdev->ib_active)
4646                 ib_dispatch_event(&ibev);
4647
4648         if (fatal)
4649                 ibdev->ib_active = false;
4650 out:
4651         kfree(work);
4652 }
4653
4654 static int mlx5_ib_event(struct notifier_block *nb,
4655                          unsigned long event, void *param)
4656 {
4657         struct mlx5_ib_event_work *work;
4658
4659         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4660         if (!work)
4661                 return NOTIFY_DONE;
4662
4663         INIT_WORK(&work->work, mlx5_ib_handle_event);
4664         work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
4665         work->is_slave = false;
4666         work->param = param;
4667         work->event = event;
4668
4669         queue_work(mlx5_ib_event_wq, &work->work);
4670
4671         return NOTIFY_OK;
4672 }
4673
4674 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
4675                                     unsigned long event, void *param)
4676 {
4677         struct mlx5_ib_event_work *work;
4678
4679         work = kmalloc(sizeof(*work), GFP_ATOMIC);
4680         if (!work)
4681                 return NOTIFY_DONE;
4682
4683         INIT_WORK(&work->work, mlx5_ib_handle_event);
4684         work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
4685         work->is_slave = true;
4686         work->param = param;
4687         work->event = event;
4688         queue_work(mlx5_ib_event_wq, &work->work);
4689
4690         return NOTIFY_OK;
4691 }
4692
4693 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4694 {
4695         struct mlx5_hca_vport_context vport_ctx;
4696         int err;
4697         int port;
4698
4699         for (port = 1; port <= ARRAY_SIZE(dev->mdev->port_caps); port++) {
4700                 dev->mdev->port_caps[port - 1].has_smi = false;
4701                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4702                     MLX5_CAP_PORT_TYPE_IB) {
4703                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4704                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4705                                                                    port, 0,
4706                                                                    &vport_ctx);
4707                                 if (err) {
4708                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4709                                                     port, err);
4710                                         return err;
4711                                 }
4712                                 dev->mdev->port_caps[port - 1].has_smi =
4713                                         vport_ctx.has_smi;
4714                         } else {
4715                                 dev->mdev->port_caps[port - 1].has_smi = true;
4716                         }
4717                 }
4718         }
4719         return 0;
4720 }
4721
4722 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4723 {
4724         int port;
4725
4726         for (port = 1; port <= dev->num_ports; port++)
4727                 mlx5_query_ext_port_caps(dev, port);
4728 }
4729
4730 static int __get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4731 {
4732         struct ib_device_attr *dprops = NULL;
4733         struct ib_port_attr *pprops = NULL;
4734         int err = -ENOMEM;
4735         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4736
4737         pprops = kzalloc(sizeof(*pprops), GFP_KERNEL);
4738         if (!pprops)
4739                 goto out;
4740
4741         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4742         if (!dprops)
4743                 goto out;
4744
4745         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4746         if (err) {
4747                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4748                 goto out;
4749         }
4750
4751         err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4752         if (err) {
4753                 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4754                              port, err);
4755                 goto out;
4756         }
4757
4758         dev->mdev->port_caps[port - 1].pkey_table_len =
4759                                         dprops->max_pkeys;
4760         dev->mdev->port_caps[port - 1].gid_table_len =
4761                                         pprops->gid_tbl_len;
4762         mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4763                     port, dprops->max_pkeys, pprops->gid_tbl_len);
4764
4765 out:
4766         kfree(pprops);
4767         kfree(dprops);
4768
4769         return err;
4770 }
4771
4772 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4773 {
4774         /* For representors use port 1, is this is the only native
4775          * port
4776          */
4777         if (dev->is_rep)
4778                 return __get_port_caps(dev, 1);
4779         return __get_port_caps(dev, port);
4780 }
4781
4782 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4783 {
4784         int err;
4785
4786         err = mlx5_mr_cache_cleanup(dev);
4787         if (err)
4788                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4789
4790         if (dev->umrc.qp)
4791                 mlx5_ib_destroy_qp(dev->umrc.qp, NULL);
4792         if (dev->umrc.cq)
4793                 ib_free_cq(dev->umrc.cq);
4794         if (dev->umrc.pd)
4795                 ib_dealloc_pd(dev->umrc.pd);
4796 }
4797
4798 enum {
4799         MAX_UMR_WR = 128,
4800 };
4801
4802 static int create_umr_res(struct mlx5_ib_dev *dev)
4803 {
4804         struct ib_qp_init_attr *init_attr = NULL;
4805         struct ib_qp_attr *attr = NULL;
4806         struct ib_pd *pd;
4807         struct ib_cq *cq;
4808         struct ib_qp *qp;
4809         int ret;
4810
4811         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4812         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4813         if (!attr || !init_attr) {
4814                 ret = -ENOMEM;
4815                 goto error_0;
4816         }
4817
4818         pd = ib_alloc_pd(&dev->ib_dev, 0);
4819         if (IS_ERR(pd)) {
4820                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4821                 ret = PTR_ERR(pd);
4822                 goto error_0;
4823         }
4824
4825         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4826         if (IS_ERR(cq)) {
4827                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4828                 ret = PTR_ERR(cq);
4829                 goto error_2;
4830         }
4831
4832         init_attr->send_cq = cq;
4833         init_attr->recv_cq = cq;
4834         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4835         init_attr->cap.max_send_wr = MAX_UMR_WR;
4836         init_attr->cap.max_send_sge = 1;
4837         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4838         init_attr->port_num = 1;
4839         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4840         if (IS_ERR(qp)) {
4841                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4842                 ret = PTR_ERR(qp);
4843                 goto error_3;
4844         }
4845         qp->device     = &dev->ib_dev;
4846         qp->real_qp    = qp;
4847         qp->uobject    = NULL;
4848         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
4849         qp->send_cq    = init_attr->send_cq;
4850         qp->recv_cq    = init_attr->recv_cq;
4851
4852         attr->qp_state = IB_QPS_INIT;
4853         attr->port_num = 1;
4854         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4855                                 IB_QP_PORT, NULL);
4856         if (ret) {
4857                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4858                 goto error_4;
4859         }
4860
4861         memset(attr, 0, sizeof(*attr));
4862         attr->qp_state = IB_QPS_RTR;
4863         attr->path_mtu = IB_MTU_256;
4864
4865         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4866         if (ret) {
4867                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4868                 goto error_4;
4869         }
4870
4871         memset(attr, 0, sizeof(*attr));
4872         attr->qp_state = IB_QPS_RTS;
4873         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4874         if (ret) {
4875                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4876                 goto error_4;
4877         }
4878
4879         dev->umrc.qp = qp;
4880         dev->umrc.cq = cq;
4881         dev->umrc.pd = pd;
4882
4883         sema_init(&dev->umrc.sem, MAX_UMR_WR);
4884         ret = mlx5_mr_cache_init(dev);
4885         if (ret) {
4886                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4887                 goto error_4;
4888         }
4889
4890         kfree(attr);
4891         kfree(init_attr);
4892
4893         return 0;
4894
4895 error_4:
4896         mlx5_ib_destroy_qp(qp, NULL);
4897         dev->umrc.qp = NULL;
4898
4899 error_3:
4900         ib_free_cq(cq);
4901         dev->umrc.cq = NULL;
4902
4903 error_2:
4904         ib_dealloc_pd(pd);
4905         dev->umrc.pd = NULL;
4906
4907 error_0:
4908         kfree(attr);
4909         kfree(init_attr);
4910         return ret;
4911 }
4912
4913 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4914 {
4915         switch (umr_fence_cap) {
4916         case MLX5_CAP_UMR_FENCE_NONE:
4917                 return MLX5_FENCE_MODE_NONE;
4918         case MLX5_CAP_UMR_FENCE_SMALL:
4919                 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4920         default:
4921                 return MLX5_FENCE_MODE_STRONG_ORDERING;
4922         }
4923 }
4924
4925 static int create_dev_resources(struct mlx5_ib_resources *devr)
4926 {
4927         struct ib_srq_init_attr attr;
4928         struct mlx5_ib_dev *dev;
4929         struct ib_device *ibdev;
4930         struct ib_cq_init_attr cq_attr = {.cqe = 1};
4931         int port;
4932         int ret = 0;
4933
4934         dev = container_of(devr, struct mlx5_ib_dev, devr);
4935         ibdev = &dev->ib_dev;
4936
4937         mutex_init(&devr->mutex);
4938
4939         devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
4940         if (!devr->p0)
4941                 return -ENOMEM;
4942
4943         devr->p0->device  = ibdev;
4944         devr->p0->uobject = NULL;
4945         atomic_set(&devr->p0->usecnt, 0);
4946
4947         ret = mlx5_ib_alloc_pd(devr->p0, NULL);
4948         if (ret)
4949                 goto error0;
4950
4951         devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
4952         if (!devr->c0) {
4953                 ret = -ENOMEM;
4954                 goto error1;
4955         }
4956
4957         devr->c0->device = &dev->ib_dev;
4958         atomic_set(&devr->c0->usecnt, 0);
4959
4960         ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
4961         if (ret)
4962                 goto err_create_cq;
4963
4964         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4965         if (IS_ERR(devr->x0)) {
4966                 ret = PTR_ERR(devr->x0);
4967                 goto error2;
4968         }
4969         devr->x0->device = &dev->ib_dev;
4970         devr->x0->inode = NULL;
4971         atomic_set(&devr->x0->usecnt, 0);
4972         mutex_init(&devr->x0->tgt_qp_mutex);
4973         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4974
4975         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL);
4976         if (IS_ERR(devr->x1)) {
4977                 ret = PTR_ERR(devr->x1);
4978                 goto error3;
4979         }
4980         devr->x1->device = &dev->ib_dev;
4981         devr->x1->inode = NULL;
4982         atomic_set(&devr->x1->usecnt, 0);
4983         mutex_init(&devr->x1->tgt_qp_mutex);
4984         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4985
4986         memset(&attr, 0, sizeof(attr));
4987         attr.attr.max_sge = 1;
4988         attr.attr.max_wr = 1;
4989         attr.srq_type = IB_SRQT_XRC;
4990         attr.ext.cq = devr->c0;
4991         attr.ext.xrc.xrcd = devr->x0;
4992
4993         devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
4994         if (!devr->s0) {
4995                 ret = -ENOMEM;
4996                 goto error4;
4997         }
4998
4999         devr->s0->device        = &dev->ib_dev;
5000         devr->s0->pd            = devr->p0;
5001         devr->s0->srq_type      = IB_SRQT_XRC;
5002         devr->s0->ext.xrc.xrcd  = devr->x0;
5003         devr->s0->ext.cq        = devr->c0;
5004         ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
5005         if (ret)
5006                 goto err_create;
5007
5008         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
5009         atomic_inc(&devr->s0->ext.cq->usecnt);
5010         atomic_inc(&devr->p0->usecnt);
5011         atomic_set(&devr->s0->usecnt, 0);
5012
5013         memset(&attr, 0, sizeof(attr));
5014         attr.attr.max_sge = 1;
5015         attr.attr.max_wr = 1;
5016         attr.srq_type = IB_SRQT_BASIC;
5017         devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
5018         if (!devr->s1) {
5019                 ret = -ENOMEM;
5020                 goto error5;
5021         }
5022
5023         devr->s1->device        = &dev->ib_dev;
5024         devr->s1->pd            = devr->p0;
5025         devr->s1->srq_type      = IB_SRQT_BASIC;
5026         devr->s1->ext.cq        = devr->c0;
5027
5028         ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
5029         if (ret)
5030                 goto error6;
5031
5032         atomic_inc(&devr->p0->usecnt);
5033         atomic_set(&devr->s1->usecnt, 0);
5034
5035         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
5036                 INIT_WORK(&devr->ports[port].pkey_change_work,
5037                           pkey_change_handler);
5038                 devr->ports[port].devr = devr;
5039         }
5040
5041         return 0;
5042
5043 error6:
5044         kfree(devr->s1);
5045 error5:
5046         mlx5_ib_destroy_srq(devr->s0, NULL);
5047 err_create:
5048         kfree(devr->s0);
5049 error4:
5050         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5051 error3:
5052         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5053 error2:
5054         mlx5_ib_destroy_cq(devr->c0, NULL);
5055 err_create_cq:
5056         kfree(devr->c0);
5057 error1:
5058         mlx5_ib_dealloc_pd(devr->p0, NULL);
5059 error0:
5060         kfree(devr->p0);
5061         return ret;
5062 }
5063
5064 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
5065 {
5066         int port;
5067
5068         mlx5_ib_destroy_srq(devr->s1, NULL);
5069         kfree(devr->s1);
5070         mlx5_ib_destroy_srq(devr->s0, NULL);
5071         kfree(devr->s0);
5072         mlx5_ib_dealloc_xrcd(devr->x0, NULL);
5073         mlx5_ib_dealloc_xrcd(devr->x1, NULL);
5074         mlx5_ib_destroy_cq(devr->c0, NULL);
5075         kfree(devr->c0);
5076         mlx5_ib_dealloc_pd(devr->p0, NULL);
5077         kfree(devr->p0);
5078
5079         /* Make sure no change P_Key work items are still executing */
5080         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
5081                 cancel_work_sync(&devr->ports[port].pkey_change_work);
5082 }
5083
5084 static u32 get_core_cap_flags(struct ib_device *ibdev,
5085                               struct mlx5_hca_vport_context *rep)
5086 {
5087         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5088         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
5089         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
5090         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
5091         bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
5092         u32 ret = 0;
5093
5094         if (rep->grh_required)
5095                 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
5096
5097         if (ll == IB_LINK_LAYER_INFINIBAND)
5098                 return ret | RDMA_CORE_PORT_IBA_IB;
5099
5100         if (raw_support)
5101                 ret |= RDMA_CORE_PORT_RAW_PACKET;
5102
5103         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
5104                 return ret;
5105
5106         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
5107                 return ret;
5108
5109         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
5110                 ret |= RDMA_CORE_PORT_IBA_ROCE;
5111
5112         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
5113                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
5114
5115         return ret;
5116 }
5117
5118 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
5119                                struct ib_port_immutable *immutable)
5120 {
5121         struct ib_port_attr attr;
5122         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5123         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
5124         struct mlx5_hca_vport_context rep = {0};
5125         int err;
5126
5127         err = ib_query_port(ibdev, port_num, &attr);
5128         if (err)
5129                 return err;
5130
5131         if (ll == IB_LINK_LAYER_INFINIBAND) {
5132                 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
5133                                                    &rep);
5134                 if (err)
5135                         return err;
5136         }
5137
5138         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5139         immutable->gid_tbl_len = attr.gid_tbl_len;
5140         immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
5141         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
5142                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
5143
5144         return 0;
5145 }
5146
5147 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
5148                                    struct ib_port_immutable *immutable)
5149 {
5150         struct ib_port_attr attr;
5151         int err;
5152
5153         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5154
5155         err = ib_query_port(ibdev, port_num, &attr);
5156         if (err)
5157                 return err;
5158
5159         immutable->pkey_tbl_len = attr.pkey_tbl_len;
5160         immutable->gid_tbl_len = attr.gid_tbl_len;
5161         immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
5162
5163         return 0;
5164 }
5165
5166 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
5167 {
5168         struct mlx5_ib_dev *dev =
5169                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
5170         snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
5171                  fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
5172                  fw_rev_sub(dev->mdev));
5173 }
5174
5175 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
5176 {
5177         struct mlx5_core_dev *mdev = dev->mdev;
5178         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
5179                                                                  MLX5_FLOW_NAMESPACE_LAG);
5180         struct mlx5_flow_table *ft;
5181         int err;
5182
5183         if (!ns || !mlx5_lag_is_roce(mdev))
5184                 return 0;
5185
5186         err = mlx5_cmd_create_vport_lag(mdev);
5187         if (err)
5188                 return err;
5189
5190         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
5191         if (IS_ERR(ft)) {
5192                 err = PTR_ERR(ft);
5193                 goto err_destroy_vport_lag;
5194         }
5195
5196         dev->flow_db->lag_demux_ft = ft;
5197         dev->lag_active = true;
5198         return 0;
5199
5200 err_destroy_vport_lag:
5201         mlx5_cmd_destroy_vport_lag(mdev);
5202         return err;
5203 }
5204
5205 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
5206 {
5207         struct mlx5_core_dev *mdev = dev->mdev;
5208
5209         if (dev->lag_active) {
5210                 dev->lag_active = false;
5211
5212                 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
5213                 dev->flow_db->lag_demux_ft = NULL;
5214
5215                 mlx5_cmd_destroy_vport_lag(mdev);
5216         }
5217 }
5218
5219 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5220 {
5221         int err;
5222
5223         dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
5224         err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
5225         if (err) {
5226                 dev->port[port_num].roce.nb.notifier_call = NULL;
5227                 return err;
5228         }
5229
5230         return 0;
5231 }
5232
5233 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
5234 {
5235         if (dev->port[port_num].roce.nb.notifier_call) {
5236                 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
5237                 dev->port[port_num].roce.nb.notifier_call = NULL;
5238         }
5239 }
5240
5241 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
5242 {
5243         int err;
5244
5245         if (MLX5_CAP_GEN(dev->mdev, roce)) {
5246                 err = mlx5_nic_vport_enable_roce(dev->mdev);
5247                 if (err)
5248                         return err;
5249         }
5250
5251         err = mlx5_eth_lag_init(dev);
5252         if (err)
5253                 goto err_disable_roce;
5254
5255         return 0;
5256
5257 err_disable_roce:
5258         if (MLX5_CAP_GEN(dev->mdev, roce))
5259                 mlx5_nic_vport_disable_roce(dev->mdev);
5260
5261         return err;
5262 }
5263
5264 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
5265 {
5266         mlx5_eth_lag_cleanup(dev);
5267         if (MLX5_CAP_GEN(dev->mdev, roce))
5268                 mlx5_nic_vport_disable_roce(dev->mdev);
5269 }
5270
5271 struct mlx5_ib_counter {
5272         const char *name;
5273         size_t offset;
5274 };
5275
5276 #define INIT_Q_COUNTER(_name)           \
5277         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5278
5279 static const struct mlx5_ib_counter basic_q_cnts[] = {
5280         INIT_Q_COUNTER(rx_write_requests),
5281         INIT_Q_COUNTER(rx_read_requests),
5282         INIT_Q_COUNTER(rx_atomic_requests),
5283         INIT_Q_COUNTER(out_of_buffer),
5284 };
5285
5286 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
5287         INIT_Q_COUNTER(out_of_sequence),
5288 };
5289
5290 static const struct mlx5_ib_counter retrans_q_cnts[] = {
5291         INIT_Q_COUNTER(duplicate_request),
5292         INIT_Q_COUNTER(rnr_nak_retry_err),
5293         INIT_Q_COUNTER(packet_seq_err),
5294         INIT_Q_COUNTER(implied_nak_seq_err),
5295         INIT_Q_COUNTER(local_ack_timeout_err),
5296 };
5297
5298 #define INIT_CONG_COUNTER(_name)                \
5299         { .name = #_name, .offset =     \
5300                 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5301
5302 static const struct mlx5_ib_counter cong_cnts[] = {
5303         INIT_CONG_COUNTER(rp_cnp_ignored),
5304         INIT_CONG_COUNTER(rp_cnp_handled),
5305         INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
5306         INIT_CONG_COUNTER(np_cnp_sent),
5307 };
5308
5309 static const struct mlx5_ib_counter extended_err_cnts[] = {
5310         INIT_Q_COUNTER(resp_local_length_error),
5311         INIT_Q_COUNTER(resp_cqe_error),
5312         INIT_Q_COUNTER(req_cqe_error),
5313         INIT_Q_COUNTER(req_remote_invalid_request),
5314         INIT_Q_COUNTER(req_remote_access_errors),
5315         INIT_Q_COUNTER(resp_remote_access_errors),
5316         INIT_Q_COUNTER(resp_cqe_flush_error),
5317         INIT_Q_COUNTER(req_cqe_flush_error),
5318 };
5319
5320 #define INIT_EXT_PPCNT_COUNTER(_name)           \
5321         { .name = #_name, .offset =     \
5322         MLX5_BYTE_OFF(ppcnt_reg, \
5323                       counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5324
5325 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
5326         INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
5327 };
5328
5329 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
5330 {
5331         int i;
5332
5333         for (i = 0; i < dev->num_ports; i++) {
5334                 if (dev->port[i].cnts.set_id_valid)
5335                         mlx5_core_dealloc_q_counter(dev->mdev,
5336                                                     dev->port[i].cnts.set_id);
5337                 kfree(dev->port[i].cnts.names);
5338                 kfree(dev->port[i].cnts.offsets);
5339         }
5340 }
5341
5342 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
5343                                     struct mlx5_ib_counters *cnts)
5344 {
5345         u32 num_counters;
5346
5347         num_counters = ARRAY_SIZE(basic_q_cnts);
5348
5349         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
5350                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
5351
5352         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
5353                 num_counters += ARRAY_SIZE(retrans_q_cnts);
5354
5355         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
5356                 num_counters += ARRAY_SIZE(extended_err_cnts);
5357
5358         cnts->num_q_counters = num_counters;
5359
5360         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5361                 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
5362                 num_counters += ARRAY_SIZE(cong_cnts);
5363         }
5364         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5365                 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
5366                 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
5367         }
5368         cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
5369         if (!cnts->names)
5370                 return -ENOMEM;
5371
5372         cnts->offsets = kcalloc(num_counters,
5373                                 sizeof(cnts->offsets), GFP_KERNEL);
5374         if (!cnts->offsets)
5375                 goto err_names;
5376
5377         return 0;
5378
5379 err_names:
5380         kfree(cnts->names);
5381         cnts->names = NULL;
5382         return -ENOMEM;
5383 }
5384
5385 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
5386                                   const char **names,
5387                                   size_t *offsets)
5388 {
5389         int i;
5390         int j = 0;
5391
5392         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5393                 names[j] = basic_q_cnts[i].name;
5394                 offsets[j] = basic_q_cnts[i].offset;
5395         }
5396
5397         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5398                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5399                         names[j] = out_of_seq_q_cnts[i].name;
5400                         offsets[j] = out_of_seq_q_cnts[i].offset;
5401                 }
5402         }
5403
5404         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5405                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5406                         names[j] = retrans_q_cnts[i].name;
5407                         offsets[j] = retrans_q_cnts[i].offset;
5408                 }
5409         }
5410
5411         if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5412                 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5413                         names[j] = extended_err_cnts[i].name;
5414                         offsets[j] = extended_err_cnts[i].offset;
5415                 }
5416         }
5417
5418         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5419                 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5420                         names[j] = cong_cnts[i].name;
5421                         offsets[j] = cong_cnts[i].offset;
5422                 }
5423         }
5424
5425         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5426                 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5427                         names[j] = ext_ppcnt_cnts[i].name;
5428                         offsets[j] = ext_ppcnt_cnts[i].offset;
5429                 }
5430         }
5431 }
5432
5433 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5434 {
5435         int err = 0;
5436         int i;
5437         bool is_shared;
5438
5439         is_shared = MLX5_CAP_GEN(dev->mdev, log_max_uctx) != 0;
5440
5441         for (i = 0; i < dev->num_ports; i++) {
5442                 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5443                 if (err)
5444                         goto err_alloc;
5445
5446                 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5447                                       dev->port[i].cnts.offsets);
5448
5449                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5450                                                &dev->port[i].cnts.set_id,
5451                                                is_shared ?
5452                                                MLX5_SHARED_RESOURCE_UID : 0);
5453                 if (err) {
5454                         mlx5_ib_warn(dev,
5455                                      "couldn't allocate queue counter for port %d, err %d\n",
5456                                      i + 1, err);
5457                         goto err_alloc;
5458                 }
5459                 dev->port[i].cnts.set_id_valid = true;
5460         }
5461
5462         return 0;
5463
5464 err_alloc:
5465         mlx5_ib_dealloc_counters(dev);
5466         return err;
5467 }
5468
5469 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5470                                                     u8 port_num)
5471 {
5472         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5473         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5474
5475         /* We support only per port stats */
5476         if (port_num == 0)
5477                 return NULL;
5478
5479         return rdma_alloc_hw_stats_struct(port->cnts.names,
5480                                           port->cnts.num_q_counters +
5481                                           port->cnts.num_cong_counters +
5482                                           port->cnts.num_ext_ppcnt_counters,
5483                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5484 }
5485
5486 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5487                                     struct mlx5_ib_port *port,
5488                                     struct rdma_hw_stats *stats,
5489                                     u16 set_id)
5490 {
5491         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5492         void *out;
5493         __be32 val;
5494         int ret, i;
5495
5496         out = kvzalloc(outlen, GFP_KERNEL);
5497         if (!out)
5498                 return -ENOMEM;
5499
5500         ret = mlx5_core_query_q_counter(mdev, set_id, 0, out, outlen);
5501         if (ret)
5502                 goto free;
5503
5504         for (i = 0; i < port->cnts.num_q_counters; i++) {
5505                 val = *(__be32 *)(out + port->cnts.offsets[i]);
5506                 stats->value[i] = (u64)be32_to_cpu(val);
5507         }
5508
5509 free:
5510         kvfree(out);
5511         return ret;
5512 }
5513
5514 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5515                                           struct mlx5_ib_port *port,
5516                                           struct rdma_hw_stats *stats)
5517 {
5518         int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5519         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5520         int ret, i;
5521         void *out;
5522
5523         out = kvzalloc(sz, GFP_KERNEL);
5524         if (!out)
5525                 return -ENOMEM;
5526
5527         ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5528         if (ret)
5529                 goto free;
5530
5531         for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5532                 stats->value[i + offset] =
5533                         be64_to_cpup((__be64 *)(out +
5534                                     port->cnts.offsets[i + offset]));
5535         }
5536
5537 free:
5538         kvfree(out);
5539         return ret;
5540 }
5541
5542 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5543                                 struct rdma_hw_stats *stats,
5544                                 u8 port_num, int index)
5545 {
5546         struct mlx5_ib_dev *dev = to_mdev(ibdev);
5547         struct mlx5_ib_port *port = &dev->port[port_num - 1];
5548         struct mlx5_core_dev *mdev;
5549         int ret, num_counters;
5550         u8 mdev_port_num;
5551
5552         if (!stats)
5553                 return -EINVAL;
5554
5555         num_counters = port->cnts.num_q_counters +
5556                        port->cnts.num_cong_counters +
5557                        port->cnts.num_ext_ppcnt_counters;
5558
5559         /* q_counters are per IB device, query the master mdev */
5560         ret = mlx5_ib_query_q_counters(dev->mdev, port, stats,
5561                                        port->cnts.set_id);
5562         if (ret)
5563                 return ret;
5564
5565         if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5566                 ret =  mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5567                 if (ret)
5568                         return ret;
5569         }
5570
5571         if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5572                 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5573                                                     &mdev_port_num);
5574                 if (!mdev) {
5575                         /* If port is not affiliated yet, its in down state
5576                          * which doesn't have any counters yet, so it would be
5577                          * zero. So no need to read from the HCA.
5578                          */
5579                         goto done;
5580                 }
5581                 ret = mlx5_lag_query_cong_counters(dev->mdev,
5582                                                    stats->value +
5583                                                    port->cnts.num_q_counters,
5584                                                    port->cnts.num_cong_counters,
5585                                                    port->cnts.offsets +
5586                                                    port->cnts.num_q_counters);
5587
5588                 mlx5_ib_put_native_port_mdev(dev, port_num);
5589                 if (ret)
5590                         return ret;
5591         }
5592
5593 done:
5594         return num_counters;
5595 }
5596
5597 static struct rdma_hw_stats *
5598 mlx5_ib_counter_alloc_stats(struct rdma_counter *counter)
5599 {
5600         struct mlx5_ib_dev *dev = to_mdev(counter->device);
5601         struct mlx5_ib_port *port = &dev->port[counter->port - 1];
5602
5603         /* Q counters are in the beginning of all counters */
5604         return rdma_alloc_hw_stats_struct(port->cnts.names,
5605                                           port->cnts.num_q_counters,
5606                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
5607 }
5608
5609 static int mlx5_ib_counter_update_stats(struct rdma_counter *counter)
5610 {
5611         struct mlx5_ib_dev *dev = to_mdev(counter->device);
5612         struct mlx5_ib_port *port = &dev->port[counter->port - 1];
5613
5614         return mlx5_ib_query_q_counters(dev->mdev, port,
5615                                         counter->stats, counter->id);
5616 }
5617
5618 static int mlx5_ib_counter_bind_qp(struct rdma_counter *counter,
5619                                    struct ib_qp *qp)
5620 {
5621         struct mlx5_ib_dev *dev = to_mdev(qp->device);
5622         u16 cnt_set_id = 0;
5623         int err;
5624
5625         if (!counter->id) {
5626                 err = mlx5_cmd_alloc_q_counter(dev->mdev,
5627                                                &cnt_set_id,
5628                                                MLX5_SHARED_RESOURCE_UID);
5629                 if (err)
5630                         return err;
5631                 counter->id = cnt_set_id;
5632         }
5633
5634         err = mlx5_ib_qp_set_counter(qp, counter);
5635         if (err)
5636                 goto fail_set_counter;
5637
5638         return 0;
5639
5640 fail_set_counter:
5641         mlx5_core_dealloc_q_counter(dev->mdev, cnt_set_id);
5642         counter->id = 0;
5643
5644         return err;
5645 }
5646
5647 static int mlx5_ib_counter_unbind_qp(struct ib_qp *qp)
5648 {
5649         return mlx5_ib_qp_set_counter(qp, NULL);
5650 }
5651
5652 static int mlx5_ib_counter_dealloc(struct rdma_counter *counter)
5653 {
5654         struct mlx5_ib_dev *dev = to_mdev(counter->device);
5655
5656         return mlx5_core_dealloc_q_counter(dev->mdev, counter->id);
5657 }
5658
5659 static int mlx5_ib_rn_get_params(struct ib_device *device, u8 port_num,
5660                                  enum rdma_netdev_t type,
5661                                  struct rdma_netdev_alloc_params *params)
5662 {
5663         if (type != RDMA_NETDEV_IPOIB)
5664                 return -EOPNOTSUPP;
5665
5666         return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
5667 }
5668
5669 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5670 {
5671         if (!dev->delay_drop.dbg)
5672                 return;
5673         debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5674         kfree(dev->delay_drop.dbg);
5675         dev->delay_drop.dbg = NULL;
5676 }
5677
5678 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5679 {
5680         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5681                 return;
5682
5683         cancel_work_sync(&dev->delay_drop.delay_drop_work);
5684         delay_drop_debugfs_cleanup(dev);
5685 }
5686
5687 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5688                                        size_t count, loff_t *pos)
5689 {
5690         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5691         char lbuf[20];
5692         int len;
5693
5694         len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5695         return simple_read_from_buffer(buf, count, pos, lbuf, len);
5696 }
5697
5698 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5699                                         size_t count, loff_t *pos)
5700 {
5701         struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5702         u32 timeout;
5703         u32 var;
5704
5705         if (kstrtouint_from_user(buf, count, 0, &var))
5706                 return -EFAULT;
5707
5708         timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5709                         1000);
5710         if (timeout != var)
5711                 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5712                             timeout);
5713
5714         delay_drop->timeout = timeout;
5715
5716         return count;
5717 }
5718
5719 static const struct file_operations fops_delay_drop_timeout = {
5720         .owner  = THIS_MODULE,
5721         .open   = simple_open,
5722         .write  = delay_drop_timeout_write,
5723         .read   = delay_drop_timeout_read,
5724 };
5725
5726 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5727 {
5728         struct mlx5_ib_dbg_delay_drop *dbg;
5729
5730         if (!mlx5_debugfs_root)
5731                 return 0;
5732
5733         dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5734         if (!dbg)
5735                 return -ENOMEM;
5736
5737         dev->delay_drop.dbg = dbg;
5738
5739         dbg->dir_debugfs =
5740                 debugfs_create_dir("delay_drop",
5741                                    dev->mdev->priv.dbg_root);
5742         if (!dbg->dir_debugfs)
5743                 goto out_debugfs;
5744
5745         dbg->events_cnt_debugfs =
5746                 debugfs_create_atomic_t("num_timeout_events", 0400,
5747                                         dbg->dir_debugfs,
5748                                         &dev->delay_drop.events_cnt);
5749         if (!dbg->events_cnt_debugfs)
5750                 goto out_debugfs;
5751
5752         dbg->rqs_cnt_debugfs =
5753                 debugfs_create_atomic_t("num_rqs", 0400,
5754                                         dbg->dir_debugfs,
5755                                         &dev->delay_drop.rqs_cnt);
5756         if (!dbg->rqs_cnt_debugfs)
5757                 goto out_debugfs;
5758
5759         dbg->timeout_debugfs =
5760                 debugfs_create_file("timeout", 0600,
5761                                     dbg->dir_debugfs,
5762                                     &dev->delay_drop,
5763                                     &fops_delay_drop_timeout);
5764         if (!dbg->timeout_debugfs)
5765                 goto out_debugfs;
5766
5767         return 0;
5768
5769 out_debugfs:
5770         delay_drop_debugfs_cleanup(dev);
5771         return -ENOMEM;
5772 }
5773
5774 static void init_delay_drop(struct mlx5_ib_dev *dev)
5775 {
5776         if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5777                 return;
5778
5779         mutex_init(&dev->delay_drop.lock);
5780         dev->delay_drop.dev = dev;
5781         dev->delay_drop.activate = false;
5782         dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5783         INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5784         atomic_set(&dev->delay_drop.rqs_cnt, 0);
5785         atomic_set(&dev->delay_drop.events_cnt, 0);
5786
5787         if (delay_drop_debugfs_init(dev))
5788                 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5789 }
5790
5791 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5792 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5793                                       struct mlx5_ib_multiport_info *mpi)
5794 {
5795         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5796         struct mlx5_ib_port *port = &ibdev->port[port_num];
5797         int comps;
5798         int err;
5799         int i;
5800
5801         mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5802
5803         spin_lock(&port->mp.mpi_lock);
5804         if (!mpi->ibdev) {
5805                 spin_unlock(&port->mp.mpi_lock);
5806                 return;
5807         }
5808
5809         mpi->ibdev = NULL;
5810
5811         spin_unlock(&port->mp.mpi_lock);
5812         if (mpi->mdev_events.notifier_call)
5813                 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
5814         mpi->mdev_events.notifier_call = NULL;
5815         mlx5_remove_netdev_notifier(ibdev, port_num);
5816         spin_lock(&port->mp.mpi_lock);
5817
5818         comps = mpi->mdev_refcnt;
5819         if (comps) {
5820                 mpi->unaffiliate = true;
5821                 init_completion(&mpi->unref_comp);
5822                 spin_unlock(&port->mp.mpi_lock);
5823
5824                 for (i = 0; i < comps; i++)
5825                         wait_for_completion(&mpi->unref_comp);
5826
5827                 spin_lock(&port->mp.mpi_lock);
5828                 mpi->unaffiliate = false;
5829         }
5830
5831         port->mp.mpi = NULL;
5832
5833         list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5834
5835         spin_unlock(&port->mp.mpi_lock);
5836
5837         err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5838
5839         mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5840         /* Log an error, still needed to cleanup the pointers and add
5841          * it back to the list.
5842          */
5843         if (err)
5844                 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5845                             port_num + 1);
5846
5847         ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
5848 }
5849
5850 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5851 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5852                                     struct mlx5_ib_multiport_info *mpi)
5853 {
5854         u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5855         int err;
5856
5857         spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5858         if (ibdev->port[port_num].mp.mpi) {
5859                 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5860                             port_num + 1);
5861                 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5862                 return false;
5863         }
5864
5865         ibdev->port[port_num].mp.mpi = mpi;
5866         mpi->ibdev = ibdev;
5867         mpi->mdev_events.notifier_call = NULL;
5868         spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5869
5870         err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5871         if (err)
5872                 goto unbind;
5873
5874         err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5875         if (err)
5876                 goto unbind;
5877
5878         err = mlx5_add_netdev_notifier(ibdev, port_num);
5879         if (err) {
5880                 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5881                             port_num + 1);
5882                 goto unbind;
5883         }
5884
5885         mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
5886         mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
5887
5888         mlx5_ib_init_cong_debugfs(ibdev, port_num);
5889
5890         return true;
5891
5892 unbind:
5893         mlx5_ib_unbind_slave_port(ibdev, mpi);
5894         return false;
5895 }
5896
5897 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5898 {
5899         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5900         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5901                                                           port_num + 1);
5902         struct mlx5_ib_multiport_info *mpi;
5903         int err;
5904         int i;
5905
5906         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5907                 return 0;
5908
5909         err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5910                                                      &dev->sys_image_guid);
5911         if (err)
5912                 return err;
5913
5914         err = mlx5_nic_vport_enable_roce(dev->mdev);
5915         if (err)
5916                 return err;
5917
5918         mutex_lock(&mlx5_ib_multiport_mutex);
5919         for (i = 0; i < dev->num_ports; i++) {
5920                 bool bound = false;
5921
5922                 /* build a stub multiport info struct for the native port. */
5923                 if (i == port_num) {
5924                         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5925                         if (!mpi) {
5926                                 mutex_unlock(&mlx5_ib_multiport_mutex);
5927                                 mlx5_nic_vport_disable_roce(dev->mdev);
5928                                 return -ENOMEM;
5929                         }
5930
5931                         mpi->is_master = true;
5932                         mpi->mdev = dev->mdev;
5933                         mpi->sys_image_guid = dev->sys_image_guid;
5934                         dev->port[i].mp.mpi = mpi;
5935                         mpi->ibdev = dev;
5936                         mpi = NULL;
5937                         continue;
5938                 }
5939
5940                 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5941                                     list) {
5942                         if (dev->sys_image_guid == mpi->sys_image_guid &&
5943                             (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5944                                 bound = mlx5_ib_bind_slave_port(dev, mpi);
5945                         }
5946
5947                         if (bound) {
5948                                 dev_dbg(mpi->mdev->device,
5949                                         "removing port from unaffiliated list.\n");
5950                                 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5951                                 list_del(&mpi->list);
5952                                 break;
5953                         }
5954                 }
5955                 if (!bound) {
5956                         get_port_caps(dev, i + 1);
5957                         mlx5_ib_dbg(dev, "no free port found for port %d\n",
5958                                     i + 1);
5959                 }
5960         }
5961
5962         list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5963         mutex_unlock(&mlx5_ib_multiport_mutex);
5964         return err;
5965 }
5966
5967 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5968 {
5969         int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5970         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5971                                                           port_num + 1);
5972         int i;
5973
5974         if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5975                 return;
5976
5977         mutex_lock(&mlx5_ib_multiport_mutex);
5978         for (i = 0; i < dev->num_ports; i++) {
5979                 if (dev->port[i].mp.mpi) {
5980                         /* Destroy the native port stub */
5981                         if (i == port_num) {
5982                                 kfree(dev->port[i].mp.mpi);
5983                                 dev->port[i].mp.mpi = NULL;
5984                         } else {
5985                                 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5986                                 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5987                         }
5988                 }
5989         }
5990
5991         mlx5_ib_dbg(dev, "removing from devlist\n");
5992         list_del(&dev->ib_dev_list);
5993         mutex_unlock(&mlx5_ib_multiport_mutex);
5994
5995         mlx5_nic_vport_disable_roce(dev->mdev);
5996 }
5997
5998 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5999         mlx5_ib_dm,
6000         UVERBS_OBJECT_DM,
6001         UVERBS_METHOD_DM_ALLOC,
6002         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
6003                             UVERBS_ATTR_TYPE(u64),
6004                             UA_MANDATORY),
6005         UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
6006                             UVERBS_ATTR_TYPE(u16),
6007                             UA_OPTIONAL),
6008         UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE,
6009                              enum mlx5_ib_uapi_dm_type,
6010                              UA_OPTIONAL));
6011
6012 ADD_UVERBS_ATTRIBUTES_SIMPLE(
6013         mlx5_ib_flow_action,
6014         UVERBS_OBJECT_FLOW_ACTION,
6015         UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
6016         UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
6017                              enum mlx5_ib_uapi_flow_action_flags));
6018
6019 static const struct uapi_definition mlx5_ib_defs[] = {
6020 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
6021         UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
6022         UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
6023 #endif
6024
6025         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
6026                                 &mlx5_ib_flow_action),
6027         UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM, &mlx5_ib_dm),
6028         {}
6029 };
6030
6031 static int mlx5_ib_read_counters(struct ib_counters *counters,
6032                                  struct ib_counters_read_attr *read_attr,
6033                                  struct uverbs_attr_bundle *attrs)
6034 {
6035         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6036         struct mlx5_read_counters_attr mread_attr = {};
6037         struct mlx5_ib_flow_counters_desc *desc;
6038         int ret, i;
6039
6040         mutex_lock(&mcounters->mcntrs_mutex);
6041         if (mcounters->cntrs_max_index > read_attr->ncounters) {
6042                 ret = -EINVAL;
6043                 goto err_bound;
6044         }
6045
6046         mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
6047                                  GFP_KERNEL);
6048         if (!mread_attr.out) {
6049                 ret = -ENOMEM;
6050                 goto err_bound;
6051         }
6052
6053         mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
6054         mread_attr.flags = read_attr->flags;
6055         ret = mcounters->read_counters(counters->device, &mread_attr);
6056         if (ret)
6057                 goto err_read;
6058
6059         /* do the pass over the counters data array to assign according to the
6060          * descriptions and indexing pairs
6061          */
6062         desc = mcounters->counters_data;
6063         for (i = 0; i < mcounters->ncounters; i++)
6064                 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
6065
6066 err_read:
6067         kfree(mread_attr.out);
6068 err_bound:
6069         mutex_unlock(&mcounters->mcntrs_mutex);
6070         return ret;
6071 }
6072
6073 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
6074 {
6075         struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
6076
6077         counters_clear_description(counters);
6078         if (mcounters->hw_cntrs_hndl)
6079                 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
6080                                 mcounters->hw_cntrs_hndl);
6081
6082         kfree(mcounters);
6083
6084         return 0;
6085 }
6086
6087 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
6088                                                    struct uverbs_attr_bundle *attrs)
6089 {
6090         struct mlx5_ib_mcounters *mcounters;
6091
6092         mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
6093         if (!mcounters)
6094                 return ERR_PTR(-ENOMEM);
6095
6096         mutex_init(&mcounters->mcntrs_mutex);
6097
6098         return &mcounters->ibcntrs;
6099 }
6100
6101 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
6102 {
6103         mlx5_ib_cleanup_multiport_master(dev);
6104         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6105                 srcu_barrier(&dev->mr_srcu);
6106                 cleanup_srcu_struct(&dev->mr_srcu);
6107         }
6108
6109         WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
6110 }
6111
6112 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
6113 {
6114         struct mlx5_core_dev *mdev = dev->mdev;
6115         int err;
6116         int i;
6117
6118         for (i = 0; i < dev->num_ports; i++) {
6119                 spin_lock_init(&dev->port[i].mp.mpi_lock);
6120                 rwlock_init(&dev->port[i].roce.netdev_lock);
6121                 dev->port[i].roce.dev = dev;
6122                 dev->port[i].roce.native_port_num = i + 1;
6123                 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
6124         }
6125
6126         mlx5_ib_internal_fill_odp_caps(dev);
6127
6128         err = mlx5_ib_init_multiport_master(dev);
6129         if (err)
6130                 return err;
6131
6132         err = set_has_smi_cap(dev);
6133         if (err)
6134                 return err;
6135
6136         if (!mlx5_core_mp_enabled(mdev)) {
6137                 for (i = 1; i <= dev->num_ports; i++) {
6138                         err = get_port_caps(dev, i);
6139                         if (err)
6140                                 break;
6141                 }
6142         } else {
6143                 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
6144         }
6145         if (err)
6146                 goto err_mp;
6147
6148         if (mlx5_use_mad_ifc(dev))
6149                 get_ext_port_caps(dev);
6150
6151         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
6152         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
6153         dev->ib_dev.phys_port_cnt       = dev->num_ports;
6154         dev->ib_dev.num_comp_vectors    = mlx5_comp_vectors_count(mdev);
6155         dev->ib_dev.dev.parent          = mdev->device;
6156
6157         mutex_init(&dev->cap_mask_mutex);
6158         INIT_LIST_HEAD(&dev->qp_list);
6159         spin_lock_init(&dev->reset_flow_resource_lock);
6160
6161         spin_lock_init(&dev->dm.lock);
6162         dev->dm.dev = mdev;
6163
6164         if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
6165                 err = init_srcu_struct(&dev->mr_srcu);
6166                 if (err)
6167                         goto err_mp;
6168         }
6169
6170         return 0;
6171
6172 err_mp:
6173         mlx5_ib_cleanup_multiport_master(dev);
6174
6175         return -ENOMEM;
6176 }
6177
6178 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
6179 {
6180         dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
6181
6182         if (!dev->flow_db)
6183                 return -ENOMEM;
6184
6185         mutex_init(&dev->flow_db->lock);
6186
6187         return 0;
6188 }
6189
6190 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
6191 {
6192         kfree(dev->flow_db);
6193 }
6194
6195 static const struct ib_device_ops mlx5_ib_dev_ops = {
6196         .owner = THIS_MODULE,
6197         .driver_id = RDMA_DRIVER_MLX5,
6198         .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
6199
6200         .add_gid = mlx5_ib_add_gid,
6201         .alloc_mr = mlx5_ib_alloc_mr,
6202         .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
6203         .alloc_pd = mlx5_ib_alloc_pd,
6204         .alloc_ucontext = mlx5_ib_alloc_ucontext,
6205         .attach_mcast = mlx5_ib_mcg_attach,
6206         .check_mr_status = mlx5_ib_check_mr_status,
6207         .create_ah = mlx5_ib_create_ah,
6208         .create_counters = mlx5_ib_create_counters,
6209         .create_cq = mlx5_ib_create_cq,
6210         .create_flow = mlx5_ib_create_flow,
6211         .create_qp = mlx5_ib_create_qp,
6212         .create_srq = mlx5_ib_create_srq,
6213         .dealloc_pd = mlx5_ib_dealloc_pd,
6214         .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
6215         .del_gid = mlx5_ib_del_gid,
6216         .dereg_mr = mlx5_ib_dereg_mr,
6217         .destroy_ah = mlx5_ib_destroy_ah,
6218         .destroy_counters = mlx5_ib_destroy_counters,
6219         .destroy_cq = mlx5_ib_destroy_cq,
6220         .destroy_flow = mlx5_ib_destroy_flow,
6221         .destroy_flow_action = mlx5_ib_destroy_flow_action,
6222         .destroy_qp = mlx5_ib_destroy_qp,
6223         .destroy_srq = mlx5_ib_destroy_srq,
6224         .detach_mcast = mlx5_ib_mcg_detach,
6225         .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
6226         .drain_rq = mlx5_ib_drain_rq,
6227         .drain_sq = mlx5_ib_drain_sq,
6228         .get_dev_fw_str = get_dev_fw_str,
6229         .get_dma_mr = mlx5_ib_get_dma_mr,
6230         .get_link_layer = mlx5_ib_port_link_layer,
6231         .map_mr_sg = mlx5_ib_map_mr_sg,
6232         .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
6233         .mmap = mlx5_ib_mmap,
6234         .modify_cq = mlx5_ib_modify_cq,
6235         .modify_device = mlx5_ib_modify_device,
6236         .modify_port = mlx5_ib_modify_port,
6237         .modify_qp = mlx5_ib_modify_qp,
6238         .modify_srq = mlx5_ib_modify_srq,
6239         .poll_cq = mlx5_ib_poll_cq,
6240         .post_recv = mlx5_ib_post_recv,
6241         .post_send = mlx5_ib_post_send,
6242         .post_srq_recv = mlx5_ib_post_srq_recv,
6243         .process_mad = mlx5_ib_process_mad,
6244         .query_ah = mlx5_ib_query_ah,
6245         .query_device = mlx5_ib_query_device,
6246         .query_gid = mlx5_ib_query_gid,
6247         .query_pkey = mlx5_ib_query_pkey,
6248         .query_qp = mlx5_ib_query_qp,
6249         .query_srq = mlx5_ib_query_srq,
6250         .read_counters = mlx5_ib_read_counters,
6251         .reg_user_mr = mlx5_ib_reg_user_mr,
6252         .req_notify_cq = mlx5_ib_arm_cq,
6253         .rereg_user_mr = mlx5_ib_rereg_user_mr,
6254         .resize_cq = mlx5_ib_resize_cq,
6255
6256         INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
6257         INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
6258         INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
6259         INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
6260         INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
6261 };
6262
6263 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops = {
6264         .create_flow_action_esp = mlx5_ib_create_flow_action_esp,
6265         .modify_flow_action_esp = mlx5_ib_modify_flow_action_esp,
6266 };
6267
6268 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
6269         .rdma_netdev_get_params = mlx5_ib_rn_get_params,
6270 };
6271
6272 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
6273         .get_vf_config = mlx5_ib_get_vf_config,
6274         .get_vf_stats = mlx5_ib_get_vf_stats,
6275         .set_vf_guid = mlx5_ib_set_vf_guid,
6276         .set_vf_link_state = mlx5_ib_set_vf_link_state,
6277 };
6278
6279 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
6280         .alloc_mw = mlx5_ib_alloc_mw,
6281         .dealloc_mw = mlx5_ib_dealloc_mw,
6282 };
6283
6284 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
6285         .alloc_xrcd = mlx5_ib_alloc_xrcd,
6286         .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
6287 };
6288
6289 static const struct ib_device_ops mlx5_ib_dev_dm_ops = {
6290         .alloc_dm = mlx5_ib_alloc_dm,
6291         .dealloc_dm = mlx5_ib_dealloc_dm,
6292         .reg_dm_mr = mlx5_ib_reg_dm_mr,
6293 };
6294
6295 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
6296 {
6297         struct mlx5_core_dev *mdev = dev->mdev;
6298         int err;
6299
6300         dev->ib_dev.uverbs_cmd_mask     =
6301                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
6302                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
6303                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
6304                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
6305                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
6306                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
6307                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
6308                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
6309                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
6310                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
6311                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
6312                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
6313                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
6314                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
6315                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
6316                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
6317                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
6318                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
6319                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
6320                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
6321                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
6322                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
6323                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
6324                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
6325                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
6326                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
6327         dev->ib_dev.uverbs_ex_cmd_mask =
6328                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
6329                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
6330                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
6331                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP)        |
6332                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ)        |
6333                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW)      |
6334                 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
6335
6336         if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
6337             IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
6338                 ib_set_device_ops(&dev->ib_dev,
6339                                   &mlx5_ib_dev_ipoib_enhanced_ops);
6340
6341         if (mlx5_core_is_pf(mdev))
6342                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
6343
6344         dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
6345
6346         if (MLX5_CAP_GEN(mdev, imaicl)) {
6347                 dev->ib_dev.uverbs_cmd_mask |=
6348                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
6349                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
6350                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
6351         }
6352
6353         if (MLX5_CAP_GEN(mdev, xrc)) {
6354                 dev->ib_dev.uverbs_cmd_mask |=
6355                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
6356                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
6357                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
6358         }
6359
6360         if (MLX5_CAP_DEV_MEM(mdev, memic) ||
6361             MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
6362             MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
6363                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
6364
6365         if (mlx5_accel_ipsec_device_caps(dev->mdev) &
6366             MLX5_ACCEL_IPSEC_CAP_DEVICE)
6367                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_flow_ipsec_ops);
6368         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
6369
6370         if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
6371                 dev->ib_dev.driver_def = mlx5_ib_defs;
6372
6373         err = init_node_data(dev);
6374         if (err)
6375                 return err;
6376
6377         if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
6378             (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
6379              MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
6380                 mutex_init(&dev->lb.mutex);
6381
6382         dev->ib_dev.use_cq_dim = true;
6383
6384         return 0;
6385 }
6386
6387 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
6388         .get_port_immutable = mlx5_port_immutable,
6389         .query_port = mlx5_ib_query_port,
6390 };
6391
6392 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
6393 {
6394         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
6395         return 0;
6396 }
6397
6398 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
6399         .get_port_immutable = mlx5_port_rep_immutable,
6400         .query_port = mlx5_ib_rep_query_port,
6401 };
6402
6403 static int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
6404 {
6405         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
6406         return 0;
6407 }
6408
6409 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
6410         .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
6411         .create_wq = mlx5_ib_create_wq,
6412         .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
6413         .destroy_wq = mlx5_ib_destroy_wq,
6414         .get_netdev = mlx5_ib_get_netdev,
6415         .modify_wq = mlx5_ib_modify_wq,
6416 };
6417
6418 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
6419 {
6420         u8 port_num;
6421
6422         dev->ib_dev.uverbs_ex_cmd_mask |=
6423                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
6424                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
6425                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
6426                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
6427                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
6428         ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
6429
6430         port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6431
6432         /* Register only for native ports */
6433         return mlx5_add_netdev_notifier(dev, port_num);
6434 }
6435
6436 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
6437 {
6438         u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
6439
6440         mlx5_remove_netdev_notifier(dev, port_num);
6441 }
6442
6443 static int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
6444 {
6445         struct mlx5_core_dev *mdev = dev->mdev;
6446         enum rdma_link_layer ll;
6447         int port_type_cap;
6448         int err = 0;
6449
6450         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6451         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6452
6453         if (ll == IB_LINK_LAYER_ETHERNET)
6454                 err = mlx5_ib_stage_common_roce_init(dev);
6455
6456         return err;
6457 }
6458
6459 static void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
6460 {
6461         mlx5_ib_stage_common_roce_cleanup(dev);
6462 }
6463
6464 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6465 {
6466         struct mlx5_core_dev *mdev = dev->mdev;
6467         enum rdma_link_layer ll;
6468         int port_type_cap;
6469         int err;
6470
6471         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6472         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6473
6474         if (ll == IB_LINK_LAYER_ETHERNET) {
6475                 err = mlx5_ib_stage_common_roce_init(dev);
6476                 if (err)
6477                         return err;
6478
6479                 err = mlx5_enable_eth(dev);
6480                 if (err)
6481                         goto cleanup;
6482         }
6483
6484         return 0;
6485 cleanup:
6486         mlx5_ib_stage_common_roce_cleanup(dev);
6487
6488         return err;
6489 }
6490
6491 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6492 {
6493         struct mlx5_core_dev *mdev = dev->mdev;
6494         enum rdma_link_layer ll;
6495         int port_type_cap;
6496
6497         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6498         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6499
6500         if (ll == IB_LINK_LAYER_ETHERNET) {
6501                 mlx5_disable_eth(dev);
6502                 mlx5_ib_stage_common_roce_cleanup(dev);
6503         }
6504 }
6505
6506 static int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6507 {
6508         return create_dev_resources(&dev->devr);
6509 }
6510
6511 static void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6512 {
6513         destroy_dev_resources(&dev->devr);
6514 }
6515
6516 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6517 {
6518         return mlx5_ib_odp_init_one(dev);
6519 }
6520
6521 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev *dev)
6522 {
6523         mlx5_ib_odp_cleanup_one(dev);
6524 }
6525
6526 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops = {
6527         .alloc_hw_stats = mlx5_ib_alloc_hw_stats,
6528         .get_hw_stats = mlx5_ib_get_hw_stats,
6529         .counter_bind_qp = mlx5_ib_counter_bind_qp,
6530         .counter_unbind_qp = mlx5_ib_counter_unbind_qp,
6531         .counter_dealloc = mlx5_ib_counter_dealloc,
6532         .counter_alloc_stats = mlx5_ib_counter_alloc_stats,
6533         .counter_update_stats = mlx5_ib_counter_update_stats,
6534 };
6535
6536 static int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6537 {
6538         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6539                 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_hw_stats_ops);
6540
6541                 return mlx5_ib_alloc_counters(dev);
6542         }
6543
6544         return 0;
6545 }
6546
6547 static void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6548 {
6549         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6550                 mlx5_ib_dealloc_counters(dev);
6551 }
6552
6553 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6554 {
6555         mlx5_ib_init_cong_debugfs(dev,
6556                                   mlx5_core_native_port_num(dev->mdev) - 1);
6557         return 0;
6558 }
6559
6560 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6561 {
6562         mlx5_ib_cleanup_cong_debugfs(dev,
6563                                      mlx5_core_native_port_num(dev->mdev) - 1);
6564 }
6565
6566 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6567 {
6568         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6569         return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6570 }
6571
6572 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6573 {
6574         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6575 }
6576
6577 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6578 {
6579         int err;
6580
6581         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6582         if (err)
6583                 return err;
6584
6585         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6586         if (err)
6587                 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6588
6589         return err;
6590 }
6591
6592 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6593 {
6594         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6595         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6596 }
6597
6598 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6599 {
6600         const char *name;
6601
6602         rdma_set_device_sysfs_group(&dev->ib_dev, &mlx5_attr_group);
6603         if (!mlx5_lag_is_roce(dev->mdev))
6604                 name = "mlx5_%d";
6605         else
6606                 name = "mlx5_bond_%d";
6607         return ib_register_device(&dev->ib_dev, name);
6608 }
6609
6610 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6611 {
6612         destroy_umrc_res(dev);
6613 }
6614
6615 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6616 {
6617         ib_unregister_device(&dev->ib_dev);
6618 }
6619
6620 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6621 {
6622         return create_umr_res(dev);
6623 }
6624
6625 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6626 {
6627         init_delay_drop(dev);
6628
6629         return 0;
6630 }
6631
6632 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6633 {
6634         cancel_delay_drop(dev);
6635 }
6636
6637 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
6638 {
6639         dev->mdev_events.notifier_call = mlx5_ib_event;
6640         mlx5_notifier_register(dev->mdev, &dev->mdev_events);
6641         return 0;
6642 }
6643
6644 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
6645 {
6646         mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
6647 }
6648
6649 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev *dev)
6650 {
6651         int uid;
6652
6653         uid = mlx5_ib_devx_create(dev, false);
6654         if (uid > 0) {
6655                 dev->devx_whitelist_uid = uid;
6656                 mlx5_ib_devx_init_event_table(dev);
6657         }
6658
6659         return 0;
6660 }
6661 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev *dev)
6662 {
6663         if (dev->devx_whitelist_uid) {
6664                 mlx5_ib_devx_cleanup_event_table(dev);
6665                 mlx5_ib_devx_destroy(dev, dev->devx_whitelist_uid);
6666         }
6667 }
6668
6669 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6670                       const struct mlx5_ib_profile *profile,
6671                       int stage)
6672 {
6673         /* Number of stages to cleanup */
6674         while (stage) {
6675                 stage--;
6676                 if (profile->stage[stage].cleanup)
6677                         profile->stage[stage].cleanup(dev);
6678         }
6679
6680         kfree(dev->port);
6681         ib_dealloc_device(&dev->ib_dev);
6682 }
6683
6684 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6685                     const struct mlx5_ib_profile *profile)
6686 {
6687         int err;
6688         int i;
6689
6690         for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6691                 if (profile->stage[i].init) {
6692                         err = profile->stage[i].init(dev);
6693                         if (err)
6694                                 goto err_out;
6695                 }
6696         }
6697
6698         dev->profile = profile;
6699         dev->ib_active = true;
6700
6701         return dev;
6702
6703 err_out:
6704         __mlx5_ib_remove(dev, profile, i);
6705
6706         return NULL;
6707 }
6708
6709 static const struct mlx5_ib_profile pf_profile = {
6710         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6711                      mlx5_ib_stage_init_init,
6712                      mlx5_ib_stage_init_cleanup),
6713         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6714                      mlx5_ib_stage_flow_db_init,
6715                      mlx5_ib_stage_flow_db_cleanup),
6716         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6717                      mlx5_ib_stage_caps_init,
6718                      NULL),
6719         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6720                      mlx5_ib_stage_non_default_cb,
6721                      NULL),
6722         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6723                      mlx5_ib_stage_roce_init,
6724                      mlx5_ib_stage_roce_cleanup),
6725         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6726                      mlx5_init_srq_table,
6727                      mlx5_cleanup_srq_table),
6728         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6729                      mlx5_ib_stage_dev_res_init,
6730                      mlx5_ib_stage_dev_res_cleanup),
6731         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6732                      mlx5_ib_stage_dev_notifier_init,
6733                      mlx5_ib_stage_dev_notifier_cleanup),
6734         STAGE_CREATE(MLX5_IB_STAGE_ODP,
6735                      mlx5_ib_stage_odp_init,
6736                      mlx5_ib_stage_odp_cleanup),
6737         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6738                      mlx5_ib_stage_counters_init,
6739                      mlx5_ib_stage_counters_cleanup),
6740         STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6741                      mlx5_ib_stage_cong_debugfs_init,
6742                      mlx5_ib_stage_cong_debugfs_cleanup),
6743         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6744                      mlx5_ib_stage_uar_init,
6745                      mlx5_ib_stage_uar_cleanup),
6746         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6747                      mlx5_ib_stage_bfrag_init,
6748                      mlx5_ib_stage_bfrag_cleanup),
6749         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6750                      NULL,
6751                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6752         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6753                      mlx5_ib_stage_devx_init,
6754                      mlx5_ib_stage_devx_cleanup),
6755         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6756                      mlx5_ib_stage_ib_reg_init,
6757                      mlx5_ib_stage_ib_reg_cleanup),
6758         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6759                      mlx5_ib_stage_post_ib_reg_umr_init,
6760                      NULL),
6761         STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6762                      mlx5_ib_stage_delay_drop_init,
6763                      mlx5_ib_stage_delay_drop_cleanup),
6764 };
6765
6766 const struct mlx5_ib_profile uplink_rep_profile = {
6767         STAGE_CREATE(MLX5_IB_STAGE_INIT,
6768                      mlx5_ib_stage_init_init,
6769                      mlx5_ib_stage_init_cleanup),
6770         STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6771                      mlx5_ib_stage_flow_db_init,
6772                      mlx5_ib_stage_flow_db_cleanup),
6773         STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6774                      mlx5_ib_stage_caps_init,
6775                      NULL),
6776         STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6777                      mlx5_ib_stage_rep_non_default_cb,
6778                      NULL),
6779         STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6780                      mlx5_ib_stage_rep_roce_init,
6781                      mlx5_ib_stage_rep_roce_cleanup),
6782         STAGE_CREATE(MLX5_IB_STAGE_SRQ,
6783                      mlx5_init_srq_table,
6784                      mlx5_cleanup_srq_table),
6785         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6786                      mlx5_ib_stage_dev_res_init,
6787                      mlx5_ib_stage_dev_res_cleanup),
6788         STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
6789                      mlx5_ib_stage_dev_notifier_init,
6790                      mlx5_ib_stage_dev_notifier_cleanup),
6791         STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6792                      mlx5_ib_stage_counters_init,
6793                      mlx5_ib_stage_counters_cleanup),
6794         STAGE_CREATE(MLX5_IB_STAGE_UAR,
6795                      mlx5_ib_stage_uar_init,
6796                      mlx5_ib_stage_uar_cleanup),
6797         STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6798                      mlx5_ib_stage_bfrag_init,
6799                      mlx5_ib_stage_bfrag_cleanup),
6800         STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6801                      NULL,
6802                      mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6803         STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
6804                      mlx5_ib_stage_devx_init,
6805                      mlx5_ib_stage_devx_cleanup),
6806         STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6807                      mlx5_ib_stage_ib_reg_init,
6808                      mlx5_ib_stage_ib_reg_cleanup),
6809         STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6810                      mlx5_ib_stage_post_ib_reg_umr_init,
6811                      NULL),
6812 };
6813
6814 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6815 {
6816         struct mlx5_ib_multiport_info *mpi;
6817         struct mlx5_ib_dev *dev;
6818         bool bound = false;
6819         int err;
6820
6821         mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6822         if (!mpi)
6823                 return NULL;
6824
6825         mpi->mdev = mdev;
6826
6827         err = mlx5_query_nic_vport_system_image_guid(mdev,
6828                                                      &mpi->sys_image_guid);
6829         if (err) {
6830                 kfree(mpi);
6831                 return NULL;
6832         }
6833
6834         mutex_lock(&mlx5_ib_multiport_mutex);
6835         list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6836                 if (dev->sys_image_guid == mpi->sys_image_guid)
6837                         bound = mlx5_ib_bind_slave_port(dev, mpi);
6838
6839                 if (bound) {
6840                         rdma_roce_rescan_device(&dev->ib_dev);
6841                         break;
6842                 }
6843         }
6844
6845         if (!bound) {
6846                 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6847                 dev_dbg(mdev->device,
6848                         "no suitable IB device found to bind to, added to unaffiliated list.\n");
6849         }
6850         mutex_unlock(&mlx5_ib_multiport_mutex);
6851
6852         return mpi;
6853 }
6854
6855 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6856 {
6857         enum rdma_link_layer ll;
6858         struct mlx5_ib_dev *dev;
6859         int port_type_cap;
6860         int num_ports;
6861
6862         printk_once(KERN_INFO "%s", mlx5_version);
6863
6864         if (MLX5_ESWITCH_MANAGER(mdev) &&
6865             mlx5_ib_eswitch_mode(mdev->priv.eswitch) == MLX5_ESWITCH_OFFLOADS) {
6866                 if (!mlx5_core_mp_enabled(mdev))
6867                         mlx5_ib_register_vport_reps(mdev);
6868                 return mdev;
6869         }
6870
6871         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6872         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6873
6874         if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6875                 return mlx5_ib_add_slave_port(mdev);
6876
6877         num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6878                         MLX5_CAP_GEN(mdev, num_vhca_ports));
6879         dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
6880         if (!dev)
6881                 return NULL;
6882         dev->port = kcalloc(num_ports, sizeof(*dev->port),
6883                              GFP_KERNEL);
6884         if (!dev->port) {
6885                 ib_dealloc_device((struct ib_device *)dev);
6886                 return NULL;
6887         }
6888
6889         dev->mdev = mdev;
6890         dev->num_ports = num_ports;
6891
6892         return __mlx5_ib_add(dev, &pf_profile);
6893 }
6894
6895 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6896 {
6897         struct mlx5_ib_multiport_info *mpi;
6898         struct mlx5_ib_dev *dev;
6899
6900         if (MLX5_ESWITCH_MANAGER(mdev) && context == mdev) {
6901                 mlx5_ib_unregister_vport_reps(mdev);
6902                 return;
6903         }
6904
6905         if (mlx5_core_is_mp_slave(mdev)) {
6906                 mpi = context;
6907                 mutex_lock(&mlx5_ib_multiport_mutex);
6908                 if (mpi->ibdev)
6909                         mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6910                 list_del(&mpi->list);
6911                 mutex_unlock(&mlx5_ib_multiport_mutex);
6912                 return;
6913         }
6914
6915         dev = context;
6916         __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6917 }
6918
6919 static struct mlx5_interface mlx5_ib_interface = {
6920         .add            = mlx5_ib_add,
6921         .remove         = mlx5_ib_remove,
6922         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
6923 };
6924
6925 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6926 {
6927         mutex_lock(&xlt_emergency_page_mutex);
6928         return xlt_emergency_page;
6929 }
6930
6931 void mlx5_ib_put_xlt_emergency_page(void)
6932 {
6933         mutex_unlock(&xlt_emergency_page_mutex);
6934 }
6935
6936 static int __init mlx5_ib_init(void)
6937 {
6938         int err;
6939
6940         xlt_emergency_page = __get_free_page(GFP_KERNEL);
6941         if (!xlt_emergency_page)
6942                 return -ENOMEM;
6943
6944         mutex_init(&xlt_emergency_page_mutex);
6945
6946         mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6947         if (!mlx5_ib_event_wq) {
6948                 free_page(xlt_emergency_page);
6949                 return -ENOMEM;
6950         }
6951
6952         mlx5_ib_odp_init();
6953
6954         err = mlx5_register_interface(&mlx5_ib_interface);
6955
6956         return err;
6957 }
6958
6959 static void __exit mlx5_ib_cleanup(void)
6960 {
6961         mlx5_unregister_interface(&mlx5_ib_interface);
6962         destroy_workqueue(mlx5_ib_event_wq);
6963         mutex_destroy(&xlt_emergency_page_mutex);
6964         free_page(xlt_emergency_page);
6965 }
6966
6967 module_init(mlx5_ib_init);
6968 module_exit(mlx5_ib_cleanup);