drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <[email protected]>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39
  40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  41 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  42 static int uvd_v6_0_start(struct amdgpu_device *adev);
  43 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  44 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  45
  46 /**
  47  * uvd_v6_0_ring_get_rptr - get read pointer
  48  *
  49  * @ring: amdgpu_ring pointer
  50  *
  51  * Returns the current hardware read pointer
  52  */
  53 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  54 {
  55         struct amdgpu_device *adev = ring->adev;
  56
  57         return RREG32(mmUVD_RBC_RB_RPTR);
  58 }
  59
  60 /**
  61  * uvd_v6_0_ring_get_wptr - get write pointer
  62  *
  63  * @ring: amdgpu_ring pointer
  64  *
  65  * Returns the current hardware write pointer
  66  */
  67 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
  68 {
  69         struct amdgpu_device *adev = ring->adev;
  70
  71         return RREG32(mmUVD_RBC_RB_WPTR);
  72 }
  73
  74 /**
  75  * uvd_v6_0_ring_set_wptr - set write pointer
  76  *
  77  * @ring: amdgpu_ring pointer
  78  *
  79  * Commits the write pointer to the hardware
  80  */
  81 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
  82 {
  83         struct amdgpu_device *adev = ring->adev;
  84
  85         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
  86 }
  87
  88 static int uvd_v6_0_early_init(void *handle)
  89 {
  90         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  91
  92         uvd_v6_0_set_ring_funcs(adev);
  93         uvd_v6_0_set_irq_funcs(adev);
  94
  95         return 0;
  96 }
  97
  98 static int uvd_v6_0_sw_init(void *handle)
  99 {
 100         struct amdgpu_ring *ring;
 101         int r;
 102         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 103
 104         /* UVD TRAP */
 105         r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
 106         if (r)
 107                 return r;
 108
 109         r = amdgpu_uvd_sw_init(adev);
 110         if (r)
 111                 return r;
 112
 113         r = amdgpu_uvd_resume(adev);
 114         if (r)
 115                 return r;
 116
 117         ring = &adev->uvd.ring;
 118         sprintf(ring->name, "uvd");
 119         r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf,
 120                              &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
 121
 122         return r;
 123 }
 124
 125 static int uvd_v6_0_sw_fini(void *handle)
 126 {
 127         int r;
 128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 129
 130         r = amdgpu_uvd_suspend(adev);
 131         if (r)
 132                 return r;
 133
 134         r = amdgpu_uvd_sw_fini(adev);
 135         if (r)
 136                 return r;
 137
 138         return r;
 139 }
 140
 141 /**
 142  * uvd_v6_0_hw_init - start and test UVD block
 143  *
 144  * @adev: amdgpu_device pointer
 145  *
 146  * Initialize the hardware, boot up the VCPU and do some testing
 147  */
 148 static int uvd_v6_0_hw_init(void *handle)
 149 {
 150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 151         struct amdgpu_ring *ring = &adev->uvd.ring;
 152         uint32_t tmp;
 153         int r;
 154
 155         r = uvd_v6_0_start(adev);
 156         if (r)
 157                 goto done;
 158
 159         ring->ready = true;
 160         r = amdgpu_ring_test_ring(ring);
 161         if (r) {
 162                 ring->ready = false;
 163                 goto done;
 164         }
 165
 166         r = amdgpu_ring_alloc(ring, 10);
 167         if (r) {
 168                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 169                 goto done;
 170         }
 171
 172         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 173         amdgpu_ring_write(ring, tmp);
 174         amdgpu_ring_write(ring, 0xFFFFF);
 175
 176         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 177         amdgpu_ring_write(ring, tmp);
 178         amdgpu_ring_write(ring, 0xFFFFF);
 179
 180         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 181         amdgpu_ring_write(ring, tmp);
 182         amdgpu_ring_write(ring, 0xFFFFF);
 183
 184         /* Clear timeout status bits */
 185         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 186         amdgpu_ring_write(ring, 0x8);
 187
 188         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 189         amdgpu_ring_write(ring, 3);
 190
 191         amdgpu_ring_commit(ring);
 192
 193 done:
 194         if (!r)
 195                 DRM_INFO("UVD initialized successfully.\n");
 196
 197         return r;
 198 }
 199
 200 /**
 201  * uvd_v6_0_hw_fini - stop the hardware block
 202  *
 203  * @adev: amdgpu_device pointer
 204  *
 205  * Stop the UVD block, mark ring as not ready any more
 206  */
 207 static int uvd_v6_0_hw_fini(void *handle)
 208 {
 209         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 210         struct amdgpu_ring *ring = &adev->uvd.ring;
 211
 212         uvd_v6_0_stop(adev);
 213         ring->ready = false;
 214
 215         return 0;
 216 }
 217
 218 static int uvd_v6_0_suspend(void *handle)
 219 {
 220         int r;
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222
 223         r = uvd_v6_0_hw_fini(adev);
 224         if (r)
 225                 return r;
 226
 227         /* Skip this for APU for now */
 228         if (!(adev->flags & AMD_IS_APU)) {
 229                 r = amdgpu_uvd_suspend(adev);
 230                 if (r)
 231                         return r;
 232         }
 233
 234         return r;
 235 }
 236
 237 static int uvd_v6_0_resume(void *handle)
 238 {
 239         int r;
 240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 241
 242         /* Skip this for APU for now */
 243         if (!(adev->flags & AMD_IS_APU)) {
 244                 r = amdgpu_uvd_resume(adev);
 245                 if (r)
 246                         return r;
 247         }
 248         r = uvd_v6_0_hw_init(adev);
 249         if (r)
 250                 return r;
 251
 252         return r;
 253 }
 254
 255 /**
 256  * uvd_v6_0_mc_resume - memory controller programming
 257  *
 258  * @adev: amdgpu_device pointer
 259  *
 260  * Let the UVD memory controller know it's offsets
 261  */
 262 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 263 {
 264         uint64_t offset;
 265         uint32_t size;
 266
 267         /* programm memory controller bits 0-27 */
 268         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 269                         lower_32_bits(adev->uvd.gpu_addr));
 270         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 271                         upper_32_bits(adev->uvd.gpu_addr));
 272
 273         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 274         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 275         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 276         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 277
 278         offset += size;
 279         size = AMDGPU_UVD_HEAP_SIZE;
 280         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 281         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 282
 283         offset += size;
 284         size = AMDGPU_UVD_STACK_SIZE +
 285                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 286         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 287         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 288
 289         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 290         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 291         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 292
 293         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 294 }
 295
 296 #if 0
 297 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 298                 bool enable)
 299 {
 300         u32 data, data1;
 301
 302         data = RREG32(mmUVD_CGC_GATE);
 303         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 304         if (enable) {
 305                 data |= UVD_CGC_GATE__SYS_MASK |
 306                                 UVD_CGC_GATE__UDEC_MASK |
 307                                 UVD_CGC_GATE__MPEG2_MASK |
 308                                 UVD_CGC_GATE__RBC_MASK |
 309                                 UVD_CGC_GATE__LMI_MC_MASK |
 310                                 UVD_CGC_GATE__IDCT_MASK |
 311                                 UVD_CGC_GATE__MPRD_MASK |
 312                                 UVD_CGC_GATE__MPC_MASK |
 313                                 UVD_CGC_GATE__LBSI_MASK |
 314                                 UVD_CGC_GATE__LRBBM_MASK |
 315                                 UVD_CGC_GATE__UDEC_RE_MASK |
 316                                 UVD_CGC_GATE__UDEC_CM_MASK |
 317                                 UVD_CGC_GATE__UDEC_IT_MASK |
 318                                 UVD_CGC_GATE__UDEC_DB_MASK |
 319                                 UVD_CGC_GATE__UDEC_MP_MASK |
 320                                 UVD_CGC_GATE__WCB_MASK |
 321                                 UVD_CGC_GATE__VCPU_MASK |
 322                                 UVD_CGC_GATE__SCPU_MASK;
 323                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 324                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 325                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 326                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 327                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 328                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 329                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 330                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 331                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 332                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 333                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 334                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 335                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 336         } else {
 337                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 338                                 UVD_CGC_GATE__UDEC_MASK |
 339                                 UVD_CGC_GATE__MPEG2_MASK |
 340                                 UVD_CGC_GATE__RBC_MASK |
 341                                 UVD_CGC_GATE__LMI_MC_MASK |
 342                                 UVD_CGC_GATE__LMI_UMC_MASK |
 343                                 UVD_CGC_GATE__IDCT_MASK |
 344                                 UVD_CGC_GATE__MPRD_MASK |
 345                                 UVD_CGC_GATE__MPC_MASK |
 346                                 UVD_CGC_GATE__LBSI_MASK |
 347                                 UVD_CGC_GATE__LRBBM_MASK |
 348                                 UVD_CGC_GATE__UDEC_RE_MASK |
 349                                 UVD_CGC_GATE__UDEC_CM_MASK |
 350                                 UVD_CGC_GATE__UDEC_IT_MASK |
 351                                 UVD_CGC_GATE__UDEC_DB_MASK |
 352                                 UVD_CGC_GATE__UDEC_MP_MASK |
 353                                 UVD_CGC_GATE__WCB_MASK |
 354                                 UVD_CGC_GATE__VCPU_MASK |
 355                                 UVD_CGC_GATE__SCPU_MASK);
 356                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 357                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 358                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 359                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 360                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 361                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 362                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 363                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 364                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 365                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 366                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 367                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 368                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 369         }
 370         WREG32(mmUVD_CGC_GATE, data);
 371         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 372 }
 373 #endif
 374
 375 /**
 376  * uvd_v6_0_start - start UVD block
 377  *
 378  * @adev: amdgpu_device pointer
 379  *
 380  * Setup and start the UVD block
 381  */
 382 static int uvd_v6_0_start(struct amdgpu_device *adev)
 383 {
 384         struct amdgpu_ring *ring = &adev->uvd.ring;
 385         uint32_t rb_bufsz, tmp;
 386         uint32_t lmi_swap_cntl;
 387         uint32_t mp_swap_cntl;
 388         int i, j, r;
 389
 390         /* disable DPG */
 391         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 392
 393         /* disable byte swapping */
 394         lmi_swap_cntl = 0;
 395         mp_swap_cntl = 0;
 396
 397         uvd_v6_0_mc_resume(adev);
 398
 399         /* disable clock gating */
 400         WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0);
 401
 402         /* disable interupt */
 403         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 404
 405         /* stall UMC and register bus before resetting VCPU */
 406         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 407         mdelay(1);
 408
 409         /* put LMI, VCPU, RBC etc... into reset */
 410         WREG32(mmUVD_SOFT_RESET,
 411                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 412                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 413                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 414                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 415                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 416                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 417                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 418                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 419         mdelay(5);
 420
 421         /* take UVD block out of reset */
 422         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 423         mdelay(5);
 424
 425         /* initialize UVD memory controller */
 426         WREG32(mmUVD_LMI_CTRL,
 427                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 428                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 429                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 430                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 431                 UVD_LMI_CTRL__REQ_MODE_MASK |
 432                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 433
 434 #ifdef __BIG_ENDIAN
 435         /* swap (8 in 32) RB and IB */
 436         lmi_swap_cntl = 0xa;
 437         mp_swap_cntl = 0;
 438 #endif
 439         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 440         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 441
 442         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 443         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 444         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 445         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 446         WREG32(mmUVD_MPC_SET_ALU, 0);
 447         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 448
 449         /* take all subblocks out of reset, except VCPU */
 450         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 451         mdelay(5);
 452
 453         /* enable VCPU clock */
 454         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 455
 456         /* enable UMC */
 457         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 458
 459         /* boot up the VCPU */
 460         WREG32(mmUVD_SOFT_RESET, 0);
 461         mdelay(10);
 462
 463         for (i = 0; i < 10; ++i) {
 464                 uint32_t status;
 465
 466                 for (j = 0; j < 100; ++j) {
 467                         status = RREG32(mmUVD_STATUS);
 468                         if (status & 2)
 469                                 break;
 470                         mdelay(10);
 471                 }
 472                 r = 0;
 473                 if (status & 2)
 474                         break;
 475
 476                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 477                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 478                 mdelay(10);
 479                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 480                 mdelay(10);
 481                 r = -1;
 482         }
 483
 484         if (r) {
 485                 DRM_ERROR("UVD not responding, giving up!!!\n");
 486                 return r;
 487         }
 488         /* enable master interrupt */
 489         WREG32_P(mmUVD_MASTINT_EN,
 490                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 491                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 492
 493         /* clear the bit 4 of UVD_STATUS */
 494         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 495
 496         /* force RBC into idle state */
 497         rb_bufsz = order_base_2(ring->ring_size);
 498         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 499         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 500         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 501         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 502         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 503         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 504         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 505
 506         /* set the write pointer delay */
 507         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 508
 509         /* set the wb address */
 510         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 511
 512         /* programm the RB_BASE for ring buffer */
 513         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 514                         lower_32_bits(ring->gpu_addr));
 515         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 516                         upper_32_bits(ring->gpu_addr));
 517
 518         /* Initialize the ring buffer's read and write pointers */
 519         WREG32(mmUVD_RBC_RB_RPTR, 0);
 520
 521         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 522         WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
 523
 524         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 525
 526         return 0;
 527 }
 528
 529 /**
 530  * uvd_v6_0_stop - stop UVD block
 531  *
 532  * @adev: amdgpu_device pointer
 533  *
 534  * stop the UVD block
 535  */
 536 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 537 {
 538         /* force RBC into idle state */
 539         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 540
 541         /* Stall UMC and register bus before resetting VCPU */
 542         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 543         mdelay(1);
 544
 545         /* put VCPU into reset */
 546         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 547         mdelay(5);
 548
 549         /* disable VCPU clock */
 550         WREG32(mmUVD_VCPU_CNTL, 0x0);
 551
 552         /* Unstall UMC and register bus */
 553         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 554 }
 555
 556 /**
 557  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 558  *
 559  * @ring: amdgpu_ring pointer
 560  * @fence: fence to emit
 561  *
 562  * Write a fence and a trap command to the ring.
 563  */
 564 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 565                                      unsigned flags)
 566 {
 567         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 568
 569         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 570         amdgpu_ring_write(ring, seq);
 571         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 572         amdgpu_ring_write(ring, addr & 0xffffffff);
 573         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 574         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 575         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 576         amdgpu_ring_write(ring, 0);
 577
 578         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 579         amdgpu_ring_write(ring, 0);
 580         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 581         amdgpu_ring_write(ring, 0);
 582         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 583         amdgpu_ring_write(ring, 2);
 584 }
 585
 586 /**
 587  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 588  *
 589  * @ring: amdgpu_ring pointer
 590  *
 591  * Emits an hdp flush.
 592  */
 593 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 594 {
 595         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 596         amdgpu_ring_write(ring, 0);
 597 }
 598
 599 /**
 600  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 601  *
 602  * @ring: amdgpu_ring pointer
 603  *
 604  * Emits an hdp invalidate.
 605  */
 606 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 607 {
 608         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 609         amdgpu_ring_write(ring, 1);
 610 }
 611
 612 /**
 613  * uvd_v6_0_ring_test_ring - register write test
 614  *
 615  * @ring: amdgpu_ring pointer
 616  *
 617  * Test if we can successfully write to the context register
 618  */
 619 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 620 {
 621         struct amdgpu_device *adev = ring->adev;
 622         uint32_t tmp = 0;
 623         unsigned i;
 624         int r;
 625
 626         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 627         r = amdgpu_ring_alloc(ring, 3);
 628         if (r) {
 629                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 630                           ring->idx, r);
 631                 return r;
 632         }
 633         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 634         amdgpu_ring_write(ring, 0xDEADBEEF);
 635         amdgpu_ring_commit(ring);
 636         for (i = 0; i < adev->usec_timeout; i++) {
 637                 tmp = RREG32(mmUVD_CONTEXT_ID);
 638                 if (tmp == 0xDEADBEEF)
 639                         break;
 640                 DRM_UDELAY(1);
 641         }
 642
 643         if (i < adev->usec_timeout) {
 644                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 645                          ring->idx, i);
 646         } else {
 647                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 648                           ring->idx, tmp);
 649                 r = -EINVAL;
 650         }
 651         return r;
 652 }
 653
 654 /**
 655  * uvd_v6_0_ring_emit_ib - execute indirect buffer
 656  *
 657  * @ring: amdgpu_ring pointer
 658  * @ib: indirect buffer to execute
 659  *
 660  * Write ring commands to execute the indirect buffer
 661  */
 662 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 663                                   struct amdgpu_ib *ib,
 664                                   unsigned vm_id, bool ctx_switch)
 665 {
 666         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
 667         amdgpu_ring_write(ring, vm_id);
 668
 669         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
 670         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 671         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
 672         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 673         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
 674         amdgpu_ring_write(ring, ib->length_dw);
 675 }
 676
 677 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 678                                          unsigned vm_id, uint64_t pd_addr)
 679 {
 680         uint32_t reg;
 681
 682         if (vm_id < 8)
 683                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
 684         else
 685                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
 686
 687         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 688         amdgpu_ring_write(ring, reg << 2);
 689         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 690         amdgpu_ring_write(ring, pd_addr >> 12);
 691         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 692         amdgpu_ring_write(ring, 0x8);
 693
 694         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 695         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 696         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 697         amdgpu_ring_write(ring, 1 << vm_id);
 698         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 699         amdgpu_ring_write(ring, 0x8);
 700
 701         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 702         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 703         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 704         amdgpu_ring_write(ring, 0);
 705         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 706         amdgpu_ring_write(ring, 1 << vm_id); /* mask */
 707         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 708         amdgpu_ring_write(ring, 0xC);
 709 }
 710
 711 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 712 {
 713         uint32_t seq = ring->fence_drv.sync_seq;
 714         uint64_t addr = ring->fence_drv.gpu_addr;
 715
 716         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 717         amdgpu_ring_write(ring, lower_32_bits(addr));
 718         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 719         amdgpu_ring_write(ring, upper_32_bits(addr));
 720         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
 721         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 722         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
 723         amdgpu_ring_write(ring, seq);
 724         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 725         amdgpu_ring_write(ring, 0xE);
 726 }
 727
 728 static unsigned uvd_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring)
 729 {
 730         return
 731                 8; /* uvd_v6_0_ring_emit_ib */
 732 }
 733
 734 static unsigned uvd_v6_0_ring_get_dma_frame_size(struct amdgpu_ring *ring)
 735 {
 736         return
 737                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
 738                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
 739                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 740                 14; /* uvd_v6_0_ring_emit_fence x1 no user fence */
 741 }
 742
 743 static unsigned uvd_v6_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring)
 744 {
 745         return
 746                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
 747                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
 748                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
 749                 20 + /* uvd_v6_0_ring_emit_vm_flush */
 750                 14 + 14; /* uvd_v6_0_ring_emit_fence x2 vm fence */
 751 }
 752
 753 static bool uvd_v6_0_is_idle(void *handle)
 754 {
 755         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 756
 757         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
 758 }
 759
 760 static int uvd_v6_0_wait_for_idle(void *handle)
 761 {
 762         unsigned i;
 763         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 764
 765         for (i = 0; i < adev->usec_timeout; i++) {
 766                 if (uvd_v6_0_is_idle(handle))
 767                         return 0;
 768         }
 769         return -ETIMEDOUT;
 770 }
 771
 772 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
 773 static int uvd_v6_0_check_soft_reset(void *handle)
 774 {
 775         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 776         u32 srbm_soft_reset = 0;
 777         u32 tmp = RREG32(mmSRBM_STATUS);
 778
 779         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
 780             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
 781             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
 782                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 783
 784         if (srbm_soft_reset) {
 785                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang = true;
 786                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
 787         } else {
 788                 adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang = false;
 789                 adev->uvd.srbm_soft_reset = 0;
 790         }
 791         return 0;
 792 }
 793 static int uvd_v6_0_pre_soft_reset(void *handle)
 794 {
 795         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 796
 797         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang)
 798                 return 0;
 799
 800         uvd_v6_0_stop(adev);
 801         return 0;
 802 }
 803
 804 static int uvd_v6_0_soft_reset(void *handle)
 805 {
 806         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 807         u32 srbm_soft_reset;
 808
 809         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang)
 810                 return 0;
 811         srbm_soft_reset = adev->uvd.srbm_soft_reset;
 812
 813         if (srbm_soft_reset) {
 814                 u32 tmp;
 815
 816                 tmp = RREG32(mmSRBM_SOFT_RESET);
 817                 tmp |= srbm_soft_reset;
 818                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 819                 WREG32(mmSRBM_SOFT_RESET, tmp);
 820                 tmp = RREG32(mmSRBM_SOFT_RESET);
 821
 822                 udelay(50);
 823
 824                 tmp &= ~srbm_soft_reset;
 825                 WREG32(mmSRBM_SOFT_RESET, tmp);
 826                 tmp = RREG32(mmSRBM_SOFT_RESET);
 827
 828                 /* Wait a little for things to settle down */
 829                 udelay(50);
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int uvd_v6_0_post_soft_reset(void *handle)
 836 {
 837         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 838
 839         if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_UVD].hang)
 840                 return 0;
 841
 842         mdelay(5);
 843
 844         return uvd_v6_0_start(adev);
 845 }
 846
 847 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
 848                                         struct amdgpu_irq_src *source,
 849                                         unsigned type,
 850                                         enum amdgpu_interrupt_state state)
 851 {
 852         // TODO
 853         return 0;
 854 }
 855
 856 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
 857                                       struct amdgpu_irq_src *source,
 858                                       struct amdgpu_iv_entry *entry)
 859 {
 860         DRM_DEBUG("IH: UVD TRAP\n");
 861         amdgpu_fence_process(&adev->uvd.ring);
 862         return 0;
 863 }
 864
 865 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
 866 {
 867         uint32_t data, data1, data2, suvd_flags;
 868
 869         data = RREG32(mmUVD_CGC_CTRL);
 870         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 871         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
 872
 873         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
 874                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
 875
 876         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 877                      UVD_SUVD_CGC_GATE__SIT_MASK |
 878                      UVD_SUVD_CGC_GATE__SMP_MASK |
 879                      UVD_SUVD_CGC_GATE__SCM_MASK |
 880                      UVD_SUVD_CGC_GATE__SDB_MASK;
 881
 882         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
 883                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
 884                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
 885
 886         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 887                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 888                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 889                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 890                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 891                         UVD_CGC_CTRL__SYS_MODE_MASK |
 892                         UVD_CGC_CTRL__UDEC_MODE_MASK |
 893                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
 894                         UVD_CGC_CTRL__REGS_MODE_MASK |
 895                         UVD_CGC_CTRL__RBC_MODE_MASK |
 896                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 897                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 898                         UVD_CGC_CTRL__IDCT_MODE_MASK |
 899                         UVD_CGC_CTRL__MPRD_MODE_MASK |
 900                         UVD_CGC_CTRL__MPC_MODE_MASK |
 901                         UVD_CGC_CTRL__LBSI_MODE_MASK |
 902                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
 903                         UVD_CGC_CTRL__WCB_MODE_MASK |
 904                         UVD_CGC_CTRL__VCPU_MODE_MASK |
 905                         UVD_CGC_CTRL__JPEG_MODE_MASK |
 906                         UVD_CGC_CTRL__SCPU_MODE_MASK |
 907                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
 908         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
 909                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
 910                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
 911                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
 912                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
 913         data1 |= suvd_flags;
 914
 915         WREG32(mmUVD_CGC_CTRL, data);
 916         WREG32(mmUVD_CGC_GATE, 0);
 917         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 918         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
 919 }
 920
 921 #if 0
 922 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
 923 {
 924         uint32_t data, data1, cgc_flags, suvd_flags;
 925
 926         data = RREG32(mmUVD_CGC_GATE);
 927         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 928
 929         cgc_flags = UVD_CGC_GATE__SYS_MASK |
 930                 UVD_CGC_GATE__UDEC_MASK |
 931                 UVD_CGC_GATE__MPEG2_MASK |
 932                 UVD_CGC_GATE__RBC_MASK |
 933                 UVD_CGC_GATE__LMI_MC_MASK |
 934                 UVD_CGC_GATE__IDCT_MASK |
 935                 UVD_CGC_GATE__MPRD_MASK |
 936                 UVD_CGC_GATE__MPC_MASK |
 937                 UVD_CGC_GATE__LBSI_MASK |
 938                 UVD_CGC_GATE__LRBBM_MASK |
 939                 UVD_CGC_GATE__UDEC_RE_MASK |
 940                 UVD_CGC_GATE__UDEC_CM_MASK |
 941                 UVD_CGC_GATE__UDEC_IT_MASK |
 942                 UVD_CGC_GATE__UDEC_DB_MASK |
 943                 UVD_CGC_GATE__UDEC_MP_MASK |
 944                 UVD_CGC_GATE__WCB_MASK |
 945                 UVD_CGC_GATE__VCPU_MASK |
 946                 UVD_CGC_GATE__SCPU_MASK |
 947                 UVD_CGC_GATE__JPEG_MASK |
 948                 UVD_CGC_GATE__JPEG2_MASK;
 949
 950         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
 951                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 952                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 953                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 954                                 UVD_SUVD_CGC_GATE__SDB_MASK;
 955
 956         data |= cgc_flags;
 957         data1 |= suvd_flags;
 958
 959         WREG32(mmUVD_CGC_GATE, data);
 960         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 961 }
 962 #endif
 963
 964 static void uvd_v6_set_bypass_mode(struct amdgpu_device *adev, bool enable)
 965 {
 966         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
 967
 968         if (enable)
 969                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
 970                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
 971         else
 972                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
 973                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
 974
 975         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
 976 }
 977
 978 static int uvd_v6_0_set_clockgating_state(void *handle,
 979                                           enum amd_clockgating_state state)
 980 {
 981         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 982
 983         if (adev->asic_type == CHIP_FIJI ||
 984             adev->asic_type == CHIP_POLARIS10)
 985                 uvd_v6_set_bypass_mode(adev, state == AMD_CG_STATE_GATE ? true : false);
 986
 987         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
 988                 return 0;
 989
 990         if (state == AMD_CG_STATE_GATE) {
 991                 /* disable HW gating and enable Sw gating */
 992                 uvd_v6_0_set_sw_clock_gating(adev);
 993         } else {
 994                 /* wait for STATUS to clear */
 995                 if (uvd_v6_0_wait_for_idle(handle))
 996                         return -EBUSY;
 997
 998                 /* enable HW gates because UVD is idle */
 999 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1000         }
1001
1002         return 0;
1003 }
1004
1005 static int uvd_v6_0_set_powergating_state(void *handle,
1006                                           enum amd_powergating_state state)
1007 {
1008         /* This doesn't actually powergate the UVD block.
1009          * That's done in the dpm code via the SMC.  This
1010          * just re-inits the block as necessary.  The actual
1011          * gating still happens in the dpm code.  We should
1012          * revisit this when there is a cleaner line between
1013          * the smc and the hw blocks
1014          */
1015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016
1017         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1018                 return 0;
1019
1020         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1021
1022         if (state == AMD_PG_STATE_GATE) {
1023                 uvd_v6_0_stop(adev);
1024                 return 0;
1025         } else {
1026                 return uvd_v6_0_start(adev);
1027         }
1028 }
1029
1030 const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1031         .name = "uvd_v6_0",
1032         .early_init = uvd_v6_0_early_init,
1033         .late_init = NULL,
1034         .sw_init = uvd_v6_0_sw_init,
1035         .sw_fini = uvd_v6_0_sw_fini,
1036         .hw_init = uvd_v6_0_hw_init,
1037         .hw_fini = uvd_v6_0_hw_fini,
1038         .suspend = uvd_v6_0_suspend,
1039         .resume = uvd_v6_0_resume,
1040         .is_idle = uvd_v6_0_is_idle,
1041         .wait_for_idle = uvd_v6_0_wait_for_idle,
1042         .check_soft_reset = uvd_v6_0_check_soft_reset,
1043         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1044         .soft_reset = uvd_v6_0_soft_reset,
1045         .post_soft_reset = uvd_v6_0_post_soft_reset,
1046         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1047         .set_powergating_state = uvd_v6_0_set_powergating_state,
1048 };
1049
1050 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1051         .get_rptr = uvd_v6_0_ring_get_rptr,
1052         .get_wptr = uvd_v6_0_ring_get_wptr,
1053         .set_wptr = uvd_v6_0_ring_set_wptr,
1054         .parse_cs = amdgpu_uvd_ring_parse_cs,
1055         .emit_ib = uvd_v6_0_ring_emit_ib,
1056         .emit_fence = uvd_v6_0_ring_emit_fence,
1057         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1058         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1059         .test_ring = uvd_v6_0_ring_test_ring,
1060         .test_ib = amdgpu_uvd_ring_test_ib,
1061         .insert_nop = amdgpu_ring_insert_nop,
1062         .pad_ib = amdgpu_ring_generic_pad_ib,
1063         .begin_use = amdgpu_uvd_ring_begin_use,
1064         .end_use = amdgpu_uvd_ring_end_use,
1065         .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size,
1066         .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size,
1067 };
1068
1069 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1070         .get_rptr = uvd_v6_0_ring_get_rptr,
1071         .get_wptr = uvd_v6_0_ring_get_wptr,
1072         .set_wptr = uvd_v6_0_ring_set_wptr,
1073         .parse_cs = NULL,
1074         .emit_ib = uvd_v6_0_ring_emit_ib,
1075         .emit_fence = uvd_v6_0_ring_emit_fence,
1076         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1077         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1078         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1079         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1080         .test_ring = uvd_v6_0_ring_test_ring,
1081         .test_ib = amdgpu_uvd_ring_test_ib,
1082         .insert_nop = amdgpu_ring_insert_nop,
1083         .pad_ib = amdgpu_ring_generic_pad_ib,
1084         .begin_use = amdgpu_uvd_ring_begin_use,
1085         .end_use = amdgpu_uvd_ring_end_use,
1086         .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size,
1087         .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size_vm,
1088 };
1089
1090 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1091 {
1092         if (adev->asic_type >= CHIP_POLARIS10) {
1093                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1094                 DRM_INFO("UVD is enabled in VM mode\n");
1095         } else {
1096                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1097                 DRM_INFO("UVD is enabled in physical mode\n");
1098         }
1099 }
1100
1101 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1102         .set = uvd_v6_0_set_interrupt_state,
1103         .process = uvd_v6_0_process_interrupt,
1104 };
1105
1106 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1107 {
1108         adev->uvd.irq.num_types = 1;
1109         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1110 }