drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <[email protected]>
  21  *          Alex Deucher <[email protected]>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  38 {
  39         if (adev->pp_enabled)
  40                 /* TODO */
  41                 return;
  42
  43         if (adev->pm.dpm_enabled) {
  44                 mutex_lock(&adev->pm.mutex);
  45                 if (power_supply_is_system_supplied() > 0)
  46                         adev->pm.dpm.ac_power = true;
  47                 else
  48                         adev->pm.dpm.ac_power = false;
  49                 if (adev->pm.funcs->enable_bapm)
  50                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  51                 mutex_unlock(&adev->pm.mutex);
  52         }
  53 }
  54
  55 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  56                                     struct device_attribute *attr,
  57                                     char *buf)
  58 {
  59         struct drm_device *ddev = dev_get_drvdata(dev);
  60         struct amdgpu_device *adev = ddev->dev_private;
  61         enum amd_pm_state_type pm;
  62
  63         if (adev->pp_enabled) {
  64                 pm = amdgpu_dpm_get_current_power_state(adev);
  65         } else
  66                 pm = adev->pm.dpm.user_state;
  67
  68         return snprintf(buf, PAGE_SIZE, "%s\n",
  69                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  70                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  71 }
  72
  73 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  74                                     struct device_attribute *attr,
  75                                     const char *buf,
  76                                     size_t count)
  77 {
  78         struct drm_device *ddev = dev_get_drvdata(dev);
  79         struct amdgpu_device *adev = ddev->dev_private;
  80         enum amd_pm_state_type  state;
  81
  82         if (strncmp("battery", buf, strlen("battery")) == 0)
  83                 state = POWER_STATE_TYPE_BATTERY;
  84         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
  85                 state = POWER_STATE_TYPE_BALANCED;
  86         else if (strncmp("performance", buf, strlen("performance")) == 0)
  87                 state = POWER_STATE_TYPE_PERFORMANCE;
  88         else {
  89                 count = -EINVAL;
  90                 goto fail;
  91         }
  92
  93         if (adev->pp_enabled) {
  94                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
  95         } else {
  96                 mutex_lock(&adev->pm.mutex);
  97                 adev->pm.dpm.user_state = state;
  98                 mutex_unlock(&adev->pm.mutex);
  99
 100                 /* Can't set dpm state when the card is off */
 101                 if (!(adev->flags & AMD_IS_PX) ||
 102                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 103                         amdgpu_pm_compute_clocks(adev);
 104         }
 105 fail:
 106         return count;
 107 }
 108
 109 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 110                                                 struct device_attribute *attr,
 111                                                                 char *buf)
 112 {
 113         struct drm_device *ddev = dev_get_drvdata(dev);
 114         struct amdgpu_device *adev = ddev->dev_private;
 115
 116         if  ((adev->flags & AMD_IS_PX) &&
 117              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 118                 return snprintf(buf, PAGE_SIZE, "off\n");
 119
 120         if (adev->pp_enabled) {
 121                 enum amd_dpm_forced_level level;
 122
 123                 level = amdgpu_dpm_get_performance_level(adev);
 124                 return snprintf(buf, PAGE_SIZE, "%s\n",
 125                                 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 126                                 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 127                                 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 128                                 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : "unknown");
 129         } else {
 130                 enum amdgpu_dpm_forced_level level;
 131
 132                 level = adev->pm.dpm.forced_level;
 133                 return snprintf(buf, PAGE_SIZE, "%s\n",
 134                                 (level == AMDGPU_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 135                                 (level == AMDGPU_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 136         }
 137 }
 138
 139 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 140                                                        struct device_attribute *attr,
 141                                                        const char *buf,
 142                                                        size_t count)
 143 {
 144         struct drm_device *ddev = dev_get_drvdata(dev);
 145         struct amdgpu_device *adev = ddev->dev_private;
 146         enum amdgpu_dpm_forced_level level;
 147         int ret = 0;
 148
 149         /* Can't force performance level when the card is off */
 150         if  ((adev->flags & AMD_IS_PX) &&
 151              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 152                 return -EINVAL;
 153
 154         if (strncmp("low", buf, strlen("low")) == 0) {
 155                 level = AMDGPU_DPM_FORCED_LEVEL_LOW;
 156         } else if (strncmp("high", buf, strlen("high")) == 0) {
 157                 level = AMDGPU_DPM_FORCED_LEVEL_HIGH;
 158         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 159                 level = AMDGPU_DPM_FORCED_LEVEL_AUTO;
 160         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 161                 level = AMDGPU_DPM_FORCED_LEVEL_MANUAL;
 162         } else {
 163                 count = -EINVAL;
 164                 goto fail;
 165         }
 166
 167         if (adev->pp_enabled)
 168                 amdgpu_dpm_force_performance_level(adev, level);
 169         else {
 170                 mutex_lock(&adev->pm.mutex);
 171                 if (adev->pm.dpm.thermal_active) {
 172                         count = -EINVAL;
 173                         mutex_unlock(&adev->pm.mutex);
 174                         goto fail;
 175                 }
 176                 ret = amdgpu_dpm_force_performance_level(adev, level);
 177                 if (ret)
 178                         count = -EINVAL;
 179                 else
 180                         adev->pm.dpm.forced_level = level;
 181                 mutex_unlock(&adev->pm.mutex);
 182         }
 183 fail:
 184         return count;
 185 }
 186
 187 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 188                 struct device_attribute *attr,
 189                 char *buf)
 190 {
 191         struct drm_device *ddev = dev_get_drvdata(dev);
 192         struct amdgpu_device *adev = ddev->dev_private;
 193         struct pp_states_info data;
 194         int i, buf_len;
 195
 196         if (adev->pp_enabled)
 197                 amdgpu_dpm_get_pp_num_states(adev, &data);
 198
 199         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 200         for (i = 0; i < data.nums; i++)
 201                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 202                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 203                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 204                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 205                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 206
 207         return buf_len;
 208 }
 209
 210 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 211                 struct device_attribute *attr,
 212                 char *buf)
 213 {
 214         struct drm_device *ddev = dev_get_drvdata(dev);
 215         struct amdgpu_device *adev = ddev->dev_private;
 216         struct pp_states_info data;
 217         enum amd_pm_state_type pm = 0;
 218         int i = 0;
 219
 220         if (adev->pp_enabled) {
 221
 222                 pm = amdgpu_dpm_get_current_power_state(adev);
 223                 amdgpu_dpm_get_pp_num_states(adev, &data);
 224
 225                 for (i = 0; i < data.nums; i++) {
 226                         if (pm == data.states[i])
 227                                 break;
 228                 }
 229
 230                 if (i == data.nums)
 231                         i = -EINVAL;
 232         }
 233
 234         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 235 }
 236
 237 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 238                 struct device_attribute *attr,
 239                 char *buf)
 240 {
 241         struct drm_device *ddev = dev_get_drvdata(dev);
 242         struct amdgpu_device *adev = ddev->dev_private;
 243         struct pp_states_info data;
 244         enum amd_pm_state_type pm = 0;
 245         int i;
 246
 247         if (adev->pp_force_state_enabled && adev->pp_enabled) {
 248                 pm = amdgpu_dpm_get_current_power_state(adev);
 249                 amdgpu_dpm_get_pp_num_states(adev, &data);
 250
 251                 for (i = 0; i < data.nums; i++) {
 252                         if (pm == data.states[i])
 253                                 break;
 254                 }
 255
 256                 if (i == data.nums)
 257                         i = -EINVAL;
 258
 259                 return snprintf(buf, PAGE_SIZE, "%d\n", i);
 260
 261         } else
 262                 return snprintf(buf, PAGE_SIZE, "\n");
 263 }
 264
 265 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 266                 struct device_attribute *attr,
 267                 const char *buf,
 268                 size_t count)
 269 {
 270         struct drm_device *ddev = dev_get_drvdata(dev);
 271         struct amdgpu_device *adev = ddev->dev_private;
 272         enum amd_pm_state_type state = 0;
 273         unsigned long idx;
 274         int ret;
 275
 276         if (strlen(buf) == 1)
 277                 adev->pp_force_state_enabled = false;
 278         else if (adev->pp_enabled) {
 279                 struct pp_states_info data;
 280
 281                 ret = kstrtoul(buf, 0, &idx);
 282                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 283                         count = -EINVAL;
 284                         goto fail;
 285                 }
 286
 287                 amdgpu_dpm_get_pp_num_states(adev, &data);
 288                 state = data.states[idx];
 289                 /* only set user selected power states */
 290                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 291                     state != POWER_STATE_TYPE_DEFAULT) {
 292                         amdgpu_dpm_dispatch_task(adev,
 293                                         AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 294                         adev->pp_force_state_enabled = true;
 295                 }
 296         }
 297 fail:
 298         return count;
 299 }
 300
 301 static ssize_t amdgpu_get_pp_table(struct device *dev,
 302                 struct device_attribute *attr,
 303                 char *buf)
 304 {
 305         struct drm_device *ddev = dev_get_drvdata(dev);
 306         struct amdgpu_device *adev = ddev->dev_private;
 307         char *table = NULL;
 308         int size;
 309
 310         if (adev->pp_enabled)
 311                 size = amdgpu_dpm_get_pp_table(adev, &table);
 312         else
 313                 return 0;
 314
 315         if (size >= PAGE_SIZE)
 316                 size = PAGE_SIZE - 1;
 317
 318         memcpy(buf, table, size);
 319
 320         return size;
 321 }
 322
 323 static ssize_t amdgpu_set_pp_table(struct device *dev,
 324                 struct device_attribute *attr,
 325                 const char *buf,
 326                 size_t count)
 327 {
 328         struct drm_device *ddev = dev_get_drvdata(dev);
 329         struct amdgpu_device *adev = ddev->dev_private;
 330
 331         if (adev->pp_enabled)
 332                 amdgpu_dpm_set_pp_table(adev, buf, count);
 333
 334         return count;
 335 }
 336
 337 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 338                 struct device_attribute *attr,
 339                 char *buf)
 340 {
 341         struct drm_device *ddev = dev_get_drvdata(dev);
 342         struct amdgpu_device *adev = ddev->dev_private;
 343         ssize_t size = 0;
 344
 345         if (adev->pp_enabled)
 346                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 347         else if (adev->pm.funcs->print_clock_levels)
 348                 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
 349
 350         return size;
 351 }
 352
 353 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 354                 struct device_attribute *attr,
 355                 const char *buf,
 356                 size_t count)
 357 {
 358         struct drm_device *ddev = dev_get_drvdata(dev);
 359         struct amdgpu_device *adev = ddev->dev_private;
 360         int ret;
 361         long level;
 362         uint32_t i, mask = 0;
 363         char sub_str[2];
 364
 365         for (i = 0; i < strlen(buf); i++) {
 366                 if (*(buf + i) == '\n')
 367                         continue;
 368                 sub_str[0] = *(buf + i);
 369                 sub_str[1] = '\0';
 370                 ret = kstrtol(sub_str, 0, &level);
 371
 372                 if (ret) {
 373                         count = -EINVAL;
 374                         goto fail;
 375                 }
 376                 mask |= 1 << level;
 377         }
 378
 379         if (adev->pp_enabled)
 380                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 381         else if (adev->pm.funcs->force_clock_level)
 382                 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
 383 fail:
 384         return count;
 385 }
 386
 387 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 388                 struct device_attribute *attr,
 389                 char *buf)
 390 {
 391         struct drm_device *ddev = dev_get_drvdata(dev);
 392         struct amdgpu_device *adev = ddev->dev_private;
 393         ssize_t size = 0;
 394
 395         if (adev->pp_enabled)
 396                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 397         else if (adev->pm.funcs->print_clock_levels)
 398                 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
 399
 400         return size;
 401 }
 402
 403 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 404                 struct device_attribute *attr,
 405                 const char *buf,
 406                 size_t count)
 407 {
 408         struct drm_device *ddev = dev_get_drvdata(dev);
 409         struct amdgpu_device *adev = ddev->dev_private;
 410         int ret;
 411         long level;
 412         uint32_t i, mask = 0;
 413         char sub_str[2];
 414
 415         for (i = 0; i < strlen(buf); i++) {
 416                 if (*(buf + i) == '\n')
 417                         continue;
 418                 sub_str[0] = *(buf + i);
 419                 sub_str[1] = '\0';
 420                 ret = kstrtol(sub_str, 0, &level);
 421
 422                 if (ret) {
 423                         count = -EINVAL;
 424                         goto fail;
 425                 }
 426                 mask |= 1 << level;
 427         }
 428
 429         if (adev->pp_enabled)
 430                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 431         else if (adev->pm.funcs->force_clock_level)
 432                 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
 433 fail:
 434         return count;
 435 }
 436
 437 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 438                 struct device_attribute *attr,
 439                 char *buf)
 440 {
 441         struct drm_device *ddev = dev_get_drvdata(dev);
 442         struct amdgpu_device *adev = ddev->dev_private;
 443         ssize_t size = 0;
 444
 445         if (adev->pp_enabled)
 446                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 447         else if (adev->pm.funcs->print_clock_levels)
 448                 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
 449
 450         return size;
 451 }
 452
 453 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 454                 struct device_attribute *attr,
 455                 const char *buf,
 456                 size_t count)
 457 {
 458         struct drm_device *ddev = dev_get_drvdata(dev);
 459         struct amdgpu_device *adev = ddev->dev_private;
 460         int ret;
 461         long level;
 462         uint32_t i, mask = 0;
 463         char sub_str[2];
 464
 465         for (i = 0; i < strlen(buf); i++) {
 466                 if (*(buf + i) == '\n')
 467                         continue;
 468                 sub_str[0] = *(buf + i);
 469                 sub_str[1] = '\0';
 470                 ret = kstrtol(sub_str, 0, &level);
 471
 472                 if (ret) {
 473                         count = -EINVAL;
 474                         goto fail;
 475                 }
 476                 mask |= 1 << level;
 477         }
 478
 479         if (adev->pp_enabled)
 480                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 481         else if (adev->pm.funcs->force_clock_level)
 482                 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
 483 fail:
 484         return count;
 485 }
 486
 487 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 488                 struct device_attribute *attr,
 489                 char *buf)
 490 {
 491         struct drm_device *ddev = dev_get_drvdata(dev);
 492         struct amdgpu_device *adev = ddev->dev_private;
 493         uint32_t value = 0;
 494
 495         if (adev->pp_enabled)
 496                 value = amdgpu_dpm_get_sclk_od(adev);
 497         else if (adev->pm.funcs->get_sclk_od)
 498                 value = adev->pm.funcs->get_sclk_od(adev);
 499
 500         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 501 }
 502
 503 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 504                 struct device_attribute *attr,
 505                 const char *buf,
 506                 size_t count)
 507 {
 508         struct drm_device *ddev = dev_get_drvdata(dev);
 509         struct amdgpu_device *adev = ddev->dev_private;
 510         int ret;
 511         long int value;
 512
 513         ret = kstrtol(buf, 0, &value);
 514
 515         if (ret) {
 516                 count = -EINVAL;
 517                 goto fail;
 518         }
 519
 520         if (adev->pp_enabled) {
 521                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 522                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 523         } else if (adev->pm.funcs->set_sclk_od) {
 524                 adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
 525                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 526                 amdgpu_pm_compute_clocks(adev);
 527         }
 528
 529 fail:
 530         return count;
 531 }
 532
 533 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 534                 struct device_attribute *attr,
 535                 char *buf)
 536 {
 537         struct drm_device *ddev = dev_get_drvdata(dev);
 538         struct amdgpu_device *adev = ddev->dev_private;
 539         uint32_t value = 0;
 540
 541         if (adev->pp_enabled)
 542                 value = amdgpu_dpm_get_mclk_od(adev);
 543         else if (adev->pm.funcs->get_mclk_od)
 544                 value = adev->pm.funcs->get_mclk_od(adev);
 545
 546         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 547 }
 548
 549 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 550                 struct device_attribute *attr,
 551                 const char *buf,
 552                 size_t count)
 553 {
 554         struct drm_device *ddev = dev_get_drvdata(dev);
 555         struct amdgpu_device *adev = ddev->dev_private;
 556         int ret;
 557         long int value;
 558
 559         ret = kstrtol(buf, 0, &value);
 560
 561         if (ret) {
 562                 count = -EINVAL;
 563                 goto fail;
 564         }
 565
 566         if (adev->pp_enabled) {
 567                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 568                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 569         } else if (adev->pm.funcs->set_mclk_od) {
 570                 adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
 571                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 572                 amdgpu_pm_compute_clocks(adev);
 573         }
 574
 575 fail:
 576         return count;
 577 }
 578
 579 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 580 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 581                    amdgpu_get_dpm_forced_performance_level,
 582                    amdgpu_set_dpm_forced_performance_level);
 583 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 584 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 585 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 586                 amdgpu_get_pp_force_state,
 587                 amdgpu_set_pp_force_state);
 588 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 589                 amdgpu_get_pp_table,
 590                 amdgpu_set_pp_table);
 591 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 592                 amdgpu_get_pp_dpm_sclk,
 593                 amdgpu_set_pp_dpm_sclk);
 594 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 595                 amdgpu_get_pp_dpm_mclk,
 596                 amdgpu_set_pp_dpm_mclk);
 597 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 598                 amdgpu_get_pp_dpm_pcie,
 599                 amdgpu_set_pp_dpm_pcie);
 600 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 601                 amdgpu_get_pp_sclk_od,
 602                 amdgpu_set_pp_sclk_od);
 603 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 604                 amdgpu_get_pp_mclk_od,
 605                 amdgpu_set_pp_mclk_od);
 606
 607 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 608                                       struct device_attribute *attr,
 609                                       char *buf)
 610 {
 611         struct amdgpu_device *adev = dev_get_drvdata(dev);
 612         struct drm_device *ddev = adev->ddev;
 613         int temp;
 614
 615         /* Can't get temperature when the card is off */
 616         if  ((adev->flags & AMD_IS_PX) &&
 617              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 618                 return -EINVAL;
 619
 620         if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
 621                 temp = 0;
 622         else
 623                 temp = amdgpu_dpm_get_temperature(adev);
 624
 625         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 626 }
 627
 628 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 629                                              struct device_attribute *attr,
 630                                              char *buf)
 631 {
 632         struct amdgpu_device *adev = dev_get_drvdata(dev);
 633         int hyst = to_sensor_dev_attr(attr)->index;
 634         int temp;
 635
 636         if (hyst)
 637                 temp = adev->pm.dpm.thermal.min_temp;
 638         else
 639                 temp = adev->pm.dpm.thermal.max_temp;
 640
 641         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 642 }
 643
 644 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 645                                             struct device_attribute *attr,
 646                                             char *buf)
 647 {
 648         struct amdgpu_device *adev = dev_get_drvdata(dev);
 649         u32 pwm_mode = 0;
 650
 651         if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
 652                 return -EINVAL;
 653
 654         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 655
 656         /* never 0 (full-speed), fuse or smc-controlled always */
 657         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 658 }
 659
 660 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 661                                             struct device_attribute *attr,
 662                                             const char *buf,
 663                                             size_t count)
 664 {
 665         struct amdgpu_device *adev = dev_get_drvdata(dev);
 666         int err;
 667         int value;
 668
 669         if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
 670                 return -EINVAL;
 671
 672         err = kstrtoint(buf, 10, &value);
 673         if (err)
 674                 return err;
 675
 676         switch (value) {
 677         case 1: /* manual, percent-based */
 678                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 679                 break;
 680         default: /* disable */
 681                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 682                 break;
 683         }
 684
 685         return count;
 686 }
 687
 688 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 689                                          struct device_attribute *attr,
 690                                          char *buf)
 691 {
 692         return sprintf(buf, "%i\n", 0);
 693 }
 694
 695 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 696                                          struct device_attribute *attr,
 697                                          char *buf)
 698 {
 699         return sprintf(buf, "%i\n", 255);
 700 }
 701
 702 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 703                                      struct device_attribute *attr,
 704                                      const char *buf, size_t count)
 705 {
 706         struct amdgpu_device *adev = dev_get_drvdata(dev);
 707         int err;
 708         u32 value;
 709
 710         err = kstrtou32(buf, 10, &value);
 711         if (err)
 712                 return err;
 713
 714         value = (value * 100) / 255;
 715
 716         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 717         if (err)
 718                 return err;
 719
 720         return count;
 721 }
 722
 723 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 724                                      struct device_attribute *attr,
 725                                      char *buf)
 726 {
 727         struct amdgpu_device *adev = dev_get_drvdata(dev);
 728         int err;
 729         u32 speed;
 730
 731         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 732         if (err)
 733                 return err;
 734
 735         speed = (speed * 255) / 100;
 736
 737         return sprintf(buf, "%i\n", speed);
 738 }
 739
 740 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 741 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 742 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 743 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 744 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 745 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 746 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 747
 748 static struct attribute *hwmon_attributes[] = {
 749         &sensor_dev_attr_temp1_input.dev_attr.attr,
 750         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 751         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 752         &sensor_dev_attr_pwm1.dev_attr.attr,
 753         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 754         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 755         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 756         NULL
 757 };
 758
 759 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 760                                         struct attribute *attr, int index)
 761 {
 762         struct device *dev = kobj_to_dev(kobj);
 763         struct amdgpu_device *adev = dev_get_drvdata(dev);
 764         umode_t effective_mode = attr->mode;
 765
 766         /* Skip limit attributes if DPM is not enabled */
 767         if (!adev->pm.dpm_enabled &&
 768             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 769              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 770              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 771              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 772              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 773              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 774                 return 0;
 775
 776         if (adev->pp_enabled)
 777                 return effective_mode;
 778
 779         /* Skip fan attributes if fan is not present */
 780         if (adev->pm.no_fan &&
 781             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 782              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 783              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 784              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 785                 return 0;
 786
 787         /* mask fan attributes if we have no bindings for this asic to expose */
 788         if ((!adev->pm.funcs->get_fan_speed_percent &&
 789              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 790             (!adev->pm.funcs->get_fan_control_mode &&
 791              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 792                 effective_mode &= ~S_IRUGO;
 793
 794         if ((!adev->pm.funcs->set_fan_speed_percent &&
 795              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 796             (!adev->pm.funcs->set_fan_control_mode &&
 797              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 798                 effective_mode &= ~S_IWUSR;
 799
 800         /* hide max/min values if we can't both query and manage the fan */
 801         if ((!adev->pm.funcs->set_fan_speed_percent &&
 802              !adev->pm.funcs->get_fan_speed_percent) &&
 803             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 804              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 805                 return 0;
 806
 807         return effective_mode;
 808 }
 809
 810 static const struct attribute_group hwmon_attrgroup = {
 811         .attrs = hwmon_attributes,
 812         .is_visible = hwmon_attributes_visible,
 813 };
 814
 815 static const struct attribute_group *hwmon_groups[] = {
 816         &hwmon_attrgroup,
 817         NULL
 818 };
 819
 820 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
 821 {
 822         struct amdgpu_device *adev =
 823                 container_of(work, struct amdgpu_device,
 824                              pm.dpm.thermal.work);
 825         /* switch to the thermal state */
 826         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 827
 828         if (!adev->pm.dpm_enabled)
 829                 return;
 830
 831         if (adev->pm.funcs->get_temperature) {
 832                 int temp = amdgpu_dpm_get_temperature(adev);
 833
 834                 if (temp < adev->pm.dpm.thermal.min_temp)
 835                         /* switch back the user state */
 836                         dpm_state = adev->pm.dpm.user_state;
 837         } else {
 838                 if (adev->pm.dpm.thermal.high_to_low)
 839                         /* switch back the user state */
 840                         dpm_state = adev->pm.dpm.user_state;
 841         }
 842         mutex_lock(&adev->pm.mutex);
 843         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 844                 adev->pm.dpm.thermal_active = true;
 845         else
 846                 adev->pm.dpm.thermal_active = false;
 847         adev->pm.dpm.state = dpm_state;
 848         mutex_unlock(&adev->pm.mutex);
 849
 850         amdgpu_pm_compute_clocks(adev);
 851 }
 852
 853 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
 854                                                      enum amd_pm_state_type dpm_state)
 855 {
 856         int i;
 857         struct amdgpu_ps *ps;
 858         u32 ui_class;
 859         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
 860                 true : false;
 861
 862         /* check if the vblank period is too short to adjust the mclk */
 863         if (single_display && adev->pm.funcs->vblank_too_short) {
 864                 if (amdgpu_dpm_vblank_too_short(adev))
 865                         single_display = false;
 866         }
 867
 868         /* certain older asics have a separare 3D performance state,
 869          * so try that first if the user selected performance
 870          */
 871         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 872                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 873         /* balanced states don't exist at the moment */
 874         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 875                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 876
 877 restart_search:
 878         /* Pick the best power state based on current conditions */
 879         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 880                 ps = &adev->pm.dpm.ps[i];
 881                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 882                 switch (dpm_state) {
 883                 /* user states */
 884                 case POWER_STATE_TYPE_BATTERY:
 885                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 886                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 887                                         if (single_display)
 888                                                 return ps;
 889                                 } else
 890                                         return ps;
 891                         }
 892                         break;
 893                 case POWER_STATE_TYPE_BALANCED:
 894                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 895                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 896                                         if (single_display)
 897                                                 return ps;
 898                                 } else
 899                                         return ps;
 900                         }
 901                         break;
 902                 case POWER_STATE_TYPE_PERFORMANCE:
 903                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 904                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 905                                         if (single_display)
 906                                                 return ps;
 907                                 } else
 908                                         return ps;
 909                         }
 910                         break;
 911                 /* internal states */
 912                 case POWER_STATE_TYPE_INTERNAL_UVD:
 913                         if (adev->pm.dpm.uvd_ps)
 914                                 return adev->pm.dpm.uvd_ps;
 915                         else
 916                                 break;
 917                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 918                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 919                                 return ps;
 920                         break;
 921                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 922                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 923                                 return ps;
 924                         break;
 925                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 926                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 927                                 return ps;
 928                         break;
 929                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 930                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 931                                 return ps;
 932                         break;
 933                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 934                         return adev->pm.dpm.boot_ps;
 935                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 936                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 937                                 return ps;
 938                         break;
 939                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 940                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 941                                 return ps;
 942                         break;
 943                 case POWER_STATE_TYPE_INTERNAL_ULV:
 944                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 945                                 return ps;
 946                         break;
 947                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 948                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 949                                 return ps;
 950                         break;
 951                 default:
 952                         break;
 953                 }
 954         }
 955         /* use a fallback state if we didn't match */
 956         switch (dpm_state) {
 957         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 958                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 959                 goto restart_search;
 960         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 961         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 962         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 963                 if (adev->pm.dpm.uvd_ps) {
 964                         return adev->pm.dpm.uvd_ps;
 965                 } else {
 966                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 967                         goto restart_search;
 968                 }
 969         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 970                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 971                 goto restart_search;
 972         case POWER_STATE_TYPE_INTERNAL_ACPI:
 973                 dpm_state = POWER_STATE_TYPE_BATTERY;
 974                 goto restart_search;
 975         case POWER_STATE_TYPE_BATTERY:
 976         case POWER_STATE_TYPE_BALANCED:
 977         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 978                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 979                 goto restart_search;
 980         default:
 981                 break;
 982         }
 983
 984         return NULL;
 985 }
 986
 987 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 988 {
 989         int i;
 990         struct amdgpu_ps *ps;
 991         enum amd_pm_state_type dpm_state;
 992         int ret;
 993
 994         /* if dpm init failed */
 995         if (!adev->pm.dpm_enabled)
 996                 return;
 997
 998         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
 999                 /* add other state override checks here */
1000                 if ((!adev->pm.dpm.thermal_active) &&
1001                     (!adev->pm.dpm.uvd_active))
1002                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1003         }
1004         dpm_state = adev->pm.dpm.state;
1005
1006         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1007         if (ps)
1008                 adev->pm.dpm.requested_ps = ps;
1009         else
1010                 return;
1011
1012         /* no need to reprogram if nothing changed unless we are on BTC+ */
1013         if (adev->pm.dpm.current_ps == adev->pm.dpm.requested_ps) {
1014                 /* vce just modifies an existing state so force a change */
1015                 if (ps->vce_active != adev->pm.dpm.vce_active)
1016                         goto force;
1017                 if (adev->flags & AMD_IS_APU) {
1018                         /* for APUs if the num crtcs changed but state is the same,
1019                          * all we need to do is update the display configuration.
1020                          */
1021                         if (adev->pm.dpm.new_active_crtcs != adev->pm.dpm.current_active_crtcs) {
1022                                 /* update display watermarks based on new power state */
1023                                 amdgpu_display_bandwidth_update(adev);
1024                                 /* update displays */
1025                                 amdgpu_dpm_display_configuration_changed(adev);
1026                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1027                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1028                         }
1029                         return;
1030                 } else {
1031                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
1032                          * nothing to do, if the num crtcs is > 1 and state is the same,
1033                          * update display configuration.
1034                          */
1035                         if (adev->pm.dpm.new_active_crtcs ==
1036                             adev->pm.dpm.current_active_crtcs) {
1037                                 return;
1038                         } else if ((adev->pm.dpm.current_active_crtc_count > 1) &&
1039                                    (adev->pm.dpm.new_active_crtc_count > 1)) {
1040                                 /* update display watermarks based on new power state */
1041                                 amdgpu_display_bandwidth_update(adev);
1042                                 /* update displays */
1043                                 amdgpu_dpm_display_configuration_changed(adev);
1044                                 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1045                                 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1046                                 return;
1047                         }
1048                 }
1049         }
1050
1051 force:
1052         if (amdgpu_dpm == 1) {
1053                 printk("switching from power state:\n");
1054                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1055                 printk("switching to power state:\n");
1056                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1057         }
1058
1059         /* update whether vce is active */
1060         ps->vce_active = adev->pm.dpm.vce_active;
1061
1062         ret = amdgpu_dpm_pre_set_power_state(adev);
1063         if (ret)
1064                 return;
1065
1066         /* update display watermarks based on new power state */
1067         amdgpu_display_bandwidth_update(adev);
1068
1069         /* wait for the rings to drain */
1070         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1071                 struct amdgpu_ring *ring = adev->rings[i];
1072                 if (ring && ring->ready)
1073                         amdgpu_fence_wait_empty(ring);
1074         }
1075
1076         /* program the new power state */
1077         amdgpu_dpm_set_power_state(adev);
1078
1079         /* update current power state */
1080         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps;
1081
1082         amdgpu_dpm_post_set_power_state(adev);
1083
1084         /* update displays */
1085         amdgpu_dpm_display_configuration_changed(adev);
1086
1087         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1088         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1089
1090         if (adev->pm.funcs->force_performance_level) {
1091                 if (adev->pm.dpm.thermal_active) {
1092                         enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;
1093                         /* force low perf level for thermal */
1094                         amdgpu_dpm_force_performance_level(adev, AMDGPU_DPM_FORCED_LEVEL_LOW);
1095                         /* save the user's level */
1096                         adev->pm.dpm.forced_level = level;
1097                 } else {
1098                         /* otherwise, user selected level */
1099                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1100                 }
1101         }
1102 }
1103
1104 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1105 {
1106         if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
1107                 /* enable/disable UVD */
1108                 mutex_lock(&adev->pm.mutex);
1109                 amdgpu_dpm_powergate_uvd(adev, !enable);
1110                 mutex_unlock(&adev->pm.mutex);
1111         } else {
1112                 if (enable) {
1113                         mutex_lock(&adev->pm.mutex);
1114                         adev->pm.dpm.uvd_active = true;
1115                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1116                         mutex_unlock(&adev->pm.mutex);
1117                 } else {
1118                         mutex_lock(&adev->pm.mutex);
1119                         adev->pm.dpm.uvd_active = false;
1120                         mutex_unlock(&adev->pm.mutex);
1121                 }
1122                 amdgpu_pm_compute_clocks(adev);
1123         }
1124 }
1125
1126 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1127 {
1128         if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
1129                 /* enable/disable VCE */
1130                 mutex_lock(&adev->pm.mutex);
1131                 amdgpu_dpm_powergate_vce(adev, !enable);
1132                 mutex_unlock(&adev->pm.mutex);
1133         } else {
1134                 if (enable) {
1135                         mutex_lock(&adev->pm.mutex);
1136                         adev->pm.dpm.vce_active = true;
1137                         /* XXX select vce level based on ring/task */
1138                         adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
1139                         mutex_unlock(&adev->pm.mutex);
1140                 } else {
1141                         mutex_lock(&adev->pm.mutex);
1142                         adev->pm.dpm.vce_active = false;
1143                         mutex_unlock(&adev->pm.mutex);
1144                 }
1145                 amdgpu_pm_compute_clocks(adev);
1146         }
1147 }
1148
1149 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1150 {
1151         int i;
1152
1153         if (adev->pp_enabled)
1154                 /* TO DO */
1155                 return;
1156
1157         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1158                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1159
1160 }
1161
1162 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1163 {
1164         int ret;
1165
1166         if (adev->pm.sysfs_initialized)
1167                 return 0;
1168
1169         if (!adev->pp_enabled) {
1170                 if (adev->pm.funcs->get_temperature == NULL)
1171                         return 0;
1172         }
1173
1174         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1175                                                                    DRIVER_NAME, adev,
1176                                                                    hwmon_groups);
1177         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1178                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1179                 dev_err(adev->dev,
1180                         "Unable to register hwmon device: %d\n", ret);
1181                 return ret;
1182         }
1183
1184         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1185         if (ret) {
1186                 DRM_ERROR("failed to create device file for dpm state\n");
1187                 return ret;
1188         }
1189         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1190         if (ret) {
1191                 DRM_ERROR("failed to create device file for dpm state\n");
1192                 return ret;
1193         }
1194
1195         if (adev->pp_enabled) {
1196                 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1197                 if (ret) {
1198                         DRM_ERROR("failed to create device file pp_num_states\n");
1199                         return ret;
1200                 }
1201                 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1202                 if (ret) {
1203                         DRM_ERROR("failed to create device file pp_cur_state\n");
1204                         return ret;
1205                 }
1206                 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1207                 if (ret) {
1208                         DRM_ERROR("failed to create device file pp_force_state\n");
1209                         return ret;
1210                 }
1211                 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1212                 if (ret) {
1213                         DRM_ERROR("failed to create device file pp_table\n");
1214                         return ret;
1215                 }
1216         }
1217
1218         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1219         if (ret) {
1220                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1221                 return ret;
1222         }
1223         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1224         if (ret) {
1225                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1226                 return ret;
1227         }
1228         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1229         if (ret) {
1230                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1231                 return ret;
1232         }
1233         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1234         if (ret) {
1235                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1236                 return ret;
1237         }
1238         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1239         if (ret) {
1240                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1241                 return ret;
1242         }
1243
1244         ret = amdgpu_debugfs_pm_init(adev);
1245         if (ret) {
1246                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1247                 return ret;
1248         }
1249
1250         adev->pm.sysfs_initialized = true;
1251
1252         return 0;
1253 }
1254
1255 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1256 {
1257         if (adev->pm.int_hwmon_dev)
1258                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1259         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1260         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1261         if (adev->pp_enabled) {
1262                 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1263                 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1264                 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1265                 device_remove_file(adev->dev, &dev_attr_pp_table);
1266         }
1267         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1268         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1269         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1270         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1271         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1272 }
1273
1274 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1275 {
1276         struct drm_device *ddev = adev->ddev;
1277         struct drm_crtc *crtc;
1278         struct amdgpu_crtc *amdgpu_crtc;
1279
1280         if (!adev->pm.dpm_enabled)
1281                 return;
1282
1283         if (adev->pp_enabled) {
1284                 int i = 0;
1285
1286                 amdgpu_display_bandwidth_update(adev);
1287                 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1288                         struct amdgpu_ring *ring = adev->rings[i];
1289                         if (ring && ring->ready)
1290                                 amdgpu_fence_wait_empty(ring);
1291                 }
1292
1293                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1294         } else {
1295                 mutex_lock(&adev->pm.mutex);
1296                 adev->pm.dpm.new_active_crtcs = 0;
1297                 adev->pm.dpm.new_active_crtc_count = 0;
1298                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1299                         list_for_each_entry(crtc,
1300                                             &ddev->mode_config.crtc_list, head) {
1301                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1302                                 if (crtc->enabled) {
1303                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1304                                         adev->pm.dpm.new_active_crtc_count++;
1305                                 }
1306                         }
1307                 }
1308                 /* update battery/ac status */
1309                 if (power_supply_is_system_supplied() > 0)
1310                         adev->pm.dpm.ac_power = true;
1311                 else
1312                         adev->pm.dpm.ac_power = false;
1313
1314                 amdgpu_dpm_change_power_state_locked(adev);
1315
1316                 mutex_unlock(&adev->pm.mutex);
1317         }
1318 }
1319
1320 /*
1321  * Debugfs info
1322  */
1323 #if defined(CONFIG_DEBUG_FS)
1324
1325 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1326 {
1327         int32_t value;
1328
1329         /* sanity check PP is enabled */
1330         if (!(adev->powerplay.pp_funcs &&
1331               adev->powerplay.pp_funcs->read_sensor))
1332               return -EINVAL;
1333
1334         /* GPU Clocks */
1335         seq_printf(m, "GFX Clocks and Power:\n");
1336         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value))
1337                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1338         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value))
1339                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1340         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value))
1341                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1342         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value))
1343                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1344         seq_printf(m, "\n");
1345
1346         /* GPU Temp */
1347         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value))
1348                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1349
1350         /* GPU Load */
1351         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value))
1352                 seq_printf(m, "GPU Load: %u %%\n", value);
1353         seq_printf(m, "\n");
1354
1355         /* UVD clocks */
1356         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, &value)) {
1357                 if (!value) {
1358                         seq_printf(m, "UVD: Disabled\n");
1359                 } else {
1360                         seq_printf(m, "UVD: Enabled\n");
1361                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, &value))
1362                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1363                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, &value))
1364                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1365                 }
1366         }
1367         seq_printf(m, "\n");
1368
1369         /* VCE clocks */
1370         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, &value)) {
1371                 if (!value) {
1372                         seq_printf(m, "VCE: Disabled\n");
1373                 } else {
1374                         seq_printf(m, "VCE: Enabled\n");
1375                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, &value))
1376                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1377                 }
1378         }
1379
1380         return 0;
1381 }
1382
1383 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1384 {
1385         struct drm_info_node *node = (struct drm_info_node *) m->private;
1386         struct drm_device *dev = node->minor->dev;
1387         struct amdgpu_device *adev = dev->dev_private;
1388         struct drm_device *ddev = adev->ddev;
1389
1390         if (!adev->pm.dpm_enabled) {
1391                 seq_printf(m, "dpm not enabled\n");
1392                 return 0;
1393         }
1394         if  ((adev->flags & AMD_IS_PX) &&
1395              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1396                 seq_printf(m, "PX asic powered off\n");
1397         } else if (adev->pp_enabled) {
1398                 return amdgpu_debugfs_pm_info_pp(m, adev);
1399         } else {
1400                 mutex_lock(&adev->pm.mutex);
1401                 if (adev->pm.funcs->debugfs_print_current_performance_level)
1402                         adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
1403                 else
1404                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1405                 mutex_unlock(&adev->pm.mutex);
1406         }
1407
1408         return 0;
1409 }
1410
1411 static const struct drm_info_list amdgpu_pm_info_list[] = {
1412         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1413 };
1414 #endif
1415
1416 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1417 {
1418 #if defined(CONFIG_DEBUG_FS)
1419         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1420 #else
1421         return 0;
1422 #endif
1423 }