drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_xcp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_trace.h"
  33
  34 #include "sdma/sdma_4_4_2_offset.h"
  35 #include "sdma/sdma_4_4_2_sh_mask.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 #include "amdgpu_ras.h"
  45
  46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
  47
  48 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
  49
  50 #define WREG32_SDMA(instance, offset, value) \
  51         WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
  52 #define RREG32_SDMA(instance, offset) \
  53         RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
  54
  55 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
  56 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
  57 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  58 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
  59 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
  60
  61 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
  62                 u32 instance, u32 offset)
  63 {
  64         u32 dev_inst = GET_INST(SDMA0, instance);
  65
  66         return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
  67 }
  68
  69 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
  70 {
  71         switch (seq_num) {
  72         case 0:
  73                 return SOC15_IH_CLIENTID_SDMA0;
  74         case 1:
  75                 return SOC15_IH_CLIENTID_SDMA1;
  76         case 2:
  77                 return SOC15_IH_CLIENTID_SDMA2;
  78         case 3:
  79                 return SOC15_IH_CLIENTID_SDMA3;
  80         default:
  81                 return -EINVAL;
  82         }
  83 }
  84
  85 static int sdma_v4_4_2_irq_id_to_seq(unsigned client_id)
  86 {
  87         switch (client_id) {
  88         case SOC15_IH_CLIENTID_SDMA0:
  89                 return 0;
  90         case SOC15_IH_CLIENTID_SDMA1:
  91                 return 1;
  92         case SOC15_IH_CLIENTID_SDMA2:
  93                 return 2;
  94         case SOC15_IH_CLIENTID_SDMA3:
  95                 return 3;
  96         default:
  97                 return -EINVAL;
  98         }
  99 }
 100
 101 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
 102                                                    uint32_t inst_mask)
 103 {
 104         u32 val;
 105         int i;
 106
 107         for (i = 0; i < adev->sdma.num_instances; i++) {
 108                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
 109                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
 110                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
 111                                     PIPE_INTERLEAVE_SIZE, 0);
 112                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
 113
 114                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
 115                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
 116                                     4);
 117                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
 118                                     PIPE_INTERLEAVE_SIZE, 0);
 119                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
 120         }
 121 }
 122
 123 /**
 124  * sdma_v4_4_2_init_microcode - load ucode images from disk
 125  *
 126  * @adev: amdgpu_device pointer
 127  *
 128  * Use the firmware interface to load the ucode images into
 129  * the driver (not loaded into hw).
 130  * Returns 0 on success, error on failure.
 131  */
 132 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
 133 {
 134         int ret, i;
 135
 136         for (i = 0; i < adev->sdma.num_instances; i++) {
 137                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) ==
 138                     IP_VERSION(4, 4, 2)) {
 139                         ret = amdgpu_sdma_init_microcode(adev, 0, true);
 140                         break;
 141                 } else {
 142                         ret = amdgpu_sdma_init_microcode(adev, i, false);
 143                         if (ret)
 144                                 return ret;
 145                 }
 146         }
 147
 148         return ret;
 149 }
 150
 151 /**
 152  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
 153  *
 154  * @ring: amdgpu ring pointer
 155  *
 156  * Get the current rptr from the hardware.
 157  */
 158 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
 159 {
 160         u64 rptr;
 161
 162         /* XXX check if swapping is necessary on BE */
 163         rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
 164
 165         DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
 166         return rptr >> 2;
 167 }
 168
 169 /**
 170  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
 171  *
 172  * @ring: amdgpu ring pointer
 173  *
 174  * Get the current wptr from the hardware.
 175  */
 176 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
 177 {
 178         struct amdgpu_device *adev = ring->adev;
 179         u64 wptr;
 180
 181         if (ring->use_doorbell) {
 182                 /* XXX check if swapping is necessary on BE */
 183                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 184                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 185         } else {
 186                 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
 187                 wptr = wptr << 32;
 188                 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
 189                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 190                                 ring->me, wptr);
 191         }
 192
 193         return wptr >> 2;
 194 }
 195
 196 /**
 197  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
 198  *
 199  * @ring: amdgpu ring pointer
 200  *
 201  * Write the wptr back to the hardware.
 202  */
 203 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
 204 {
 205         struct amdgpu_device *adev = ring->adev;
 206
 207         DRM_DEBUG("Setting write pointer\n");
 208         if (ring->use_doorbell) {
 209                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 210
 211                 DRM_DEBUG("Using doorbell -- "
 212                                 "wptr_offs == 0x%08x "
 213                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 214                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 215                                 ring->wptr_offs,
 216                                 lower_32_bits(ring->wptr << 2),
 217                                 upper_32_bits(ring->wptr << 2));
 218                 /* XXX check if swapping is necessary on BE */
 219                 WRITE_ONCE(*wb, (ring->wptr << 2));
 220                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 221                                 ring->doorbell_index, ring->wptr << 2);
 222                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 223         } else {
 224                 DRM_DEBUG("Not using doorbell -- "
 225                                 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 226                                 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 227                                 ring->me,
 228                                 lower_32_bits(ring->wptr << 2),
 229                                 ring->me,
 230                                 upper_32_bits(ring->wptr << 2));
 231                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
 232                             lower_32_bits(ring->wptr << 2));
 233                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
 234                             upper_32_bits(ring->wptr << 2));
 235         }
 236 }
 237
 238 /**
 239  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
 240  *
 241  * @ring: amdgpu ring pointer
 242  *
 243  * Get the current wptr from the hardware.
 244  */
 245 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
 246 {
 247         struct amdgpu_device *adev = ring->adev;
 248         u64 wptr;
 249
 250         if (ring->use_doorbell) {
 251                 /* XXX check if swapping is necessary on BE */
 252                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 253         } else {
 254                 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
 255                 wptr = wptr << 32;
 256                 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
 257         }
 258
 259         return wptr >> 2;
 260 }
 261
 262 /**
 263  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
 264  *
 265  * @ring: amdgpu ring pointer
 266  *
 267  * Write the wptr back to the hardware.
 268  */
 269 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
 270 {
 271         struct amdgpu_device *adev = ring->adev;
 272
 273         if (ring->use_doorbell) {
 274                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 275
 276                 /* XXX check if swapping is necessary on BE */
 277                 WRITE_ONCE(*wb, (ring->wptr << 2));
 278                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 279         } else {
 280                 uint64_t wptr = ring->wptr << 2;
 281
 282                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
 283                             lower_32_bits(wptr));
 284                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
 285                             upper_32_bits(wptr));
 286         }
 287 }
 288
 289 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 290 {
 291         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 292         int i;
 293
 294         for (i = 0; i < count; i++)
 295                 if (sdma && sdma->burst_nop && (i == 0))
 296                         amdgpu_ring_write(ring, ring->funcs->nop |
 297                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 298                 else
 299                         amdgpu_ring_write(ring, ring->funcs->nop);
 300 }
 301
 302 /**
 303  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
 304  *
 305  * @ring: amdgpu ring pointer
 306  * @job: job to retrieve vmid from
 307  * @ib: IB object to schedule
 308  * @flags: unused
 309  *
 310  * Schedule an IB in the DMA ring.
 311  */
 312 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
 313                                    struct amdgpu_job *job,
 314                                    struct amdgpu_ib *ib,
 315                                    uint32_t flags)
 316 {
 317         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 318
 319         /* IB packet must end on a 8 DW boundary */
 320         sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 321
 322         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 323                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 324         /* base must be 32 byte aligned */
 325         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 326         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 327         amdgpu_ring_write(ring, ib->length_dw);
 328         amdgpu_ring_write(ring, 0);
 329         amdgpu_ring_write(ring, 0);
 330
 331 }
 332
 333 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
 334                                    int mem_space, int hdp,
 335                                    uint32_t addr0, uint32_t addr1,
 336                                    uint32_t ref, uint32_t mask,
 337                                    uint32_t inv)
 338 {
 339         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 340                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 341                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 342                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 343         if (mem_space) {
 344                 /* memory */
 345                 amdgpu_ring_write(ring, addr0);
 346                 amdgpu_ring_write(ring, addr1);
 347         } else {
 348                 /* registers */
 349                 amdgpu_ring_write(ring, addr0 << 2);
 350                 amdgpu_ring_write(ring, addr1 << 2);
 351         }
 352         amdgpu_ring_write(ring, ref); /* reference */
 353         amdgpu_ring_write(ring, mask); /* mask */
 354         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 355                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 356 }
 357
 358 /**
 359  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 360  *
 361  * @ring: amdgpu ring pointer
 362  *
 363  * Emit an hdp flush packet on the requested DMA ring.
 364  */
 365 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 366 {
 367         struct amdgpu_device *adev = ring->adev;
 368         u32 ref_and_mask = 0;
 369         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 370
 371         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
 372                        << (ring->me % adev->sdma.num_inst_per_aid);
 373
 374         sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
 375                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 376                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 377                                ref_and_mask, ref_and_mask, 10);
 378 }
 379
 380 /**
 381  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
 382  *
 383  * @ring: amdgpu ring pointer
 384  * @addr: address
 385  * @seq: sequence number
 386  * @flags: fence related flags
 387  *
 388  * Add a DMA fence packet to the ring to write
 389  * the fence seq number and DMA trap packet to generate
 390  * an interrupt if needed.
 391  */
 392 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 393                                       unsigned flags)
 394 {
 395         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 396         /* write the fence */
 397         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 398         /* zero in first two bits */
 399         BUG_ON(addr & 0x3);
 400         amdgpu_ring_write(ring, lower_32_bits(addr));
 401         amdgpu_ring_write(ring, upper_32_bits(addr));
 402         amdgpu_ring_write(ring, lower_32_bits(seq));
 403
 404         /* optionally write high bits as well */
 405         if (write64bit) {
 406                 addr += 4;
 407                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 408                 /* zero in first two bits */
 409                 BUG_ON(addr & 0x3);
 410                 amdgpu_ring_write(ring, lower_32_bits(addr));
 411                 amdgpu_ring_write(ring, upper_32_bits(addr));
 412                 amdgpu_ring_write(ring, upper_32_bits(seq));
 413         }
 414
 415         /* generate an interrupt */
 416         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 417         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 418 }
 419
 420
 421 /**
 422  * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
 423  *
 424  * @adev: amdgpu_device pointer
 425  * @inst_mask: mask of dma engine instances to be disabled
 426  *
 427  * Stop the gfx async dma ring buffers.
 428  */
 429 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
 430                                       uint32_t inst_mask)
 431 {
 432         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 433         u32 doorbell_offset, doorbell;
 434         u32 rb_cntl, ib_cntl;
 435         int i;
 436
 437         for_each_inst(i, inst_mask) {
 438                 sdma[i] = &adev->sdma.instance[i].ring;
 439
 440                 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 441                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
 442                 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 443                 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 444                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
 445                 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 446
 447                 if (sdma[i]->use_doorbell) {
 448                         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 449                         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 450
 451                         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
 452                         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 453                                         SDMA_GFX_DOORBELL_OFFSET,
 454                                         OFFSET, 0);
 455                         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 456                         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 457                 }
 458         }
 459 }
 460
 461 /**
 462  * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
 463  *
 464  * @adev: amdgpu_device pointer
 465  * @inst_mask: mask of dma engine instances to be disabled
 466  *
 467  * Stop the compute async dma queues.
 468  */
 469 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
 470                                       uint32_t inst_mask)
 471 {
 472         /* XXX todo */
 473 }
 474
 475 /**
 476  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
 477  *
 478  * @adev: amdgpu_device pointer
 479  * @inst_mask: mask of dma engine instances to be disabled
 480  *
 481  * Stop the page async dma ring buffers.
 482  */
 483 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
 484                                        uint32_t inst_mask)
 485 {
 486         u32 rb_cntl, ib_cntl;
 487         int i;
 488
 489         for_each_inst(i, inst_mask) {
 490                 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 491                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 492                                         RB_ENABLE, 0);
 493                 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 494                 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 495                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
 496                                         IB_ENABLE, 0);
 497                 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 498         }
 499 }
 500
 501 /**
 502  * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
 503  *
 504  * @adev: amdgpu_device pointer
 505  * @enable: enable/disable the DMA MEs context switch.
 506  * @inst_mask: mask of dma engine instances to be enabled
 507  *
 508  * Halt or unhalt the async dma engines context switch.
 509  */
 510 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
 511                                                bool enable, uint32_t inst_mask)
 512 {
 513         u32 f32_cntl, phase_quantum = 0;
 514         int i;
 515
 516         if (amdgpu_sdma_phase_quantum) {
 517                 unsigned value = amdgpu_sdma_phase_quantum;
 518                 unsigned unit = 0;
 519
 520                 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 521                                 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
 522                         value = (value + 1) >> 1;
 523                         unit++;
 524                 }
 525                 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 526                             SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
 527                         value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 528                                  SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
 529                         unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 530                                 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
 531                         WARN_ONCE(1,
 532                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 533                                   value << unit);
 534                 }
 535                 phase_quantum =
 536                         value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
 537                         unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
 538         }
 539
 540         for_each_inst(i, inst_mask) {
 541                 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
 542                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
 543                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 544                 if (enable && amdgpu_sdma_phase_quantum) {
 545                         WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
 546                         WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
 547                         WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
 548                 }
 549                 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
 550
 551                 /* Extend page fault timeout to avoid interrupt storm */
 552                 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
 553         }
 554 }
 555
 556 /**
 557  * sdma_v4_4_2_inst_enable - stop the async dma engines
 558  *
 559  * @adev: amdgpu_device pointer
 560  * @enable: enable/disable the DMA MEs.
 561  * @inst_mask: mask of dma engine instances to be enabled
 562  *
 563  * Halt or unhalt the async dma engines.
 564  */
 565 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
 566                                     uint32_t inst_mask)
 567 {
 568         u32 f32_cntl;
 569         int i;
 570
 571         if (!enable) {
 572                 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
 573                 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
 574                 if (adev->sdma.has_page_queue)
 575                         sdma_v4_4_2_inst_page_stop(adev, inst_mask);
 576
 577                 /* SDMA FW needs to respond to FREEZE requests during reset.
 578                  * Keep it running during reset */
 579                 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
 580                         return;
 581         }
 582
 583         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 584                 return;
 585
 586         for_each_inst(i, inst_mask) {
 587                 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
 588                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
 589                 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
 590         }
 591 }
 592
 593 /*
 594  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
 595  */
 596 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 597 {
 598         /* Set ring buffer size in dwords */
 599         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 600
 601         barrier(); /* work around https://llvm.org/pr42576 */
 602         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 603 #ifdef __BIG_ENDIAN
 604         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 605         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 606                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 607 #endif
 608         return rb_cntl;
 609 }
 610
 611 /**
 612  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
 613  *
 614  * @adev: amdgpu_device pointer
 615  * @i: instance to resume
 616  *
 617  * Set up the gfx DMA ring buffers and enable them.
 618  * Returns 0 for success, error for failure.
 619  */
 620 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 621 {
 622         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 623         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 624         u32 wb_offset;
 625         u32 doorbell;
 626         u32 doorbell_offset;
 627         u64 wptr_gpu_addr;
 628
 629         wb_offset = (ring->rptr_offs * 4);
 630
 631         rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 632         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 633         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 634
 635         /* set the wb address whether it's enabled or not */
 636         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
 637                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 638         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
 639                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 640
 641         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 642                                 RPTR_WRITEBACK_ENABLE, 1);
 643
 644         WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
 645         WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 646
 647         ring->wptr = 0;
 648
 649         /* before programing wptr to a less value, need set minor_ptr_update first */
 650         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
 651
 652         /* Initialize the ring buffer's read and write pointers */
 653         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
 654         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
 655         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
 656         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
 657
 658         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 659         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 660
 661         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
 662                                  ring->use_doorbell);
 663         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 664                                         SDMA_GFX_DOORBELL_OFFSET,
 665                                         OFFSET, ring->doorbell_index);
 666         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 667         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 668
 669         sdma_v4_4_2_ring_set_wptr(ring);
 670
 671         /* set minor_ptr_update to 0 after wptr programed */
 672         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
 673
 674         /* setup the wptr shadow polling */
 675         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 676         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
 677                     lower_32_bits(wptr_gpu_addr));
 678         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
 679                     upper_32_bits(wptr_gpu_addr));
 680         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
 681         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 682                                        SDMA_GFX_RB_WPTR_POLL_CNTL,
 683                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 684         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 685
 686         /* enable DMA RB */
 687         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
 688         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 689
 690         ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 691         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
 692 #ifdef __BIG_ENDIAN
 693         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 694 #endif
 695         /* enable DMA IBs */
 696         WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 697 }
 698
 699 /**
 700  * sdma_v4_4_2_page_resume - setup and start the async dma engines
 701  *
 702  * @adev: amdgpu_device pointer
 703  * @i: instance to resume
 704  *
 705  * Set up the page DMA ring buffers and enable them.
 706  * Returns 0 for success, error for failure.
 707  */
 708 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
 709 {
 710         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 711         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 712         u32 wb_offset;
 713         u32 doorbell;
 714         u32 doorbell_offset;
 715         u64 wptr_gpu_addr;
 716
 717         wb_offset = (ring->rptr_offs * 4);
 718
 719         rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 720         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 721         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 722
 723         /* Initialize the ring buffer's read and write pointers */
 724         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
 725         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
 726         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
 727         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
 728
 729         /* set the wb address whether it's enabled or not */
 730         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
 731                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 732         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
 733                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 734
 735         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 736                                 RPTR_WRITEBACK_ENABLE, 1);
 737
 738         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
 739         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 740
 741         ring->wptr = 0;
 742
 743         /* before programing wptr to a less value, need set minor_ptr_update first */
 744         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
 745
 746         doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
 747         doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
 748
 749         doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
 750                                  ring->use_doorbell);
 751         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 752                                         SDMA_PAGE_DOORBELL_OFFSET,
 753                                         OFFSET, ring->doorbell_index);
 754         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
 755         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
 756
 757         /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
 758         sdma_v4_4_2_page_ring_set_wptr(ring);
 759
 760         /* set minor_ptr_update to 0 after wptr programed */
 761         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
 762
 763         /* setup the wptr shadow polling */
 764         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 765         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
 766                     lower_32_bits(wptr_gpu_addr));
 767         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
 768                     upper_32_bits(wptr_gpu_addr));
 769         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
 770         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 771                                        SDMA_PAGE_RB_WPTR_POLL_CNTL,
 772                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 773         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 774
 775         /* enable DMA RB */
 776         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
 777         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 778
 779         ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 780         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
 781 #ifdef __BIG_ENDIAN
 782         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
 783 #endif
 784         /* enable DMA IBs */
 785         WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 786 }
 787
 788 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
 789 {
 790
 791 }
 792
 793 /**
 794  * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
 795  *
 796  * @adev: amdgpu_device pointer
 797  * @inst_mask: mask of dma engine instances to be enabled
 798  *
 799  * Set up the compute DMA queues and enable them.
 800  * Returns 0 for success, error for failure.
 801  */
 802 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
 803                                        uint32_t inst_mask)
 804 {
 805         sdma_v4_4_2_init_pg(adev);
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
 812  *
 813  * @adev: amdgpu_device pointer
 814  * @inst_mask: mask of dma engine instances to be enabled
 815  *
 816  * Loads the sDMA0/1 ucode.
 817  * Returns 0 for success, -EINVAL if the ucode is not available.
 818  */
 819 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
 820                                            uint32_t inst_mask)
 821 {
 822         const struct sdma_firmware_header_v1_0 *hdr;
 823         const __le32 *fw_data;
 824         u32 fw_size;
 825         int i, j;
 826
 827         /* halt the MEs */
 828         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 829
 830         for_each_inst(i, inst_mask) {
 831                 if (!adev->sdma.instance[i].fw)
 832                         return -EINVAL;
 833
 834                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 835                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 836                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 837
 838                 fw_data = (const __le32 *)
 839                         (adev->sdma.instance[i].fw->data +
 840                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 841
 842                 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
 843
 844                 for (j = 0; j < fw_size; j++)
 845                         WREG32_SDMA(i, regSDMA_UCODE_DATA,
 846                                     le32_to_cpup(fw_data++));
 847
 848                 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
 849                             adev->sdma.instance[i].fw_version);
 850         }
 851
 852         return 0;
 853 }
 854
 855 /**
 856  * sdma_v4_4_2_inst_start - setup and start the async dma engines
 857  *
 858  * @adev: amdgpu_device pointer
 859  * @inst_mask: mask of dma engine instances to be enabled
 860  *
 861  * Set up the DMA engines and enable them.
 862  * Returns 0 for success, error for failure.
 863  */
 864 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 865                                   uint32_t inst_mask)
 866 {
 867         struct amdgpu_ring *ring;
 868         uint32_t tmp_mask;
 869         int i, r = 0;
 870
 871         if (amdgpu_sriov_vf(adev)) {
 872                 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 873                 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 874         } else {
 875                 /* bypass sdma microcode loading on Gopher */
 876                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
 877                     adev->sdma.instance[0].fw) {
 878                         r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
 879                         if (r)
 880                                 return r;
 881                 }
 882
 883                 /* unhalt the MEs */
 884                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 885                 /* enable sdma ring preemption */
 886                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 887         }
 888
 889         /* start the gfx rings and rlc compute queues */
 890         tmp_mask = inst_mask;
 891         for_each_inst(i, tmp_mask) {
 892                 uint32_t temp;
 893
 894                 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
 895                 sdma_v4_4_2_gfx_resume(adev, i);
 896                 if (adev->sdma.has_page_queue)
 897                         sdma_v4_4_2_page_resume(adev, i);
 898
 899                 /* set utc l1 enable flag always to 1 */
 900                 temp = RREG32_SDMA(i, regSDMA_CNTL);
 901                 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
 902                 /* enable context empty interrupt during initialization */
 903                 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
 904                 WREG32_SDMA(i, regSDMA_CNTL, temp);
 905
 906                 if (!amdgpu_sriov_vf(adev)) {
 907                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 908                                 /* unhalt engine */
 909                                 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
 910                                 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
 911                                 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
 912                         }
 913                 }
 914         }
 915
 916         if (amdgpu_sriov_vf(adev)) {
 917                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 918                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 919         } else {
 920                 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
 921                 if (r)
 922                         return r;
 923         }
 924
 925         tmp_mask = inst_mask;
 926         for_each_inst(i, tmp_mask) {
 927                 ring = &adev->sdma.instance[i].ring;
 928
 929                 r = amdgpu_ring_test_helper(ring);
 930                 if (r)
 931                         return r;
 932
 933                 if (adev->sdma.has_page_queue) {
 934                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
 935
 936                         r = amdgpu_ring_test_helper(page);
 937                         if (r)
 938                                 return r;
 939                 }
 940         }
 941
 942         return r;
 943 }
 944
 945 /**
 946  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
 947  *
 948  * @ring: amdgpu_ring structure holding ring information
 949  *
 950  * Test the DMA engine by writing using it to write an
 951  * value to memory.
 952  * Returns 0 for success, error for failure.
 953  */
 954 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
 955 {
 956         struct amdgpu_device *adev = ring->adev;
 957         unsigned i;
 958         unsigned index;
 959         int r;
 960         u32 tmp;
 961         u64 gpu_addr;
 962
 963         r = amdgpu_device_wb_get(adev, &index);
 964         if (r)
 965                 return r;
 966
 967         gpu_addr = adev->wb.gpu_addr + (index * 4);
 968         tmp = 0xCAFEDEAD;
 969         adev->wb.wb[index] = cpu_to_le32(tmp);
 970
 971         r = amdgpu_ring_alloc(ring, 5);
 972         if (r)
 973                 goto error_free_wb;
 974
 975         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 976                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 977         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 978         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 979         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 980         amdgpu_ring_write(ring, 0xDEADBEEF);
 981         amdgpu_ring_commit(ring);
 982
 983         for (i = 0; i < adev->usec_timeout; i++) {
 984                 tmp = le32_to_cpu(adev->wb.wb[index]);
 985                 if (tmp == 0xDEADBEEF)
 986                         break;
 987                 udelay(1);
 988         }
 989
 990         if (i >= adev->usec_timeout)
 991                 r = -ETIMEDOUT;
 992
 993 error_free_wb:
 994         amdgpu_device_wb_free(adev, index);
 995         return r;
 996 }
 997
 998 /**
 999  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1000  *
1001  * @ring: amdgpu_ring structure holding ring information
1002  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1003  *
1004  * Test a simple IB in the DMA ring.
1005  * Returns 0 on success, error on failure.
1006  */
1007 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1008 {
1009         struct amdgpu_device *adev = ring->adev;
1010         struct amdgpu_ib ib;
1011         struct dma_fence *f = NULL;
1012         unsigned index;
1013         long r;
1014         u32 tmp = 0;
1015         u64 gpu_addr;
1016
1017         r = amdgpu_device_wb_get(adev, &index);
1018         if (r)
1019                 return r;
1020
1021         gpu_addr = adev->wb.gpu_addr + (index * 4);
1022         tmp = 0xCAFEDEAD;
1023         adev->wb.wb[index] = cpu_to_le32(tmp);
1024         memset(&ib, 0, sizeof(ib));
1025         r = amdgpu_ib_get(adev, NULL, 256,
1026                                         AMDGPU_IB_POOL_DIRECT, &ib);
1027         if (r)
1028                 goto err0;
1029
1030         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1031                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1032         ib.ptr[1] = lower_32_bits(gpu_addr);
1033         ib.ptr[2] = upper_32_bits(gpu_addr);
1034         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1035         ib.ptr[4] = 0xDEADBEEF;
1036         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1037         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1038         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1039         ib.length_dw = 8;
1040
1041         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1042         if (r)
1043                 goto err1;
1044
1045         r = dma_fence_wait_timeout(f, false, timeout);
1046         if (r == 0) {
1047                 r = -ETIMEDOUT;
1048                 goto err1;
1049         } else if (r < 0) {
1050                 goto err1;
1051         }
1052         tmp = le32_to_cpu(adev->wb.wb[index]);
1053         if (tmp == 0xDEADBEEF)
1054                 r = 0;
1055         else
1056                 r = -EINVAL;
1057
1058 err1:
1059         amdgpu_ib_free(adev, &ib, NULL);
1060         dma_fence_put(f);
1061 err0:
1062         amdgpu_device_wb_free(adev, index);
1063         return r;
1064 }
1065
1066
1067 /**
1068  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1069  *
1070  * @ib: indirect buffer to fill with commands
1071  * @pe: addr of the page entry
1072  * @src: src addr to copy from
1073  * @count: number of page entries to update
1074  *
1075  * Update PTEs by copying them from the GART using sDMA.
1076  */
1077 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1078                                   uint64_t pe, uint64_t src,
1079                                   unsigned count)
1080 {
1081         unsigned bytes = count * 8;
1082
1083         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1084                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1085         ib->ptr[ib->length_dw++] = bytes - 1;
1086         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1087         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1088         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1089         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1090         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1091
1092 }
1093
1094 /**
1095  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1096  *
1097  * @ib: indirect buffer to fill with commands
1098  * @pe: addr of the page entry
1099  * @value: dst addr to write into pe
1100  * @count: number of page entries to update
1101  * @incr: increase next addr by incr bytes
1102  *
1103  * Update PTEs by writing them manually using sDMA.
1104  */
1105 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1106                                    uint64_t value, unsigned count,
1107                                    uint32_t incr)
1108 {
1109         unsigned ndw = count * 2;
1110
1111         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1112                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1113         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1114         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1115         ib->ptr[ib->length_dw++] = ndw - 1;
1116         for (; ndw > 0; ndw -= 2) {
1117                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1118                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1119                 value += incr;
1120         }
1121 }
1122
1123 /**
1124  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1125  *
1126  * @ib: indirect buffer to fill with commands
1127  * @pe: addr of the page entry
1128  * @addr: dst addr to write into pe
1129  * @count: number of page entries to update
1130  * @incr: increase next addr by incr bytes
1131  * @flags: access flags
1132  *
1133  * Update the page tables using sDMA.
1134  */
1135 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1136                                      uint64_t pe,
1137                                      uint64_t addr, unsigned count,
1138                                      uint32_t incr, uint64_t flags)
1139 {
1140         /* for physically contiguous pages (vram) */
1141         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1142         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1143         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1144         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1145         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1146         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1147         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1148         ib->ptr[ib->length_dw++] = incr; /* increment size */
1149         ib->ptr[ib->length_dw++] = 0;
1150         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1151 }
1152
1153 /**
1154  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1155  *
1156  * @ring: amdgpu_ring structure holding ring information
1157  * @ib: indirect buffer to fill with padding
1158  */
1159 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1160 {
1161         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1162         u32 pad_count;
1163         int i;
1164
1165         pad_count = (-ib->length_dw) & 7;
1166         for (i = 0; i < pad_count; i++)
1167                 if (sdma && sdma->burst_nop && (i == 0))
1168                         ib->ptr[ib->length_dw++] =
1169                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1170                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1171                 else
1172                         ib->ptr[ib->length_dw++] =
1173                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1174 }
1175
1176
1177 /**
1178  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1179  *
1180  * @ring: amdgpu_ring pointer
1181  *
1182  * Make sure all previous operations are completed (CIK).
1183  */
1184 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1185 {
1186         uint32_t seq = ring->fence_drv.sync_seq;
1187         uint64_t addr = ring->fence_drv.gpu_addr;
1188
1189         /* wait for idle */
1190         sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1191                                addr & 0xfffffffc,
1192                                upper_32_bits(addr) & 0xffffffff,
1193                                seq, 0xffffffff, 4);
1194 }
1195
1196
1197 /**
1198  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1199  *
1200  * @ring: amdgpu_ring pointer
1201  * @vmid: vmid number to use
1202  * @pd_addr: address
1203  *
1204  * Update the page table base and flush the VM TLB
1205  * using sDMA.
1206  */
1207 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1208                                          unsigned vmid, uint64_t pd_addr)
1209 {
1210         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1211 }
1212
1213 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1214                                      uint32_t reg, uint32_t val)
1215 {
1216         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1217                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1218         amdgpu_ring_write(ring, reg);
1219         amdgpu_ring_write(ring, val);
1220 }
1221
1222 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1223                                          uint32_t val, uint32_t mask)
1224 {
1225         sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1226 }
1227
1228 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1229 {
1230         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1231         case IP_VERSION(4, 4, 2):
1232                 return false;
1233         default:
1234                 return false;
1235         }
1236 }
1237
1238 static int sdma_v4_4_2_early_init(void *handle)
1239 {
1240         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1241         int r;
1242
1243         r = sdma_v4_4_2_init_microcode(adev);
1244         if (r)
1245                 return r;
1246
1247         /* TODO: Page queue breaks driver reload under SRIOV */
1248         if (sdma_v4_4_2_fw_support_paging_queue(adev))
1249                 adev->sdma.has_page_queue = true;
1250
1251         sdma_v4_4_2_set_ring_funcs(adev);
1252         sdma_v4_4_2_set_buffer_funcs(adev);
1253         sdma_v4_4_2_set_vm_pte_funcs(adev);
1254         sdma_v4_4_2_set_irq_funcs(adev);
1255         sdma_v4_4_2_set_ras_funcs(adev);
1256
1257         return 0;
1258 }
1259
1260 #if 0
1261 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1262                 void *err_data,
1263                 struct amdgpu_iv_entry *entry);
1264 #endif
1265
1266 static int sdma_v4_4_2_late_init(void *handle)
1267 {
1268         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1269 #if 0
1270         struct ras_ih_if ih_info = {
1271                 .cb = sdma_v4_4_2_process_ras_data_cb,
1272         };
1273 #endif
1274         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1275                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1276
1277         return 0;
1278 }
1279
1280 static int sdma_v4_4_2_sw_init(void *handle)
1281 {
1282         struct amdgpu_ring *ring;
1283         int r, i;
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285         u32 aid_id;
1286
1287         /* SDMA trap event */
1288         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1289                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1290                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1291                                       &adev->sdma.trap_irq);
1292                 if (r)
1293                         return r;
1294         }
1295
1296         /* SDMA SRAM ECC event */
1297         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1298                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1299                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1300                                       &adev->sdma.ecc_irq);
1301                 if (r)
1302                         return r;
1303         }
1304
1305         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1306         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1307                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1308                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1309                                       &adev->sdma.vm_hole_irq);
1310                 if (r)
1311                         return r;
1312
1313                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1314                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1315                                       &adev->sdma.doorbell_invalid_irq);
1316                 if (r)
1317                         return r;
1318
1319                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1320                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1321                                       &adev->sdma.pool_timeout_irq);
1322                 if (r)
1323                         return r;
1324
1325                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1326                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1327                                       &adev->sdma.srbm_write_irq);
1328                 if (r)
1329                         return r;
1330         }
1331
1332         for (i = 0; i < adev->sdma.num_instances; i++) {
1333                 ring = &adev->sdma.instance[i].ring;
1334                 ring->ring_obj = NULL;
1335                 ring->use_doorbell = true;
1336                 aid_id = adev->sdma.instance[i].aid_id;
1337
1338                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1339                                 ring->use_doorbell?"true":"false");
1340
1341                 /* doorbell size is 2 dwords, get DWORD offset */
1342                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1343                 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1344
1345                 sprintf(ring->name, "sdma%d.%d", aid_id,
1346                                 i % adev->sdma.num_inst_per_aid);
1347                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1348                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1349                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1350                 if (r)
1351                         return r;
1352
1353                 if (adev->sdma.has_page_queue) {
1354                         ring = &adev->sdma.instance[i].page;
1355                         ring->ring_obj = NULL;
1356                         ring->use_doorbell = true;
1357
1358                         /* doorbell index of page queue is assigned right after
1359                          * gfx queue on the same instance
1360                          */
1361                         ring->doorbell_index =
1362                                 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1363                         ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1364
1365                         sprintf(ring->name, "page%d.%d", aid_id,
1366                                         i % adev->sdma.num_inst_per_aid);
1367                         r = amdgpu_ring_init(adev, ring, 1024,
1368                                              &adev->sdma.trap_irq,
1369                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1370                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
1371                         if (r)
1372                                 return r;
1373                 }
1374         }
1375
1376         if (amdgpu_sdma_ras_sw_init(adev)) {
1377                 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1378                 return -EINVAL;
1379         }
1380
1381         return r;
1382 }
1383
1384 static int sdma_v4_4_2_sw_fini(void *handle)
1385 {
1386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1387         int i;
1388
1389         for (i = 0; i < adev->sdma.num_instances; i++) {
1390                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1391                 if (adev->sdma.has_page_queue)
1392                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1393         }
1394
1395         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2))
1396                 amdgpu_sdma_destroy_inst_ctx(adev, true);
1397         else
1398                 amdgpu_sdma_destroy_inst_ctx(adev, false);
1399
1400         return 0;
1401 }
1402
1403 static int sdma_v4_4_2_hw_init(void *handle)
1404 {
1405         int r;
1406         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1407         uint32_t inst_mask;
1408
1409         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1410         if (!amdgpu_sriov_vf(adev))
1411                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1412
1413         r = sdma_v4_4_2_inst_start(adev, inst_mask);
1414
1415         return r;
1416 }
1417
1418 static int sdma_v4_4_2_hw_fini(void *handle)
1419 {
1420         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1421         uint32_t inst_mask;
1422         int i;
1423
1424         if (amdgpu_sriov_vf(adev))
1425                 return 0;
1426
1427         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1428         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1429                 for (i = 0; i < adev->sdma.num_instances; i++) {
1430                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1431                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1432                 }
1433         }
1434
1435         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1436         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1437
1438         return 0;
1439 }
1440
1441 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1442                                              enum amd_clockgating_state state);
1443
1444 static int sdma_v4_4_2_suspend(void *handle)
1445 {
1446         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1447
1448         if (amdgpu_in_reset(adev))
1449                 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1450
1451         return sdma_v4_4_2_hw_fini(adev);
1452 }
1453
1454 static int sdma_v4_4_2_resume(void *handle)
1455 {
1456         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1457
1458         return sdma_v4_4_2_hw_init(adev);
1459 }
1460
1461 static bool sdma_v4_4_2_is_idle(void *handle)
1462 {
1463         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1464         u32 i;
1465
1466         for (i = 0; i < adev->sdma.num_instances; i++) {
1467                 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1468
1469                 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1470                         return false;
1471         }
1472
1473         return true;
1474 }
1475
1476 static int sdma_v4_4_2_wait_for_idle(void *handle)
1477 {
1478         unsigned i, j;
1479         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1480         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1481
1482         for (i = 0; i < adev->usec_timeout; i++) {
1483                 for (j = 0; j < adev->sdma.num_instances; j++) {
1484                         sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1485                         if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1486                                 break;
1487                 }
1488                 if (j == adev->sdma.num_instances)
1489                         return 0;
1490                 udelay(1);
1491         }
1492         return -ETIMEDOUT;
1493 }
1494
1495 static int sdma_v4_4_2_soft_reset(void *handle)
1496 {
1497         /* todo */
1498
1499         return 0;
1500 }
1501
1502 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1503                                         struct amdgpu_irq_src *source,
1504                                         unsigned type,
1505                                         enum amdgpu_interrupt_state state)
1506 {
1507         u32 sdma_cntl;
1508
1509         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1510         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1511                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1512         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1513
1514         return 0;
1515 }
1516
1517 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1518                                       struct amdgpu_irq_src *source,
1519                                       struct amdgpu_iv_entry *entry)
1520 {
1521         uint32_t instance, i;
1522
1523         DRM_DEBUG("IH: SDMA trap\n");
1524         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1525
1526         /* Client id gives the SDMA instance in AID. To know the exact SDMA
1527          * instance, interrupt entry gives the node id which corresponds to the AID instance.
1528          * Match node id with the AID id associated with the SDMA instance. */
1529         for (i = instance; i < adev->sdma.num_instances;
1530              i += adev->sdma.num_inst_per_aid) {
1531                 if (adev->sdma.instance[i].aid_id ==
1532                     node_id_to_phys_map[entry->node_id])
1533                         break;
1534         }
1535
1536         if (i >= adev->sdma.num_instances) {
1537                 dev_WARN_ONCE(
1538                         adev->dev, 1,
1539                         "Couldn't find the right sdma instance in trap handler");
1540                 return 0;
1541         }
1542
1543         switch (entry->ring_id) {
1544         case 0:
1545                 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1546                 break;
1547         default:
1548                 break;
1549         }
1550         return 0;
1551 }
1552
1553 #if 0
1554 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1555                 void *err_data,
1556                 struct amdgpu_iv_entry *entry)
1557 {
1558         int instance;
1559
1560         /* When “Full RAS” is enabled, the per-IP interrupt sources should
1561          * be disabled and the driver should only look for the aggregated
1562          * interrupt via sync flood
1563          */
1564         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1565                 goto out;
1566
1567         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1568         if (instance < 0)
1569                 goto out;
1570
1571         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1572
1573 out:
1574         return AMDGPU_RAS_SUCCESS;
1575 }
1576 #endif
1577
1578 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1579                                               struct amdgpu_irq_src *source,
1580                                               struct amdgpu_iv_entry *entry)
1581 {
1582         int instance;
1583
1584         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1585
1586         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1587         if (instance < 0)
1588                 return 0;
1589
1590         switch (entry->ring_id) {
1591         case 0:
1592                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1593                 break;
1594         }
1595         return 0;
1596 }
1597
1598 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1599                                         struct amdgpu_irq_src *source,
1600                                         unsigned type,
1601                                         enum amdgpu_interrupt_state state)
1602 {
1603         u32 sdma_cntl;
1604
1605         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1606         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1607                                         state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1608         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1609
1610         return 0;
1611 }
1612
1613 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1614                                               struct amdgpu_iv_entry *entry)
1615 {
1616         int instance;
1617         struct amdgpu_task_info *task_info;
1618         u64 addr;
1619
1620         instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
1621         if (instance < 0 || instance >= adev->sdma.num_instances) {
1622                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1623                 return -EINVAL;
1624         }
1625
1626         addr = (u64)entry->src_data[0] << 12;
1627         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1628
1629         dev_dbg_ratelimited(adev->dev,
1630                             "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1631                             instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1632                             entry->pasid);
1633
1634         task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1635         if (task_info) {
1636                 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1637                                     task_info->process_name, task_info->tgid,
1638                                     task_info->task_name, task_info->pid);
1639                 amdgpu_vm_put_task_info(task_info);
1640         }
1641
1642         return 0;
1643 }
1644
1645 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1646                                               struct amdgpu_irq_src *source,
1647                                               struct amdgpu_iv_entry *entry)
1648 {
1649         dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1650         sdma_v4_4_2_print_iv_entry(adev, entry);
1651         return 0;
1652 }
1653
1654 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1655                                               struct amdgpu_irq_src *source,
1656                                               struct amdgpu_iv_entry *entry)
1657 {
1658
1659         dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1660         sdma_v4_4_2_print_iv_entry(adev, entry);
1661         return 0;
1662 }
1663
1664 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1665                                               struct amdgpu_irq_src *source,
1666                                               struct amdgpu_iv_entry *entry)
1667 {
1668         dev_dbg_ratelimited(adev->dev,
1669                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1670         sdma_v4_4_2_print_iv_entry(adev, entry);
1671         return 0;
1672 }
1673
1674 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1675                                               struct amdgpu_irq_src *source,
1676                                               struct amdgpu_iv_entry *entry)
1677 {
1678         dev_dbg_ratelimited(adev->dev,
1679                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1680         sdma_v4_4_2_print_iv_entry(adev, entry);
1681         return 0;
1682 }
1683
1684 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1685         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1686 {
1687         uint32_t data, def;
1688         int i;
1689
1690         /* leave as default if it is not driver controlled */
1691         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1692                 return;
1693
1694         if (enable) {
1695                 for_each_inst(i, inst_mask) {
1696                         /* 1-not override: enable sdma mem light sleep */
1697                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1698                         data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1699                         if (def != data)
1700                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1701                 }
1702         } else {
1703                 for_each_inst(i, inst_mask) {
1704                         /* 0-override:disable sdma mem light sleep */
1705                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1706                         data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1707                         if (def != data)
1708                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1709                 }
1710         }
1711 }
1712
1713 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1714         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1715 {
1716         uint32_t data, def;
1717         int i;
1718
1719         /* leave as default if it is not driver controlled */
1720         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1721                 return;
1722
1723         if (enable) {
1724                 for_each_inst(i, inst_mask) {
1725                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1726                         data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1727                                   SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1728                                   SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1729                                   SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1730                                   SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1731                                   SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1732                         if (def != data)
1733                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1734                 }
1735         } else {
1736                 for_each_inst(i, inst_mask) {
1737                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1738                         data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1739                                  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1740                                  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1741                                  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1742                                  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1743                                  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1744                         if (def != data)
1745                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1746                 }
1747         }
1748 }
1749
1750 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1751                                           enum amd_clockgating_state state)
1752 {
1753         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1754         uint32_t inst_mask;
1755
1756         if (amdgpu_sriov_vf(adev))
1757                 return 0;
1758
1759         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1760
1761         sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1762                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1763         sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1764                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1765         return 0;
1766 }
1767
1768 static int sdma_v4_4_2_set_powergating_state(void *handle,
1769                                           enum amd_powergating_state state)
1770 {
1771         return 0;
1772 }
1773
1774 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1775 {
1776         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1777         int data;
1778
1779         if (amdgpu_sriov_vf(adev))
1780                 *flags = 0;
1781
1782         /* AMD_CG_SUPPORT_SDMA_MGCG */
1783         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1784         if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1785                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1786
1787         /* AMD_CG_SUPPORT_SDMA_LS */
1788         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1789         if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1790                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1791 }
1792
1793 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1794         .name = "sdma_v4_4_2",
1795         .early_init = sdma_v4_4_2_early_init,
1796         .late_init = sdma_v4_4_2_late_init,
1797         .sw_init = sdma_v4_4_2_sw_init,
1798         .sw_fini = sdma_v4_4_2_sw_fini,
1799         .hw_init = sdma_v4_4_2_hw_init,
1800         .hw_fini = sdma_v4_4_2_hw_fini,
1801         .suspend = sdma_v4_4_2_suspend,
1802         .resume = sdma_v4_4_2_resume,
1803         .is_idle = sdma_v4_4_2_is_idle,
1804         .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1805         .soft_reset = sdma_v4_4_2_soft_reset,
1806         .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1807         .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1808         .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1809 };
1810
1811 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1812         .type = AMDGPU_RING_TYPE_SDMA,
1813         .align_mask = 0xff,
1814         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1815         .support_64bit_ptrs = true,
1816         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1817         .get_wptr = sdma_v4_4_2_ring_get_wptr,
1818         .set_wptr = sdma_v4_4_2_ring_set_wptr,
1819         .emit_frame_size =
1820                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1821                 3 + /* hdp invalidate */
1822                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1823                 /* sdma_v4_4_2_ring_emit_vm_flush */
1824                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1825                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1826                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1827         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1828         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1829         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1830         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1831         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1832         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1833         .test_ring = sdma_v4_4_2_ring_test_ring,
1834         .test_ib = sdma_v4_4_2_ring_test_ib,
1835         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1836         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1837         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1838         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1839         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1840 };
1841
1842 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1843         .type = AMDGPU_RING_TYPE_SDMA,
1844         .align_mask = 0xff,
1845         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1846         .support_64bit_ptrs = true,
1847         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1848         .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1849         .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1850         .emit_frame_size =
1851                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1852                 3 + /* hdp invalidate */
1853                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1854                 /* sdma_v4_4_2_ring_emit_vm_flush */
1855                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1856                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1857                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1858         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1859         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1860         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1861         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1862         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1863         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1864         .test_ring = sdma_v4_4_2_ring_test_ring,
1865         .test_ib = sdma_v4_4_2_ring_test_ib,
1866         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1867         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1868         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1869         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1870         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1871 };
1872
1873 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1874 {
1875         int i, dev_inst;
1876
1877         for (i = 0; i < adev->sdma.num_instances; i++) {
1878                 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1879                 adev->sdma.instance[i].ring.me = i;
1880                 if (adev->sdma.has_page_queue) {
1881                         adev->sdma.instance[i].page.funcs =
1882                                 &sdma_v4_4_2_page_ring_funcs;
1883                         adev->sdma.instance[i].page.me = i;
1884                 }
1885
1886                 dev_inst = GET_INST(SDMA0, i);
1887                 /* AID to which SDMA belongs depends on physical instance */
1888                 adev->sdma.instance[i].aid_id =
1889                         dev_inst / adev->sdma.num_inst_per_aid;
1890         }
1891 }
1892
1893 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
1894         .set = sdma_v4_4_2_set_trap_irq_state,
1895         .process = sdma_v4_4_2_process_trap_irq,
1896 };
1897
1898 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
1899         .process = sdma_v4_4_2_process_illegal_inst_irq,
1900 };
1901
1902 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
1903         .set = sdma_v4_4_2_set_ecc_irq_state,
1904         .process = amdgpu_sdma_process_ecc_irq,
1905 };
1906
1907 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
1908         .process = sdma_v4_4_2_process_vm_hole_irq,
1909 };
1910
1911 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
1912         .process = sdma_v4_4_2_process_doorbell_invalid_irq,
1913 };
1914
1915 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
1916         .process = sdma_v4_4_2_process_pool_timeout_irq,
1917 };
1918
1919 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
1920         .process = sdma_v4_4_2_process_srbm_write_irq,
1921 };
1922
1923 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
1924 {
1925         adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
1926         adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
1927         adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
1928         adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
1929         adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
1930         adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
1931
1932         adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
1933         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
1934         adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
1935         adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
1936         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
1937         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
1938         adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
1939 }
1940
1941 /**
1942  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
1943  *
1944  * @ib: indirect buffer to copy to
1945  * @src_offset: src GPU address
1946  * @dst_offset: dst GPU address
1947  * @byte_count: number of bytes to xfer
1948  * @tmz: if a secure copy should be used
1949  *
1950  * Copy GPU buffers using the DMA engine.
1951  * Used by the amdgpu ttm implementation to move pages if
1952  * registered as the asic copy callback.
1953  */
1954 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1955                                        uint64_t src_offset,
1956                                        uint64_t dst_offset,
1957                                        uint32_t byte_count,
1958                                        bool tmz)
1959 {
1960         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1961                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1962                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1963         ib->ptr[ib->length_dw++] = byte_count - 1;
1964         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1965         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1966         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1967         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1968         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1969 }
1970
1971 /**
1972  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
1973  *
1974  * @ib: indirect buffer to copy to
1975  * @src_data: value to write to buffer
1976  * @dst_offset: dst GPU address
1977  * @byte_count: number of bytes to xfer
1978  *
1979  * Fill GPU buffers using the DMA engine.
1980  */
1981 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1982                                        uint32_t src_data,
1983                                        uint64_t dst_offset,
1984                                        uint32_t byte_count)
1985 {
1986         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1987         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1988         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1989         ib->ptr[ib->length_dw++] = src_data;
1990         ib->ptr[ib->length_dw++] = byte_count - 1;
1991 }
1992
1993 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
1994         .copy_max_bytes = 0x400000,
1995         .copy_num_dw = 7,
1996         .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
1997
1998         .fill_max_bytes = 0x400000,
1999         .fill_num_dw = 5,
2000         .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2001 };
2002
2003 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2004 {
2005         adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2006         if (adev->sdma.has_page_queue)
2007                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2008         else
2009                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2010 }
2011
2012 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2013         .copy_pte_num_dw = 7,
2014         .copy_pte = sdma_v4_4_2_vm_copy_pte,
2015
2016         .write_pte = sdma_v4_4_2_vm_write_pte,
2017         .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2018 };
2019
2020 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2021 {
2022         struct drm_gpu_scheduler *sched;
2023         unsigned i;
2024
2025         adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2026         for (i = 0; i < adev->sdma.num_instances; i++) {
2027                 if (adev->sdma.has_page_queue)
2028                         sched = &adev->sdma.instance[i].page.sched;
2029                 else
2030                         sched = &adev->sdma.instance[i].ring.sched;
2031                 adev->vm_manager.vm_pte_scheds[i] = sched;
2032         }
2033         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2034 }
2035
2036 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2037         .type = AMD_IP_BLOCK_TYPE_SDMA,
2038         .major = 4,
2039         .minor = 4,
2040         .rev = 2,
2041         .funcs = &sdma_v4_4_2_ip_funcs,
2042 };
2043
2044 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2045 {
2046         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2047         int r;
2048
2049         if (!amdgpu_sriov_vf(adev))
2050                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2051
2052         r = sdma_v4_4_2_inst_start(adev, inst_mask);
2053
2054         return r;
2055 }
2056
2057 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2058 {
2059         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2060         uint32_t tmp_mask = inst_mask;
2061         int i;
2062
2063         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2064                 for_each_inst(i, tmp_mask) {
2065                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2066                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2067                 }
2068         }
2069
2070         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2071         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2072
2073         return 0;
2074 }
2075
2076 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2077         .suspend = &sdma_v4_4_2_xcp_suspend,
2078         .resume = &sdma_v4_4_2_xcp_resume
2079 };
2080
2081 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2082         {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2083         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2084 };
2085
2086 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2087         {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2088         {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2089         {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2090         {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2091         {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2092         {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2093         {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2094         {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2095         {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2096         {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2097         {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2098         {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2099         {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2100         {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2101         {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2102         {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2103         {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2104         {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2105         {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2106         {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2107         {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2108         {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2109         {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2110         {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2111 };
2112
2113 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2114                                                    uint32_t sdma_inst,
2115                                                    void *ras_err_status)
2116 {
2117         struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2118         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2119         unsigned long ue_count = 0;
2120         struct amdgpu_smuio_mcm_config_info mcm_info = {
2121                 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2122                 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2123         };
2124
2125         /* sdma v4_4_2 doesn't support query ce counts */
2126         amdgpu_ras_inst_query_ras_error_count(adev,
2127                                         sdma_v4_2_2_ue_reg_list,
2128                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2129                                         sdma_v4_4_2_ras_memory_list,
2130                                         ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2131                                         sdma_dev_inst,
2132                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2133                                         &ue_count);
2134
2135         amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count);
2136 }
2137
2138 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2139                                               void *ras_err_status)
2140 {
2141         uint32_t inst_mask;
2142         int i = 0;
2143
2144         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2145         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2146                 for_each_inst(i, inst_mask)
2147                         sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2148         } else {
2149                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2150         }
2151 }
2152
2153 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2154                                                    uint32_t sdma_inst)
2155 {
2156         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2157
2158         amdgpu_ras_inst_reset_ras_error_count(adev,
2159                                         sdma_v4_2_2_ue_reg_list,
2160                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2161                                         sdma_dev_inst);
2162 }
2163
2164 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2165 {
2166         uint32_t inst_mask;
2167         int i = 0;
2168
2169         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2170         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2171                 for_each_inst(i, inst_mask)
2172                         sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2173         } else {
2174                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2175         }
2176 }
2177
2178 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2179         .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2180         .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2181 };
2182
2183 static int sdma_v4_4_2_aca_bank_generate_report(struct aca_handle *handle,
2184                                                 struct aca_bank *bank, enum aca_error_type type,
2185                                                 struct aca_bank_report *report, void *data)
2186 {
2187         u64 status, misc0;
2188         int ret;
2189
2190         status = bank->regs[ACA_REG_IDX_STATUS];
2191         if ((type == ACA_ERROR_TYPE_UE &&
2192              ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) ||
2193             (type == ACA_ERROR_TYPE_CE &&
2194              ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {
2195
2196                 ret = aca_bank_info_decode(bank, &report->info);
2197                 if (ret)
2198                         return ret;
2199
2200                 misc0 = bank->regs[ACA_REG_IDX_MISC0];
2201                 report->count[type] = ACA_REG__MISC0__ERRCNT(misc0);
2202         }
2203
2204         return 0;
2205 }
2206
2207 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2208 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2209
2210 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2211                                           enum aca_error_type type, void *data)
2212 {
2213         u32 instlo;
2214
2215         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2216         instlo &= GENMASK(31, 1);
2217
2218         if (instlo != mmSMNAID_AID0_MCA_SMU)
2219                 return false;
2220
2221         if (aca_bank_check_error_codes(handle->adev, bank,
2222                                        sdma_v4_4_2_err_codes,
2223                                        ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2224                 return false;
2225
2226         return true;
2227 }
2228
2229 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2230         .aca_bank_generate_report = sdma_v4_4_2_aca_bank_generate_report,
2231         .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2232 };
2233
2234 static const struct aca_info sdma_v4_4_2_aca_info = {
2235         .hwip = ACA_HWIP_TYPE_SMU,
2236         .mask = ACA_ERROR_UE_MASK,
2237         .bank_ops = &sdma_v4_4_2_aca_bank_ops,
2238 };
2239
2240 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2241 {
2242         int r;
2243
2244         r = amdgpu_sdma_ras_late_init(adev, ras_block);
2245         if (r)
2246                 return r;
2247
2248         return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2249                                    &sdma_v4_4_2_aca_info, NULL);
2250 }
2251
2252 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2253         .ras_block = {
2254                 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2255                 .ras_late_init = sdma_v4_4_2_ras_late_init,
2256         },
2257 };
2258
2259 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2260 {
2261         adev->sdma.ras = &sdma_v4_4_2_ras;
2262 }