drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_3_0_offset.h"
  34 #include "gc/gc_10_3_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40 #include "soc15_common.h"
  41 #include "soc15.h"
  42 #include "navi10_sdma_pkt_open.h"
  43 #include "nbio_v2_3.h"
  44 #include "sdma_common.h"
  45 #include "sdma_v5_2.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
  50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
  51
  52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
  53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
  54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
  55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
  56
  57 #define SDMA1_REG_OFFSET 0x600
  58 #define SDMA3_REG_OFFSET 0x400
  59 #define SDMA0_HYP_DEC_REG_START 0x5880
  60 #define SDMA0_HYP_DEC_REG_END 0x5893
  61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  62
  63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  67
  68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  69 {
  70         u32 base;
  71
  72         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  73             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  74                 base = adev->reg_offset[GC_HWIP][0][1];
  75                 if (instance != 0)
  76                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  77         } else {
  78                 if (instance < 2) {
  79                         base = adev->reg_offset[GC_HWIP][0][0];
  80                         if (instance == 1)
  81                                 internal_offset += SDMA1_REG_OFFSET;
  82                 } else {
  83                         base = adev->reg_offset[GC_HWIP][0][2];
  84                         if (instance == 3)
  85                                 internal_offset += SDMA3_REG_OFFSET;
  86                 }
  87         }
  88
  89         return base + internal_offset;
  90 }
  91
  92 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
  93 {
  94         int err = 0;
  95         const struct sdma_firmware_header_v1_0 *hdr;
  96
  97         err = amdgpu_ucode_validate(sdma_inst->fw);
  98         if (err)
  99                 return err;
 100
 101         hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 102         sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 103         sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 104
 105         if (sdma_inst->feature_version >= 20)
 106                 sdma_inst->burst_nop = true;
 107
 108         return 0;
 109 }
 110
 111 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 112 {
 113         release_firmware(adev->sdma.instance[0].fw);
 114
 115         memset((void *)adev->sdma.instance, 0,
 116                sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 117 }
 118
 119 /**
 120  * sdma_v5_2_init_microcode - load ucode images from disk
 121  *
 122  * @adev: amdgpu_device pointer
 123  *
 124  * Use the firmware interface to load the ucode images into
 125  * the driver (not loaded into hw).
 126  * Returns 0 on success, error on failure.
 127  */
 128
 129 // emulation only, won't work on real chip
 130 // navi10 real chip need to use PSP to load firmware
 131 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 132 {
 133         const char *chip_name;
 134         char fw_name[40];
 135         int err = 0, i;
 136         struct amdgpu_firmware_info *info = NULL;
 137         const struct common_firmware_header *header = NULL;
 138
 139         DRM_DEBUG("\n");
 140
 141         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 142         case IP_VERSION(5, 2, 0):
 143                 chip_name = "sienna_cichlid_sdma";
 144                 break;
 145         case IP_VERSION(5, 2, 2):
 146                 chip_name = "navy_flounder_sdma";
 147                 break;
 148         case IP_VERSION(5, 2, 1):
 149                 chip_name = "vangogh_sdma";
 150                 break;
 151         case IP_VERSION(5, 2, 4):
 152                 chip_name = "dimgrey_cavefish_sdma";
 153                 break;
 154         case IP_VERSION(5, 2, 5):
 155                 chip_name = "beige_goby_sdma";
 156                 break;
 157         case IP_VERSION(5, 2, 3):
 158                 chip_name = "yellow_carp_sdma";
 159                 break;
 160         case IP_VERSION(5, 2, 6):
 161                 chip_name = "sdma_5_2_6";
 162                 break;
 163         case IP_VERSION(5, 2, 7):
 164                 chip_name = "sdma_5_2_7";
 165                 break;
 166         default:
 167                 BUG();
 168         }
 169
 170         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
 171
 172         err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 173         if (err)
 174                 goto out;
 175
 176         err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 177         if (err)
 178                 goto out;
 179
 180         for (i = 1; i < adev->sdma.num_instances; i++)
 181                 memcpy((void *)&adev->sdma.instance[i],
 182                        (void *)&adev->sdma.instance[0],
 183                        sizeof(struct amdgpu_sdma_instance));
 184
 185         if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
 186                 return 0;
 187
 188         DRM_DEBUG("psp_load == '%s'\n",
 189                   adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 190
 191         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 192                 for (i = 0; i < adev->sdma.num_instances; i++) {
 193                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 194                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 195                         info->fw = adev->sdma.instance[i].fw;
 196                         header = (const struct common_firmware_header *)info->fw->data;
 197                         adev->firmware.fw_size +=
 198                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 199                 }
 200         }
 201
 202 out:
 203         if (err) {
 204                 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 205                 sdma_v5_2_destroy_inst_ctx(adev);
 206         }
 207         return err;
 208 }
 209
 210 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 211 {
 212         unsigned ret;
 213
 214         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 215         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 216         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 217         amdgpu_ring_write(ring, 1);
 218         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 219         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 220
 221         return ret;
 222 }
 223
 224 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 225                                            unsigned offset)
 226 {
 227         unsigned cur;
 228
 229         BUG_ON(offset > ring->buf_mask);
 230         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 231
 232         cur = (ring->wptr - 1) & ring->buf_mask;
 233         if (cur > offset)
 234                 ring->ring[offset] = cur - offset;
 235         else
 236                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 237 }
 238
 239 /**
 240  * sdma_v5_2_ring_get_rptr - get the current read pointer
 241  *
 242  * @ring: amdgpu ring pointer
 243  *
 244  * Get the current rptr from the hardware (NAVI10+).
 245  */
 246 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 247 {
 248         u64 *rptr;
 249
 250         /* XXX check if swapping is necessary on BE */
 251         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 252
 253         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 254         return ((*rptr) >> 2);
 255 }
 256
 257 /**
 258  * sdma_v5_2_ring_get_wptr - get the current write pointer
 259  *
 260  * @ring: amdgpu ring pointer
 261  *
 262  * Get the current wptr from the hardware (NAVI10+).
 263  */
 264 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 265 {
 266         struct amdgpu_device *adev = ring->adev;
 267         u64 wptr;
 268
 269         if (ring->use_doorbell) {
 270                 /* XXX check if swapping is necessary on BE */
 271                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 272                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 273         } else {
 274                 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 275                 wptr = wptr << 32;
 276                 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 277                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 278         }
 279
 280         return wptr >> 2;
 281 }
 282
 283 /**
 284  * sdma_v5_2_ring_set_wptr - commit the write pointer
 285  *
 286  * @ring: amdgpu ring pointer
 287  *
 288  * Write the wptr back to the hardware (NAVI10+).
 289  */
 290 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 291 {
 292         struct amdgpu_device *adev = ring->adev;
 293
 294         DRM_DEBUG("Setting write pointer\n");
 295         if (ring->use_doorbell) {
 296                 DRM_DEBUG("Using doorbell -- "
 297                                 "wptr_offs == 0x%08x "
 298                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 299                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 300                                 ring->wptr_offs,
 301                                 lower_32_bits(ring->wptr << 2),
 302                                 upper_32_bits(ring->wptr << 2));
 303                 /* XXX check if swapping is necessary on BE */
 304                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 305                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 306                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 307                                 ring->doorbell_index, ring->wptr << 2);
 308                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 309         } else {
 310                 DRM_DEBUG("Not using doorbell -- "
 311                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 312                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 313                                 ring->me,
 314                                 lower_32_bits(ring->wptr << 2),
 315                                 ring->me,
 316                                 upper_32_bits(ring->wptr << 2));
 317                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 318                         lower_32_bits(ring->wptr << 2));
 319                 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 320                         upper_32_bits(ring->wptr << 2));
 321         }
 322 }
 323
 324 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 325 {
 326         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 327         int i;
 328
 329         for (i = 0; i < count; i++)
 330                 if (sdma && sdma->burst_nop && (i == 0))
 331                         amdgpu_ring_write(ring, ring->funcs->nop |
 332                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 333                 else
 334                         amdgpu_ring_write(ring, ring->funcs->nop);
 335 }
 336
 337 /**
 338  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 339  *
 340  * @ring: amdgpu ring pointer
 341  * @job: job to retrieve vmid from
 342  * @ib: IB object to schedule
 343  * @flags: unused
 344  *
 345  * Schedule an IB in the DMA ring.
 346  */
 347 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 348                                    struct amdgpu_job *job,
 349                                    struct amdgpu_ib *ib,
 350                                    uint32_t flags)
 351 {
 352         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 353         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 354
 355         /* An IB packet must end on a 8 DW boundary--the next dword
 356          * must be on a 8-dword boundary. Our IB packet below is 6
 357          * dwords long, thus add x number of NOPs, such that, in
 358          * modular arithmetic,
 359          * wptr + 6 + x = 8k, k >= 0, which in C is,
 360          * (wptr + 6 + x) % 8 = 0.
 361          * The expression below, is a solution of x.
 362          */
 363         sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 364
 365         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 366                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 367         /* base must be 32 byte aligned */
 368         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 369         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 370         amdgpu_ring_write(ring, ib->length_dw);
 371         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 372         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 373 }
 374
 375 /**
 376  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
 377  *
 378  * @ring: amdgpu ring pointer
 379  *
 380  * flush the IB by graphics cache rinse.
 381  */
 382 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
 383 {
 384         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
 385                             SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
 386                             SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 387                             SDMA_GCR_GLI_INV(1);
 388
 389         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 390         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 391         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 392         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 393                         SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 394         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 395                         SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 396         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 397                         SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 398 }
 399
 400 /**
 401  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 402  *
 403  * @ring: amdgpu ring pointer
 404  *
 405  * Emit an hdp flush packet on the requested DMA ring.
 406  */
 407 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 408 {
 409         struct amdgpu_device *adev = ring->adev;
 410         u32 ref_and_mask = 0;
 411         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 412
 413         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 414
 415         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 416                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 417                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 418         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 419         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 420         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 421         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 422         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 423                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 424 }
 425
 426 /**
 427  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 428  *
 429  * @ring: amdgpu ring pointer
 430  * @addr: address
 431  * @seq: sequence number
 432  * @flags: fence related flags
 433  *
 434  * Add a DMA fence packet to the ring to write
 435  * the fence seq number and DMA trap packet to generate
 436  * an interrupt if needed.
 437  */
 438 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 439                                       unsigned flags)
 440 {
 441         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 442         /* write the fence */
 443         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 444                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 445         /* zero in first two bits */
 446         BUG_ON(addr & 0x3);
 447         amdgpu_ring_write(ring, lower_32_bits(addr));
 448         amdgpu_ring_write(ring, upper_32_bits(addr));
 449         amdgpu_ring_write(ring, lower_32_bits(seq));
 450
 451         /* optionally write high bits as well */
 452         if (write64bit) {
 453                 addr += 4;
 454                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 455                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 456                 /* zero in first two bits */
 457                 BUG_ON(addr & 0x3);
 458                 amdgpu_ring_write(ring, lower_32_bits(addr));
 459                 amdgpu_ring_write(ring, upper_32_bits(addr));
 460                 amdgpu_ring_write(ring, upper_32_bits(seq));
 461         }
 462
 463         if (flags & AMDGPU_FENCE_FLAG_INT) {
 464                 /* generate an interrupt */
 465                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 466                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 467         }
 468 }
 469
 470
 471 /**
 472  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 473  *
 474  * @adev: amdgpu_device pointer
 475  *
 476  * Stop the gfx async dma ring buffers.
 477  */
 478 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 479 {
 480         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 481         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 482         struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 483         struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 484         u32 rb_cntl, ib_cntl;
 485         int i;
 486
 487         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 488             (adev->mman.buffer_funcs_ring == sdma1) ||
 489             (adev->mman.buffer_funcs_ring == sdma2) ||
 490             (adev->mman.buffer_funcs_ring == sdma3))
 491                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 492
 493         for (i = 0; i < adev->sdma.num_instances; i++) {
 494                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 495                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 496                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 497                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 498                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 499                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 500         }
 501 }
 502
 503 /**
 504  * sdma_v5_2_rlc_stop - stop the compute async dma engines
 505  *
 506  * @adev: amdgpu_device pointer
 507  *
 508  * Stop the compute async dma queues.
 509  */
 510 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 511 {
 512         /* XXX todo */
 513 }
 514
 515 /**
 516  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
 517  *
 518  * @adev: amdgpu_device pointer
 519  * @enable: enable/disable the DMA MEs context switch.
 520  *
 521  * Halt or unhalt the async dma engines context switch.
 522  */
 523 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 524 {
 525         u32 f32_cntl, phase_quantum = 0;
 526         int i;
 527
 528         if (amdgpu_sdma_phase_quantum) {
 529                 unsigned value = amdgpu_sdma_phase_quantum;
 530                 unsigned unit = 0;
 531
 532                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 533                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 534                         value = (value + 1) >> 1;
 535                         unit++;
 536                 }
 537                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 538                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 539                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 540                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 541                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 542                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 543                         WARN_ONCE(1,
 544                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 545                                   value << unit);
 546                 }
 547                 phase_quantum =
 548                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 549                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 550         }
 551
 552         for (i = 0; i < adev->sdma.num_instances; i++) {
 553                 if (enable && amdgpu_sdma_phase_quantum) {
 554                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 555                                phase_quantum);
 556                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 557                                phase_quantum);
 558                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 559                                phase_quantum);
 560                 }
 561
 562                 if (!amdgpu_sriov_vf(adev)) {
 563                         f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 564                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 565                                         AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 566                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 567                 }
 568         }
 569
 570 }
 571
 572 /**
 573  * sdma_v5_2_enable - stop the async dma engines
 574  *
 575  * @adev: amdgpu_device pointer
 576  * @enable: enable/disable the DMA MEs.
 577  *
 578  * Halt or unhalt the async dma engines.
 579  */
 580 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 581 {
 582         u32 f32_cntl;
 583         int i;
 584
 585         if (!enable) {
 586                 sdma_v5_2_gfx_stop(adev);
 587                 sdma_v5_2_rlc_stop(adev);
 588         }
 589
 590         if (!amdgpu_sriov_vf(adev)) {
 591                 for (i = 0; i < adev->sdma.num_instances; i++) {
 592                         f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 593                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 594                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 595                 }
 596         }
 597 }
 598
 599 /**
 600  * sdma_v5_2_gfx_resume - setup and start the async dma engines
 601  *
 602  * @adev: amdgpu_device pointer
 603  *
 604  * Set up the gfx DMA ring buffers and enable them.
 605  * Returns 0 for success, error for failure.
 606  */
 607 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 608 {
 609         struct amdgpu_ring *ring;
 610         u32 rb_cntl, ib_cntl;
 611         u32 rb_bufsz;
 612         u32 wb_offset;
 613         u32 doorbell;
 614         u32 doorbell_offset;
 615         u32 temp;
 616         u32 wptr_poll_cntl;
 617         u64 wptr_gpu_addr;
 618         int i, r;
 619
 620         for (i = 0; i < adev->sdma.num_instances; i++) {
 621                 ring = &adev->sdma.instance[i].ring;
 622                 wb_offset = (ring->rptr_offs * 4);
 623
 624                 if (!amdgpu_sriov_vf(adev))
 625                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 626
 627                 /* Set ring buffer size in dwords */
 628                 rb_bufsz = order_base_2(ring->ring_size / 4);
 629                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 630                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 631 #ifdef __BIG_ENDIAN
 632                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 633                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 634                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 635 #endif
 636                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 637
 638                 /* Initialize the ring buffer's read and write pointers */
 639                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 640                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 641                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 642                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 643
 644                 /* setup the wptr shadow polling */
 645                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 646                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 647                        lower_32_bits(wptr_gpu_addr));
 648                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 649                        upper_32_bits(wptr_gpu_addr));
 650                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
 651                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 652                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 653                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 654                                                F32_POLL_ENABLE, 1);
 655                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 656                        wptr_poll_cntl);
 657
 658                 /* set the wb address whether it's enabled or not */
 659                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 660                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 661                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 662                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 663
 664                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 665
 666                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 667                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 668
 669                 ring->wptr = 0;
 670
 671                 /* before programing wptr to a less value, need set minor_ptr_update first */
 672                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 673
 674                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 675                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 676                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 677                 }
 678
 679                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 680                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 681
 682                 if (ring->use_doorbell) {
 683                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 684                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 685                                         OFFSET, ring->doorbell_index);
 686                 } else {
 687                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 688                 }
 689                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 690                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 691
 692                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 693                                                       ring->doorbell_index,
 694                                                       adev->doorbell_index.sdma_doorbell_range);
 695
 696                 if (amdgpu_sriov_vf(adev))
 697                         sdma_v5_2_ring_set_wptr(ring);
 698
 699                 /* set minor_ptr_update to 0 after wptr programed */
 700
 701                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 702
 703                 /* SRIOV VF has no control of any of registers below */
 704                 if (!amdgpu_sriov_vf(adev)) {
 705                         /* set utc l1 enable flag always to 1 */
 706                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 707                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 708
 709                         /* enable MCBP */
 710                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 711                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 712
 713                         /* Set up RESP_MODE to non-copy addresses */
 714                         temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 715                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 716                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 717                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 718
 719                         /* program default cache read and write policy */
 720                         temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 721                         /* clean read policy and write policy bits */
 722                         temp &= 0xFF0FFF;
 723                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 724                                  (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 725                                  SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 726                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 727
 728                         /* unhalt engine */
 729                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 730                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 731                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 732                 }
 733
 734                 /* enable DMA RB */
 735                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 736                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 737
 738                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 739                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 740 #ifdef __BIG_ENDIAN
 741                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 742 #endif
 743                 /* enable DMA IBs */
 744                 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 745
 746                 ring->sched.ready = true;
 747
 748                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 749                         sdma_v5_2_ctx_switch_enable(adev, true);
 750                         sdma_v5_2_enable(adev, true);
 751                 }
 752
 753                 r = amdgpu_ring_test_ring(ring);
 754                 if (r) {
 755                         ring->sched.ready = false;
 756                         return r;
 757                 }
 758
 759                 if (adev->mman.buffer_funcs_ring == ring)
 760                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 761         }
 762
 763         return 0;
 764 }
 765
 766 /**
 767  * sdma_v5_2_rlc_resume - setup and start the async dma engines
 768  *
 769  * @adev: amdgpu_device pointer
 770  *
 771  * Set up the compute DMA queues and enable them.
 772  * Returns 0 for success, error for failure.
 773  */
 774 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 775 {
 776         return 0;
 777 }
 778
 779 /**
 780  * sdma_v5_2_load_microcode - load the sDMA ME ucode
 781  *
 782  * @adev: amdgpu_device pointer
 783  *
 784  * Loads the sDMA0/1/2/3 ucode.
 785  * Returns 0 for success, -EINVAL if the ucode is not available.
 786  */
 787 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 788 {
 789         const struct sdma_firmware_header_v1_0 *hdr;
 790         const __le32 *fw_data;
 791         u32 fw_size;
 792         int i, j;
 793
 794         /* halt the MEs */
 795         sdma_v5_2_enable(adev, false);
 796
 797         for (i = 0; i < adev->sdma.num_instances; i++) {
 798                 if (!adev->sdma.instance[i].fw)
 799                         return -EINVAL;
 800
 801                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 802                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 803                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 804
 805                 fw_data = (const __le32 *)
 806                         (adev->sdma.instance[i].fw->data +
 807                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 808
 809                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 810
 811                 for (j = 0; j < fw_size; j++) {
 812                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 813                                 msleep(1);
 814                         WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 815                 }
 816
 817                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 818         }
 819
 820         return 0;
 821 }
 822
 823 static int sdma_v5_2_soft_reset(void *handle)
 824 {
 825         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 826         u32 grbm_soft_reset;
 827         u32 tmp;
 828         int i;
 829
 830         for (i = 0; i < adev->sdma.num_instances; i++) {
 831                 grbm_soft_reset = REG_SET_FIELD(0,
 832                                                 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
 833                                                 1);
 834                 grbm_soft_reset <<= i;
 835
 836                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 837                 tmp |= grbm_soft_reset;
 838                 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
 839                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 840                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 841
 842                 udelay(50);
 843
 844                 tmp &= ~grbm_soft_reset;
 845                 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
 846                 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
 847
 848                 udelay(50);
 849         }
 850
 851         return 0;
 852 }
 853
 854 /**
 855  * sdma_v5_2_start - setup and start the async dma engines
 856  *
 857  * @adev: amdgpu_device pointer
 858  *
 859  * Set up the DMA engines and enable them.
 860  * Returns 0 for success, error for failure.
 861  */
 862 static int sdma_v5_2_start(struct amdgpu_device *adev)
 863 {
 864         int r = 0;
 865
 866         if (amdgpu_sriov_vf(adev)) {
 867                 sdma_v5_2_ctx_switch_enable(adev, false);
 868                 sdma_v5_2_enable(adev, false);
 869
 870                 /* set RB registers */
 871                 r = sdma_v5_2_gfx_resume(adev);
 872                 return r;
 873         }
 874
 875         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 876                 r = sdma_v5_2_load_microcode(adev);
 877                 if (r)
 878                         return r;
 879
 880                 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 881                 if (amdgpu_emu_mode == 1)
 882                         msleep(1000);
 883         }
 884
 885         /* TODO: check whether can submit a doorbell request to raise
 886          * a doorbell fence to exit gfxoff.
 887          */
 888         if (adev->in_s0ix)
 889                 amdgpu_gfx_off_ctrl(adev, false);
 890
 891         sdma_v5_2_soft_reset(adev);
 892         /* unhalt the MEs */
 893         sdma_v5_2_enable(adev, true);
 894         /* enable sdma ring preemption */
 895         sdma_v5_2_ctx_switch_enable(adev, true);
 896
 897         /* start the gfx rings and rlc compute queues */
 898         r = sdma_v5_2_gfx_resume(adev);
 899         if (adev->in_s0ix)
 900                 amdgpu_gfx_off_ctrl(adev, true);
 901         if (r)
 902                 return r;
 903         r = sdma_v5_2_rlc_resume(adev);
 904
 905         return r;
 906 }
 907
 908 /**
 909  * sdma_v5_2_ring_test_ring - simple async dma engine test
 910  *
 911  * @ring: amdgpu_ring structure holding ring information
 912  *
 913  * Test the DMA engine by writing using it to write an
 914  * value to memory.
 915  * Returns 0 for success, error for failure.
 916  */
 917 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 918 {
 919         struct amdgpu_device *adev = ring->adev;
 920         unsigned i;
 921         unsigned index;
 922         int r;
 923         u32 tmp;
 924         u64 gpu_addr;
 925
 926         r = amdgpu_device_wb_get(adev, &index);
 927         if (r) {
 928                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 929                 return r;
 930         }
 931
 932         gpu_addr = adev->wb.gpu_addr + (index * 4);
 933         tmp = 0xCAFEDEAD;
 934         adev->wb.wb[index] = cpu_to_le32(tmp);
 935
 936         r = amdgpu_ring_alloc(ring, 5);
 937         if (r) {
 938                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 939                 amdgpu_device_wb_free(adev, index);
 940                 return r;
 941         }
 942
 943         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 944                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 945         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 946         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 947         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 948         amdgpu_ring_write(ring, 0xDEADBEEF);
 949         amdgpu_ring_commit(ring);
 950
 951         for (i = 0; i < adev->usec_timeout; i++) {
 952                 tmp = le32_to_cpu(adev->wb.wb[index]);
 953                 if (tmp == 0xDEADBEEF)
 954                         break;
 955                 if (amdgpu_emu_mode == 1)
 956                         msleep(1);
 957                 else
 958                         udelay(1);
 959         }
 960
 961         if (i >= adev->usec_timeout)
 962                 r = -ETIMEDOUT;
 963
 964         amdgpu_device_wb_free(adev, index);
 965
 966         return r;
 967 }
 968
 969 /**
 970  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 971  *
 972  * @ring: amdgpu_ring structure holding ring information
 973  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 974  *
 975  * Test a simple IB in the DMA ring.
 976  * Returns 0 on success, error on failure.
 977  */
 978 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 979 {
 980         struct amdgpu_device *adev = ring->adev;
 981         struct amdgpu_ib ib;
 982         struct dma_fence *f = NULL;
 983         unsigned index;
 984         long r;
 985         u32 tmp = 0;
 986         u64 gpu_addr;
 987
 988         r = amdgpu_device_wb_get(adev, &index);
 989         if (r) {
 990                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 991                 return r;
 992         }
 993
 994         gpu_addr = adev->wb.gpu_addr + (index * 4);
 995         tmp = 0xCAFEDEAD;
 996         adev->wb.wb[index] = cpu_to_le32(tmp);
 997         memset(&ib, 0, sizeof(ib));
 998         r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 999         if (r) {
1000                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1001                 goto err0;
1002         }
1003
1004         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1005                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1006         ib.ptr[1] = lower_32_bits(gpu_addr);
1007         ib.ptr[2] = upper_32_bits(gpu_addr);
1008         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1009         ib.ptr[4] = 0xDEADBEEF;
1010         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1011         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1012         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1013         ib.length_dw = 8;
1014
1015         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1016         if (r)
1017                 goto err1;
1018
1019         r = dma_fence_wait_timeout(f, false, timeout);
1020         if (r == 0) {
1021                 DRM_ERROR("amdgpu: IB test timed out\n");
1022                 r = -ETIMEDOUT;
1023                 goto err1;
1024         } else if (r < 0) {
1025                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1026                 goto err1;
1027         }
1028         tmp = le32_to_cpu(adev->wb.wb[index]);
1029         if (tmp == 0xDEADBEEF)
1030                 r = 0;
1031         else
1032                 r = -EINVAL;
1033
1034 err1:
1035         amdgpu_ib_free(adev, &ib, NULL);
1036         dma_fence_put(f);
1037 err0:
1038         amdgpu_device_wb_free(adev, index);
1039         return r;
1040 }
1041
1042
1043 /**
1044  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1045  *
1046  * @ib: indirect buffer to fill with commands
1047  * @pe: addr of the page entry
1048  * @src: src addr to copy from
1049  * @count: number of page entries to update
1050  *
1051  * Update PTEs by copying them from the GART using sDMA.
1052  */
1053 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1054                                   uint64_t pe, uint64_t src,
1055                                   unsigned count)
1056 {
1057         unsigned bytes = count * 8;
1058
1059         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1060                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1061         ib->ptr[ib->length_dw++] = bytes - 1;
1062         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1063         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1064         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1065         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1066         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1067
1068 }
1069
1070 /**
1071  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1072  *
1073  * @ib: indirect buffer to fill with commands
1074  * @pe: addr of the page entry
1075  * @value: dst addr to write into pe
1076  * @count: number of page entries to update
1077  * @incr: increase next addr by incr bytes
1078  *
1079  * Update PTEs by writing them manually using sDMA.
1080  */
1081 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1082                                    uint64_t value, unsigned count,
1083                                    uint32_t incr)
1084 {
1085         unsigned ndw = count * 2;
1086
1087         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1088                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1089         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1090         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1091         ib->ptr[ib->length_dw++] = ndw - 1;
1092         for (; ndw > 0; ndw -= 2) {
1093                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1094                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1095                 value += incr;
1096         }
1097 }
1098
1099 /**
1100  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1101  *
1102  * @ib: indirect buffer to fill with commands
1103  * @pe: addr of the page entry
1104  * @addr: dst addr to write into pe
1105  * @count: number of page entries to update
1106  * @incr: increase next addr by incr bytes
1107  * @flags: access flags
1108  *
1109  * Update the page tables using sDMA.
1110  */
1111 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1112                                      uint64_t pe,
1113                                      uint64_t addr, unsigned count,
1114                                      uint32_t incr, uint64_t flags)
1115 {
1116         /* for physically contiguous pages (vram) */
1117         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1118         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1119         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1120         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1121         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1122         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1123         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1124         ib->ptr[ib->length_dw++] = incr; /* increment size */
1125         ib->ptr[ib->length_dw++] = 0;
1126         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1127 }
1128
1129 /**
1130  * sdma_v5_2_ring_pad_ib - pad the IB
1131  *
1132  * @ib: indirect buffer to fill with padding
1133  * @ring: amdgpu_ring structure holding ring information
1134  *
1135  * Pad the IB with NOPs to a boundary multiple of 8.
1136  */
1137 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1138 {
1139         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1140         u32 pad_count;
1141         int i;
1142
1143         pad_count = (-ib->length_dw) & 0x7;
1144         for (i = 0; i < pad_count; i++)
1145                 if (sdma && sdma->burst_nop && (i == 0))
1146                         ib->ptr[ib->length_dw++] =
1147                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1148                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1149                 else
1150                         ib->ptr[ib->length_dw++] =
1151                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1152 }
1153
1154
1155 /**
1156  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1157  *
1158  * @ring: amdgpu_ring pointer
1159  *
1160  * Make sure all previous operations are completed (CIK).
1161  */
1162 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1163 {
1164         uint32_t seq = ring->fence_drv.sync_seq;
1165         uint64_t addr = ring->fence_drv.gpu_addr;
1166
1167         /* wait for idle */
1168         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1169                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1170                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1171                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1172         amdgpu_ring_write(ring, addr & 0xfffffffc);
1173         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1174         amdgpu_ring_write(ring, seq); /* reference */
1175         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1176         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1177                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1178 }
1179
1180
1181 /**
1182  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1183  *
1184  * @ring: amdgpu_ring pointer
1185  * @vmid: vmid number to use
1186  * @pd_addr: address
1187  *
1188  * Update the page table base and flush the VM TLB
1189  * using sDMA.
1190  */
1191 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1192                                          unsigned vmid, uint64_t pd_addr)
1193 {
1194         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1195 }
1196
1197 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1198                                      uint32_t reg, uint32_t val)
1199 {
1200         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1201                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1202         amdgpu_ring_write(ring, reg);
1203         amdgpu_ring_write(ring, val);
1204 }
1205
1206 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1207                                          uint32_t val, uint32_t mask)
1208 {
1209         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1210                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1211                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1212         amdgpu_ring_write(ring, reg << 2);
1213         amdgpu_ring_write(ring, 0);
1214         amdgpu_ring_write(ring, val); /* reference */
1215         amdgpu_ring_write(ring, mask); /* mask */
1216         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1217                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1218 }
1219
1220 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1221                                                    uint32_t reg0, uint32_t reg1,
1222                                                    uint32_t ref, uint32_t mask)
1223 {
1224         amdgpu_ring_emit_wreg(ring, reg0, ref);
1225         /* wait for a cycle to reset vm_inv_eng*_ack */
1226         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1227         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1228 }
1229
1230 static int sdma_v5_2_early_init(void *handle)
1231 {
1232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233
1234         sdma_v5_2_set_ring_funcs(adev);
1235         sdma_v5_2_set_buffer_funcs(adev);
1236         sdma_v5_2_set_vm_pte_funcs(adev);
1237         sdma_v5_2_set_irq_funcs(adev);
1238
1239         return 0;
1240 }
1241
1242 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1243 {
1244         switch (seq_num) {
1245         case 0:
1246                 return SOC15_IH_CLIENTID_SDMA0;
1247         case 1:
1248                 return SOC15_IH_CLIENTID_SDMA1;
1249         case 2:
1250                 return SOC15_IH_CLIENTID_SDMA2;
1251         case 3:
1252                 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1253         default:
1254                 break;
1255         }
1256         return -EINVAL;
1257 }
1258
1259 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1260 {
1261         switch (seq_num) {
1262         case 0:
1263                 return SDMA0_5_0__SRCID__SDMA_TRAP;
1264         case 1:
1265                 return SDMA1_5_0__SRCID__SDMA_TRAP;
1266         case 2:
1267                 return SDMA2_5_0__SRCID__SDMA_TRAP;
1268         case 3:
1269                 return SDMA3_5_0__SRCID__SDMA_TRAP;
1270         default:
1271                 break;
1272         }
1273         return -EINVAL;
1274 }
1275
1276 static int sdma_v5_2_sw_init(void *handle)
1277 {
1278         struct amdgpu_ring *ring;
1279         int r, i;
1280         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1281
1282         /* SDMA trap event */
1283         for (i = 0; i < adev->sdma.num_instances; i++) {
1284                 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1285                                       sdma_v5_2_seq_to_trap_id(i),
1286                                       &adev->sdma.trap_irq);
1287                 if (r)
1288                         return r;
1289         }
1290
1291         r = sdma_v5_2_init_microcode(adev);
1292         if (r) {
1293                 DRM_ERROR("Failed to load sdma firmware!\n");
1294                 return r;
1295         }
1296
1297         for (i = 0; i < adev->sdma.num_instances; i++) {
1298                 ring = &adev->sdma.instance[i].ring;
1299                 ring->ring_obj = NULL;
1300                 ring->use_doorbell = true;
1301                 ring->me = i;
1302
1303                 DRM_INFO("use_doorbell being set to: [%s]\n",
1304                                 ring->use_doorbell?"true":"false");
1305
1306                 ring->doorbell_index =
1307                         (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1308
1309                 sprintf(ring->name, "sdma%d", i);
1310                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1311                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1312                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1313                 if (r)
1314                         return r;
1315         }
1316
1317         return r;
1318 }
1319
1320 static int sdma_v5_2_sw_fini(void *handle)
1321 {
1322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1323         int i;
1324
1325         for (i = 0; i < adev->sdma.num_instances; i++)
1326                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1327
1328         sdma_v5_2_destroy_inst_ctx(adev);
1329
1330         return 0;
1331 }
1332
1333 static int sdma_v5_2_hw_init(void *handle)
1334 {
1335         int r;
1336         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337
1338         r = sdma_v5_2_start(adev);
1339
1340         return r;
1341 }
1342
1343 static int sdma_v5_2_hw_fini(void *handle)
1344 {
1345         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347         if (amdgpu_sriov_vf(adev))
1348                 return 0;
1349
1350         sdma_v5_2_ctx_switch_enable(adev, false);
1351         sdma_v5_2_enable(adev, false);
1352
1353         return 0;
1354 }
1355
1356 static int sdma_v5_2_suspend(void *handle)
1357 {
1358         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1359
1360         return sdma_v5_2_hw_fini(adev);
1361 }
1362
1363 static int sdma_v5_2_resume(void *handle)
1364 {
1365         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1366
1367         return sdma_v5_2_hw_init(adev);
1368 }
1369
1370 static bool sdma_v5_2_is_idle(void *handle)
1371 {
1372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373         u32 i;
1374
1375         for (i = 0; i < adev->sdma.num_instances; i++) {
1376                 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1377
1378                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1379                         return false;
1380         }
1381
1382         return true;
1383 }
1384
1385 static int sdma_v5_2_wait_for_idle(void *handle)
1386 {
1387         unsigned i;
1388         u32 sdma0, sdma1, sdma2, sdma3;
1389         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1390
1391         for (i = 0; i < adev->usec_timeout; i++) {
1392                 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1393                 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1394                 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1395                 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1396
1397                 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1398                         return 0;
1399                 udelay(1);
1400         }
1401         return -ETIMEDOUT;
1402 }
1403
1404 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1405 {
1406         int i, r = 0;
1407         struct amdgpu_device *adev = ring->adev;
1408         u32 index = 0;
1409         u64 sdma_gfx_preempt;
1410
1411         amdgpu_sdma_get_index_from_ring(ring, &index);
1412         sdma_gfx_preempt =
1413                 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1414
1415         /* assert preemption condition */
1416         amdgpu_ring_set_preempt_cond_exec(ring, false);
1417
1418         /* emit the trailing fence */
1419         ring->trail_seq += 1;
1420         amdgpu_ring_alloc(ring, 10);
1421         sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1422                                   ring->trail_seq, 0);
1423         amdgpu_ring_commit(ring);
1424
1425         /* assert IB preemption */
1426         WREG32(sdma_gfx_preempt, 1);
1427
1428         /* poll the trailing fence */
1429         for (i = 0; i < adev->usec_timeout; i++) {
1430                 if (ring->trail_seq ==
1431                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1432                         break;
1433                 udelay(1);
1434         }
1435
1436         if (i >= adev->usec_timeout) {
1437                 r = -EINVAL;
1438                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1439         }
1440
1441         /* deassert IB preemption */
1442         WREG32(sdma_gfx_preempt, 0);
1443
1444         /* deassert the preemption condition */
1445         amdgpu_ring_set_preempt_cond_exec(ring, true);
1446         return r;
1447 }
1448
1449 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1450                                         struct amdgpu_irq_src *source,
1451                                         unsigned type,
1452                                         enum amdgpu_interrupt_state state)
1453 {
1454         u32 sdma_cntl;
1455         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1456
1457         if (!amdgpu_sriov_vf(adev)) {
1458                 sdma_cntl = RREG32(reg_offset);
1459                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1460                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1461                 WREG32(reg_offset, sdma_cntl);
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1468                                       struct amdgpu_irq_src *source,
1469                                       struct amdgpu_iv_entry *entry)
1470 {
1471         DRM_DEBUG("IH: SDMA trap\n");
1472         switch (entry->client_id) {
1473         case SOC15_IH_CLIENTID_SDMA0:
1474                 switch (entry->ring_id) {
1475                 case 0:
1476                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1477                         break;
1478                 case 1:
1479                         /* XXX compute */
1480                         break;
1481                 case 2:
1482                         /* XXX compute */
1483                         break;
1484                 case 3:
1485                         /* XXX page queue*/
1486                         break;
1487                 }
1488                 break;
1489         case SOC15_IH_CLIENTID_SDMA1:
1490                 switch (entry->ring_id) {
1491                 case 0:
1492                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1493                         break;
1494                 case 1:
1495                         /* XXX compute */
1496                         break;
1497                 case 2:
1498                         /* XXX compute */
1499                         break;
1500                 case 3:
1501                         /* XXX page queue*/
1502                         break;
1503                 }
1504                 break;
1505         case SOC15_IH_CLIENTID_SDMA2:
1506                 switch (entry->ring_id) {
1507                 case 0:
1508                         amdgpu_fence_process(&adev->sdma.instance[2].ring);
1509                         break;
1510                 case 1:
1511                         /* XXX compute */
1512                         break;
1513                 case 2:
1514                         /* XXX compute */
1515                         break;
1516                 case 3:
1517                         /* XXX page queue*/
1518                         break;
1519                 }
1520                 break;
1521         case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1522                 switch (entry->ring_id) {
1523                 case 0:
1524                         amdgpu_fence_process(&adev->sdma.instance[3].ring);
1525                         break;
1526                 case 1:
1527                         /* XXX compute */
1528                         break;
1529                 case 2:
1530                         /* XXX compute */
1531                         break;
1532                 case 3:
1533                         /* XXX page queue*/
1534                         break;
1535                 }
1536                 break;
1537         }
1538         return 0;
1539 }
1540
1541 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1542                                               struct amdgpu_irq_src *source,
1543                                               struct amdgpu_iv_entry *entry)
1544 {
1545         return 0;
1546 }
1547
1548 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1549                                                        bool enable)
1550 {
1551         uint32_t data, def;
1552         int i;
1553
1554         for (i = 0; i < adev->sdma.num_instances; i++) {
1555
1556                 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1557                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1558
1559                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1560                         /* Enable sdma clock gating */
1561                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1562                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1563                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1564                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1565                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1566                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1567                                   SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1568                         if (def != data)
1569                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1570                 } else {
1571                         /* Disable sdma clock gating */
1572                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1573                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1574                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1575                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1576                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1577                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1578                                  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1579                         if (def != data)
1580                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1581                 }
1582         }
1583 }
1584
1585 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1586                                                       bool enable)
1587 {
1588         uint32_t data, def;
1589         int i;
1590
1591         for (i = 0; i < adev->sdma.num_instances; i++) {
1592
1593                 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1594                         adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1595
1596                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1597                         /* Enable sdma mem light sleep */
1598                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1599                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1600                         if (def != data)
1601                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1602
1603                 } else {
1604                         /* Disable sdma mem light sleep */
1605                         def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1606                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1607                         if (def != data)
1608                                 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1609
1610                 }
1611         }
1612 }
1613
1614 static int sdma_v5_2_set_clockgating_state(void *handle,
1615                                            enum amd_clockgating_state state)
1616 {
1617         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1618
1619         if (amdgpu_sriov_vf(adev))
1620                 return 0;
1621
1622         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1623         case IP_VERSION(5, 2, 0):
1624         case IP_VERSION(5, 2, 2):
1625         case IP_VERSION(5, 2, 1):
1626         case IP_VERSION(5, 2, 4):
1627         case IP_VERSION(5, 2, 5):
1628         case IP_VERSION(5, 2, 6):
1629         case IP_VERSION(5, 2, 3):
1630                 sdma_v5_2_update_medium_grain_clock_gating(adev,
1631                                 state == AMD_CG_STATE_GATE);
1632                 sdma_v5_2_update_medium_grain_light_sleep(adev,
1633                                 state == AMD_CG_STATE_GATE);
1634                 break;
1635         default:
1636                 break;
1637         }
1638
1639         return 0;
1640 }
1641
1642 static int sdma_v5_2_set_powergating_state(void *handle,
1643                                           enum amd_powergating_state state)
1644 {
1645         return 0;
1646 }
1647
1648 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1649 {
1650         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1651         int data;
1652
1653         if (amdgpu_sriov_vf(adev))
1654                 *flags = 0;
1655
1656         /* AMD_CG_SUPPORT_SDMA_MGCG */
1657         data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1658         if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1659                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1660
1661         /* AMD_CG_SUPPORT_SDMA_LS */
1662         data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1663         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1664                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1665 }
1666
1667 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1668         .name = "sdma_v5_2",
1669         .early_init = sdma_v5_2_early_init,
1670         .late_init = NULL,
1671         .sw_init = sdma_v5_2_sw_init,
1672         .sw_fini = sdma_v5_2_sw_fini,
1673         .hw_init = sdma_v5_2_hw_init,
1674         .hw_fini = sdma_v5_2_hw_fini,
1675         .suspend = sdma_v5_2_suspend,
1676         .resume = sdma_v5_2_resume,
1677         .is_idle = sdma_v5_2_is_idle,
1678         .wait_for_idle = sdma_v5_2_wait_for_idle,
1679         .soft_reset = sdma_v5_2_soft_reset,
1680         .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1681         .set_powergating_state = sdma_v5_2_set_powergating_state,
1682         .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1683 };
1684
1685 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1686         .type = AMDGPU_RING_TYPE_SDMA,
1687         .align_mask = 0xf,
1688         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1689         .support_64bit_ptrs = true,
1690         .secure_submission_supported = true,
1691         .vmhub = AMDGPU_GFXHUB_0,
1692         .get_rptr = sdma_v5_2_ring_get_rptr,
1693         .get_wptr = sdma_v5_2_ring_get_wptr,
1694         .set_wptr = sdma_v5_2_ring_set_wptr,
1695         .emit_frame_size =
1696                 5 + /* sdma_v5_2_ring_init_cond_exec */
1697                 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1698                 3 + /* hdp_invalidate */
1699                 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1700                 /* sdma_v5_2_ring_emit_vm_flush */
1701                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1702                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1703                 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1704         .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1705         .emit_ib = sdma_v5_2_ring_emit_ib,
1706         .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1707         .emit_fence = sdma_v5_2_ring_emit_fence,
1708         .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1709         .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1710         .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1711         .test_ring = sdma_v5_2_ring_test_ring,
1712         .test_ib = sdma_v5_2_ring_test_ib,
1713         .insert_nop = sdma_v5_2_ring_insert_nop,
1714         .pad_ib = sdma_v5_2_ring_pad_ib,
1715         .emit_wreg = sdma_v5_2_ring_emit_wreg,
1716         .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1717         .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1718         .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1719         .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1720         .preempt_ib = sdma_v5_2_ring_preempt_ib,
1721 };
1722
1723 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1724 {
1725         int i;
1726
1727         for (i = 0; i < adev->sdma.num_instances; i++) {
1728                 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1729                 adev->sdma.instance[i].ring.me = i;
1730         }
1731 }
1732
1733 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1734         .set = sdma_v5_2_set_trap_irq_state,
1735         .process = sdma_v5_2_process_trap_irq,
1736 };
1737
1738 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1739         .process = sdma_v5_2_process_illegal_inst_irq,
1740 };
1741
1742 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1743 {
1744         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1745                                         adev->sdma.num_instances;
1746         adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1747         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1748 }
1749
1750 /**
1751  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1752  *
1753  * @ib: indirect buffer to copy to
1754  * @src_offset: src GPU address
1755  * @dst_offset: dst GPU address
1756  * @byte_count: number of bytes to xfer
1757  * @tmz: if a secure copy should be used
1758  *
1759  * Copy GPU buffers using the DMA engine.
1760  * Used by the amdgpu ttm implementation to move pages if
1761  * registered as the asic copy callback.
1762  */
1763 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1764                                        uint64_t src_offset,
1765                                        uint64_t dst_offset,
1766                                        uint32_t byte_count,
1767                                        bool tmz)
1768 {
1769         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1770                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1771                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1772         ib->ptr[ib->length_dw++] = byte_count - 1;
1773         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1774         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1775         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1776         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1777         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1778 }
1779
1780 /**
1781  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1782  *
1783  * @ib: indirect buffer to fill
1784  * @src_data: value to write to buffer
1785  * @dst_offset: dst GPU address
1786  * @byte_count: number of bytes to xfer
1787  *
1788  * Fill GPU buffers using the DMA engine.
1789  */
1790 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1791                                        uint32_t src_data,
1792                                        uint64_t dst_offset,
1793                                        uint32_t byte_count)
1794 {
1795         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1796         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1797         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1798         ib->ptr[ib->length_dw++] = src_data;
1799         ib->ptr[ib->length_dw++] = byte_count - 1;
1800 }
1801
1802 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1803         .copy_max_bytes = 0x400000,
1804         .copy_num_dw = 7,
1805         .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1806
1807         .fill_max_bytes = 0x400000,
1808         .fill_num_dw = 5,
1809         .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1810 };
1811
1812 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1813 {
1814         if (adev->mman.buffer_funcs == NULL) {
1815                 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1816                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1817         }
1818 }
1819
1820 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1821         .copy_pte_num_dw = 7,
1822         .copy_pte = sdma_v5_2_vm_copy_pte,
1823         .write_pte = sdma_v5_2_vm_write_pte,
1824         .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1825 };
1826
1827 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1828 {
1829         unsigned i;
1830
1831         if (adev->vm_manager.vm_pte_funcs == NULL) {
1832                 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1833                 for (i = 0; i < adev->sdma.num_instances; i++) {
1834                         adev->vm_manager.vm_pte_scheds[i] =
1835                                 &adev->sdma.instance[i].ring.sched;
1836                 }
1837                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1838         }
1839 }
1840
1841 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1842         .type = AMD_IP_BLOCK_TYPE_SDMA,
1843         .major = 5,
1844         .minor = 2,
1845         .rev = 0,
1846         .funcs = &sdma_v5_2_ip_funcs,
1847 };