drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_10_1_0_offset.h"
  34 #include "gc/gc_10_1_0_sh_mask.h"
  35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37
  38 #include "soc15_common.h"
  39 #include "soc15.h"
  40 #include "navi10_sdma_pkt_open.h"
  41 #include "nbio_v2_3.h"
  42 #include "sdma_common.h"
  43 #include "sdma_v5_0.h"
  44
  45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin");
  46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin");
  47
  48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin");
  49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin");
  50
  51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin");
  52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin");
  53
  54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin");
  56
  57 #define SDMA1_REG_OFFSET 0x600
  58 #define SDMA0_HYP_DEC_REG_START 0x5880
  59 #define SDMA0_HYP_DEC_REG_END 0x5893
  60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  61
  62 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  63 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev);
  64 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  65 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  66
  67 static const struct soc15_reg_golden golden_settings_sdma_5[] = {
  68         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  69         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  70         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  71         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  73         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  75         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  76         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  78         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00),
  80         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
  81         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  82         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00)
  92 };
  93
  94 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
  95         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  96         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  97         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
 120 };
 121
 122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = {
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 125 };
 126
 127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = {
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 134 };
 135
 136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = {
 137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00)
 165 };
 166
 167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
 168 {
 169         u32 base;
 170
 171         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
 172             internal_offset <= SDMA0_HYP_DEC_REG_END) {
 173                 base = adev->reg_offset[GC_HWIP][0][1];
 174                 if (instance == 1)
 175                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET;
 176         } else {
 177                 base = adev->reg_offset[GC_HWIP][0][0];
 178                 if (instance == 1)
 179                         internal_offset += SDMA1_REG_OFFSET;
 180         }
 181
 182         return base + internal_offset;
 183 }
 184
 185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev)
 186 {
 187         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 188         case IP_VERSION(5, 0, 0):
 189                 soc15_program_register_sequence(adev,
 190                                                 golden_settings_sdma_5,
 191                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 192                 soc15_program_register_sequence(adev,
 193                                                 golden_settings_sdma_nv10,
 194                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10));
 195                 break;
 196         case IP_VERSION(5, 0, 2):
 197                 soc15_program_register_sequence(adev,
 198                                                 golden_settings_sdma_5,
 199                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 200                 soc15_program_register_sequence(adev,
 201                                                 golden_settings_sdma_nv14,
 202                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14));
 203                 break;
 204         case IP_VERSION(5, 0, 5):
 205                 if (amdgpu_sriov_vf(adev))
 206                         soc15_program_register_sequence(adev,
 207                                                         golden_settings_sdma_5_sriov,
 208                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
 209                 else
 210                         soc15_program_register_sequence(adev,
 211                                                         golden_settings_sdma_5,
 212                                                         (const u32)ARRAY_SIZE(golden_settings_sdma_5));
 213                 soc15_program_register_sequence(adev,
 214                                                 golden_settings_sdma_nv12,
 215                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12));
 216                 break;
 217         case IP_VERSION(5, 0, 1):
 218                 soc15_program_register_sequence(adev,
 219                                                 golden_settings_sdma_cyan_skillfish,
 220                                                 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish));
 221                 break;
 222         default:
 223                 break;
 224         }
 225 }
 226
 227 /**
 228  * sdma_v5_0_init_microcode - load ucode images from disk
 229  *
 230  * @adev: amdgpu_device pointer
 231  *
 232  * Use the firmware interface to load the ucode images into
 233  * the driver (not loaded into hw).
 234  * Returns 0 on success, error on failure.
 235  */
 236
 237 // emulation only, won't work on real chip
 238 // navi10 real chip need to use PSP to load firmware
 239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
 240 {
 241         const char *chip_name;
 242         char fw_name[40];
 243         int err = 0, i;
 244         struct amdgpu_firmware_info *info = NULL;
 245         const struct common_firmware_header *header = NULL;
 246         const struct sdma_firmware_header_v1_0 *hdr;
 247
 248         if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5)))
 249                 return 0;
 250
 251         DRM_DEBUG("\n");
 252
 253         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 254         case IP_VERSION(5, 0, 0):
 255                 chip_name = "navi10";
 256                 break;
 257         case IP_VERSION(5, 0, 2):
 258                 chip_name = "navi14";
 259                 break;
 260         case IP_VERSION(5, 0, 5):
 261                 chip_name = "navi12";
 262                 break;
 263         case IP_VERSION(5, 0, 1):
 264                 chip_name = "cyan_skillfish2";
 265                 break;
 266         default:
 267                 BUG();
 268         }
 269
 270         for (i = 0; i < adev->sdma.num_instances; i++) {
 271                 if (i == 0)
 272                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 273                 else
 274                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 275                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 276                 if (err)
 277                         goto out;
 278                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 279                 if (err)
 280                         goto out;
 281                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 282                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 283                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 284                 if (adev->sdma.instance[i].feature_version >= 20)
 285                         adev->sdma.instance[i].burst_nop = true;
 286                 DRM_DEBUG("psp_load == '%s'\n",
 287                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 288
 289                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 290                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 291                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 292                         info->fw = adev->sdma.instance[i].fw;
 293                         header = (const struct common_firmware_header *)info->fw->data;
 294                         adev->firmware.fw_size +=
 295                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 296                 }
 297         }
 298 out:
 299         if (err) {
 300                 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name);
 301                 for (i = 0; i < adev->sdma.num_instances; i++) {
 302                         release_firmware(adev->sdma.instance[i].fw);
 303                         adev->sdma.instance[i].fw = NULL;
 304                 }
 305         }
 306         return err;
 307 }
 308
 309 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring)
 310 {
 311         unsigned ret;
 312
 313         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 314         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 315         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 316         amdgpu_ring_write(ring, 1);
 317         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 318         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 319
 320         return ret;
 321 }
 322
 323 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
 324                                            unsigned offset)
 325 {
 326         unsigned cur;
 327
 328         BUG_ON(offset > ring->buf_mask);
 329         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 330
 331         cur = (ring->wptr - 1) & ring->buf_mask;
 332         if (cur > offset)
 333                 ring->ring[offset] = cur - offset;
 334         else
 335                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 336 }
 337
 338 /**
 339  * sdma_v5_0_ring_get_rptr - get the current read pointer
 340  *
 341  * @ring: amdgpu ring pointer
 342  *
 343  * Get the current rptr from the hardware (NAVI10+).
 344  */
 345 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
 346 {
 347         u64 *rptr;
 348
 349         /* XXX check if swapping is necessary on BE */
 350         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 351
 352         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 353         return ((*rptr) >> 2);
 354 }
 355
 356 /**
 357  * sdma_v5_0_ring_get_wptr - get the current write pointer
 358  *
 359  * @ring: amdgpu ring pointer
 360  *
 361  * Get the current wptr from the hardware (NAVI10+).
 362  */
 363 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         u64 wptr;
 367
 368         if (ring->use_doorbell) {
 369                 /* XXX check if swapping is necessary on BE */
 370                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 371                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 372         } else {
 373                 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 374                 wptr = wptr << 32;
 375                 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 376                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 377         }
 378
 379         return wptr >> 2;
 380 }
 381
 382 /**
 383  * sdma_v5_0_ring_set_wptr - commit the write pointer
 384  *
 385  * @ring: amdgpu ring pointer
 386  *
 387  * Write the wptr back to the hardware (NAVI10+).
 388  */
 389 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
 390 {
 391         struct amdgpu_device *adev = ring->adev;
 392
 393         DRM_DEBUG("Setting write pointer\n");
 394         if (ring->use_doorbell) {
 395                 DRM_DEBUG("Using doorbell -- "
 396                                 "wptr_offs == 0x%08x "
 397                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 398                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 399                                 ring->wptr_offs,
 400                                 lower_32_bits(ring->wptr << 2),
 401                                 upper_32_bits(ring->wptr << 2));
 402                 /* XXX check if swapping is necessary on BE */
 403                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 404                 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 405                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 406                                 ring->doorbell_index, ring->wptr << 2);
 407                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 408         } else {
 409                 DRM_DEBUG("Not using doorbell -- "
 410                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 411                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 412                                 ring->me,
 413                                 lower_32_bits(ring->wptr << 2),
 414                                 ring->me,
 415                                 upper_32_bits(ring->wptr << 2));
 416                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 417                         lower_32_bits(ring->wptr << 2));
 418                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 419                         upper_32_bits(ring->wptr << 2));
 420         }
 421 }
 422
 423 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 424 {
 425         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 426         int i;
 427
 428         for (i = 0; i < count; i++)
 429                 if (sdma && sdma->burst_nop && (i == 0))
 430                         amdgpu_ring_write(ring, ring->funcs->nop |
 431                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 432                 else
 433                         amdgpu_ring_write(ring, ring->funcs->nop);
 434 }
 435
 436 /**
 437  * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine
 438  *
 439  * @ring: amdgpu ring pointer
 440  * @job: job to retrieve vmid from
 441  * @ib: IB object to schedule
 442  * @flags: unused
 443  *
 444  * Schedule an IB in the DMA ring (NAVI10).
 445  */
 446 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
 447                                    struct amdgpu_job *job,
 448                                    struct amdgpu_ib *ib,
 449                                    uint32_t flags)
 450 {
 451         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 452         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 453
 454         /* An IB packet must end on a 8 DW boundary--the next dword
 455          * must be on a 8-dword boundary. Our IB packet below is 6
 456          * dwords long, thus add x number of NOPs, such that, in
 457          * modular arithmetic,
 458          * wptr + 6 + x = 8k, k >= 0, which in C is,
 459          * (wptr + 6 + x) % 8 = 0.
 460          * The expression below, is a solution of x.
 461          */
 462         sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 463
 464         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 465                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 466         /* base must be 32 byte aligned */
 467         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 468         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 469         amdgpu_ring_write(ring, ib->length_dw);
 470         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 471         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 472 }
 473
 474 /**
 475  * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 476  *
 477  * @ring: amdgpu ring pointer
 478  *
 479  * flush the IB by graphics cache rinse.
 480  */
 481 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 482 {
 483         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 484                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 485                             SDMA_GCR_GLI_INV(1);
 486
 487         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 488         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
 489         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 490         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 491                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 492         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 493                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 494         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 495                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 496 }
 497
 498 /**
 499  * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 500  *
 501  * @ring: amdgpu ring pointer
 502  *
 503  * Emit an hdp flush packet on the requested DMA ring.
 504  */
 505 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 506 {
 507         struct amdgpu_device *adev = ring->adev;
 508         u32 ref_and_mask = 0;
 509         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 510
 511         if (ring->me == 0)
 512                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 513         else
 514                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 515
 516         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 517                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 518                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 519         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 520         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 521         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 522         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 523         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 524                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 525 }
 526
 527 /**
 528  * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring
 529  *
 530  * @ring: amdgpu ring pointer
 531  * @addr: address
 532  * @seq: sequence number
 533  * @flags: fence related flags
 534  *
 535  * Add a DMA fence packet to the ring to write
 536  * the fence seq number and DMA trap packet to generate
 537  * an interrupt if needed (NAVI10).
 538  */
 539 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 540                                       unsigned flags)
 541 {
 542         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 543         /* write the fence */
 544         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 545                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 546         /* zero in first two bits */
 547         BUG_ON(addr & 0x3);
 548         amdgpu_ring_write(ring, lower_32_bits(addr));
 549         amdgpu_ring_write(ring, upper_32_bits(addr));
 550         amdgpu_ring_write(ring, lower_32_bits(seq));
 551
 552         /* optionally write high bits as well */
 553         if (write64bit) {
 554                 addr += 4;
 555                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 556                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 557                 /* zero in first two bits */
 558                 BUG_ON(addr & 0x3);
 559                 amdgpu_ring_write(ring, lower_32_bits(addr));
 560                 amdgpu_ring_write(ring, upper_32_bits(addr));
 561                 amdgpu_ring_write(ring, upper_32_bits(seq));
 562         }
 563
 564         if (flags & AMDGPU_FENCE_FLAG_INT) {
 565                 /* generate an interrupt */
 566                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 567                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 568         }
 569 }
 570
 571
 572 /**
 573  * sdma_v5_0_gfx_stop - stop the gfx async dma engines
 574  *
 575  * @adev: amdgpu_device pointer
 576  *
 577  * Stop the gfx async dma ring buffers (NAVI10).
 578  */
 579 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
 580 {
 581         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 582         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 583         u32 rb_cntl, ib_cntl;
 584         int i;
 585
 586         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 587             (adev->mman.buffer_funcs_ring == sdma1))
 588                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 589
 590         for (i = 0; i < adev->sdma.num_instances; i++) {
 591                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 592                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 593                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 594                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 595                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 596                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 597         }
 598 }
 599
 600 /**
 601  * sdma_v5_0_rlc_stop - stop the compute async dma engines
 602  *
 603  * @adev: amdgpu_device pointer
 604  *
 605  * Stop the compute async dma queues (NAVI10).
 606  */
 607 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev)
 608 {
 609         /* XXX todo */
 610 }
 611
 612 /**
 613  * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch
 614  *
 615  * @adev: amdgpu_device pointer
 616  * @enable: enable/disable the DMA MEs context switch.
 617  *
 618  * Halt or unhalt the async dma engines context switch (NAVI10).
 619  */
 620 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 621 {
 622         u32 f32_cntl = 0, phase_quantum = 0;
 623         int i;
 624
 625         if (amdgpu_sdma_phase_quantum) {
 626                 unsigned value = amdgpu_sdma_phase_quantum;
 627                 unsigned unit = 0;
 628
 629                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 630                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 631                         value = (value + 1) >> 1;
 632                         unit++;
 633                 }
 634                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 635                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 636                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 637                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 638                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 639                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 640                         WARN_ONCE(1,
 641                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 642                                   value << unit);
 643                 }
 644                 phase_quantum =
 645                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 646                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 647         }
 648
 649         for (i = 0; i < adev->sdma.num_instances; i++) {
 650                 if (!amdgpu_sriov_vf(adev)) {
 651                         f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 652                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 653                                                  AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 654                 }
 655
 656                 if (enable && amdgpu_sdma_phase_quantum) {
 657                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 658                                phase_quantum);
 659                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 660                                phase_quantum);
 661                         WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 662                                phase_quantum);
 663                 }
 664                 if (!amdgpu_sriov_vf(adev))
 665                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 666         }
 667
 668 }
 669
 670 /**
 671  * sdma_v5_0_enable - stop the async dma engines
 672  *
 673  * @adev: amdgpu_device pointer
 674  * @enable: enable/disable the DMA MEs.
 675  *
 676  * Halt or unhalt the async dma engines (NAVI10).
 677  */
 678 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable)
 679 {
 680         u32 f32_cntl;
 681         int i;
 682
 683         if (!enable) {
 684                 sdma_v5_0_gfx_stop(adev);
 685                 sdma_v5_0_rlc_stop(adev);
 686         }
 687
 688         if (amdgpu_sriov_vf(adev))
 689                 return;
 690
 691         for (i = 0; i < adev->sdma.num_instances; i++) {
 692                 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 693                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 694                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 695         }
 696 }
 697
 698 /**
 699  * sdma_v5_0_gfx_resume - setup and start the async dma engines
 700  *
 701  * @adev: amdgpu_device pointer
 702  *
 703  * Set up the gfx DMA ring buffers and enable them (NAVI10).
 704  * Returns 0 for success, error for failure.
 705  */
 706 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
 707 {
 708         struct amdgpu_ring *ring;
 709         u32 rb_cntl, ib_cntl;
 710         u32 rb_bufsz;
 711         u32 wb_offset;
 712         u32 doorbell;
 713         u32 doorbell_offset;
 714         u32 temp;
 715         u32 wptr_poll_cntl;
 716         u64 wptr_gpu_addr;
 717         int i, r;
 718
 719         for (i = 0; i < adev->sdma.num_instances; i++) {
 720                 ring = &adev->sdma.instance[i].ring;
 721                 wb_offset = (ring->rptr_offs * 4);
 722
 723                 if (!amdgpu_sriov_vf(adev))
 724                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 725
 726                 /* Set ring buffer size in dwords */
 727                 rb_bufsz = order_base_2(ring->ring_size / 4);
 728                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 729                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 730 #ifdef __BIG_ENDIAN
 731                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 732                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 733                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 734 #endif
 735                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 736
 737                 /* Initialize the ring buffer's read and write pointers */
 738                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 739                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 740                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 741                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 742
 743                 /* setup the wptr shadow polling */
 744                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 745                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 746                        lower_32_bits(wptr_gpu_addr));
 747                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 748                        upper_32_bits(wptr_gpu_addr));
 749                 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 750                                                          mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 751                 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 752                                                SDMA0_GFX_RB_WPTR_POLL_CNTL,
 753                                                F32_POLL_ENABLE, 1);
 754                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 755                        wptr_poll_cntl);
 756
 757                 /* set the wb address whether it's enabled or not */
 758                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 759                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 760                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 761                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 762
 763                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 764
 765                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
 766                        ring->gpu_addr >> 8);
 767                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
 768                        ring->gpu_addr >> 40);
 769
 770                 ring->wptr = 0;
 771
 772                 /* before programing wptr to a less value, need set minor_ptr_update first */
 773                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 774
 775                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 776                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
 777                                lower_32_bits(ring->wptr) << 2);
 778                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
 779                                upper_32_bits(ring->wptr) << 2);
 780                 }
 781
 782                 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 783                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
 784                                                 mmSDMA0_GFX_DOORBELL_OFFSET));
 785
 786                 if (ring->use_doorbell) {
 787                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 788                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 789                                         OFFSET, ring->doorbell_index);
 790                 } else {
 791                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 792                 }
 793                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 794                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
 795                        doorbell_offset);
 796
 797                 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 798                                                       ring->doorbell_index, 20);
 799
 800                 if (amdgpu_sriov_vf(adev))
 801                         sdma_v5_0_ring_set_wptr(ring);
 802
 803                 /* set minor_ptr_update to 0 after wptr programed */
 804                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 805
 806                 if (!amdgpu_sriov_vf(adev)) {
 807                         /* set utc l1 enable flag always to 1 */
 808                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 809                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 810
 811                         /* enable MCBP */
 812                         temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 813                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 814
 815                         /* Set up RESP_MODE to non-copy addresses */
 816                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 817                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 818                         temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 819                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 820
 821                         /* program default cache read and write policy */
 822                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 823                         /* clean read policy and write policy bits */
 824                         temp &= 0xFF0FFF;
 825                         temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14));
 826                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 827                 }
 828
 829                 if (!amdgpu_sriov_vf(adev)) {
 830                         /* unhalt engine */
 831                         temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 832                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 833                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 834                 }
 835
 836                 /* enable DMA RB */
 837                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 838                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 839
 840                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 841                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 842 #ifdef __BIG_ENDIAN
 843                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 844 #endif
 845                 /* enable DMA IBs */
 846                 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 847
 848                 ring->sched.ready = true;
 849
 850                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 851                         sdma_v5_0_ctx_switch_enable(adev, true);
 852                         sdma_v5_0_enable(adev, true);
 853                 }
 854
 855                 r = amdgpu_ring_test_helper(ring);
 856                 if (r)
 857                         return r;
 858
 859                 if (adev->mman.buffer_funcs_ring == ring)
 860                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 861         }
 862
 863         return 0;
 864 }
 865
 866 /**
 867  * sdma_v5_0_rlc_resume - setup and start the async dma engines
 868  *
 869  * @adev: amdgpu_device pointer
 870  *
 871  * Set up the compute DMA queues and enable them (NAVI10).
 872  * Returns 0 for success, error for failure.
 873  */
 874 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev)
 875 {
 876         return 0;
 877 }
 878
 879 /**
 880  * sdma_v5_0_load_microcode - load the sDMA ME ucode
 881  *
 882  * @adev: amdgpu_device pointer
 883  *
 884  * Loads the sDMA0/1 ucode.
 885  * Returns 0 for success, -EINVAL if the ucode is not available.
 886  */
 887 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev)
 888 {
 889         const struct sdma_firmware_header_v1_0 *hdr;
 890         const __le32 *fw_data;
 891         u32 fw_size;
 892         int i, j;
 893
 894         /* halt the MEs */
 895         sdma_v5_0_enable(adev, false);
 896
 897         for (i = 0; i < adev->sdma.num_instances; i++) {
 898                 if (!adev->sdma.instance[i].fw)
 899                         return -EINVAL;
 900
 901                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 902                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 903                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 904
 905                 fw_data = (const __le32 *)
 906                         (adev->sdma.instance[i].fw->data +
 907                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 908
 909                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 910
 911                 for (j = 0; j < fw_size; j++) {
 912                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 913                                 msleep(1);
 914                         WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 915                 }
 916
 917                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 918         }
 919
 920         return 0;
 921 }
 922
 923 /**
 924  * sdma_v5_0_start - setup and start the async dma engines
 925  *
 926  * @adev: amdgpu_device pointer
 927  *
 928  * Set up the DMA engines and enable them (NAVI10).
 929  * Returns 0 for success, error for failure.
 930  */
 931 static int sdma_v5_0_start(struct amdgpu_device *adev)
 932 {
 933         int r = 0;
 934
 935         if (amdgpu_sriov_vf(adev)) {
 936                 sdma_v5_0_ctx_switch_enable(adev, false);
 937                 sdma_v5_0_enable(adev, false);
 938
 939                 /* set RB registers */
 940                 r = sdma_v5_0_gfx_resume(adev);
 941                 return r;
 942         }
 943
 944         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 945                 r = sdma_v5_0_load_microcode(adev);
 946                 if (r)
 947                         return r;
 948         }
 949
 950         /* unhalt the MEs */
 951         sdma_v5_0_enable(adev, true);
 952         /* enable sdma ring preemption */
 953         sdma_v5_0_ctx_switch_enable(adev, true);
 954
 955         /* start the gfx rings and rlc compute queues */
 956         r = sdma_v5_0_gfx_resume(adev);
 957         if (r)
 958                 return r;
 959         r = sdma_v5_0_rlc_resume(adev);
 960
 961         return r;
 962 }
 963
 964 /**
 965  * sdma_v5_0_ring_test_ring - simple async dma engine test
 966  *
 967  * @ring: amdgpu_ring structure holding ring information
 968  *
 969  * Test the DMA engine by writing using it to write an
 970  * value to memory. (NAVI10).
 971  * Returns 0 for success, error for failure.
 972  */
 973 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring)
 974 {
 975         struct amdgpu_device *adev = ring->adev;
 976         unsigned i;
 977         unsigned index;
 978         int r;
 979         u32 tmp;
 980         u64 gpu_addr;
 981
 982         r = amdgpu_device_wb_get(adev, &index);
 983         if (r) {
 984                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 985                 return r;
 986         }
 987
 988         gpu_addr = adev->wb.gpu_addr + (index * 4);
 989         tmp = 0xCAFEDEAD;
 990         adev->wb.wb[index] = cpu_to_le32(tmp);
 991
 992         r = amdgpu_ring_alloc(ring, 5);
 993         if (r) {
 994                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 995                 amdgpu_device_wb_free(adev, index);
 996                 return r;
 997         }
 998
 999         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1000                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1001         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1002         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1003         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1004         amdgpu_ring_write(ring, 0xDEADBEEF);
1005         amdgpu_ring_commit(ring);
1006
1007         for (i = 0; i < adev->usec_timeout; i++) {
1008                 tmp = le32_to_cpu(adev->wb.wb[index]);
1009                 if (tmp == 0xDEADBEEF)
1010                         break;
1011                 if (amdgpu_emu_mode == 1)
1012                         msleep(1);
1013                 else
1014                         udelay(1);
1015         }
1016
1017         if (i >= adev->usec_timeout)
1018                 r = -ETIMEDOUT;
1019
1020         amdgpu_device_wb_free(adev, index);
1021
1022         return r;
1023 }
1024
1025 /**
1026  * sdma_v5_0_ring_test_ib - test an IB on the DMA engine
1027  *
1028  * @ring: amdgpu_ring structure holding ring information
1029  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1030  *
1031  * Test a simple IB in the DMA ring (NAVI10).
1032  * Returns 0 on success, error on failure.
1033  */
1034 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1035 {
1036         struct amdgpu_device *adev = ring->adev;
1037         struct amdgpu_ib ib;
1038         struct dma_fence *f = NULL;
1039         unsigned index;
1040         long r;
1041         u32 tmp = 0;
1042         u64 gpu_addr;
1043
1044         r = amdgpu_device_wb_get(adev, &index);
1045         if (r) {
1046                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1047                 return r;
1048         }
1049
1050         gpu_addr = adev->wb.gpu_addr + (index * 4);
1051         tmp = 0xCAFEDEAD;
1052         adev->wb.wb[index] = cpu_to_le32(tmp);
1053         memset(&ib, 0, sizeof(ib));
1054         r = amdgpu_ib_get(adev, NULL, 256,
1055                                         AMDGPU_IB_POOL_DIRECT, &ib);
1056         if (r) {
1057                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1058                 goto err0;
1059         }
1060
1061         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1062                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1063         ib.ptr[1] = lower_32_bits(gpu_addr);
1064         ib.ptr[2] = upper_32_bits(gpu_addr);
1065         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1066         ib.ptr[4] = 0xDEADBEEF;
1067         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1068         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1069         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1070         ib.length_dw = 8;
1071
1072         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1073         if (r)
1074                 goto err1;
1075
1076         r = dma_fence_wait_timeout(f, false, timeout);
1077         if (r == 0) {
1078                 DRM_ERROR("amdgpu: IB test timed out\n");
1079                 r = -ETIMEDOUT;
1080                 goto err1;
1081         } else if (r < 0) {
1082                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1083                 goto err1;
1084         }
1085         tmp = le32_to_cpu(adev->wb.wb[index]);
1086         if (tmp == 0xDEADBEEF)
1087                 r = 0;
1088         else
1089                 r = -EINVAL;
1090
1091 err1:
1092         amdgpu_ib_free(adev, &ib, NULL);
1093         dma_fence_put(f);
1094 err0:
1095         amdgpu_device_wb_free(adev, index);
1096         return r;
1097 }
1098
1099
1100 /**
1101  * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART
1102  *
1103  * @ib: indirect buffer to fill with commands
1104  * @pe: addr of the page entry
1105  * @src: src addr to copy from
1106  * @count: number of page entries to update
1107  *
1108  * Update PTEs by copying them from the GART using sDMA (NAVI10).
1109  */
1110 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib,
1111                                   uint64_t pe, uint64_t src,
1112                                   unsigned count)
1113 {
1114         unsigned bytes = count * 8;
1115
1116         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1117                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1118         ib->ptr[ib->length_dw++] = bytes - 1;
1119         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1120         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1121         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1122         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1123         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1124
1125 }
1126
1127 /**
1128  * sdma_v5_0_vm_write_pte - update PTEs by writing them manually
1129  *
1130  * @ib: indirect buffer to fill with commands
1131  * @pe: addr of the page entry
1132  * @value: dst addr to write into pe
1133  * @count: number of page entries to update
1134  * @incr: increase next addr by incr bytes
1135  *
1136  * Update PTEs by writing them manually using sDMA (NAVI10).
1137  */
1138 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1139                                    uint64_t value, unsigned count,
1140                                    uint32_t incr)
1141 {
1142         unsigned ndw = count * 2;
1143
1144         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1145                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1146         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1147         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1148         ib->ptr[ib->length_dw++] = ndw - 1;
1149         for (; ndw > 0; ndw -= 2) {
1150                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1151                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1152                 value += incr;
1153         }
1154 }
1155
1156 /**
1157  * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA
1158  *
1159  * @ib: indirect buffer to fill with commands
1160  * @pe: addr of the page entry
1161  * @addr: dst addr to write into pe
1162  * @count: number of page entries to update
1163  * @incr: increase next addr by incr bytes
1164  * @flags: access flags
1165  *
1166  * Update the page tables using sDMA (NAVI10).
1167  */
1168 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1169                                      uint64_t pe,
1170                                      uint64_t addr, unsigned count,
1171                                      uint32_t incr, uint64_t flags)
1172 {
1173         /* for physically contiguous pages (vram) */
1174         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1175         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1176         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1177         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1178         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1179         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1180         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1181         ib->ptr[ib->length_dw++] = incr; /* increment size */
1182         ib->ptr[ib->length_dw++] = 0;
1183         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1184 }
1185
1186 /**
1187  * sdma_v5_0_ring_pad_ib - pad the IB
1188  * @ring: amdgpu_ring structure holding ring information
1189  * @ib: indirect buffer to fill with padding
1190  *
1191  * Pad the IB with NOPs to a boundary multiple of 8.
1192  */
1193 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1194 {
1195         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1196         u32 pad_count;
1197         int i;
1198
1199         pad_count = (-ib->length_dw) & 0x7;
1200         for (i = 0; i < pad_count; i++)
1201                 if (sdma && sdma->burst_nop && (i == 0))
1202                         ib->ptr[ib->length_dw++] =
1203                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1204                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1205                 else
1206                         ib->ptr[ib->length_dw++] =
1207                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1208 }
1209
1210
1211 /**
1212  * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline
1213  *
1214  * @ring: amdgpu_ring pointer
1215  *
1216  * Make sure all previous operations are completed (CIK).
1217  */
1218 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1219 {
1220         uint32_t seq = ring->fence_drv.sync_seq;
1221         uint64_t addr = ring->fence_drv.gpu_addr;
1222
1223         /* wait for idle */
1224         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1225                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1226                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1227                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1228         amdgpu_ring_write(ring, addr & 0xfffffffc);
1229         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1230         amdgpu_ring_write(ring, seq); /* reference */
1231         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1232         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1233                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1234 }
1235
1236
1237 /**
1238  * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA
1239  *
1240  * @ring: amdgpu_ring pointer
1241  * @vmid: vmid number to use
1242  * @pd_addr: address
1243  *
1244  * Update the page table base and flush the VM TLB
1245  * using sDMA (NAVI10).
1246  */
1247 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1248                                          unsigned vmid, uint64_t pd_addr)
1249 {
1250         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1251 }
1252
1253 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring,
1254                                      uint32_t reg, uint32_t val)
1255 {
1256         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1257                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1258         amdgpu_ring_write(ring, reg);
1259         amdgpu_ring_write(ring, val);
1260 }
1261
1262 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1263                                          uint32_t val, uint32_t mask)
1264 {
1265         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1266                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1267                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1268         amdgpu_ring_write(ring, reg << 2);
1269         amdgpu_ring_write(ring, 0);
1270         amdgpu_ring_write(ring, val); /* reference */
1271         amdgpu_ring_write(ring, mask); /* mask */
1272         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1273                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1274 }
1275
1276 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1277                                                    uint32_t reg0, uint32_t reg1,
1278                                                    uint32_t ref, uint32_t mask)
1279 {
1280         amdgpu_ring_emit_wreg(ring, reg0, ref);
1281         /* wait for a cycle to reset vm_inv_eng*_ack */
1282         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1283         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1284 }
1285
1286 static int sdma_v5_0_early_init(void *handle)
1287 {
1288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289
1290         sdma_v5_0_set_ring_funcs(adev);
1291         sdma_v5_0_set_buffer_funcs(adev);
1292         sdma_v5_0_set_vm_pte_funcs(adev);
1293         sdma_v5_0_set_irq_funcs(adev);
1294
1295         return 0;
1296 }
1297
1298
1299 static int sdma_v5_0_sw_init(void *handle)
1300 {
1301         struct amdgpu_ring *ring;
1302         int r, i;
1303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1304
1305         /* SDMA trap event */
1306         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0,
1307                               SDMA0_5_0__SRCID__SDMA_TRAP,
1308                               &adev->sdma.trap_irq);
1309         if (r)
1310                 return r;
1311
1312         /* SDMA trap event */
1313         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1,
1314                               SDMA1_5_0__SRCID__SDMA_TRAP,
1315                               &adev->sdma.trap_irq);
1316         if (r)
1317                 return r;
1318
1319         r = sdma_v5_0_init_microcode(adev);
1320         if (r) {
1321                 DRM_ERROR("Failed to load sdma firmware!\n");
1322                 return r;
1323         }
1324
1325         for (i = 0; i < adev->sdma.num_instances; i++) {
1326                 ring = &adev->sdma.instance[i].ring;
1327                 ring->ring_obj = NULL;
1328                 ring->use_doorbell = true;
1329
1330                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1331                                 ring->use_doorbell?"true":"false");
1332
1333                 ring->doorbell_index = (i == 0) ?
1334                         (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset
1335                         : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset
1336
1337                 sprintf(ring->name, "sdma%d", i);
1338                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1339                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1340                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1341                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1342                 if (r)
1343                         return r;
1344         }
1345
1346         return r;
1347 }
1348
1349 static int sdma_v5_0_sw_fini(void *handle)
1350 {
1351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1352         int i;
1353
1354         for (i = 0; i < adev->sdma.num_instances; i++) {
1355                 release_firmware(adev->sdma.instance[i].fw);
1356                 adev->sdma.instance[i].fw = NULL;
1357
1358                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int sdma_v5_0_hw_init(void *handle)
1365 {
1366         int r;
1367         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1368
1369         sdma_v5_0_init_golden_registers(adev);
1370
1371         r = sdma_v5_0_start(adev);
1372
1373         return r;
1374 }
1375
1376 static int sdma_v5_0_hw_fini(void *handle)
1377 {
1378         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1379
1380         if (amdgpu_sriov_vf(adev))
1381                 return 0;
1382
1383         sdma_v5_0_ctx_switch_enable(adev, false);
1384         sdma_v5_0_enable(adev, false);
1385
1386         return 0;
1387 }
1388
1389 static int sdma_v5_0_suspend(void *handle)
1390 {
1391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1392
1393         return sdma_v5_0_hw_fini(adev);
1394 }
1395
1396 static int sdma_v5_0_resume(void *handle)
1397 {
1398         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1399
1400         return sdma_v5_0_hw_init(adev);
1401 }
1402
1403 static bool sdma_v5_0_is_idle(void *handle)
1404 {
1405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1406         u32 i;
1407
1408         for (i = 0; i < adev->sdma.num_instances; i++) {
1409                 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1410
1411                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1412                         return false;
1413         }
1414
1415         return true;
1416 }
1417
1418 static int sdma_v5_0_wait_for_idle(void *handle)
1419 {
1420         unsigned i;
1421         u32 sdma0, sdma1;
1422         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1423
1424         for (i = 0; i < adev->usec_timeout; i++) {
1425                 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1426                 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1427
1428                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1429                         return 0;
1430                 udelay(1);
1431         }
1432         return -ETIMEDOUT;
1433 }
1434
1435 static int sdma_v5_0_soft_reset(void *handle)
1436 {
1437         /* todo */
1438
1439         return 0;
1440 }
1441
1442 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring)
1443 {
1444         int i, r = 0;
1445         struct amdgpu_device *adev = ring->adev;
1446         u32 index = 0;
1447         u64 sdma_gfx_preempt;
1448
1449         amdgpu_sdma_get_index_from_ring(ring, &index);
1450         if (index == 0)
1451                 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT;
1452         else
1453                 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT;
1454
1455         /* assert preemption condition */
1456         amdgpu_ring_set_preempt_cond_exec(ring, false);
1457
1458         /* emit the trailing fence */
1459         ring->trail_seq += 1;
1460         amdgpu_ring_alloc(ring, 10);
1461         sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1462                                   ring->trail_seq, 0);
1463         amdgpu_ring_commit(ring);
1464
1465         /* assert IB preemption */
1466         WREG32(sdma_gfx_preempt, 1);
1467
1468         /* poll the trailing fence */
1469         for (i = 0; i < adev->usec_timeout; i++) {
1470                 if (ring->trail_seq ==
1471                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1472                         break;
1473                 udelay(1);
1474         }
1475
1476         if (i >= adev->usec_timeout) {
1477                 r = -EINVAL;
1478                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1479         }
1480
1481         /* deassert IB preemption */
1482         WREG32(sdma_gfx_preempt, 0);
1483
1484         /* deassert the preemption condition */
1485         amdgpu_ring_set_preempt_cond_exec(ring, true);
1486         return r;
1487 }
1488
1489 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
1490                                         struct amdgpu_irq_src *source,
1491                                         unsigned type,
1492                                         enum amdgpu_interrupt_state state)
1493 {
1494         u32 sdma_cntl;
1495
1496         if (!amdgpu_sriov_vf(adev)) {
1497                 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
1498                         sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1499                         sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1500
1501                 sdma_cntl = RREG32(reg_offset);
1502                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1503                                           state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1504                 WREG32(reg_offset, sdma_cntl);
1505         }
1506
1507         return 0;
1508 }
1509
1510 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
1511                                       struct amdgpu_irq_src *source,
1512                                       struct amdgpu_iv_entry *entry)
1513 {
1514         DRM_DEBUG("IH: SDMA trap\n");
1515         switch (entry->client_id) {
1516         case SOC15_IH_CLIENTID_SDMA0:
1517                 switch (entry->ring_id) {
1518                 case 0:
1519                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1520                         break;
1521                 case 1:
1522                         /* XXX compute */
1523                         break;
1524                 case 2:
1525                         /* XXX compute */
1526                         break;
1527                 case 3:
1528                         /* XXX page queue*/
1529                         break;
1530                 }
1531                 break;
1532         case SOC15_IH_CLIENTID_SDMA1:
1533                 switch (entry->ring_id) {
1534                 case 0:
1535                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1536                         break;
1537                 case 1:
1538                         /* XXX compute */
1539                         break;
1540                 case 2:
1541                         /* XXX compute */
1542                         break;
1543                 case 3:
1544                         /* XXX page queue*/
1545                         break;
1546                 }
1547                 break;
1548         }
1549         return 0;
1550 }
1551
1552 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1553                                               struct amdgpu_irq_src *source,
1554                                               struct amdgpu_iv_entry *entry)
1555 {
1556         return 0;
1557 }
1558
1559 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1560                                                        bool enable)
1561 {
1562         uint32_t data, def;
1563         int i;
1564
1565         for (i = 0; i < adev->sdma.num_instances; i++) {
1566                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1567                         /* Enable sdma clock gating */
1568                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1569                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1570                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1571                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1572                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1573                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1574                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1575                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1576                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1577                         if (def != data)
1578                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1579                 } else {
1580                         /* Disable sdma clock gating */
1581                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1582                         data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1583                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1584                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1585                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1586                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1587                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1588                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1589                                  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1590                         if (def != data)
1591                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1592                 }
1593         }
1594 }
1595
1596 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1597                                                       bool enable)
1598 {
1599         uint32_t data, def;
1600         int i;
1601
1602         for (i = 0; i < adev->sdma.num_instances; i++) {
1603                 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1604                         /* Enable sdma mem light sleep */
1605                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1606                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1607                         if (def != data)
1608                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1609
1610                 } else {
1611                         /* Disable sdma mem light sleep */
1612                         def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1613                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1614                         if (def != data)
1615                                 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1616
1617                 }
1618         }
1619 }
1620
1621 static int sdma_v5_0_set_clockgating_state(void *handle,
1622                                            enum amd_clockgating_state state)
1623 {
1624         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1625
1626         if (amdgpu_sriov_vf(adev))
1627                 return 0;
1628
1629         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1630         case IP_VERSION(5, 0, 0):
1631         case IP_VERSION(5, 0, 2):
1632         case IP_VERSION(5, 0, 5):
1633                 sdma_v5_0_update_medium_grain_clock_gating(adev,
1634                                 state == AMD_CG_STATE_GATE);
1635                 sdma_v5_0_update_medium_grain_light_sleep(adev,
1636                                 state == AMD_CG_STATE_GATE);
1637                 break;
1638         default:
1639                 break;
1640         }
1641
1642         return 0;
1643 }
1644
1645 static int sdma_v5_0_set_powergating_state(void *handle,
1646                                           enum amd_powergating_state state)
1647 {
1648         return 0;
1649 }
1650
1651 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags)
1652 {
1653         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1654         int data;
1655
1656         if (amdgpu_sriov_vf(adev))
1657                 *flags = 0;
1658
1659         /* AMD_CG_SUPPORT_SDMA_MGCG */
1660         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1661         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1662                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1663
1664         /* AMD_CG_SUPPORT_SDMA_LS */
1665         data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1666         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1667                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1668 }
1669
1670 const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
1671         .name = "sdma_v5_0",
1672         .early_init = sdma_v5_0_early_init,
1673         .late_init = NULL,
1674         .sw_init = sdma_v5_0_sw_init,
1675         .sw_fini = sdma_v5_0_sw_fini,
1676         .hw_init = sdma_v5_0_hw_init,
1677         .hw_fini = sdma_v5_0_hw_fini,
1678         .suspend = sdma_v5_0_suspend,
1679         .resume = sdma_v5_0_resume,
1680         .is_idle = sdma_v5_0_is_idle,
1681         .wait_for_idle = sdma_v5_0_wait_for_idle,
1682         .soft_reset = sdma_v5_0_soft_reset,
1683         .set_clockgating_state = sdma_v5_0_set_clockgating_state,
1684         .set_powergating_state = sdma_v5_0_set_powergating_state,
1685         .get_clockgating_state = sdma_v5_0_get_clockgating_state,
1686 };
1687
1688 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = {
1689         .type = AMDGPU_RING_TYPE_SDMA,
1690         .align_mask = 0xf,
1691         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1692         .support_64bit_ptrs = true,
1693         .secure_submission_supported = true,
1694         .vmhub = AMDGPU_GFXHUB_0,
1695         .get_rptr = sdma_v5_0_ring_get_rptr,
1696         .get_wptr = sdma_v5_0_ring_get_wptr,
1697         .set_wptr = sdma_v5_0_ring_set_wptr,
1698         .emit_frame_size =
1699                 5 + /* sdma_v5_0_ring_init_cond_exec */
1700                 6 + /* sdma_v5_0_ring_emit_hdp_flush */
1701                 3 + /* hdp_invalidate */
1702                 6 + /* sdma_v5_0_ring_emit_pipeline_sync */
1703                 /* sdma_v5_0_ring_emit_vm_flush */
1704                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1705                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 +
1706                 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */
1707         .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */
1708         .emit_ib = sdma_v5_0_ring_emit_ib,
1709         .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync,
1710         .emit_fence = sdma_v5_0_ring_emit_fence,
1711         .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync,
1712         .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush,
1713         .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush,
1714         .test_ring = sdma_v5_0_ring_test_ring,
1715         .test_ib = sdma_v5_0_ring_test_ib,
1716         .insert_nop = sdma_v5_0_ring_insert_nop,
1717         .pad_ib = sdma_v5_0_ring_pad_ib,
1718         .emit_wreg = sdma_v5_0_ring_emit_wreg,
1719         .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait,
1720         .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait,
1721         .init_cond_exec = sdma_v5_0_ring_init_cond_exec,
1722         .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec,
1723         .preempt_ib = sdma_v5_0_ring_preempt_ib,
1724 };
1725
1726 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev)
1727 {
1728         int i;
1729
1730         for (i = 0; i < adev->sdma.num_instances; i++) {
1731                 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs;
1732                 adev->sdma.instance[i].ring.me = i;
1733         }
1734 }
1735
1736 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = {
1737         .set = sdma_v5_0_set_trap_irq_state,
1738         .process = sdma_v5_0_process_trap_irq,
1739 };
1740
1741 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = {
1742         .process = sdma_v5_0_process_illegal_inst_irq,
1743 };
1744
1745 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev)
1746 {
1747         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1748                                         adev->sdma.num_instances;
1749         adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs;
1750         adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs;
1751 }
1752
1753 /**
1754  * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine
1755  *
1756  * @ib: indirect buffer to copy to
1757  * @src_offset: src GPU address
1758  * @dst_offset: dst GPU address
1759  * @byte_count: number of bytes to xfer
1760  * @tmz: if a secure copy should be used
1761  *
1762  * Copy GPU buffers using the DMA engine (NAVI10).
1763  * Used by the amdgpu ttm implementation to move pages if
1764  * registered as the asic copy callback.
1765  */
1766 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib,
1767                                        uint64_t src_offset,
1768                                        uint64_t dst_offset,
1769                                        uint32_t byte_count,
1770                                        bool tmz)
1771 {
1772         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1773                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1774                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1775         ib->ptr[ib->length_dw++] = byte_count - 1;
1776         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1777         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1778         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1779         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1780         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1781 }
1782
1783 /**
1784  * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine
1785  *
1786  * @ib: indirect buffer to fill
1787  * @src_data: value to write to buffer
1788  * @dst_offset: dst GPU address
1789  * @byte_count: number of bytes to xfer
1790  *
1791  * Fill GPU buffers using the DMA engine (NAVI10).
1792  */
1793 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib,
1794                                        uint32_t src_data,
1795                                        uint64_t dst_offset,
1796                                        uint32_t byte_count)
1797 {
1798         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1799         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1800         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1801         ib->ptr[ib->length_dw++] = src_data;
1802         ib->ptr[ib->length_dw++] = byte_count - 1;
1803 }
1804
1805 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
1806         .copy_max_bytes = 0x400000,
1807         .copy_num_dw = 7,
1808         .emit_copy_buffer = sdma_v5_0_emit_copy_buffer,
1809
1810         .fill_max_bytes = 0x400000,
1811         .fill_num_dw = 5,
1812         .emit_fill_buffer = sdma_v5_0_emit_fill_buffer,
1813 };
1814
1815 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
1816 {
1817         if (adev->mman.buffer_funcs == NULL) {
1818                 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
1819                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1820         }
1821 }
1822
1823 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
1824         .copy_pte_num_dw = 7,
1825         .copy_pte = sdma_v5_0_vm_copy_pte,
1826         .write_pte = sdma_v5_0_vm_write_pte,
1827         .set_pte_pde = sdma_v5_0_vm_set_pte_pde,
1828 };
1829
1830 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1831 {
1832         unsigned i;
1833
1834         if (adev->vm_manager.vm_pte_funcs == NULL) {
1835                 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
1836                 for (i = 0; i < adev->sdma.num_instances; i++) {
1837                         adev->vm_manager.vm_pte_scheds[i] =
1838                                 &adev->sdma.instance[i].ring.sched;
1839                 }
1840                 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1841         }
1842 }
1843
1844 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
1845         .type = AMD_IP_BLOCK_TYPE_SDMA,
1846         .major = 5,
1847         .minor = 0,
1848         .rev = 0,
1849         .funcs = &sdma_v5_0_ip_funcs,
1850 };