1 /* smp.c: Sparc SMP support.
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/threads.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/delay.h>
23 #include <linux/profile.h>
24 #include <linux/cpu.h>
26 #include <asm/ptrace.h>
27 #include <linux/atomic.h>
31 #include <asm/pgalloc.h>
32 #include <asm/pgtable.h>
33 #include <asm/oplib.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/cpudata.h>
37 #include <asm/timer.h>
43 volatile unsigned long cpu_callin_map[NR_CPUS] = {0,};
45 cpumask_t smp_commenced_mask = CPU_MASK_NONE;
47 const struct sparc32_ipi_ops *sparc32_ipi_ops;
49 /* The only guaranteed locking primitive available on all Sparc
50 * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically
51 * places the current byte at the effective address into dest_reg and
52 * places 0xff there afterwards. Pretty lame locking primitive
53 * compared to the Alpha and the Intel no? Most Sparcs have 'swap'
54 * instruction which is much better...
57 void smp_store_cpu_info(int id)
62 cpu_data(id).udelay_val = loops_per_jiffy;
64 cpu_find_by_mid(id, &cpu_node);
65 cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
66 "clock-frequency", 0);
67 cpu_data(id).prom_node = cpu_node;
68 mid = cpu_get_hwmid(cpu_node);
71 printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08x", id, cpu_node);
74 cpu_data(id).mid = mid;
77 void __init smp_cpus_done(unsigned int max_cpus)
79 unsigned long bogosum = 0;
82 for_each_online_cpu(cpu) {
84 bogosum += cpu_data(cpu).udelay_val;
87 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
88 num, bogosum/(500000/HZ),
89 (bogosum/(5000/HZ))%100);
91 switch(sparc_cpu_model) {
110 printk("UNKNOWN!\n");
118 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
119 panic("SMP bolixed\n");
122 struct linux_prom_registers smp_penguin_ctable = { 0 };
124 void smp_send_reschedule(int cpu)
127 * CPU model dependent way of implementing IPI generation targeting
128 * a single CPU. The trap handler needs only to do trap entry/return
131 sparc32_ipi_ops->resched(cpu);
134 void smp_send_stop(void)
138 void arch_send_call_function_single_ipi(int cpu)
140 /* trigger one IPI single call on one CPU */
141 sparc32_ipi_ops->single(cpu);
144 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
148 /* trigger IPI mask call on each CPU */
149 for_each_cpu(cpu, mask)
150 sparc32_ipi_ops->mask_one(cpu);
153 void smp_resched_interrupt(void)
157 local_cpu_data().irq_resched_count++;
159 /* re-schedule routine called by interrupt return code. */
162 void smp_call_function_single_interrupt(void)
165 generic_smp_call_function_single_interrupt();
166 local_cpu_data().irq_call_count++;
170 void smp_call_function_interrupt(void)
173 generic_smp_call_function_interrupt();
174 local_cpu_data().irq_call_count++;
178 int setup_profiling_timer(unsigned int multiplier)
183 void __init smp_prepare_cpus(unsigned int max_cpus)
187 printk("Entering SMP Mode...\n");
190 for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) {
191 if (cpuid >= NR_CPUS)
194 /* i = number of cpus */
195 if (extra && max_cpus > i - extra)
196 printk("Warning: NR_CPUS is too low to start all cpus\n");
198 smp_store_cpu_info(boot_cpu_id);
200 switch(sparc_cpu_model) {
219 printk("UNKNOWN!\n");
225 /* Set this up early so that things like the scheduler can init
226 * properly. We use the same cpu mask for both the present and
229 void __init smp_setup_cpu_possible_map(void)
234 while (!cpu_find_by_instance(instance, NULL, &mid)) {
236 set_cpu_possible(mid, true);
237 set_cpu_present(mid, true);
243 void __init smp_prepare_boot_cpu(void)
245 int cpuid = hard_smp_processor_id();
247 if (cpuid >= NR_CPUS) {
248 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
252 printk("boot cpu id != 0, this could work but is untested\n");
254 current_thread_info()->cpu = cpuid;
255 set_cpu_online(cpuid, true);
256 set_cpu_possible(cpuid, true);
259 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
263 switch(sparc_cpu_model) {
265 ret = smp4m_boot_one_cpu(cpu, tidle);
268 ret = smp4d_boot_one_cpu(cpu, tidle);
271 ret = leon_boot_one_cpu(cpu, tidle);
282 printk("UNKNOWN!\n");
288 cpumask_set_cpu(cpu, &smp_commenced_mask);
289 while (!cpu_online(cpu))
295 static void arch_cpu_pre_starting(void *arg)
297 local_ops->cache_all();
298 local_ops->tlb_all();
300 switch(sparc_cpu_model) {
302 sun4m_cpu_pre_starting(arg);
305 sun4d_cpu_pre_starting(arg);
308 leon_cpu_pre_starting(arg);
315 static void arch_cpu_pre_online(void *arg)
317 unsigned int cpuid = hard_smp_processor_id();
319 register_percpu_ce(cpuid);
322 smp_store_cpu_info(cpuid);
324 local_ops->cache_all();
325 local_ops->tlb_all();
327 switch(sparc_cpu_model) {
329 sun4m_cpu_pre_online(arg);
332 sun4d_cpu_pre_online(arg);
335 leon_cpu_pre_online(arg);
342 static void sparc_start_secondary(void *arg)
347 * SMP booting is extremely fragile in some architectures. So run
348 * the cpu initialization code first before anything else.
350 arch_cpu_pre_starting(arg);
353 cpu = smp_processor_id();
355 /* Invoke the CPU_STARTING notifier callbacks */
356 notify_cpu_starting(cpu);
358 arch_cpu_pre_online(arg);
360 /* Set the CPU in the cpu_online_mask */
361 set_cpu_online(cpu, true);
363 /* Enable local interrupts now */
367 cpu_startup_entry(CPUHP_ONLINE);
369 /* We should never reach here! */
373 void smp_callin(void)
375 sparc_start_secondary(NULL);
378 void smp_bogo(struct seq_file *m)
382 for_each_online_cpu(i) {
384 "Cpu%dBogo\t: %lu.%02lu\n",
386 cpu_data(i).udelay_val/(500000/HZ),
387 (cpu_data(i).udelay_val/(5000/HZ))%100);
391 void smp_info(struct seq_file *m)
395 seq_printf(m, "State:\n");
396 for_each_online_cpu(i)
397 seq_printf(m, "CPU%d\t\t: online\n", i);