drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/pagemap.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  34                        u32 ip_instance, u32 ring,
  35                        struct amdgpu_ring **out_ring)
  36 {
  37         /* Right now all IPs have only one instance - multiple rings. */
  38         if (ip_instance != 0) {
  39                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  40                 return -EINVAL;
  41         }
  42
  43         switch (ip_type) {
  44         default:
  45                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  46                 return -EINVAL;
  47         case AMDGPU_HW_IP_GFX:
  48                 if (ring < adev->gfx.num_gfx_rings) {
  49                         *out_ring = &adev->gfx.gfx_ring[ring];
  50                 } else {
  51                         DRM_ERROR("only %d gfx rings are supported now\n",
  52                                   adev->gfx.num_gfx_rings);
  53                         return -EINVAL;
  54                 }
  55                 break;
  56         case AMDGPU_HW_IP_COMPUTE:
  57                 if (ring < adev->gfx.num_compute_rings) {
  58                         *out_ring = &adev->gfx.compute_ring[ring];
  59                 } else {
  60                         DRM_ERROR("only %d compute rings are supported now\n",
  61                                   adev->gfx.num_compute_rings);
  62                         return -EINVAL;
  63                 }
  64                 break;
  65         case AMDGPU_HW_IP_DMA:
  66                 if (ring < adev->sdma.num_instances) {
  67                         *out_ring = &adev->sdma.instance[ring].ring;
  68                 } else {
  69                         DRM_ERROR("only %d SDMA rings are supported\n",
  70                                   adev->sdma.num_instances);
  71                         return -EINVAL;
  72                 }
  73                 break;
  74         case AMDGPU_HW_IP_UVD:
  75                 *out_ring = &adev->uvd.ring;
  76                 break;
  77         case AMDGPU_HW_IP_VCE:
  78                 if (ring < 2){
  79                         *out_ring = &adev->vce.ring[ring];
  80                 } else {
  81                         DRM_ERROR("only two VCE rings are supported\n");
  82                         return -EINVAL;
  83                 }
  84                 break;
  85         }
  86         return 0;
  87 }
  88
  89 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  90                                       struct drm_amdgpu_cs_chunk_fence *data,
  91                                       uint32_t *offset)
  92 {
  93         struct drm_gem_object *gobj;
  94
  95         gobj = drm_gem_object_lookup(p->filp, data->handle);
  96         if (gobj == NULL)
  97                 return -EINVAL;
  98
  99         p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
 100         p->uf_entry.priority = 0;
 101         p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
 102         p->uf_entry.tv.shared = true;
 103         p->uf_entry.user_pages = NULL;
 104         *offset = data->offset;
 105
 106         drm_gem_object_unreference_unlocked(gobj);
 107
 108         if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
 109                 amdgpu_bo_unref(&p->uf_entry.robj);
 110                 return -EINVAL;
 111         }
 112
 113         return 0;
 114 }
 115
 116 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 117 {
 118         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 119         struct amdgpu_vm *vm = &fpriv->vm;
 120         union drm_amdgpu_cs *cs = data;
 121         uint64_t *chunk_array_user;
 122         uint64_t *chunk_array;
 123         unsigned size, num_ibs = 0;
 124         uint32_t uf_offset = 0;
 125         int i;
 126         int ret;
 127
 128         if (cs->in.num_chunks == 0)
 129                 return 0;
 130
 131         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 132         if (!chunk_array)
 133                 return -ENOMEM;
 134
 135         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 136         if (!p->ctx) {
 137                 ret = -EINVAL;
 138                 goto free_chunk;
 139         }
 140
 141         /* get chunks */
 142         chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks);
 143         if (copy_from_user(chunk_array, chunk_array_user,
 144                            sizeof(uint64_t)*cs->in.num_chunks)) {
 145                 ret = -EFAULT;
 146                 goto put_ctx;
 147         }
 148
 149         p->nchunks = cs->in.num_chunks;
 150         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 151                             GFP_KERNEL);
 152         if (!p->chunks) {
 153                 ret = -ENOMEM;
 154                 goto put_ctx;
 155         }
 156
 157         for (i = 0; i < p->nchunks; i++) {
 158                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 159                 struct drm_amdgpu_cs_chunk user_chunk;
 160                 uint32_t __user *cdata;
 161
 162                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 163                 if (copy_from_user(&user_chunk, chunk_ptr,
 164                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 165                         ret = -EFAULT;
 166                         i--;
 167                         goto free_partial_kdata;
 168                 }
 169                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 170                 p->chunks[i].length_dw = user_chunk.length_dw;
 171
 172                 size = p->chunks[i].length_dw;
 173                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 174
 175                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 176                 if (p->chunks[i].kdata == NULL) {
 177                         ret = -ENOMEM;
 178                         i--;
 179                         goto free_partial_kdata;
 180                 }
 181                 size *= sizeof(uint32_t);
 182                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 183                         ret = -EFAULT;
 184                         goto free_partial_kdata;
 185                 }
 186
 187                 switch (p->chunks[i].chunk_id) {
 188                 case AMDGPU_CHUNK_ID_IB:
 189                         ++num_ibs;
 190                         break;
 191
 192                 case AMDGPU_CHUNK_ID_FENCE:
 193                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 194                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 195                                 ret = -EINVAL;
 196                                 goto free_partial_kdata;
 197                         }
 198
 199                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 200                                                          &uf_offset);
 201                         if (ret)
 202                                 goto free_partial_kdata;
 203
 204                         break;
 205
 206                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 207                         break;
 208
 209                 default:
 210                         ret = -EINVAL;
 211                         goto free_partial_kdata;
 212                 }
 213         }
 214
 215         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 216         if (ret)
 217                 goto free_all_kdata;
 218
 219         if (p->uf_entry.robj)
 220                 p->job->uf_addr = uf_offset;
 221         kfree(chunk_array);
 222         return 0;
 223
 224 free_all_kdata:
 225         i = p->nchunks - 1;
 226 free_partial_kdata:
 227         for (; i >= 0; i--)
 228                 drm_free_large(p->chunks[i].kdata);
 229         kfree(p->chunks);
 230 put_ctx:
 231         amdgpu_ctx_put(p->ctx);
 232 free_chunk:
 233         kfree(chunk_array);
 234
 235         return ret;
 236 }
 237
 238 /* Returns how many bytes TTM can move per IB.
 239  */
 240 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 241 {
 242         u64 real_vram_size = adev->mc.real_vram_size;
 243         u64 vram_usage = atomic64_read(&adev->vram_usage);
 244
 245         /* This function is based on the current VRAM usage.
 246          *
 247          * - If all of VRAM is free, allow relocating the number of bytes that
 248          *   is equal to 1/4 of the size of VRAM for this IB.
 249
 250          * - If more than one half of VRAM is occupied, only allow relocating
 251          *   1 MB of data for this IB.
 252          *
 253          * - From 0 to one half of used VRAM, the threshold decreases
 254          *   linearly.
 255          *         __________________
 256          * 1/4 of -|\               |
 257          * VRAM    | \              |
 258          *         |  \             |
 259          *         |   \            |
 260          *         |    \           |
 261          *         |     \          |
 262          *         |      \         |
 263          *         |       \________|1 MB
 264          *         |----------------|
 265          *    VRAM 0 %             100 %
 266          *         used            used
 267          *
 268          * Note: It's a threshold, not a limit. The threshold must be crossed
 269          * for buffer relocations to stop, so any buffer of an arbitrary size
 270          * can be moved as long as the threshold isn't crossed before
 271          * the relocation takes place. We don't want to disable buffer
 272          * relocations completely.
 273          *
 274          * The idea is that buffers should be placed in VRAM at creation time
 275          * and TTM should only do a minimum number of relocations during
 276          * command submission. In practice, you need to submit at least
 277          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 278          *
 279          * Also, things can get pretty crazy under memory pressure and actual
 280          * VRAM usage can change a lot, so playing safe even at 50% does
 281          * consistently increase performance.
 282          */
 283
 284         u64 half_vram = real_vram_size >> 1;
 285         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 286         u64 bytes_moved_threshold = half_free_vram >> 1;
 287         return max(bytes_moved_threshold, 1024*1024ull);
 288 }
 289
 290 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 291                                  struct amdgpu_bo *bo)
 292 {
 293         u64 initial_bytes_moved;
 294         uint32_t domain;
 295         int r;
 296
 297         if (bo->pin_count)
 298                 return 0;
 299
 300         /* Avoid moving this one if we have moved too many buffers
 301          * for this IB already.
 302          *
 303          * Note that this allows moving at least one buffer of
 304          * any size, because it doesn't take the current "bo"
 305          * into account. We don't want to disallow buffer moves
 306          * completely.
 307          */
 308         if (p->bytes_moved <= p->bytes_moved_threshold)
 309                 domain = bo->prefered_domains;
 310         else
 311                 domain = bo->allowed_domains;
 312
 313 retry:
 314         amdgpu_ttm_placement_from_domain(bo, domain);
 315         initial_bytes_moved = atomic64_read(&bo->adev->num_bytes_moved);
 316         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 317         p->bytes_moved += atomic64_read(&bo->adev->num_bytes_moved) -
 318                 initial_bytes_moved;
 319
 320         if (unlikely(r)) {
 321                 if (r != -ERESTARTSYS && domain != bo->allowed_domains) {
 322                         domain = bo->allowed_domains;
 323                         goto retry;
 324                 }
 325         }
 326
 327         return r;
 328 }
 329
 330 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 331                             struct list_head *validated)
 332 {
 333         struct amdgpu_bo_list_entry *lobj;
 334         int r;
 335
 336         list_for_each_entry(lobj, validated, tv.head) {
 337                 struct amdgpu_bo *bo = lobj->robj;
 338                 bool binding_userptr = false;
 339                 struct mm_struct *usermm;
 340
 341                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 342                 if (usermm && usermm != current->mm)
 343                         return -EPERM;
 344
 345                 /* Check if we have user pages and nobody bound the BO already */
 346                 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
 347                         size_t size = sizeof(struct page *);
 348
 349                         size *= bo->tbo.ttm->num_pages;
 350                         memcpy(bo->tbo.ttm->pages, lobj->user_pages, size);
 351                         binding_userptr = true;
 352                 }
 353
 354                 r = amdgpu_cs_bo_validate(p, bo);
 355                 if (r)
 356                         return r;
 357                 if (bo->shadow) {
 358                         r = amdgpu_cs_bo_validate(p, bo);
 359                         if (r)
 360                                 return r;
 361                 }
 362
 363                 if (binding_userptr) {
 364                         drm_free_large(lobj->user_pages);
 365                         lobj->user_pages = NULL;
 366                 }
 367         }
 368         return 0;
 369 }
 370
 371 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 372                                 union drm_amdgpu_cs *cs)
 373 {
 374         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 375         struct amdgpu_bo_list_entry *e;
 376         struct list_head duplicates;
 377         bool need_mmap_lock = false;
 378         unsigned i, tries = 10;
 379         int r;
 380
 381         INIT_LIST_HEAD(&p->validated);
 382
 383         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 384         if (p->bo_list) {
 385                 need_mmap_lock = p->bo_list->first_userptr !=
 386                         p->bo_list->num_entries;
 387                 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 388         }
 389
 390         INIT_LIST_HEAD(&duplicates);
 391         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 392
 393         if (p->uf_entry.robj)
 394                 list_add(&p->uf_entry.tv.head, &p->validated);
 395
 396         if (need_mmap_lock)
 397                 down_read(&current->mm->mmap_sem);
 398
 399         while (1) {
 400                 struct list_head need_pages;
 401                 unsigned i;
 402
 403                 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 404                                            &duplicates);
 405                 if (unlikely(r != 0)) {
 406                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 407                         goto error_free_pages;
 408                 }
 409
 410                 /* Without a BO list we don't have userptr BOs */
 411                 if (!p->bo_list)
 412                         break;
 413
 414                 INIT_LIST_HEAD(&need_pages);
 415                 for (i = p->bo_list->first_userptr;
 416                      i < p->bo_list->num_entries; ++i) {
 417
 418                         e = &p->bo_list->array[i];
 419
 420                         if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
 421                                  &e->user_invalidated) && e->user_pages) {
 422
 423                                 /* We acquired a page array, but somebody
 424                                  * invalidated it. Free it an try again
 425                                  */
 426                                 release_pages(e->user_pages,
 427                                               e->robj->tbo.ttm->num_pages,
 428                                               false);
 429                                 drm_free_large(e->user_pages);
 430                                 e->user_pages = NULL;
 431                         }
 432
 433                         if (e->robj->tbo.ttm->state != tt_bound &&
 434                             !e->user_pages) {
 435                                 list_del(&e->tv.head);
 436                                 list_add(&e->tv.head, &need_pages);
 437
 438                                 amdgpu_bo_unreserve(e->robj);
 439                         }
 440                 }
 441
 442                 if (list_empty(&need_pages))
 443                         break;
 444
 445                 /* Unreserve everything again. */
 446                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 447
 448                 /* We tried too many times, just abort */
 449                 if (!--tries) {
 450                         r = -EDEADLK;
 451                         DRM_ERROR("deadlock in %s\n", __func__);
 452                         goto error_free_pages;
 453                 }
 454
 455                 /* Fill the page arrays for all useptrs. */
 456                 list_for_each_entry(e, &need_pages, tv.head) {
 457                         struct ttm_tt *ttm = e->robj->tbo.ttm;
 458
 459                         e->user_pages = drm_calloc_large(ttm->num_pages,
 460                                                          sizeof(struct page*));
 461                         if (!e->user_pages) {
 462                                 r = -ENOMEM;
 463                                 DRM_ERROR("calloc failure in %s\n", __func__);
 464                                 goto error_free_pages;
 465                         }
 466
 467                         r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
 468                         if (r) {
 469                                 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
 470                                 drm_free_large(e->user_pages);
 471                                 e->user_pages = NULL;
 472                                 goto error_free_pages;
 473                         }
 474                 }
 475
 476                 /* And try again. */
 477                 list_splice(&need_pages, &p->validated);
 478         }
 479
 480         amdgpu_vm_get_pt_bos(p->adev, &fpriv->vm, &duplicates);
 481
 482         p->bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(p->adev);
 483         p->bytes_moved = 0;
 484
 485         r = amdgpu_cs_list_validate(p, &duplicates);
 486         if (r) {
 487                 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
 488                 goto error_validate;
 489         }
 490
 491         r = amdgpu_cs_list_validate(p, &p->validated);
 492         if (r) {
 493                 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
 494                 goto error_validate;
 495         }
 496
 497         fpriv->vm.last_eviction_counter =
 498                 atomic64_read(&p->adev->num_evictions);
 499
 500         if (p->bo_list) {
 501                 struct amdgpu_bo *gds = p->bo_list->gds_obj;
 502                 struct amdgpu_bo *gws = p->bo_list->gws_obj;
 503                 struct amdgpu_bo *oa = p->bo_list->oa_obj;
 504                 struct amdgpu_vm *vm = &fpriv->vm;
 505                 unsigned i;
 506
 507                 for (i = 0; i < p->bo_list->num_entries; i++) {
 508                         struct amdgpu_bo *bo = p->bo_list->array[i].robj;
 509
 510                         p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
 511                 }
 512
 513                 if (gds) {
 514                         p->job->gds_base = amdgpu_bo_gpu_offset(gds);
 515                         p->job->gds_size = amdgpu_bo_size(gds);
 516                 }
 517                 if (gws) {
 518                         p->job->gws_base = amdgpu_bo_gpu_offset(gws);
 519                         p->job->gws_size = amdgpu_bo_size(gws);
 520                 }
 521                 if (oa) {
 522                         p->job->oa_base = amdgpu_bo_gpu_offset(oa);
 523                         p->job->oa_size = amdgpu_bo_size(oa);
 524                 }
 525         }
 526
 527         if (p->uf_entry.robj)
 528                 p->job->uf_addr += amdgpu_bo_gpu_offset(p->uf_entry.robj);
 529
 530 error_validate:
 531         if (r) {
 532                 amdgpu_vm_move_pt_bos_in_lru(p->adev, &fpriv->vm);
 533                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 534         }
 535
 536 error_free_pages:
 537
 538         if (need_mmap_lock)
 539                 up_read(&current->mm->mmap_sem);
 540
 541         if (p->bo_list) {
 542                 for (i = p->bo_list->first_userptr;
 543                      i < p->bo_list->num_entries; ++i) {
 544                         e = &p->bo_list->array[i];
 545
 546                         if (!e->user_pages)
 547                                 continue;
 548
 549                         release_pages(e->user_pages,
 550                                       e->robj->tbo.ttm->num_pages,
 551                                       false);
 552                         drm_free_large(e->user_pages);
 553                 }
 554         }
 555
 556         return r;
 557 }
 558
 559 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 560 {
 561         struct amdgpu_bo_list_entry *e;
 562         int r;
 563
 564         list_for_each_entry(e, &p->validated, tv.head) {
 565                 struct reservation_object *resv = e->robj->tbo.resv;
 566                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
 567
 568                 if (r)
 569                         return r;
 570         }
 571         return 0;
 572 }
 573
 574 /**
 575  * cs_parser_fini() - clean parser states
 576  * @parser:     parser structure holding parsing context.
 577  * @error:      error number
 578  *
 579  * If error is set than unvalidate buffer, otherwise just free memory
 580  * used by parsing context.
 581  **/
 582 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 583 {
 584         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 585         unsigned i;
 586
 587         if (!error) {
 588                 amdgpu_vm_move_pt_bos_in_lru(parser->adev, &fpriv->vm);
 589
 590                 ttm_eu_fence_buffer_objects(&parser->ticket,
 591                                             &parser->validated,
 592                                             parser->fence);
 593         } else if (backoff) {
 594                 ttm_eu_backoff_reservation(&parser->ticket,
 595                                            &parser->validated);
 596         }
 597         fence_put(parser->fence);
 598
 599         if (parser->ctx)
 600                 amdgpu_ctx_put(parser->ctx);
 601         if (parser->bo_list)
 602                 amdgpu_bo_list_put(parser->bo_list);
 603
 604         for (i = 0; i < parser->nchunks; i++)
 605                 drm_free_large(parser->chunks[i].kdata);
 606         kfree(parser->chunks);
 607         if (parser->job)
 608                 amdgpu_job_free(parser->job);
 609         amdgpu_bo_unref(&parser->uf_entry.robj);
 610 }
 611
 612 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 613                                    struct amdgpu_vm *vm)
 614 {
 615         struct amdgpu_device *adev = p->adev;
 616         struct amdgpu_bo_va *bo_va;
 617         struct amdgpu_bo *bo;
 618         int i, r;
 619
 620         r = amdgpu_vm_update_page_directory(adev, vm);
 621         if (r)
 622                 return r;
 623
 624         r = amdgpu_sync_fence(adev, &p->job->sync, vm->page_directory_fence);
 625         if (r)
 626                 return r;
 627
 628         r = amdgpu_vm_clear_freed(adev, vm);
 629         if (r)
 630                 return r;
 631
 632         if (p->bo_list) {
 633                 for (i = 0; i < p->bo_list->num_entries; i++) {
 634                         struct fence *f;
 635
 636                         /* ignore duplicates */
 637                         bo = p->bo_list->array[i].robj;
 638                         if (!bo)
 639                                 continue;
 640
 641                         bo_va = p->bo_list->array[i].bo_va;
 642                         if (bo_va == NULL)
 643                                 continue;
 644
 645                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 646                         if (r)
 647                                 return r;
 648
 649                         f = bo_va->last_pt_update;
 650                         r = amdgpu_sync_fence(adev, &p->job->sync, f);
 651                         if (r)
 652                                 return r;
 653                 }
 654
 655         }
 656
 657         r = amdgpu_vm_clear_invalids(adev, vm, &p->job->sync);
 658
 659         if (amdgpu_vm_debug && p->bo_list) {
 660                 /* Invalidate all BOs to test for userspace bugs */
 661                 for (i = 0; i < p->bo_list->num_entries; i++) {
 662                         /* ignore duplicates */
 663                         bo = p->bo_list->array[i].robj;
 664                         if (!bo)
 665                                 continue;
 666
 667                         amdgpu_vm_bo_invalidate(adev, bo);
 668                 }
 669         }
 670
 671         return r;
 672 }
 673
 674 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 675                                  struct amdgpu_cs_parser *p)
 676 {
 677         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 678         struct amdgpu_vm *vm = &fpriv->vm;
 679         struct amdgpu_ring *ring = p->job->ring;
 680         int i, r;
 681
 682         /* Only for UVD/VCE VM emulation */
 683         if (ring->funcs->parse_cs) {
 684                 p->job->vm = NULL;
 685                 for (i = 0; i < p->job->num_ibs; i++) {
 686                         r = amdgpu_ring_parse_cs(ring, p, i);
 687                         if (r)
 688                                 return r;
 689                 }
 690         } else {
 691                 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
 692
 693                 r = amdgpu_bo_vm_update_pte(p, vm);
 694                 if (r)
 695                         return r;
 696         }
 697
 698         return amdgpu_cs_sync_rings(p);
 699 }
 700
 701 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 702 {
 703         if (r == -EDEADLK) {
 704                 r = amdgpu_gpu_reset(adev);
 705                 if (!r)
 706                         r = -EAGAIN;
 707         }
 708         return r;
 709 }
 710
 711 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 712                              struct amdgpu_cs_parser *parser)
 713 {
 714         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 715         struct amdgpu_vm *vm = &fpriv->vm;
 716         int i, j;
 717         int r;
 718
 719         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 720                 struct amdgpu_cs_chunk *chunk;
 721                 struct amdgpu_ib *ib;
 722                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 723                 struct amdgpu_ring *ring;
 724
 725                 chunk = &parser->chunks[i];
 726                 ib = &parser->job->ibs[j];
 727                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 728
 729                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 730                         continue;
 731
 732                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 733                                        chunk_ib->ip_instance, chunk_ib->ring,
 734                                        &ring);
 735                 if (r)
 736                         return r;
 737
 738                 if (parser->job->ring && parser->job->ring != ring)
 739                         return -EINVAL;
 740
 741                 parser->job->ring = ring;
 742
 743                 if (ring->funcs->parse_cs) {
 744                         struct amdgpu_bo_va_mapping *m;
 745                         struct amdgpu_bo *aobj = NULL;
 746                         uint64_t offset;
 747                         uint8_t *kptr;
 748
 749                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 750                                                    &aobj);
 751                         if (!aobj) {
 752                                 DRM_ERROR("IB va_start is invalid\n");
 753                                 return -EINVAL;
 754                         }
 755
 756                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 757                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 758                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 759                                 return -EINVAL;
 760                         }
 761
 762                         /* the IB should be reserved at this point */
 763                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 764                         if (r) {
 765                                 return r;
 766                         }
 767
 768                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 769                         kptr += chunk_ib->va_start - offset;
 770
 771                         r =  amdgpu_ib_get(adev, NULL, chunk_ib->ib_bytes, ib);
 772                         if (r) {
 773                                 DRM_ERROR("Failed to get ib !\n");
 774                                 return r;
 775                         }
 776
 777                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 778                         amdgpu_bo_kunmap(aobj);
 779                 } else {
 780                         r =  amdgpu_ib_get(adev, vm, 0, ib);
 781                         if (r) {
 782                                 DRM_ERROR("Failed to get ib !\n");
 783                                 return r;
 784                         }
 785
 786                         ib->gpu_addr = chunk_ib->va_start;
 787                 }
 788
 789                 ib->length_dw = chunk_ib->ib_bytes / 4;
 790                 ib->flags = chunk_ib->flags;
 791                 j++;
 792         }
 793
 794         /* UVD & VCE fw doesn't support user fences */
 795         if (parser->job->uf_addr && (
 796             parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||
 797             parser->job->ring->type == AMDGPU_RING_TYPE_VCE))
 798                 return -EINVAL;
 799
 800         return 0;
 801 }
 802
 803 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 804                                   struct amdgpu_cs_parser *p)
 805 {
 806         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 807         int i, j, r;
 808
 809         for (i = 0; i < p->nchunks; ++i) {
 810                 struct drm_amdgpu_cs_chunk_dep *deps;
 811                 struct amdgpu_cs_chunk *chunk;
 812                 unsigned num_deps;
 813
 814                 chunk = &p->chunks[i];
 815
 816                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 817                         continue;
 818
 819                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 820                 num_deps = chunk->length_dw * 4 /
 821                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 822
 823                 for (j = 0; j < num_deps; ++j) {
 824                         struct amdgpu_ring *ring;
 825                         struct amdgpu_ctx *ctx;
 826                         struct fence *fence;
 827
 828                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 829                                                deps[j].ip_instance,
 830                                                deps[j].ring, &ring);
 831                         if (r)
 832                                 return r;
 833
 834                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 835                         if (ctx == NULL)
 836                                 return -EINVAL;
 837
 838                         fence = amdgpu_ctx_get_fence(ctx, ring,
 839                                                      deps[j].handle);
 840                         if (IS_ERR(fence)) {
 841                                 r = PTR_ERR(fence);
 842                                 amdgpu_ctx_put(ctx);
 843                                 return r;
 844
 845                         } else if (fence) {
 846                                 r = amdgpu_sync_fence(adev, &p->job->sync,
 847                                                       fence);
 848                                 fence_put(fence);
 849                                 amdgpu_ctx_put(ctx);
 850                                 if (r)
 851                                         return r;
 852                         }
 853                 }
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
 860                             union drm_amdgpu_cs *cs)
 861 {
 862         struct amdgpu_ring *ring = p->job->ring;
 863         struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
 864         struct amdgpu_job *job;
 865         int r;
 866
 867         job = p->job;
 868         p->job = NULL;
 869
 870         r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
 871         if (r) {
 872                 amdgpu_job_free(job);
 873                 return r;
 874         }
 875
 876         job->owner = p->filp;
 877         job->ctx = entity->fence_context;
 878         p->fence = fence_get(&job->base.s_fence->finished);
 879         cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
 880         job->uf_sequence = cs->out.handle;
 881         amdgpu_job_free_resources(job);
 882
 883         trace_amdgpu_cs_ioctl(job);
 884         amd_sched_entity_push_job(&job->base);
 885
 886         return 0;
 887 }
 888
 889 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 890 {
 891         struct amdgpu_device *adev = dev->dev_private;
 892         union drm_amdgpu_cs *cs = data;
 893         struct amdgpu_cs_parser parser = {};
 894         bool reserved_buffers = false;
 895         int i, r;
 896
 897         if (!adev->accel_working)
 898                 return -EBUSY;
 899
 900         parser.adev = adev;
 901         parser.filp = filp;
 902
 903         r = amdgpu_cs_parser_init(&parser, data);
 904         if (r) {
 905                 DRM_ERROR("Failed to initialize parser !\n");
 906                 amdgpu_cs_parser_fini(&parser, r, false);
 907                 r = amdgpu_cs_handle_lockup(adev, r);
 908                 return r;
 909         }
 910         r = amdgpu_cs_parser_bos(&parser, data);
 911         if (r == -ENOMEM)
 912                 DRM_ERROR("Not enough memory for command submission!\n");
 913         else if (r && r != -ERESTARTSYS)
 914                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 915         else if (!r) {
 916                 reserved_buffers = true;
 917                 r = amdgpu_cs_ib_fill(adev, &parser);
 918         }
 919
 920         if (!r) {
 921                 r = amdgpu_cs_dependencies(adev, &parser);
 922                 if (r)
 923                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 924         }
 925
 926         if (r)
 927                 goto out;
 928
 929         for (i = 0; i < parser.job->num_ibs; i++)
 930                 trace_amdgpu_cs(&parser, i);
 931
 932         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 933         if (r)
 934                 goto out;
 935
 936         r = amdgpu_cs_submit(&parser, cs);
 937
 938 out:
 939         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 940         r = amdgpu_cs_handle_lockup(adev, r);
 941         return r;
 942 }
 943
 944 /**
 945  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 946  *
 947  * @dev: drm device
 948  * @data: data from userspace
 949  * @filp: file private
 950  *
 951  * Wait for the command submission identified by handle to finish.
 952  */
 953 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 954                          struct drm_file *filp)
 955 {
 956         union drm_amdgpu_wait_cs *wait = data;
 957         struct amdgpu_device *adev = dev->dev_private;
 958         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 959         struct amdgpu_ring *ring = NULL;
 960         struct amdgpu_ctx *ctx;
 961         struct fence *fence;
 962         long r;
 963
 964         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 965                                wait->in.ring, &ring);
 966         if (r)
 967                 return r;
 968
 969         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 970         if (ctx == NULL)
 971                 return -EINVAL;
 972
 973         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 974         if (IS_ERR(fence))
 975                 r = PTR_ERR(fence);
 976         else if (fence) {
 977                 r = fence_wait_timeout(fence, true, timeout);
 978                 fence_put(fence);
 979         } else
 980                 r = 1;
 981
 982         amdgpu_ctx_put(ctx);
 983         if (r < 0)
 984                 return r;
 985
 986         memset(wait, 0, sizeof(*wait));
 987         wait->out.status = (r == 0);
 988
 989         return 0;
 990 }
 991
 992 /**
 993  * amdgpu_cs_find_bo_va - find bo_va for VM address
 994  *
 995  * @parser: command submission parser context
 996  * @addr: VM address
 997  * @bo: resulting BO of the mapping found
 998  *
 999  * Search the buffer objects in the command submission context for a certain
1000  * virtual memory address. Returns allocation structure when found, NULL
1001  * otherwise.
1002  */
1003 struct amdgpu_bo_va_mapping *
1004 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1005                        uint64_t addr, struct amdgpu_bo **bo)
1006 {
1007         struct amdgpu_bo_va_mapping *mapping;
1008         unsigned i;
1009
1010         if (!parser->bo_list)
1011                 return NULL;
1012
1013         addr /= AMDGPU_GPU_PAGE_SIZE;
1014
1015         for (i = 0; i < parser->bo_list->num_entries; i++) {
1016                 struct amdgpu_bo_list_entry *lobj;
1017
1018                 lobj = &parser->bo_list->array[i];
1019                 if (!lobj->bo_va)
1020                         continue;
1021
1022                 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1023                         if (mapping->it.start > addr ||
1024                             addr > mapping->it.last)
1025                                 continue;
1026
1027                         *bo = lobj->bo_va->bo;
1028                         return mapping;
1029                 }
1030
1031                 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1032                         if (mapping->it.start > addr ||
1033                             addr > mapping->it.last)
1034                                 continue;
1035
1036                         *bo = lobj->bo_va->bo;
1037                         return mapping;
1038                 }
1039         }
1040
1041         return NULL;
1042 }