drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Rockchip SoC DP (Display Port) interface driver.
   4  *
   5  * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
   6  * Author: Andy Yan <[email protected]>
   7  *         Yakir Yang <[email protected]>
   8  *         Jeff Chen <[email protected]>
   9  */
  10
  11 #include <linux/component.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/of.h>
  14 #include <linux/of_graph.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18 #include <linux/clk.h>
  19
  20 #include <video/of_videomode.h>
  21 #include <video/videomode.h>
  22
  23 #include <drm/display/drm_dp_helper.h>
  24 #include <drm/drm_atomic.h>
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/bridge/analogix_dp.h>
  27 #include <drm/drm_of.h>
  28 #include <drm/drm_panel.h>
  29 #include <drm/drm_probe_helper.h>
  30 #include <drm/drm_simple_kms_helper.h>
  31
  32 #include "rockchip_drm_drv.h"
  33
  34 #define RK3288_GRF_SOC_CON6             0x25c
  35 #define RK3288_EDP_LCDC_SEL             BIT(5)
  36 #define RK3399_GRF_SOC_CON20            0x6250
  37 #define RK3399_EDP_LCDC_SEL             BIT(5)
  38
  39 #define HIWORD_UPDATE(val, mask)        (val | (mask) << 16)
  40
  41 #define PSR_WAIT_LINE_FLAG_TIMEOUT_MS   100
  42
  43 /**
  44  * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
  45  * @lcdsel_grf_reg: grf register offset of lcdc select
  46  * @lcdsel_big: reg value of selecting vop big for eDP
  47  * @lcdsel_lit: reg value of selecting vop little for eDP
  48  * @chip_type: specific chip type
  49  */
  50 struct rockchip_dp_chip_data {
  51         u32     lcdsel_grf_reg;
  52         u32     lcdsel_big;
  53         u32     lcdsel_lit;
  54         u32     chip_type;
  55 };
  56
  57 struct rockchip_dp_device {
  58         struct drm_device        *drm_dev;
  59         struct device            *dev;
  60         struct rockchip_encoder  encoder;
  61         struct drm_display_mode  mode;
  62
  63         struct clk               *pclk;
  64         struct clk               *grfclk;
  65         struct regmap            *grf;
  66         struct reset_control     *rst;
  67
  68         const struct rockchip_dp_chip_data *data;
  69
  70         struct analogix_dp_device *adp;
  71         struct analogix_dp_plat_data plat_data;
  72 };
  73
  74 static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
  75 {
  76         struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
  77
  78         return container_of(rkencoder, struct rockchip_dp_device, encoder);
  79 }
  80
  81 static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
  82 {
  83         return container_of(plat_data, struct rockchip_dp_device, plat_data);
  84 }
  85
  86 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
  87 {
  88         reset_control_assert(dp->rst);
  89         usleep_range(10, 20);
  90         reset_control_deassert(dp->rst);
  91
  92         return 0;
  93 }
  94
  95 static int rockchip_dp_poweron_start(struct analogix_dp_plat_data *plat_data)
  96 {
  97         struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
  98         int ret;
  99
 100         ret = clk_prepare_enable(dp->pclk);
 101         if (ret < 0) {
 102                 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
 103                 return ret;
 104         }
 105
 106         ret = rockchip_dp_pre_init(dp);
 107         if (ret < 0) {
 108                 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
 109                 clk_disable_unprepare(dp->pclk);
 110                 return ret;
 111         }
 112
 113         return ret;
 114 }
 115
 116 static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
 117 {
 118         struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
 119
 120         clk_disable_unprepare(dp->pclk);
 121
 122         return 0;
 123 }
 124
 125 static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
 126                                  struct drm_connector *connector)
 127 {
 128         struct drm_display_info *di = &connector->display_info;
 129         /* VOP couldn't output YUV video format for eDP rightly */
 130         u32 mask = DRM_COLOR_FORMAT_YCBCR444 | DRM_COLOR_FORMAT_YCBCR422;
 131
 132         if ((di->color_formats & mask)) {
 133                 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
 134                 di->color_formats &= ~mask;
 135                 di->color_formats |= DRM_COLOR_FORMAT_RGB444;
 136                 di->bpc = 8;
 137         }
 138
 139         return 0;
 140 }
 141
 142 static bool
 143 rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
 144                                    const struct drm_display_mode *mode,
 145                                    struct drm_display_mode *adjusted_mode)
 146 {
 147         /* do nothing */
 148         return true;
 149 }
 150
 151 static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
 152                                              struct drm_display_mode *mode,
 153                                              struct drm_display_mode *adjusted)
 154 {
 155         /* do nothing */
 156 }
 157
 158 static
 159 struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
 160                                               struct drm_atomic_state *state)
 161 {
 162         struct drm_connector *connector;
 163         struct drm_connector_state *conn_state;
 164
 165         connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
 166         if (!connector)
 167                 return NULL;
 168
 169         conn_state = drm_atomic_get_new_connector_state(state, connector);
 170         if (!conn_state)
 171                 return NULL;
 172
 173         return conn_state->crtc;
 174 }
 175
 176 static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
 177                                            struct drm_atomic_state *state)
 178 {
 179         struct rockchip_dp_device *dp = encoder_to_dp(encoder);
 180         struct drm_crtc *crtc;
 181         struct drm_crtc_state *old_crtc_state;
 182         int ret;
 183         u32 val;
 184
 185         crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
 186         if (!crtc)
 187                 return;
 188
 189         old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
 190         /* Coming back from self refresh, nothing to do */
 191         if (old_crtc_state && old_crtc_state->self_refresh_active)
 192                 return;
 193
 194         ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
 195         if (ret < 0)
 196                 return;
 197
 198         if (ret)
 199                 val = dp->data->lcdsel_lit;
 200         else
 201                 val = dp->data->lcdsel_big;
 202
 203         DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
 204
 205         ret = clk_prepare_enable(dp->grfclk);
 206         if (ret < 0) {
 207                 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
 208                 return;
 209         }
 210
 211         ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
 212         if (ret != 0)
 213                 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
 214
 215         clk_disable_unprepare(dp->grfclk);
 216 }
 217
 218 static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
 219                                             struct drm_atomic_state *state)
 220 {
 221         struct rockchip_dp_device *dp = encoder_to_dp(encoder);
 222         struct drm_crtc *crtc;
 223         struct drm_crtc_state *new_crtc_state = NULL;
 224         int ret;
 225
 226         crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
 227         /* No crtc means we're doing a full shutdown */
 228         if (!crtc)
 229                 return;
 230
 231         new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
 232         /* If we're not entering self-refresh, no need to wait for vact */
 233         if (!new_crtc_state || !new_crtc_state->self_refresh_active)
 234                 return;
 235
 236         ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
 237         if (ret)
 238                 DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
 239 }
 240
 241 static int
 242 rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
 243                                       struct drm_crtc_state *crtc_state,
 244                                       struct drm_connector_state *conn_state)
 245 {
 246         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 247         struct drm_display_info *di = &conn_state->connector->display_info;
 248
 249         /*
 250          * The hardware IC designed that VOP must output the RGB10 video
 251          * format to eDP controller, and if eDP panel only support RGB8,
 252          * then eDP controller should cut down the video data, not via VOP
 253          * controller, that's why we need to hardcode the VOP output mode
 254          * to RGA10 here.
 255          */
 256
 257         s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
 258         s->output_type = DRM_MODE_CONNECTOR_eDP;
 259         s->output_bpc = di->bpc;
 260
 261         return 0;
 262 }
 263
 264 static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
 265         .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
 266         .mode_set = rockchip_dp_drm_encoder_mode_set,
 267         .atomic_enable = rockchip_dp_drm_encoder_enable,
 268         .atomic_disable = rockchip_dp_drm_encoder_disable,
 269         .atomic_check = rockchip_dp_drm_encoder_atomic_check,
 270 };
 271
 272 static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
 273 {
 274         struct device *dev = dp->dev;
 275         struct device_node *np = dev->of_node;
 276
 277         dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
 278         if (IS_ERR(dp->grf)) {
 279                 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
 280                 return PTR_ERR(dp->grf);
 281         }
 282
 283         dp->grfclk = devm_clk_get(dev, "grf");
 284         if (PTR_ERR(dp->grfclk) == -ENOENT) {
 285                 dp->grfclk = NULL;
 286         } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
 287                 return -EPROBE_DEFER;
 288         } else if (IS_ERR(dp->grfclk)) {
 289                 DRM_DEV_ERROR(dev, "failed to get grf clock\n");
 290                 return PTR_ERR(dp->grfclk);
 291         }
 292
 293         dp->pclk = devm_clk_get(dev, "pclk");
 294         if (IS_ERR(dp->pclk)) {
 295                 DRM_DEV_ERROR(dev, "failed to get pclk property\n");
 296                 return PTR_ERR(dp->pclk);
 297         }
 298
 299         dp->rst = devm_reset_control_get(dev, "dp");
 300         if (IS_ERR(dp->rst)) {
 301                 DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
 302                 return PTR_ERR(dp->rst);
 303         }
 304
 305         return 0;
 306 }
 307
 308 static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
 309 {
 310         struct drm_encoder *encoder = &dp->encoder.encoder;
 311         struct drm_device *drm_dev = dp->drm_dev;
 312         struct device *dev = dp->dev;
 313         int ret;
 314
 315         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
 316                                                              dev->of_node);
 317         DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
 318
 319         ret = drm_simple_encoder_init(drm_dev, encoder,
 320                                       DRM_MODE_ENCODER_TMDS);
 321         if (ret) {
 322                 DRM_ERROR("failed to initialize encoder with drm\n");
 323                 return ret;
 324         }
 325
 326         drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
 327
 328         return 0;
 329 }
 330
 331 static int rockchip_dp_bind(struct device *dev, struct device *master,
 332                             void *data)
 333 {
 334         struct rockchip_dp_device *dp = dev_get_drvdata(dev);
 335         struct drm_device *drm_dev = data;
 336         int ret;
 337
 338         dp->drm_dev = drm_dev;
 339
 340         ret = rockchip_dp_drm_create_encoder(dp);
 341         if (ret) {
 342                 DRM_ERROR("failed to create drm encoder\n");
 343                 return ret;
 344         }
 345
 346         dp->plat_data.encoder = &dp->encoder.encoder;
 347
 348         ret = analogix_dp_bind(dp->adp, drm_dev);
 349         if (ret)
 350                 goto err_cleanup_encoder;
 351
 352         return 0;
 353 err_cleanup_encoder:
 354         dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
 355         return ret;
 356 }
 357
 358 static void rockchip_dp_unbind(struct device *dev, struct device *master,
 359                                void *data)
 360 {
 361         struct rockchip_dp_device *dp = dev_get_drvdata(dev);
 362
 363         analogix_dp_unbind(dp->adp);
 364         dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
 365 }
 366
 367 static const struct component_ops rockchip_dp_component_ops = {
 368         .bind = rockchip_dp_bind,
 369         .unbind = rockchip_dp_unbind,
 370 };
 371
 372 static int rockchip_dp_probe(struct platform_device *pdev)
 373 {
 374         struct device *dev = &pdev->dev;
 375         const struct rockchip_dp_chip_data *dp_data;
 376         struct drm_panel *panel = NULL;
 377         struct rockchip_dp_device *dp;
 378         int ret;
 379
 380         dp_data = of_device_get_match_data(dev);
 381         if (!dp_data)
 382                 return -ENODEV;
 383
 384         ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
 385         if (ret < 0)
 386                 return ret;
 387
 388         dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
 389         if (!dp)
 390                 return -ENOMEM;
 391
 392         dp->dev = dev;
 393         dp->adp = ERR_PTR(-ENODEV);
 394         dp->data = dp_data;
 395         dp->plat_data.panel = panel;
 396         dp->plat_data.dev_type = dp->data->chip_type;
 397         dp->plat_data.power_on_start = rockchip_dp_poweron_start;
 398         dp->plat_data.power_off = rockchip_dp_powerdown;
 399         dp->plat_data.get_modes = rockchip_dp_get_modes;
 400
 401         ret = rockchip_dp_of_probe(dp);
 402         if (ret < 0)
 403                 return ret;
 404
 405         platform_set_drvdata(pdev, dp);
 406
 407         dp->adp = analogix_dp_probe(dev, &dp->plat_data);
 408         if (IS_ERR(dp->adp))
 409                 return PTR_ERR(dp->adp);
 410
 411         ret = component_add(dev, &rockchip_dp_component_ops);
 412         if (ret)
 413                 goto err_dp_remove;
 414
 415         return 0;
 416
 417 err_dp_remove:
 418         analogix_dp_remove(dp->adp);
 419         return ret;
 420 }
 421
 422 static void rockchip_dp_remove(struct platform_device *pdev)
 423 {
 424         struct rockchip_dp_device *dp = platform_get_drvdata(pdev);
 425
 426         component_del(&pdev->dev, &rockchip_dp_component_ops);
 427         analogix_dp_remove(dp->adp);
 428 }
 429
 430 #ifdef CONFIG_PM_SLEEP
 431 static int rockchip_dp_suspend(struct device *dev)
 432 {
 433         struct rockchip_dp_device *dp = dev_get_drvdata(dev);
 434
 435         if (IS_ERR(dp->adp))
 436                 return 0;
 437
 438         return analogix_dp_suspend(dp->adp);
 439 }
 440
 441 static int rockchip_dp_resume(struct device *dev)
 442 {
 443         struct rockchip_dp_device *dp = dev_get_drvdata(dev);
 444
 445         if (IS_ERR(dp->adp))
 446                 return 0;
 447
 448         return analogix_dp_resume(dp->adp);
 449 }
 450 #endif
 451
 452 static const struct dev_pm_ops rockchip_dp_pm_ops = {
 453 #ifdef CONFIG_PM_SLEEP
 454         .suspend_late = rockchip_dp_suspend,
 455         .resume_early = rockchip_dp_resume,
 456 #endif
 457 };
 458
 459 static const struct rockchip_dp_chip_data rk3399_edp = {
 460         .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
 461         .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
 462         .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
 463         .chip_type = RK3399_EDP,
 464 };
 465
 466 static const struct rockchip_dp_chip_data rk3288_dp = {
 467         .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
 468         .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
 469         .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
 470         .chip_type = RK3288_DP,
 471 };
 472
 473 static const struct of_device_id rockchip_dp_dt_ids[] = {
 474         {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
 475         {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
 476         {}
 477 };
 478 MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
 479
 480 struct platform_driver rockchip_dp_driver = {
 481         .probe = rockchip_dp_probe,
 482         .remove_new = rockchip_dp_remove,
 483         .driver = {
 484                    .name = "rockchip-dp",
 485                    .pm = &rockchip_dp_pm_ops,
 486                    .of_match_table = rockchip_dp_dt_ids,
 487         },
 488 };