drivers/tty/serial/jsm/jsm_neo.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /************************************************************************
   3  * Copyright 2003 Digi International (www.digi.com)
   4  *
   5  * Copyright (C) 2004 IBM Corporation. All rights reserved.
   6  *
   7  * Contact Information:
   8  * Scott H Kilau <[email protected]>
   9  * Wendy Xiong   <[email protected]>
  10  *
  11  ***********************************************************************/
  12 #include <linux/delay.h>        /* For udelay */
  13 #include <linux/serial_reg.h>   /* For the various UART offsets */
  14 #include <linux/tty.h>
  15 #include <linux/pci.h>
  16 #include <asm/io.h>
  17
  18 #include "jsm.h"                /* Driver main header file */
  19
  20 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
  21
  22 /*
  23  * This function allows calls to ensure that all outstanding
  24  * PCI writes have been completed, by doing a PCI read against
  25  * a non-destructive, read-only location on the Neo card.
  26  *
  27  * In this case, we are reading the DVID (Read-only Device Identification)
  28  * value of the Neo card.
  29  */
  30 static inline void neo_pci_posting_flush(struct jsm_board *bd)
  31 {
  32       readb(bd->re_map_membase + 0x8D);
  33 }
  34
  35 static void neo_set_cts_flow_control(struct jsm_channel *ch)
  36 {
  37         u8 ier, efr;
  38         ier = readb(&ch->ch_neo_uart->ier);
  39         efr = readb(&ch->ch_neo_uart->efr);
  40
  41         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
  42
  43         /* Turn on auto CTS flow control */
  44         ier |= (UART_17158_IER_CTSDSR);
  45         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
  46
  47         /* Turn off auto Xon flow control */
  48         efr &= ~(UART_17158_EFR_IXON);
  49
  50         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
  51         writeb(0, &ch->ch_neo_uart->efr);
  52
  53         /* Turn on UART enhanced bits */
  54         writeb(efr, &ch->ch_neo_uart->efr);
  55
  56         /* Turn on table D, with 8 char hi/low watermarks */
  57         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
  58
  59         /* Feed the UART our trigger levels */
  60         writeb(8, &ch->ch_neo_uart->tfifo);
  61         ch->ch_t_tlevel = 8;
  62
  63         writeb(ier, &ch->ch_neo_uart->ier);
  64 }
  65
  66 static void neo_set_rts_flow_control(struct jsm_channel *ch)
  67 {
  68         u8 ier, efr;
  69         ier = readb(&ch->ch_neo_uart->ier);
  70         efr = readb(&ch->ch_neo_uart->efr);
  71
  72         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
  73
  74         /* Turn on auto RTS flow control */
  75         ier |= (UART_17158_IER_RTSDTR);
  76         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
  77
  78         /* Turn off auto Xoff flow control */
  79         ier &= ~(UART_17158_IER_XOFF);
  80         efr &= ~(UART_17158_EFR_IXOFF);
  81
  82         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
  83         writeb(0, &ch->ch_neo_uart->efr);
  84
  85         /* Turn on UART enhanced bits */
  86         writeb(efr, &ch->ch_neo_uart->efr);
  87
  88         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
  89         ch->ch_r_watermark = 4;
  90
  91         writeb(56, &ch->ch_neo_uart->rfifo);
  92         ch->ch_r_tlevel = 56;
  93
  94         writeb(ier, &ch->ch_neo_uart->ier);
  95
  96         /*
  97          * From the Neo UART spec sheet:
  98          * The auto RTS/DTR function must be started by asserting
  99          * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
 100          * it is enabled.
 101          */
 102         ch->ch_mostat |= (UART_MCR_RTS);
 103 }
 104
 105
 106 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
 107 {
 108         u8 ier, efr;
 109         ier = readb(&ch->ch_neo_uart->ier);
 110         efr = readb(&ch->ch_neo_uart->efr);
 111
 112         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
 113
 114         /* Turn off auto CTS flow control */
 115         ier &= ~(UART_17158_IER_CTSDSR);
 116         efr &= ~(UART_17158_EFR_CTSDSR);
 117
 118         /* Turn on auto Xon flow control */
 119         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
 120
 121         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 122         writeb(0, &ch->ch_neo_uart->efr);
 123
 124         /* Turn on UART enhanced bits */
 125         writeb(efr, &ch->ch_neo_uart->efr);
 126
 127         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 128         ch->ch_r_watermark = 4;
 129
 130         writeb(32, &ch->ch_neo_uart->rfifo);
 131         ch->ch_r_tlevel = 32;
 132
 133         /* Tell UART what start/stop chars it should be looking for */
 134         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
 135         writeb(0, &ch->ch_neo_uart->xonchar2);
 136
 137         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
 138         writeb(0, &ch->ch_neo_uart->xoffchar2);
 139
 140         writeb(ier, &ch->ch_neo_uart->ier);
 141 }
 142
 143 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
 144 {
 145         u8 ier, efr;
 146         ier = readb(&ch->ch_neo_uart->ier);
 147         efr = readb(&ch->ch_neo_uart->efr);
 148
 149         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
 150
 151         /* Turn off auto RTS flow control */
 152         ier &= ~(UART_17158_IER_RTSDTR);
 153         efr &= ~(UART_17158_EFR_RTSDTR);
 154
 155         /* Turn on auto Xoff flow control */
 156         ier |= (UART_17158_IER_XOFF);
 157         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
 158
 159         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 160         writeb(0, &ch->ch_neo_uart->efr);
 161
 162         /* Turn on UART enhanced bits */
 163         writeb(efr, &ch->ch_neo_uart->efr);
 164
 165         /* Turn on table D, with 8 char hi/low watermarks */
 166         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 167
 168         writeb(8, &ch->ch_neo_uart->tfifo);
 169         ch->ch_t_tlevel = 8;
 170
 171         /* Tell UART what start/stop chars it should be looking for */
 172         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
 173         writeb(0, &ch->ch_neo_uart->xonchar2);
 174
 175         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
 176         writeb(0, &ch->ch_neo_uart->xoffchar2);
 177
 178         writeb(ier, &ch->ch_neo_uart->ier);
 179 }
 180
 181 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
 182 {
 183         u8 ier, efr;
 184         ier = readb(&ch->ch_neo_uart->ier);
 185         efr = readb(&ch->ch_neo_uart->efr);
 186
 187         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
 188
 189         /* Turn off auto RTS flow control */
 190         ier &= ~(UART_17158_IER_RTSDTR);
 191         efr &= ~(UART_17158_EFR_RTSDTR);
 192
 193         /* Turn off auto Xoff flow control */
 194         ier &= ~(UART_17158_IER_XOFF);
 195         if (ch->ch_c_iflag & IXON)
 196                 efr &= ~(UART_17158_EFR_IXOFF);
 197         else
 198                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
 199
 200         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 201         writeb(0, &ch->ch_neo_uart->efr);
 202
 203         /* Turn on UART enhanced bits */
 204         writeb(efr, &ch->ch_neo_uart->efr);
 205
 206         /* Turn on table D, with 8 char hi/low watermarks */
 207         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 208
 209         ch->ch_r_watermark = 0;
 210
 211         writeb(16, &ch->ch_neo_uart->tfifo);
 212         ch->ch_t_tlevel = 16;
 213
 214         writeb(16, &ch->ch_neo_uart->rfifo);
 215         ch->ch_r_tlevel = 16;
 216
 217         writeb(ier, &ch->ch_neo_uart->ier);
 218 }
 219
 220 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
 221 {
 222         u8 ier, efr;
 223         ier = readb(&ch->ch_neo_uart->ier);
 224         efr = readb(&ch->ch_neo_uart->efr);
 225
 226         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
 227
 228         /* Turn off auto CTS flow control */
 229         ier &= ~(UART_17158_IER_CTSDSR);
 230         efr &= ~(UART_17158_EFR_CTSDSR);
 231
 232         /* Turn off auto Xon flow control */
 233         if (ch->ch_c_iflag & IXOFF)
 234                 efr &= ~(UART_17158_EFR_IXON);
 235         else
 236                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
 237
 238         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
 239         writeb(0, &ch->ch_neo_uart->efr);
 240
 241         /* Turn on UART enhanced bits */
 242         writeb(efr, &ch->ch_neo_uart->efr);
 243
 244         /* Turn on table D, with 8 char hi/low watermarks */
 245         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
 246
 247         ch->ch_r_watermark = 0;
 248
 249         writeb(16, &ch->ch_neo_uart->tfifo);
 250         ch->ch_t_tlevel = 16;
 251
 252         writeb(16, &ch->ch_neo_uart->rfifo);
 253         ch->ch_r_tlevel = 16;
 254
 255         writeb(ier, &ch->ch_neo_uart->ier);
 256 }
 257
 258 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
 259 {
 260
 261         /* if hardware flow control is set, then skip this whole thing */
 262         if (ch->ch_c_cflag & CRTSCTS)
 263                 return;
 264
 265         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
 266
 267         /* Tell UART what start/stop chars it should be looking for */
 268         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
 269         writeb(0, &ch->ch_neo_uart->xonchar2);
 270
 271         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
 272         writeb(0, &ch->ch_neo_uart->xoffchar2);
 273 }
 274
 275 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
 276 {
 277         int qleft = 0;
 278         u8 linestatus = 0;
 279         u8 error_mask = 0;
 280         int n = 0;
 281         int total = 0;
 282         u16 head;
 283         u16 tail;
 284
 285         /* cache head and tail of queue */
 286         head = ch->ch_r_head & RQUEUEMASK;
 287         tail = ch->ch_r_tail & RQUEUEMASK;
 288
 289         /* Get our cached LSR */
 290         linestatus = ch->ch_cached_lsr;
 291         ch->ch_cached_lsr = 0;
 292
 293         /* Store how much space we have left in the queue */
 294         qleft = tail - head - 1;
 295         if (qleft < 0)
 296                 qleft += RQUEUEMASK + 1;
 297
 298         /*
 299          * If the UART is not in FIFO mode, force the FIFO copy to
 300          * NOT be run, by setting total to 0.
 301          *
 302          * On the other hand, if the UART IS in FIFO mode, then ask
 303          * the UART to give us an approximation of data it has RX'ed.
 304          */
 305         if (!(ch->ch_flags & CH_FIFO_ENABLED))
 306                 total = 0;
 307         else {
 308                 total = readb(&ch->ch_neo_uart->rfifo);
 309
 310                 /*
 311                  * EXAR chip bug - RX FIFO COUNT - Fudge factor.
 312                  *
 313                  * This resolves a problem/bug with the Exar chip that sometimes
 314                  * returns a bogus value in the rfifo register.
 315                  * The count can be any where from 0-3 bytes "off".
 316                  * Bizarre, but true.
 317                  */
 318                 total -= 3;
 319         }
 320
 321         /*
 322          * Finally, bound the copy to make sure we don't overflow
 323          * our own queue...
 324          * The byte by byte copy loop below this loop this will
 325          * deal with the queue overflow possibility.
 326          */
 327         total = min(total, qleft);
 328
 329         while (total > 0) {
 330                 /*
 331                  * Grab the linestatus register, we need to check
 332                  * to see if there are any errors in the FIFO.
 333                  */
 334                 linestatus = readb(&ch->ch_neo_uart->lsr);
 335
 336                 /*
 337                  * Break out if there is a FIFO error somewhere.
 338                  * This will allow us to go byte by byte down below,
 339                  * finding the exact location of the error.
 340                  */
 341                 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
 342                         break;
 343
 344                 /* Make sure we don't go over the end of our queue */
 345                 n = min(((u32) total), (RQUEUESIZE - (u32) head));
 346
 347                 /*
 348                  * Cut down n even further if needed, this is to fix
 349                  * a problem with memcpy_fromio() with the Neo on the
 350                  * IBM pSeries platform.
 351                  * 15 bytes max appears to be the magic number.
 352                  */
 353                 n = min((u32) n, (u32) 12);
 354
 355                 /*
 356                  * Since we are grabbing the linestatus register, which
 357                  * will reset some bits after our read, we need to ensure
 358                  * we don't miss our TX FIFO emptys.
 359                  */
 360                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
 361                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 362
 363                 linestatus = 0;
 364
 365                 /* Copy data from uart to the queue */
 366                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
 367                 /*
 368                  * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
 369                  * that all the data currently in the FIFO is free of
 370                  * breaks and parity/frame/orun errors.
 371                  */
 372                 memset(ch->ch_equeue + head, 0, n);
 373
 374                 /* Add to and flip head if needed */
 375                 head = (head + n) & RQUEUEMASK;
 376                 total -= n;
 377                 qleft -= n;
 378                 ch->ch_rxcount += n;
 379         }
 380
 381         /*
 382          * Create a mask to determine whether we should
 383          * insert the character (if any) into our queue.
 384          */
 385         if (ch->ch_c_iflag & IGNBRK)
 386                 error_mask |= UART_LSR_BI;
 387
 388         /*
 389          * Now cleanup any leftover bytes still in the UART.
 390          * Also deal with any possible queue overflow here as well.
 391          */
 392         while (1) {
 393
 394                 /*
 395                  * Its possible we have a linestatus from the loop above
 396                  * this, so we "OR" on any extra bits.
 397                  */
 398                 linestatus |= readb(&ch->ch_neo_uart->lsr);
 399
 400                 /*
 401                  * If the chip tells us there is no more data pending to
 402                  * be read, we can then leave.
 403                  * But before we do, cache the linestatus, just in case.
 404                  */
 405                 if (!(linestatus & UART_LSR_DR)) {
 406                         ch->ch_cached_lsr = linestatus;
 407                         break;
 408                 }
 409
 410                 /* No need to store this bit */
 411                 linestatus &= ~UART_LSR_DR;
 412
 413                 /*
 414                  * Since we are grabbing the linestatus register, which
 415                  * will reset some bits after our read, we need to ensure
 416                  * we don't miss our TX FIFO emptys.
 417                  */
 418                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
 419                         linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
 420                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 421                 }
 422
 423                 /*
 424                  * Discard character if we are ignoring the error mask.
 425                  */
 426                 if (linestatus & error_mask) {
 427                         u8 discard;
 428                         linestatus = 0;
 429                         memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
 430                         continue;
 431                 }
 432
 433                 /*
 434                  * If our queue is full, we have no choice but to drop some data.
 435                  * The assumption is that HWFLOW or SWFLOW should have stopped
 436                  * things way way before we got to this point.
 437                  *
 438                  * I decided that I wanted to ditch the oldest data first,
 439                  * I hope thats okay with everyone? Yes? Good.
 440                  */
 441                 while (qleft < 1) {
 442                         jsm_dbg(READ, &ch->ch_bd->pci_dev,
 443                                 "Queue full, dropping DATA:%x LSR:%x\n",
 444                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
 445
 446                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
 447                         ch->ch_err_overrun++;
 448                         qleft++;
 449                 }
 450
 451                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
 452                 ch->ch_equeue[head] = (u8) linestatus;
 453
 454                 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
 455                         ch->ch_rqueue[head], ch->ch_equeue[head]);
 456
 457                 /* Ditch any remaining linestatus value. */
 458                 linestatus = 0;
 459
 460                 /* Add to and flip head if needed */
 461                 head = (head + 1) & RQUEUEMASK;
 462
 463                 qleft--;
 464                 ch->ch_rxcount++;
 465         }
 466
 467         /*
 468          * Write new final heads to channel structure.
 469          */
 470         ch->ch_r_head = head & RQUEUEMASK;
 471         ch->ch_e_head = head & EQUEUEMASK;
 472         jsm_input(ch);
 473 }
 474
 475 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
 476 {
 477         u16 head;
 478         u16 tail;
 479         int n;
 480         int s;
 481         int qlen;
 482         u32 len_written = 0;
 483         struct circ_buf *circ;
 484
 485         if (!ch)
 486                 return;
 487
 488         circ = &ch->uart_port.state->xmit;
 489
 490         /* No data to write to the UART */
 491         if (uart_circ_empty(circ))
 492                 return;
 493
 494         /* If port is "stopped", don't send any data to the UART */
 495         if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
 496                 return;
 497         /*
 498          * If FIFOs are disabled. Send data directly to txrx register
 499          */
 500         if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
 501                 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
 502
 503                 ch->ch_cached_lsr |= lsrbits;
 504                 if (ch->ch_cached_lsr & UART_LSR_THRE) {
 505                         ch->ch_cached_lsr &= ~(UART_LSR_THRE);
 506
 507                         writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
 508                         jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
 509                                 "Tx data: %x\n", circ->buf[circ->tail]);
 510                         circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
 511                         ch->ch_txcount++;
 512                 }
 513                 return;
 514         }
 515
 516         /*
 517          * We have to do it this way, because of the EXAR TXFIFO count bug.
 518          */
 519         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
 520                 return;
 521
 522         n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
 523
 524         /* cache head and tail of queue */
 525         head = circ->head & (UART_XMIT_SIZE - 1);
 526         tail = circ->tail & (UART_XMIT_SIZE - 1);
 527         qlen = uart_circ_chars_pending(circ);
 528
 529         /* Find minimum of the FIFO space, versus queue length */
 530         n = min(n, qlen);
 531
 532         while (n > 0) {
 533
 534                 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
 535                 s = min(s, n);
 536
 537                 if (s <= 0)
 538                         break;
 539
 540                 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
 541                 /* Add and flip queue if needed */
 542                 tail = (tail + s) & (UART_XMIT_SIZE - 1);
 543                 n -= s;
 544                 ch->ch_txcount += s;
 545                 len_written += s;
 546         }
 547
 548         /* Update the final tail */
 549         circ->tail = tail & (UART_XMIT_SIZE - 1);
 550
 551         if (len_written >= ch->ch_t_tlevel)
 552                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 553
 554         if (uart_circ_empty(circ))
 555                 uart_write_wakeup(&ch->uart_port);
 556 }
 557
 558 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
 559 {
 560         u8 msignals = signals;
 561
 562         jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
 563                 "neo_parse_modem: port: %d msignals: %x\n",
 564                 ch->ch_portnum, msignals);
 565
 566         /* Scrub off lower bits. They signify delta's, which I don't care about */
 567         /* Keep DDCD and DDSR though */
 568         msignals &= 0xf8;
 569
 570         if (msignals & UART_MSR_DDCD)
 571                 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
 572         if (msignals & UART_MSR_DDSR)
 573                 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
 574         if (msignals & UART_MSR_DCD)
 575                 ch->ch_mistat |= UART_MSR_DCD;
 576         else
 577                 ch->ch_mistat &= ~UART_MSR_DCD;
 578
 579         if (msignals & UART_MSR_DSR)
 580                 ch->ch_mistat |= UART_MSR_DSR;
 581         else
 582                 ch->ch_mistat &= ~UART_MSR_DSR;
 583
 584         if (msignals & UART_MSR_RI)
 585                 ch->ch_mistat |= UART_MSR_RI;
 586         else
 587                 ch->ch_mistat &= ~UART_MSR_RI;
 588
 589         if (msignals & UART_MSR_CTS)
 590                 ch->ch_mistat |= UART_MSR_CTS;
 591         else
 592                 ch->ch_mistat &= ~UART_MSR_CTS;
 593
 594         jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
 595                 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
 596                 ch->ch_portnum,
 597                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
 598                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
 599                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
 600                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
 601                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
 602                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
 603 }
 604
 605 /* Make the UART raise any of the output signals we want up */
 606 static void neo_assert_modem_signals(struct jsm_channel *ch)
 607 {
 608         if (!ch)
 609                 return;
 610
 611         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
 612
 613         /* flush write operation */
 614         neo_pci_posting_flush(ch->ch_bd);
 615 }
 616
 617 /*
 618  * Flush the WRITE FIFO on the Neo.
 619  *
 620  * NOTE: Channel lock MUST be held before calling this function!
 621  */
 622 static void neo_flush_uart_write(struct jsm_channel *ch)
 623 {
 624         u8 tmp = 0;
 625         int i = 0;
 626
 627         if (!ch)
 628                 return;
 629
 630         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
 631
 632         for (i = 0; i < 10; i++) {
 633
 634                 /* Check to see if the UART feels it completely flushed the FIFO. */
 635                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
 636                 if (tmp & UART_FCR_CLEAR_XMIT) {
 637                         jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
 638                                 "Still flushing TX UART... i: %d\n", i);
 639                         udelay(10);
 640                 }
 641                 else
 642                         break;
 643         }
 644
 645         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 646 }
 647
 648
 649 /*
 650  * Flush the READ FIFO on the Neo.
 651  *
 652  * NOTE: Channel lock MUST be held before calling this function!
 653  */
 654 static void neo_flush_uart_read(struct jsm_channel *ch)
 655 {
 656         u8 tmp = 0;
 657         int i = 0;
 658
 659         if (!ch)
 660                 return;
 661
 662         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
 663
 664         for (i = 0; i < 10; i++) {
 665
 666                 /* Check to see if the UART feels it completely flushed the FIFO. */
 667                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
 668                 if (tmp & 2) {
 669                         jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
 670                                 "Still flushing RX UART... i: %d\n", i);
 671                         udelay(10);
 672                 }
 673                 else
 674                         break;
 675         }
 676 }
 677
 678 /*
 679  * No locks are assumed to be held when calling this function.
 680  */
 681 static void neo_clear_break(struct jsm_channel *ch)
 682 {
 683         unsigned long lock_flags;
 684
 685         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 686
 687         /* Turn break off, and unset some variables */
 688         if (ch->ch_flags & CH_BREAK_SENDING) {
 689                 u8 temp = readb(&ch->ch_neo_uart->lcr);
 690                 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
 691
 692                 ch->ch_flags &= ~(CH_BREAK_SENDING);
 693                 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
 694                         "clear break Finishing UART_LCR_SBC! finished: %lx\n",
 695                         jiffies);
 696
 697                 /* flush write operation */
 698                 neo_pci_posting_flush(ch->ch_bd);
 699         }
 700         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 701 }
 702
 703 /*
 704  * Parse the ISR register.
 705  */
 706 static void neo_parse_isr(struct jsm_board *brd, u32 port)
 707 {
 708         struct jsm_channel *ch;
 709         u8 isr;
 710         u8 cause;
 711         unsigned long lock_flags;
 712
 713         if (!brd)
 714                 return;
 715
 716         if (port >= brd->maxports)
 717                 return;
 718
 719         ch = brd->channels[port];
 720         if (!ch)
 721                 return;
 722
 723         /* Here we try to figure out what caused the interrupt to happen */
 724         while (1) {
 725
 726                 isr = readb(&ch->ch_neo_uart->isr_fcr);
 727
 728                 /* Bail if no pending interrupt */
 729                 if (isr & UART_IIR_NO_INT)
 730                         break;
 731
 732                 /*
 733                  * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
 734                  */
 735                 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
 736
 737                 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
 738                         __FILE__, __LINE__, isr);
 739
 740                 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
 741                         /* Read data from uart -> queue */
 742                         neo_copy_data_from_uart_to_queue(ch);
 743
 744                         /* Call our tty layer to enforce queue flow control if needed. */
 745                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 746                         jsm_check_queue_flow_control(ch);
 747                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 748                 }
 749
 750                 if (isr & UART_IIR_THRI) {
 751                         /* Transfer data (if any) from Write Queue -> UART. */
 752                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 753                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 754                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 755                         neo_copy_data_from_queue_to_uart(ch);
 756                 }
 757
 758                 if (isr & UART_17158_IIR_XONXOFF) {
 759                         cause = readb(&ch->ch_neo_uart->xoffchar1);
 760
 761                         jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 762                                 "Port %d. Got ISR_XONXOFF: cause:%x\n",
 763                                 port, cause);
 764
 765                         /*
 766                          * Since the UART detected either an XON or
 767                          * XOFF match, we need to figure out which
 768                          * one it was, so we can suspend or resume data flow.
 769                          */
 770                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 771                         if (cause == UART_17158_XON_DETECT) {
 772                                 /* Is output stopped right now, if so, resume it */
 773                                 if (brd->channels[port]->ch_flags & CH_STOP) {
 774                                         ch->ch_flags &= ~(CH_STOP);
 775                                 }
 776                                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 777                                         "Port %d. XON detected in incoming data\n",
 778                                         port);
 779                         }
 780                         else if (cause == UART_17158_XOFF_DETECT) {
 781                                 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
 782                                         ch->ch_flags |= CH_STOP;
 783                                         jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 784                                                 "Setting CH_STOP\n");
 785                                 }
 786                                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 787                                         "Port: %d. XOFF detected in incoming data\n",
 788                                         port);
 789                         }
 790                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 791                 }
 792
 793                 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
 794                         /*
 795                          * If we get here, this means the hardware is doing auto flow control.
 796                          * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
 797                          */
 798                         cause = readb(&ch->ch_neo_uart->mcr);
 799
 800                         /* Which pin is doing auto flow? RTS or DTR? */
 801                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
 802                         if ((cause & 0x4) == 0) {
 803                                 if (cause & UART_MCR_RTS)
 804                                         ch->ch_mostat |= UART_MCR_RTS;
 805                                 else
 806                                         ch->ch_mostat &= ~(UART_MCR_RTS);
 807                         } else {
 808                                 if (cause & UART_MCR_DTR)
 809                                         ch->ch_mostat |= UART_MCR_DTR;
 810                                 else
 811                                         ch->ch_mostat &= ~(UART_MCR_DTR);
 812                         }
 813                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 814                 }
 815
 816                 /* Parse any modem signal changes */
 817                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 818                         "MOD_STAT: sending to parse_modem_sigs\n");
 819                 uart_port_lock_irqsave(&ch->uart_port, &lock_flags);
 820                 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
 821                 uart_port_unlock_irqrestore(&ch->uart_port, lock_flags);
 822         }
 823 }
 824
 825 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
 826 {
 827         struct jsm_channel *ch;
 828         int linestatus;
 829         unsigned long lock_flags;
 830
 831         if (!brd)
 832                 return;
 833
 834         if (port >= brd->maxports)
 835                 return;
 836
 837         ch = brd->channels[port];
 838         if (!ch)
 839                 return;
 840
 841         linestatus = readb(&ch->ch_neo_uart->lsr);
 842
 843         jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
 844                 __FILE__, __LINE__, port, linestatus);
 845
 846         ch->ch_cached_lsr |= linestatus;
 847
 848         if (ch->ch_cached_lsr & UART_LSR_DR) {
 849                 /* Read data from uart -> queue */
 850                 neo_copy_data_from_uart_to_queue(ch);
 851                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
 852                 jsm_check_queue_flow_control(ch);
 853                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 854         }
 855
 856         /*
 857          * This is a special flag. It indicates that at least 1
 858          * RX error (parity, framing, or break) has happened.
 859          * Mark this in our struct, which will tell me that I have
 860          *to do the special RX+LSR read for this FIFO load.
 861          */
 862         if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
 863                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 864                         "%s:%d Port: %d Got an RX error, need to parse LSR\n",
 865                         __FILE__, __LINE__, port);
 866
 867         /*
 868          * The next 3 tests should *NOT* happen, as the above test
 869          * should encapsulate all 3... At least, thats what Exar says.
 870          */
 871
 872         if (linestatus & UART_LSR_PE) {
 873                 ch->ch_err_parity++;
 874                 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
 875                         __FILE__, __LINE__, port);
 876         }
 877
 878         if (linestatus & UART_LSR_FE) {
 879                 ch->ch_err_frame++;
 880                 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
 881                         __FILE__, __LINE__, port);
 882         }
 883
 884         if (linestatus & UART_LSR_BI) {
 885                 ch->ch_err_break++;
 886                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 887                         "%s:%d Port: %d. BRK INTR!\n",
 888                         __FILE__, __LINE__, port);
 889         }
 890
 891         if (linestatus & UART_LSR_OE) {
 892                 /*
 893                  * Rx Oruns. Exar says that an orun will NOT corrupt
 894                  * the FIFO. It will just replace the holding register
 895                  * with this new data byte. So basically just ignore this.
 896                  * Probably we should eventually have an orun stat in our driver...
 897                  */
 898                 ch->ch_err_overrun++;
 899                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
 900                         "%s:%d Port: %d. Rx Overrun!\n",
 901                         __FILE__, __LINE__, port);
 902         }
 903
 904         if (linestatus & UART_LSR_THRE) {
 905                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
 906                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 907                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 908
 909                 /* Transfer data (if any) from Write Queue -> UART. */
 910                 neo_copy_data_from_queue_to_uart(ch);
 911         }
 912         else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
 913                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
 914                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
 915                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
 916
 917                 /* Transfer data (if any) from Write Queue -> UART. */
 918                 neo_copy_data_from_queue_to_uart(ch);
 919         }
 920 }
 921
 922 /*
 923  * neo_param()
 924  * Send any/all changes to the line to the UART.
 925  */
 926 static void neo_param(struct jsm_channel *ch)
 927 {
 928         u8 lcr = 0;
 929         u8 uart_lcr, ier;
 930         u32 baud;
 931         int quot;
 932         struct jsm_board *bd;
 933
 934         bd = ch->ch_bd;
 935         if (!bd)
 936                 return;
 937
 938         /*
 939          * If baud rate is zero, flush queues, and set mval to drop DTR.
 940          */
 941         if ((ch->ch_c_cflag & CBAUD) == B0) {
 942                 ch->ch_r_head = ch->ch_r_tail = 0;
 943                 ch->ch_e_head = ch->ch_e_tail = 0;
 944
 945                 neo_flush_uart_write(ch);
 946                 neo_flush_uart_read(ch);
 947
 948                 ch->ch_flags |= (CH_BAUD0);
 949                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
 950                 neo_assert_modem_signals(ch);
 951                 return;
 952
 953         } else {
 954                 int i;
 955                 unsigned int cflag;
 956                 static struct {
 957                         unsigned int rate;
 958                         unsigned int cflag;
 959                 } baud_rates[] = {
 960                         { 921600, B921600 },
 961                         { 460800, B460800 },
 962                         { 230400, B230400 },
 963                         { 115200, B115200 },
 964                         {  57600, B57600  },
 965                         {  38400, B38400  },
 966                         {  19200, B19200  },
 967                         {   9600, B9600   },
 968                         {   4800, B4800   },
 969                         {   2400, B2400   },
 970                         {   1200, B1200   },
 971                         {    600, B600    },
 972                         {    300, B300    },
 973                         {    200, B200    },
 974                         {    150, B150    },
 975                         {    134, B134    },
 976                         {    110, B110    },
 977                         {     75, B75     },
 978                         {     50, B50     },
 979                 };
 980
 981                 cflag = C_BAUD(ch->uart_port.state->port.tty);
 982                 baud = 9600;
 983                 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
 984                         if (baud_rates[i].cflag == cflag) {
 985                                 baud = baud_rates[i].rate;
 986                                 break;
 987                         }
 988                 }
 989
 990                 if (ch->ch_flags & CH_BAUD0)
 991                         ch->ch_flags &= ~(CH_BAUD0);
 992         }
 993
 994         if (ch->ch_c_cflag & PARENB)
 995                 lcr |= UART_LCR_PARITY;
 996
 997         if (!(ch->ch_c_cflag & PARODD))
 998                 lcr |= UART_LCR_EPAR;
 999
1000         if (ch->ch_c_cflag & CMSPAR)
1001                 lcr |= UART_LCR_SPAR;
1002
1003         if (ch->ch_c_cflag & CSTOPB)
1004                 lcr |= UART_LCR_STOP;
1005
1006         lcr |= UART_LCR_WLEN(tty_get_char_size(ch->ch_c_cflag));
1007
1008         ier = readb(&ch->ch_neo_uart->ier);
1009         uart_lcr = readb(&ch->ch_neo_uart->lcr);
1010
1011         quot = ch->ch_bd->bd_dividend / baud;
1012
1013         if (quot != 0) {
1014                 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1015                 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1016                 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1017                 writeb(lcr, &ch->ch_neo_uart->lcr);
1018         }
1019
1020         if (uart_lcr != lcr)
1021                 writeb(lcr, &ch->ch_neo_uart->lcr);
1022
1023         if (ch->ch_c_cflag & CREAD)
1024                 ier |= (UART_IER_RDI | UART_IER_RLSI);
1025
1026         ier |= (UART_IER_THRI | UART_IER_MSI);
1027
1028         writeb(ier, &ch->ch_neo_uart->ier);
1029
1030         /* Set new start/stop chars */
1031         neo_set_new_start_stop_chars(ch);
1032
1033         if (ch->ch_c_cflag & CRTSCTS)
1034                 neo_set_cts_flow_control(ch);
1035         else if (ch->ch_c_iflag & IXON) {
1036                 /* If start/stop is set to disable, then we should disable flow control */
1037                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1038                         neo_set_no_output_flow_control(ch);
1039                 else
1040                         neo_set_ixon_flow_control(ch);
1041         }
1042         else
1043                 neo_set_no_output_flow_control(ch);
1044
1045         if (ch->ch_c_cflag & CRTSCTS)
1046                 neo_set_rts_flow_control(ch);
1047         else if (ch->ch_c_iflag & IXOFF) {
1048                 /* If start/stop is set to disable, then we should disable flow control */
1049                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1050                         neo_set_no_input_flow_control(ch);
1051                 else
1052                         neo_set_ixoff_flow_control(ch);
1053         }
1054         else
1055                 neo_set_no_input_flow_control(ch);
1056         /*
1057          * Adjust the RX FIFO Trigger level if baud is less than 9600.
1058          * Not exactly elegant, but this is needed because of the Exar chip's
1059          * delay on firing off the RX FIFO interrupt on slower baud rates.
1060          */
1061         if (baud < 9600) {
1062                 writeb(1, &ch->ch_neo_uart->rfifo);
1063                 ch->ch_r_tlevel = 1;
1064         }
1065
1066         neo_assert_modem_signals(ch);
1067
1068         /* Get current status of the modem signals now */
1069         neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1070         return;
1071 }
1072
1073 /*
1074  * jsm_neo_intr()
1075  *
1076  * Neo specific interrupt handler.
1077  */
1078 static irqreturn_t neo_intr(int irq, void *voidbrd)
1079 {
1080         struct jsm_board *brd = voidbrd;
1081         struct jsm_channel *ch;
1082         int port = 0;
1083         int type = 0;
1084         int current_port;
1085         u32 tmp;
1086         u32 uart_poll;
1087         unsigned long lock_flags;
1088         unsigned long lock_flags2;
1089         int outofloop_count = 0;
1090
1091         /* Lock out the slow poller from running on this board. */
1092         spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1093
1094         /*
1095          * Read in "extended" IRQ information from the 32bit Neo register.
1096          * Bits 0-7: What port triggered the interrupt.
1097          * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1098          */
1099         uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1100
1101         jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
1102                 __FILE__, __LINE__, uart_poll);
1103
1104         if (!uart_poll) {
1105                 jsm_dbg(INTR, &brd->pci_dev,
1106                         "Kernel interrupted to me, but no pending interrupts...\n");
1107                 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1108                 return IRQ_NONE;
1109         }
1110
1111         /* At this point, we have at least SOMETHING to service, dig further... */
1112
1113         current_port = 0;
1114
1115         /* Loop on each port */
1116         while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1117
1118                 tmp = uart_poll;
1119                 outofloop_count++;
1120
1121                 /* Check current port to see if it has interrupt pending */
1122                 if ((tmp & jsm_offset_table[current_port]) != 0) {
1123                         port = current_port;
1124                         type = tmp >> (8 + (port * 3));
1125                         type &= 0x7;
1126                 } else {
1127                         current_port++;
1128                         continue;
1129                 }
1130
1131                 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
1132                         __FILE__, __LINE__, port, type);
1133
1134                 /* Remove this port + type from uart_poll */
1135                 uart_poll &= ~(jsm_offset_table[port]);
1136
1137                 if (!type) {
1138                         /* If no type, just ignore it, and move onto next port */
1139                         jsm_dbg(INTR, &brd->pci_dev,
1140                                 "Interrupt with no type! port: %d\n", port);
1141                         continue;
1142                 }
1143
1144                 /* Switch on type of interrupt we have */
1145                 switch (type) {
1146
1147                 case UART_17158_RXRDY_TIMEOUT:
1148                         /*
1149                          * RXRDY Time-out is cleared by reading data in the
1150                         * RX FIFO until it falls below the trigger level.
1151                          */
1152
1153                         /* Verify the port is in range. */
1154                         if (port >= brd->nasync)
1155                                 continue;
1156
1157                         ch = brd->channels[port];
1158                         if (!ch)
1159                                 continue;
1160
1161                         neo_copy_data_from_uart_to_queue(ch);
1162
1163                         /* Call our tty layer to enforce queue flow control if needed. */
1164                         spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1165                         jsm_check_queue_flow_control(ch);
1166                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1167
1168                         continue;
1169
1170                 case UART_17158_RX_LINE_STATUS:
1171                         /*
1172                          * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1173                          */
1174                         neo_parse_lsr(brd, port);
1175                         continue;
1176
1177                 case UART_17158_TXRDY:
1178                         /*
1179                          * TXRDY interrupt clears after reading ISR register for the UART channel.
1180                          */
1181
1182                         /*
1183                          * Yes, this is odd...
1184                          * Why would I check EVERY possibility of type of
1185                          * interrupt, when we know its TXRDY???
1186                          * Becuz for some reason, even tho we got triggered for TXRDY,
1187                          * it seems to be occasionally wrong. Instead of TX, which
1188                          * it should be, I was getting things like RXDY too. Weird.
1189                          */
1190                         neo_parse_isr(brd, port);
1191                         continue;
1192
1193                 case UART_17158_MSR:
1194                         /*
1195                          * MSR or flow control was seen.
1196                          */
1197                         neo_parse_isr(brd, port);
1198                         continue;
1199
1200                 default:
1201                         /*
1202                          * The UART triggered us with a bogus interrupt type.
1203                          * It appears the Exar chip, when REALLY bogged down, will throw
1204                          * these once and awhile.
1205                          * Its harmless, just ignore it and move on.
1206                          */
1207                         jsm_dbg(INTR, &brd->pci_dev,
1208                                 "%s:%d Unknown Interrupt type: %x\n",
1209                                 __FILE__, __LINE__, type);
1210                         continue;
1211                 }
1212         }
1213
1214         spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1215
1216         jsm_dbg(INTR, &brd->pci_dev, "finish\n");
1217         return IRQ_HANDLED;
1218 }
1219
1220 /*
1221  * Neo specific way of turning off the receiver.
1222  * Used as a way to enforce queue flow control when in
1223  * hardware flow control mode.
1224  */
1225 static void neo_disable_receiver(struct jsm_channel *ch)
1226 {
1227         u8 tmp = readb(&ch->ch_neo_uart->ier);
1228         tmp &= ~(UART_IER_RDI);
1229         writeb(tmp, &ch->ch_neo_uart->ier);
1230
1231         /* flush write operation */
1232         neo_pci_posting_flush(ch->ch_bd);
1233 }
1234
1235
1236 /*
1237  * Neo specific way of turning on the receiver.
1238  * Used as a way to un-enforce queue flow control when in
1239  * hardware flow control mode.
1240  */
1241 static void neo_enable_receiver(struct jsm_channel *ch)
1242 {
1243         u8 tmp = readb(&ch->ch_neo_uart->ier);
1244         tmp |= (UART_IER_RDI);
1245         writeb(tmp, &ch->ch_neo_uart->ier);
1246
1247         /* flush write operation */
1248         neo_pci_posting_flush(ch->ch_bd);
1249 }
1250
1251 static void neo_send_start_character(struct jsm_channel *ch)
1252 {
1253         if (!ch)
1254                 return;
1255
1256         if (ch->ch_startc != __DISABLED_CHAR) {
1257                 ch->ch_xon_sends++;
1258                 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1259
1260                 /* flush write operation */
1261                 neo_pci_posting_flush(ch->ch_bd);
1262         }
1263 }
1264
1265 static void neo_send_stop_character(struct jsm_channel *ch)
1266 {
1267         if (!ch)
1268                 return;
1269
1270         if (ch->ch_stopc != __DISABLED_CHAR) {
1271                 ch->ch_xoff_sends++;
1272                 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1273
1274                 /* flush write operation */
1275                 neo_pci_posting_flush(ch->ch_bd);
1276         }
1277 }
1278
1279 /*
1280  * neo_uart_init
1281  */
1282 static void neo_uart_init(struct jsm_channel *ch)
1283 {
1284         writeb(0, &ch->ch_neo_uart->ier);
1285         writeb(0, &ch->ch_neo_uart->efr);
1286         writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1287
1288         /* Clear out UART and FIFO */
1289         readb(&ch->ch_neo_uart->txrx);
1290         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1291         readb(&ch->ch_neo_uart->lsr);
1292         readb(&ch->ch_neo_uart->msr);
1293
1294         ch->ch_flags |= CH_FIFO_ENABLED;
1295
1296         /* Assert any signals we want up */
1297         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1298 }
1299
1300 /*
1301  * Make the UART completely turn off.
1302  */
1303 static void neo_uart_off(struct jsm_channel *ch)
1304 {
1305         /* Turn off UART enhanced bits */
1306         writeb(0, &ch->ch_neo_uart->efr);
1307
1308         /* Stop all interrupts from occurring. */
1309         writeb(0, &ch->ch_neo_uart->ier);
1310 }
1311
1312 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1313 {
1314         u8 left = 0;
1315         u8 lsr = readb(&ch->ch_neo_uart->lsr);
1316
1317         /* We must cache the LSR as some of the bits get reset once read... */
1318         ch->ch_cached_lsr |= lsr;
1319
1320         /* Determine whether the Transmitter is empty or not */
1321         if (!(lsr & UART_LSR_TEMT))
1322                 left = 1;
1323         else {
1324                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1325                 left = 0;
1326         }
1327
1328         return left;
1329 }
1330
1331 /* Channel lock MUST be held by the calling function! */
1332 static void neo_send_break(struct jsm_channel *ch)
1333 {
1334         /*
1335          * Set the time we should stop sending the break.
1336          * If we are already sending a break, toss away the existing
1337          * time to stop, and use this new value instead.
1338          */
1339
1340         /* Tell the UART to start sending the break */
1341         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1342                 u8 temp = readb(&ch->ch_neo_uart->lcr);
1343                 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1344                 ch->ch_flags |= (CH_BREAK_SENDING);
1345
1346                 /* flush write operation */
1347                 neo_pci_posting_flush(ch->ch_bd);
1348         }
1349 }
1350
1351 /*
1352  * neo_send_immediate_char.
1353  *
1354  * Sends a specific character as soon as possible to the UART,
1355  * jumping over any bytes that might be in the write queue.
1356  *
1357  * The channel lock MUST be held by the calling function.
1358  */
1359 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1360 {
1361         if (!ch)
1362                 return;
1363
1364         writeb(c, &ch->ch_neo_uart->txrx);
1365
1366         /* flush write operation */
1367         neo_pci_posting_flush(ch->ch_bd);
1368 }
1369
1370 struct board_ops jsm_neo_ops = {
1371         .intr                           = neo_intr,
1372         .uart_init                      = neo_uart_init,
1373         .uart_off                       = neo_uart_off,
1374         .param                          = neo_param,
1375         .assert_modem_signals           = neo_assert_modem_signals,
1376         .flush_uart_write               = neo_flush_uart_write,
1377         .flush_uart_read                = neo_flush_uart_read,
1378         .disable_receiver               = neo_disable_receiver,
1379         .enable_receiver                = neo_enable_receiver,
1380         .send_break                     = neo_send_break,
1381         .clear_break                    = neo_clear_break,
1382         .send_start_character           = neo_send_start_character,
1383         .send_stop_character            = neo_send_stop_character,
1384         .copy_data_from_queue_to_uart   = neo_copy_data_from_queue_to_uart,
1385         .get_uart_bytes_left            = neo_get_uart_bytes_left,
1386         .send_immediate_char            = neo_send_immediate_char
1387 };