drivers/soc/qcom/spm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2014,2015, Linaro Ltd.
   5  *
   6  * SAW power controller driver
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/of.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <soc/qcom/spm.h>
  18
  19 #define SPM_CTL_INDEX           0x7f
  20 #define SPM_CTL_INDEX_SHIFT     4
  21 #define SPM_CTL_EN              BIT(0)
  22
  23 enum spm_reg {
  24         SPM_REG_CFG,
  25         SPM_REG_SPM_CTL,
  26         SPM_REG_DLY,
  27         SPM_REG_PMIC_DLY,
  28         SPM_REG_PMIC_DATA_0,
  29         SPM_REG_PMIC_DATA_1,
  30         SPM_REG_VCTL,
  31         SPM_REG_SEQ_ENTRY,
  32         SPM_REG_SPM_STS,
  33         SPM_REG_PMIC_STS,
  34         SPM_REG_AVS_CTL,
  35         SPM_REG_AVS_LIMIT,
  36         SPM_REG_NR,
  37 };
  38
  39 static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
  40         [SPM_REG_AVS_CTL]       = 0x904,
  41         [SPM_REG_AVS_LIMIT]     = 0x908,
  42 };
  43
  44 static const struct spm_reg_data spm_reg_660_gold_l2  = {
  45         .reg_offset = spm_reg_offset_v4_1,
  46         .avs_ctl = 0x1010031,
  47         .avs_limit = 0x4580458,
  48 };
  49
  50 static const struct spm_reg_data spm_reg_660_silver_l2  = {
  51         .reg_offset = spm_reg_offset_v4_1,
  52         .avs_ctl = 0x101c031,
  53         .avs_limit = 0x4580458,
  54 };
  55
  56 static const struct spm_reg_data spm_reg_8998_gold_l2  = {
  57         .reg_offset = spm_reg_offset_v4_1,
  58         .avs_ctl = 0x1010031,
  59         .avs_limit = 0x4700470,
  60 };
  61
  62 static const struct spm_reg_data spm_reg_8998_silver_l2  = {
  63         .reg_offset = spm_reg_offset_v4_1,
  64         .avs_ctl = 0x1010031,
  65         .avs_limit = 0x4200420,
  66 };
  67
  68 static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = {
  69         [SPM_REG_CFG]           = 0x08,
  70         [SPM_REG_SPM_CTL]       = 0x30,
  71         [SPM_REG_DLY]           = 0x34,
  72         [SPM_REG_SEQ_ENTRY]     = 0x400,
  73 };
  74
  75 /* SPM register data for 8909 */
  76 static const struct spm_reg_data spm_reg_8909_cpu = {
  77         .reg_offset = spm_reg_offset_v3_0,
  78         .spm_cfg = 0x1,
  79         .spm_dly = 0x3C102800,
  80         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
  81                 0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
  82                 0x10, 0x26, 0x30, 0x0F },
  83         .start_index[PM_SLEEP_MODE_STBY] = 0,
  84         .start_index[PM_SLEEP_MODE_SPC] = 5,
  85 };
  86
  87 /* SPM register data for 8916 */
  88 static const struct spm_reg_data spm_reg_8916_cpu = {
  89         .reg_offset = spm_reg_offset_v3_0,
  90         .spm_cfg = 0x1,
  91         .spm_dly = 0x3C102800,
  92         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
  93                 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
  94                 0x80, 0x10, 0x26, 0x30, 0x0F },
  95         .start_index[PM_SLEEP_MODE_STBY] = 0,
  96         .start_index[PM_SLEEP_MODE_SPC] = 5,
  97 };
  98
  99 static const struct spm_reg_data spm_reg_8939_cpu = {
 100         .reg_offset = spm_reg_offset_v3_0,
 101         .spm_cfg = 0x1,
 102         .spm_dly = 0x3C102800,
 103         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x50, 0x1B, 0x10, 0x80,
 104                 0x30, 0x90, 0x5B, 0x60, 0x50, 0x03, 0x60, 0x76, 0x76, 0x0B,
 105                 0x50, 0x1B, 0x94, 0x5B, 0x80, 0x10, 0x26, 0x30, 0x50, 0x0F },
 106         .start_index[PM_SLEEP_MODE_STBY] = 0,
 107         .start_index[PM_SLEEP_MODE_SPC] = 5,
 108 };
 109
 110 static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
 111         [SPM_REG_CFG]           = 0x08,
 112         [SPM_REG_SPM_CTL]       = 0x30,
 113         [SPM_REG_DLY]           = 0x34,
 114         [SPM_REG_PMIC_DATA_0]   = 0x40,
 115         [SPM_REG_PMIC_DATA_1]   = 0x44,
 116 };
 117
 118 /* SPM register data for 8976 */
 119 static const struct spm_reg_data spm_reg_8976_gold_l2 = {
 120         .reg_offset = spm_reg_offset_v2_3,
 121         .spm_cfg = 0x14,
 122         .spm_dly = 0x3c11840a,
 123         .pmic_data[0] = 0x03030080,
 124         .pmic_data[1] = 0x00030000,
 125         .start_index[PM_SLEEP_MODE_STBY] = 0,
 126         .start_index[PM_SLEEP_MODE_SPC] = 3,
 127 };
 128
 129 static const struct spm_reg_data spm_reg_8976_silver_l2 = {
 130         .reg_offset = spm_reg_offset_v2_3,
 131         .spm_cfg = 0x14,
 132         .spm_dly = 0x3c102800,
 133         .pmic_data[0] = 0x03030080,
 134         .pmic_data[1] = 0x00030000,
 135         .start_index[PM_SLEEP_MODE_STBY] = 0,
 136         .start_index[PM_SLEEP_MODE_SPC] = 2,
 137 };
 138
 139 static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
 140         [SPM_REG_CFG]           = 0x08,
 141         [SPM_REG_SPM_CTL]       = 0x30,
 142         [SPM_REG_DLY]           = 0x34,
 143         [SPM_REG_SEQ_ENTRY]     = 0x80,
 144 };
 145
 146 /* SPM register data for 8974, 8084 */
 147 static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
 148         .reg_offset = spm_reg_offset_v2_1,
 149         .spm_cfg = 0x1,
 150         .spm_dly = 0x3C102800,
 151         .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
 152                 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
 153                 0x0F },
 154         .start_index[PM_SLEEP_MODE_STBY] = 0,
 155         .start_index[PM_SLEEP_MODE_SPC] = 3,
 156 };
 157
 158 /* SPM register data for 8226 */
 159 static const struct spm_reg_data spm_reg_8226_cpu  = {
 160         .reg_offset = spm_reg_offset_v2_1,
 161         .spm_cfg = 0x0,
 162         .spm_dly = 0x3C102800,
 163         .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
 164                 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
 165                 0x80, 0x10, 0x26, 0x30, 0x0F },
 166         .start_index[PM_SLEEP_MODE_STBY] = 0,
 167         .start_index[PM_SLEEP_MODE_SPC] = 5,
 168 };
 169
 170 static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
 171         [SPM_REG_CFG]           = 0x08,
 172         [SPM_REG_SPM_CTL]       = 0x20,
 173         [SPM_REG_PMIC_DLY]      = 0x24,
 174         [SPM_REG_PMIC_DATA_0]   = 0x28,
 175         [SPM_REG_PMIC_DATA_1]   = 0x2C,
 176         [SPM_REG_SEQ_ENTRY]     = 0x80,
 177 };
 178
 179 /* SPM register data for 8064 */
 180 static const struct spm_reg_data spm_reg_8064_cpu = {
 181         .reg_offset = spm_reg_offset_v1_1,
 182         .spm_cfg = 0x1F,
 183         .pmic_dly = 0x02020004,
 184         .pmic_data[0] = 0x0084009C,
 185         .pmic_data[1] = 0x00A4001C,
 186         .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
 187                 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
 188         .start_index[PM_SLEEP_MODE_STBY] = 0,
 189         .start_index[PM_SLEEP_MODE_SPC] = 2,
 190 };
 191
 192 static inline void spm_register_write(struct spm_driver_data *drv,
 193                                         enum spm_reg reg, u32 val)
 194 {
 195         if (drv->reg_data->reg_offset[reg])
 196                 writel_relaxed(val, drv->reg_base +
 197                                 drv->reg_data->reg_offset[reg]);
 198 }
 199
 200 /* Ensure a guaranteed write, before return */
 201 static inline void spm_register_write_sync(struct spm_driver_data *drv,
 202                                         enum spm_reg reg, u32 val)
 203 {
 204         u32 ret;
 205
 206         if (!drv->reg_data->reg_offset[reg])
 207                 return;
 208
 209         do {
 210                 writel_relaxed(val, drv->reg_base +
 211                                 drv->reg_data->reg_offset[reg]);
 212                 ret = readl_relaxed(drv->reg_base +
 213                                 drv->reg_data->reg_offset[reg]);
 214                 if (ret == val)
 215                         break;
 216                 cpu_relax();
 217         } while (1);
 218 }
 219
 220 static inline u32 spm_register_read(struct spm_driver_data *drv,
 221                                     enum spm_reg reg)
 222 {
 223         return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
 224 }
 225
 226 void spm_set_low_power_mode(struct spm_driver_data *drv,
 227                             enum pm_sleep_mode mode)
 228 {
 229         u32 start_index;
 230         u32 ctl_val;
 231
 232         start_index = drv->reg_data->start_index[mode];
 233
 234         ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
 235         ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
 236         ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
 237         ctl_val |= SPM_CTL_EN;
 238         spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
 239 }
 240
 241 static const struct of_device_id spm_match_table[] = {
 242         { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
 243           .data = &spm_reg_660_gold_l2 },
 244         { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2",
 245           .data = &spm_reg_660_silver_l2 },
 246         { .compatible = "qcom,msm8226-saw2-v2.1-cpu",
 247           .data = &spm_reg_8226_cpu },
 248         { .compatible = "qcom,msm8909-saw2-v3.0-cpu",
 249           .data = &spm_reg_8909_cpu },
 250         { .compatible = "qcom,msm8916-saw2-v3.0-cpu",
 251           .data = &spm_reg_8916_cpu },
 252         { .compatible = "qcom,msm8939-saw2-v3.0-cpu",
 253           .data = &spm_reg_8939_cpu },
 254         { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
 255           .data = &spm_reg_8974_8084_cpu },
 256         { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
 257           .data = &spm_reg_8976_gold_l2 },
 258         { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
 259           .data = &spm_reg_8976_silver_l2 },
 260         { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
 261           .data = &spm_reg_8998_gold_l2 },
 262         { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
 263           .data = &spm_reg_8998_silver_l2 },
 264         { .compatible = "qcom,apq8084-saw2-v2.1-cpu",
 265           .data = &spm_reg_8974_8084_cpu },
 266         { .compatible = "qcom,apq8064-saw2-v1.1-cpu",
 267           .data = &spm_reg_8064_cpu },
 268         { },
 269 };
 270 MODULE_DEVICE_TABLE(of, spm_match_table);
 271
 272 static int spm_dev_probe(struct platform_device *pdev)
 273 {
 274         const struct of_device_id *match_id;
 275         struct spm_driver_data *drv;
 276         void __iomem *addr;
 277
 278         drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
 279         if (!drv)
 280                 return -ENOMEM;
 281
 282         drv->reg_base = devm_platform_ioremap_resource(pdev, 0);
 283         if (IS_ERR(drv->reg_base))
 284                 return PTR_ERR(drv->reg_base);
 285
 286         match_id = of_match_node(spm_match_table, pdev->dev.of_node);
 287         if (!match_id)
 288                 return -ENODEV;
 289
 290         drv->reg_data = match_id->data;
 291         platform_set_drvdata(pdev, drv);
 292
 293         /* Write the SPM sequences first.. */
 294         addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
 295         __iowrite32_copy(addr, drv->reg_data->seq,
 296                         ARRAY_SIZE(drv->reg_data->seq) / 4);
 297
 298         /*
 299          * ..and then the control registers.
 300          * On some SoC if the control registers are written first and if the
 301          * CPU was held in reset, the reset signal could trigger the SPM state
 302          * machine, before the sequences are completely written.
 303          */
 304         spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl);
 305         spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit);
 306         spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
 307         spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
 308         spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
 309         spm_register_write(drv, SPM_REG_PMIC_DATA_0,
 310                                 drv->reg_data->pmic_data[0]);
 311         spm_register_write(drv, SPM_REG_PMIC_DATA_1,
 312                                 drv->reg_data->pmic_data[1]);
 313
 314         /* Set up Standby as the default low power mode */
 315         if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
 316                 spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
 317
 318         return 0;
 319 }
 320
 321 static struct platform_driver spm_driver = {
 322         .probe = spm_dev_probe,
 323         .driver = {
 324                 .name = "qcom_spm",
 325                 .of_match_table = spm_match_table,
 326         },
 327 };
 328
 329 static int __init qcom_spm_init(void)
 330 {
 331         return platform_driver_register(&spm_driver);
 332 }
 333 arch_initcall(qcom_spm_init);
 334
 335 MODULE_LICENSE("GPL v2");