drivers/phy/qualcomm/phy-qcom-qmp-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include "phy-qcom-qmp.h"
  23 #include "phy-qcom-qmp-pcs-misc-v3.h"
  24 #include "phy-qcom-qmp-pcs-misc-v4.h"
  25 #include "phy-qcom-qmp-pcs-usb-v4.h"
  26 #include "phy-qcom-qmp-pcs-usb-v5.h"
  27
  28 /* QPHY_SW_RESET bit */
  29 #define SW_RESET                                BIT(0)
  30 /* QPHY_POWER_DOWN_CONTROL */
  31 #define SW_PWRDN                                BIT(0)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 /* QPHY_PCS_STATUS bit */
  36 #define PHYSTATUS                               BIT(6)
  37
  38 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  39 /* DP PHY soft reset */
  40 #define SW_DPPHY_RESET                          BIT(0)
  41 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  42 #define SW_DPPHY_RESET_MUX                      BIT(1)
  43 /* USB3 PHY soft reset */
  44 #define SW_USB3PHY_RESET                        BIT(2)
  45 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  46 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  47
  48 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  49 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  50 #define DP_MODE                                 BIT(1) /* enables DP mode */
  51
  52 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  53 #define ARCVR_DTCT_EN                           BIT(0)
  54 #define ALFPS_DTCT_EN                           BIT(1)
  55 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  56
  57 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  58 #define IRQ_CLEAR                               BIT(0)
  59
  60 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  61 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  62
  63 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  64
  65 struct qmp_phy_init_tbl {
  66         unsigned int offset;
  67         unsigned int val;
  68         /*
  69          * mask of lanes for which this register is written
  70          * for cases when second lane needs different values
  71          */
  72         u8 lane_mask;
  73 };
  74
  75 #define QMP_PHY_INIT_CFG(o, v)          \
  76         {                               \
  77                 .offset = o,            \
  78                 .val = v,               \
  79                 .lane_mask = 0xff,      \
  80         }
  81
  82 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  83         {                               \
  84                 .offset = o,            \
  85                 .val = v,               \
  86                 .lane_mask = l,         \
  87         }
  88
  89 /* set of registers with offsets different per-PHY */
  90 enum qphy_reg_layout {
  91         /* PCS registers */
  92         QPHY_SW_RESET,
  93         QPHY_START_CTRL,
  94         QPHY_PCS_STATUS,
  95         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
  96         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
  97         QPHY_PCS_POWER_DOWN_CONTROL,
  98         QPHY_PCS_MISC_CLAMP_ENABLE,
  99         /* Keep last to ensure regs_layout arrays are properly initialized */
 100         QPHY_LAYOUT_SIZE
 101 };
 102
 103 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 104         [QPHY_SW_RESET]                 = QPHY_V2_PCS_SW_RESET,
 105         [QPHY_START_CTRL]               = QPHY_V2_PCS_START_CONTROL,
 106         [QPHY_PCS_STATUS]               = QPHY_V2_PCS_USB_PCS_STATUS,
 107         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
 108         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
 109         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_POWER_DOWN_CONTROL,
 110 };
 111
 112 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 113         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 114         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 115         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 116         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 117         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 118         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 119         [QPHY_PCS_MISC_CLAMP_ENABLE]    = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
 120 };
 121
 122 static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
 123         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 124         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 125         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 126         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 127         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 128         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 129 };
 130
 131 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 132         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 133         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 134         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 135         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 136
 137         /* In PCS_USB */
 138         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 139         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 140         [QPHY_PCS_MISC_CLAMP_ENABLE]    = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
 141 };
 142
 143 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 144         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
 145         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
 146         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
 147         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
 148
 149         /* In PCS_USB */
 150         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 151         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 152 };
 153
 154 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
 155         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 156         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 157         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 158         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 159         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 160         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 161         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 162         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 163         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 164         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 165         /* PLL and Loop filter settings */
 166         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
 167         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
 168         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
 169         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
 170         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
 171         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 172         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 173         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
 174         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
 175         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
 176         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 177         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 178         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 179         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 180         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 181         /* SSC settings */
 182         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 183         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
 184         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 185         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 186         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 187         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
 188         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
 189 };
 190
 191 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
 192         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 193         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 194         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 195 };
 196
 197 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
 198         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 199         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 200         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
 201         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 202         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 203         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 204         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 205         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 206         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 207         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
 208 };
 209
 210 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
 211         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 212         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 213         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 214         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 215         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 216         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 217         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 218         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 219         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 220         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 221         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 222         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 223         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 224         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 225         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 226         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 227         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 228         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 229         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 230         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 231         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 232         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 233         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 234 };
 235
 236 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 237         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 238         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 239         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 240         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 241         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 242         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 243         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 244         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 245         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 246         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 247         /* PLL and Loop filter settings */
 248         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 250         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 251         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 253         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 262         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 263         /* SSC settings */
 264         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 265         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 266         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 267         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 268         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 271 };
 272
 273 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 274         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 275         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 276         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 277         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 278         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 279         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 280         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 281         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 282         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 283 };
 284
 285 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 286         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 287         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 288         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 289         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 290         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 291         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 292         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 293         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 294         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 295         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 296         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 297         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 298         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 299         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 300         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 304         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 305         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 306         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 307         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 308         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 309 };
 310
 311 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 312         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 321         /* PLL and Loop filter settings */
 322         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 338         /* SSC settings */
 339         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 346 };
 347
 348 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 349         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 350         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 351         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 352 };
 353
 354 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 355         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 356         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 357         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 358         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 359         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 360         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 361         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 362         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 363         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 364         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 365 };
 366
 367 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 368         /* FLL settings */
 369         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
 370         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
 371         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
 372         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
 373         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
 374
 375         /* Lock Det settings */
 376         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 377         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 378         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
 379         QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
 380 };
 381
 382 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 383         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 385         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 386         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 388         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 414         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 415         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 416         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 417         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 418         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 419 };
 420
 421 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 422         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 424         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 425         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 426         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 427 };
 428
 429 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 430         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 441 };
 442
 443 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 444         /* FLL settings */
 445         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 446         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 450
 451         /* Lock Det settings */
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 456
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 458         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 459         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 460         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 461         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 462         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 463         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 464         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 465         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 466         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 467         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 468         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 469         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 470         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 471         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 472         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 473         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 474         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 475         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 476
 477         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 478         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 479         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 480         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 481         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 482         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 483         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 484         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 485         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 486         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 487         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 488
 489         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 490         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 491 };
 492
 493 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
 494         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 495         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 496         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 497         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
 498         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 499         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 500         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 501         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 502         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 503         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 504         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 505         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 506         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 507         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 508         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 509         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 510         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 511         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 512         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 513         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 514         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 515         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 516         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 517         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 518         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 519         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 520         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 521         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 522         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 523         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
 524         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 525         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 526         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 527         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 528         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 529         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 530         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 531         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 532 };
 533
 534 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
 535         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 536         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 537         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 538         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 539 };
 540
 541 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
 542         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 543         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 544         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 545         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 546         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
 547         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 548         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
 549         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 550         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 551         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 552         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 553         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 554         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 555         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 556         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 557         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
 558         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 559 };
 560
 561 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
 562         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 563         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 564         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 565         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 566         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 567         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 568         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 569         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 570         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 571         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 572         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 573         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 574         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 575         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 576         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 577         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 578         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 579         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 580         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 581         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 582         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 583         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 584         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
 585         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 586         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 587         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 588         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 589         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 590         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 591         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 592         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 593         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 594         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 595         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 596         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
 597         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 598         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 599         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 600 };
 601
 602 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
 603         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 604         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 605         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 606         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 608         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 609         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 610         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 611         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 612         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 613         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 614         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 615         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 616         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 617         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 618         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 619         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 620         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 621         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 622         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 623         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 624         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 625         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 626         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 627         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 628         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 629         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 630         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 631         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 632         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 633         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 634         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 635         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 636         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 637         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 638         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 639         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 640         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 641         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 642         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 643 };
 644
 645 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
 646         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 647         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
 648         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 649         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
 650 };
 651
 652 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
 653         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 654         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 655         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
 656         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
 657         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
 658         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 659         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 660         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 661         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 662         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 663         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 664         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 665         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 666         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 667         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 668         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 669         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 670         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 671         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 672         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
 673         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 674         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 675         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 676         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 677         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 678         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 679         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 680         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 681         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 682         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 683         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 684         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 685         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 686         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
 687         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 688         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 689 };
 690
 691 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
 692         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 693         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 694         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 695         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 696         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 697         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 698         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 699         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
 700         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 701         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 702         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 703         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 704         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 705         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 706 };
 707
 708 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
 709         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 710         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 711 };
 712
 713 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
 714         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 715         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 716         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
 717         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 718         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 719         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 720 };
 721
 722 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
 723         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 724         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
 725         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 726         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 727         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 728         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 729         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 730         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 731         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 732         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 733         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 734         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 735         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 736         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 737         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 738         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 739         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 740         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 741         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 742         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
 743         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 744         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 745         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 746         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 747         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 748         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 749         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 750         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 751         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 752         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 753         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 754         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 755         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 756         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 757         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 758         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 759 };
 760
 761 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
 762         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 763         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 764         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 765         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 766         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 767         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 768         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 769         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 770         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 771         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 772         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 773         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 774         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 775         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 776 };
 777
 778 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
 779         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 780         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 781 };
 782
 783 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
 784         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 785         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 786         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
 787         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 788         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
 789 };
 790
 791 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
 792         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
 793         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 794         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 795         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 796         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 797         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 798         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 799         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 800         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 801         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 802         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 803         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
 804         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 805         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
 806         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
 807         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 808         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 809         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 810         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 811         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
 812         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 813         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 814         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 815         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 816         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 817         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 818         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 819         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 820         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 821         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 822         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 823         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 824         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 825         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 826         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 827         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 828 };
 829
 830 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
 831         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 832         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 833         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 834         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 835         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 836         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 837         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
 838 };
 839
 840 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
 841         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 842         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 843         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 844         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 845         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 846         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 847         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 848         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 849         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 850         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 851         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 852         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 853         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 854         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 855         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 856         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 857         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 858         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 859         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 860         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 861         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 862         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 863         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 864         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 865         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 866         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 867         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 868         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 869         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 870         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 871         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
 872 };
 873
 874 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
 875         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 876         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 877         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 878         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 879         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 880         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
 881         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 882 };
 883
 884 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
 885         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
 886         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 887         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 888         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 889         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 890         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 891         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 892         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 893         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 894         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 895         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 896         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 897         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 898         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 899         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 900         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 901         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 902         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 903         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 904         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 905         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 906         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 907         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 908         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 909         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 910         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 911         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 912         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 913         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 914         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 915         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
 916 };
 917
 918 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
 919         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 920         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 921         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 922         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 923         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 924         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 925         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 926         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 927         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 928         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 929         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 930         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 931         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 932         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 933 };
 934
 935 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
 936         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 937         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 938 };
 939
 940 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
 941         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 942         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 943         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 944         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 945         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
 946         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
 947         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 948         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 949         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 950         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 951         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 952         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 953         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 954         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 955         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 956         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 957         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 958         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 959         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 960         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 961         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 962         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 963         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
 964         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 965         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 966         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 967         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 968         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 969         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 970         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 971         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 972         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 973         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 974         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 975         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 976         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 977         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
 978         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
 979 };
 980
 981 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
 982         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 983         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 984         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 985         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 986         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
 987 };
 988
 989 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
 990         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 991         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 992         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 993         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 994         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 995         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 996         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 997         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 998         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 999         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1000         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1001         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1002         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
1003         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1004         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1005         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1006         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
1007 };
1008
1009 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
1010         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1011         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
1012         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1013         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1014         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1015         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1016         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1017         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1018         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1019         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1020         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1021         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1022         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1023         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1024         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1025         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1026         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1027         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1028         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1029         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1030         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1031 };
1032
1033 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1034         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1035         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1036         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1037         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1038         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1039         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1040         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1041         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1042         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1043         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1044         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1045         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1046         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1047         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1048         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1049         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1050         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1051         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1052         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1053         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1054         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1055         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1056         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1057         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1058         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1059         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1060         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1061         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1062         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1063         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1064         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1065         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1066         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1067         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1068         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1069         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1070         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1071         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1072         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1073 };
1074
1075 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1076         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1077         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1078         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1079         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1080         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1081         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1082         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1083 };
1084
1085 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1086         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1087         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1088         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1089         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1090         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1091         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1092         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1093         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1094         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1095         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1096         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1097         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1098         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1099         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1100         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1101         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1102         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1103         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1104         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1105         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1106         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1107         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1108         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1109         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1110         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1111         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1112         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1113         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1114         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1115         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1116         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1117 };
1118
1119 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1120         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1121         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1122         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1123         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1124         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1125         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1126         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1127         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1128         QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1129         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1130         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1131         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1132         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1133         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1134 };
1135
1136 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {
1137         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1138         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1139 };
1140
1141 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1142         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1143         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1144         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1145         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1146         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1147         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1148         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1149         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1150         QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1151         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1152         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1153         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1154         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1155         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1156 };
1157
1158 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {
1159         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1160         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1161         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1162 };
1163
1164 struct qmp_usb_offsets {
1165         u16 serdes;
1166         u16 pcs;
1167         u16 pcs_misc;
1168         u16 pcs_usb;
1169         u16 tx;
1170         u16 rx;
1171         /* for PHYs with >= 2 lanes */
1172         u16 tx2;
1173         u16 rx2;
1174 };
1175
1176 /* struct qmp_phy_cfg - per-PHY initialization config */
1177 struct qmp_phy_cfg {
1178         int lanes;
1179
1180         const struct qmp_usb_offsets *offsets;
1181
1182         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1183         const struct qmp_phy_init_tbl *serdes_tbl;
1184         int serdes_tbl_num;
1185         const struct qmp_phy_init_tbl *tx_tbl;
1186         int tx_tbl_num;
1187         const struct qmp_phy_init_tbl *rx_tbl;
1188         int rx_tbl_num;
1189         const struct qmp_phy_init_tbl *pcs_tbl;
1190         int pcs_tbl_num;
1191         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1192         int pcs_usb_tbl_num;
1193
1194         /* regulators to be requested */
1195         const char * const *vreg_list;
1196         int num_vregs;
1197
1198         /* array of registers with different offsets */
1199         const unsigned int *regs;
1200
1201         /* true, if PHY needs delay after POWER_DOWN */
1202         bool has_pwrdn_delay;
1203
1204         /* Offset from PCS to PCS_USB region */
1205         unsigned int pcs_usb_offset;
1206 };
1207
1208 struct qmp_usb {
1209         struct device *dev;
1210
1211         const struct qmp_phy_cfg *cfg;
1212
1213         void __iomem *serdes;
1214         void __iomem *pcs;
1215         void __iomem *pcs_misc;
1216         void __iomem *pcs_usb;
1217         void __iomem *tx;
1218         void __iomem *rx;
1219         void __iomem *tx2;
1220         void __iomem *rx2;
1221
1222         struct clk *pipe_clk;
1223         struct clk_bulk_data *clks;
1224         int num_clks;
1225         int num_resets;
1226         struct reset_control_bulk_data *resets;
1227         struct regulator_bulk_data *vregs;
1228
1229         enum phy_mode mode;
1230
1231         struct phy *phy;
1232
1233         struct clk_fixed_rate pipe_clk_fixed;
1234 };
1235
1236 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1237 {
1238         u32 reg;
1239
1240         reg = readl(base + offset);
1241         reg |= val;
1242         writel(reg, base + offset);
1243
1244         /* ensure that above write is through */
1245         readl(base + offset);
1246 }
1247
1248 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1249 {
1250         u32 reg;
1251
1252         reg = readl(base + offset);
1253         reg &= ~val;
1254         writel(reg, base + offset);
1255
1256         /* ensure that above write is through */
1257         readl(base + offset);
1258 }
1259
1260 /* list of clocks required by phy */
1261 static const char * const qmp_usb_phy_clk_l[] = {
1262         "aux", "cfg_ahb", "ref", "com_aux",
1263 };
1264
1265 /* list of resets */
1266 static const char * const usb3phy_legacy_reset_l[] = {
1267         "phy", "common",
1268 };
1269
1270 static const char * const usb3phy_reset_l[] = {
1271         "phy_phy", "phy",
1272 };
1273
1274 /* list of regulators */
1275 static const char * const qmp_phy_vreg_l[] = {
1276         "vdda-phy", "vdda-pll",
1277 };
1278
1279 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1280         .serdes         = 0,
1281         .pcs            = 0x800,
1282         .pcs_usb        = 0x800,
1283         .tx             = 0x200,
1284         .rx             = 0x400,
1285 };
1286
1287 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1288         .serdes         = 0,
1289         .pcs            = 0x600,
1290         .tx             = 0x200,
1291         .rx             = 0x400,
1292 };
1293
1294 static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = {
1295         .serdes         = 0x0,
1296         .pcs            = 0xc00,
1297         .pcs_misc       = 0xa00,
1298         .tx             = 0x200,
1299         .rx             = 0x400,
1300         .tx2            = 0x600,
1301         .rx2            = 0x800,
1302 };
1303
1304 static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
1305         .serdes         = 0,
1306         .pcs            = 0x0800,
1307         .pcs_usb        = 0x0e00,
1308         .tx             = 0x0200,
1309         .rx             = 0x0400,
1310 };
1311
1312 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1313         .serdes         = 0,
1314         .pcs            = 0x0200,
1315         .pcs_usb        = 0x1200,
1316         .tx             = 0x0e00,
1317         .rx             = 0x1000,
1318 };
1319
1320 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1321         .lanes                  = 1,
1322
1323         .offsets                = &qmp_usb_offsets_v3,
1324
1325         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
1326         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1327         .tx_tbl                 = msm8996_usb3_tx_tbl,
1328         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1329         .rx_tbl                 = ipq8074_usb3_rx_tbl,
1330         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1331         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
1332         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1333         .vreg_list              = qmp_phy_vreg_l,
1334         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1335         .regs                   = qmp_v3_usb3phy_regs_layout,
1336 };
1337
1338 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1339         .lanes                  = 1,
1340
1341         .offsets                = &qmp_usb_offsets_ipq9574,
1342
1343         .serdes_tbl             = ipq9574_usb3_serdes_tbl,
1344         .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1345         .tx_tbl                 = ipq9574_usb3_tx_tbl,
1346         .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1347         .rx_tbl                 = ipq9574_usb3_rx_tbl,
1348         .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1349         .pcs_tbl                = ipq9574_usb3_pcs_tbl,
1350         .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1351         .vreg_list              = qmp_phy_vreg_l,
1352         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1353         .regs                   = qmp_v3_usb3phy_regs_layout,
1354 };
1355
1356 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1357         .lanes                  = 1,
1358
1359         .offsets                = &qmp_usb_offsets_v3,
1360
1361         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1362         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1363         .tx_tbl                 = msm8996_usb3_tx_tbl,
1364         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1365         .rx_tbl                 = msm8996_usb3_rx_tbl,
1366         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1367         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1368         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1369         .vreg_list              = qmp_phy_vreg_l,
1370         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1371         .regs                   = qmp_v2_usb3phy_regs_layout,
1372 };
1373
1374 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1375         .lanes                  = 1,
1376
1377         .offsets                = &qmp_usb_offsets_v5,
1378
1379         .serdes_tbl             = sc8280xp_usb3_uniphy_serdes_tbl,
1380         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1381         .tx_tbl                 = sc8280xp_usb3_uniphy_tx_tbl,
1382         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1383         .rx_tbl                 = sc8280xp_usb3_uniphy_rx_tbl,
1384         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1385         .pcs_tbl                = sa8775p_usb3_uniphy_pcs_tbl,
1386         .pcs_tbl_num            = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1387         .pcs_usb_tbl            = sa8775p_usb3_uniphy_pcs_usb_tbl,
1388         .pcs_usb_tbl_num        = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1389         .vreg_list              = qmp_phy_vreg_l,
1390         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1391         .regs                   = qmp_v5_usb3phy_regs_layout,
1392 };
1393
1394 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1395         .lanes                  = 1,
1396
1397         .offsets                = &qmp_usb_offsets_v5,
1398
1399         .serdes_tbl             = sc8280xp_usb3_uniphy_serdes_tbl,
1400         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1401         .tx_tbl                 = sc8280xp_usb3_uniphy_tx_tbl,
1402         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1403         .rx_tbl                 = sc8280xp_usb3_uniphy_rx_tbl,
1404         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1405         .pcs_tbl                = sc8280xp_usb3_uniphy_pcs_tbl,
1406         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1407         .pcs_usb_tbl            = sc8280xp_usb3_uniphy_pcs_usb_tbl,
1408         .pcs_usb_tbl_num        = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),
1409         .vreg_list              = qmp_phy_vreg_l,
1410         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1411         .regs                   = qmp_v5_usb3phy_regs_layout,
1412 };
1413
1414 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1415         .lanes                  = 1,
1416
1417         .offsets                = &qmp_usb_offsets_v3,
1418
1419         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1420         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1421         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1422         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1423         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1424         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1425         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1426         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1427         .vreg_list              = qmp_phy_vreg_l,
1428         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1429         .regs                   = qmp_v3_usb3phy_regs_layout,
1430
1431         .has_pwrdn_delay        = true,
1432 };
1433
1434 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1435         .lanes                  = 2,
1436
1437         .offsets                = &qmp_usb_offsets_v3_qcm2290,
1438
1439         .serdes_tbl             = msm8998_usb3_serdes_tbl,
1440         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1441         .tx_tbl                 = msm8998_usb3_tx_tbl,
1442         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1443         .rx_tbl                 = msm8998_usb3_rx_tbl,
1444         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1445         .pcs_tbl                = msm8998_usb3_pcs_tbl,
1446         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1447         .vreg_list              = qmp_phy_vreg_l,
1448         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1449         .regs                   = qmp_v3_usb3phy_regs_layout,
1450 };
1451
1452 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1453         .lanes                  = 1,
1454
1455         .offsets                = &qmp_usb_offsets_v4,
1456
1457         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1458         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1459         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
1460         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1461         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
1462         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1463         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
1464         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1465         .pcs_usb_tbl            = sm8150_usb3_uniphy_pcs_usb_tbl,
1466         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1467         .vreg_list              = qmp_phy_vreg_l,
1468         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1469         .regs                   = qmp_v4_usb3phy_regs_layout,
1470         .pcs_usb_offset         = 0x600,
1471
1472         .has_pwrdn_delay        = true,
1473 };
1474
1475 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1476         .lanes                  = 1,
1477
1478         .offsets                = &qmp_usb_offsets_v4,
1479
1480         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1481         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1482         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
1483         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1484         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
1485         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1486         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1487         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1488         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1489         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1490         .vreg_list              = qmp_phy_vreg_l,
1491         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1492         .regs                   = qmp_v4_usb3phy_regs_layout,
1493         .pcs_usb_offset         = 0x600,
1494
1495         .has_pwrdn_delay        = true,
1496 };
1497
1498 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1499         .lanes                  = 1,
1500
1501         .offsets                = &qmp_usb_offsets_v4,
1502
1503         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1504         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1505         .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
1506         .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1507         .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
1508         .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1509         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1510         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1511         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1512         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1513         .vreg_list              = qmp_phy_vreg_l,
1514         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1515         .regs                   = qmp_v4_usb3phy_regs_layout,
1516         .pcs_usb_offset         = 0x600,
1517
1518         .has_pwrdn_delay        = true,
1519 };
1520
1521 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1522         .lanes                  = 1,
1523
1524         .offsets                = &qmp_usb_offsets_v5,
1525
1526         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1527         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1528         .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
1529         .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1530         .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
1531         .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1532         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1533         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1534         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1535         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1536         .vreg_list              = qmp_phy_vreg_l,
1537         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1538         .regs                   = qmp_v5_usb3phy_regs_layout,
1539         .pcs_usb_offset         = 0x1000,
1540
1541         .has_pwrdn_delay        = true,
1542 };
1543
1544 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1545         .lanes                  = 1,
1546
1547         .offsets                = &qmp_usb_offsets_v5,
1548
1549         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1550         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1551         .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
1552         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1553         .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
1554         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1555         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1556         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1557         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1558         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1559         .vreg_list              = qmp_phy_vreg_l,
1560         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1561         .regs                   = qmp_v5_usb3phy_regs_layout,
1562         .pcs_usb_offset         = 0x1000,
1563
1564         .has_pwrdn_delay        = true,
1565 };
1566
1567 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1568         .lanes                  = 2,
1569
1570         .offsets                = &qmp_usb_offsets_v3_qcm2290,
1571
1572         .serdes_tbl             = qcm2290_usb3_serdes_tbl,
1573         .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1574         .tx_tbl                 = qcm2290_usb3_tx_tbl,
1575         .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1576         .rx_tbl                 = qcm2290_usb3_rx_tbl,
1577         .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1578         .pcs_tbl                = qcm2290_usb3_pcs_tbl,
1579         .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1580         .vreg_list              = qmp_phy_vreg_l,
1581         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1582         .regs                   = qmp_v3_usb3phy_regs_layout_qcm2290,
1583 };
1584
1585 static void qmp_usb_configure_lane(void __iomem *base,
1586                                         const struct qmp_phy_init_tbl tbl[],
1587                                         int num,
1588                                         u8 lane_mask)
1589 {
1590         int i;
1591         const struct qmp_phy_init_tbl *t = tbl;
1592
1593         if (!t)
1594                 return;
1595
1596         for (i = 0; i < num; i++, t++) {
1597                 if (!(t->lane_mask & lane_mask))
1598                         continue;
1599
1600                 writel(t->val, base + t->offset);
1601         }
1602 }
1603
1604 static void qmp_usb_configure(void __iomem *base,
1605                                    const struct qmp_phy_init_tbl tbl[],
1606                                    int num)
1607 {
1608         qmp_usb_configure_lane(base, tbl, num, 0xff);
1609 }
1610
1611 static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1612 {
1613         const struct qmp_phy_cfg *cfg = qmp->cfg;
1614         void __iomem *serdes = qmp->serdes;
1615         const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1616         int serdes_tbl_num = cfg->serdes_tbl_num;
1617
1618         qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1619
1620         return 0;
1621 }
1622
1623 static int qmp_usb_init(struct phy *phy)
1624 {
1625         struct qmp_usb *qmp = phy_get_drvdata(phy);
1626         const struct qmp_phy_cfg *cfg = qmp->cfg;
1627         void __iomem *pcs = qmp->pcs;
1628         int ret;
1629
1630         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1631         if (ret) {
1632                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1633                 return ret;
1634         }
1635
1636         ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1637         if (ret) {
1638                 dev_err(qmp->dev, "reset assert failed\n");
1639                 goto err_disable_regulators;
1640         }
1641
1642         ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
1643         if (ret) {
1644                 dev_err(qmp->dev, "reset deassert failed\n");
1645                 goto err_disable_regulators;
1646         }
1647
1648         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1649         if (ret)
1650                 goto err_assert_reset;
1651
1652         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1653
1654         return 0;
1655
1656 err_assert_reset:
1657         reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1658 err_disable_regulators:
1659         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1660
1661         return ret;
1662 }
1663
1664 static int qmp_usb_exit(struct phy *phy)
1665 {
1666         struct qmp_usb *qmp = phy_get_drvdata(phy);
1667         const struct qmp_phy_cfg *cfg = qmp->cfg;
1668
1669         reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1670
1671         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1672
1673         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1674
1675         return 0;
1676 }
1677
1678 static int qmp_usb_power_on(struct phy *phy)
1679 {
1680         struct qmp_usb *qmp = phy_get_drvdata(phy);
1681         const struct qmp_phy_cfg *cfg = qmp->cfg;
1682         void __iomem *tx = qmp->tx;
1683         void __iomem *rx = qmp->rx;
1684         void __iomem *pcs = qmp->pcs;
1685         void __iomem *pcs_usb = qmp->pcs_usb;
1686         void __iomem *status;
1687         unsigned int val;
1688         int ret;
1689
1690         qmp_usb_serdes_init(qmp);
1691
1692         ret = clk_prepare_enable(qmp->pipe_clk);
1693         if (ret) {
1694                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1695                 return ret;
1696         }
1697
1698         /* Tx, Rx, and PCS configurations */
1699         qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1700         qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1701
1702         if (cfg->lanes >= 2) {
1703                 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
1704                 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
1705         }
1706
1707         qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1708
1709         if (pcs_usb)
1710                 qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
1711
1712         if (cfg->has_pwrdn_delay)
1713                 usleep_range(10, 20);
1714
1715         /* Pull PHY out of reset state */
1716         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1717
1718         /* start SerDes and Phy-Coding-Sublayer */
1719         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
1720
1721         status = pcs + cfg->regs[QPHY_PCS_STATUS];
1722         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
1723                                  PHY_INIT_COMPLETE_TIMEOUT);
1724         if (ret) {
1725                 dev_err(qmp->dev, "phy initialization timed-out\n");
1726                 goto err_disable_pipe_clk;
1727         }
1728
1729         return 0;
1730
1731 err_disable_pipe_clk:
1732         clk_disable_unprepare(qmp->pipe_clk);
1733
1734         return ret;
1735 }
1736
1737 static int qmp_usb_power_off(struct phy *phy)
1738 {
1739         struct qmp_usb *qmp = phy_get_drvdata(phy);
1740         const struct qmp_phy_cfg *cfg = qmp->cfg;
1741
1742         clk_disable_unprepare(qmp->pipe_clk);
1743
1744         /* PHY reset */
1745         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1746
1747         /* stop SerDes and Phy-Coding-Sublayer */
1748         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
1749                         SERDES_START | PCS_START);
1750
1751         /* Put PHY into POWER DOWN state: active low */
1752         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1753                         SW_PWRDN);
1754
1755         return 0;
1756 }
1757
1758 static int qmp_usb_enable(struct phy *phy)
1759 {
1760         int ret;
1761
1762         ret = qmp_usb_init(phy);
1763         if (ret)
1764                 return ret;
1765
1766         ret = qmp_usb_power_on(phy);
1767         if (ret)
1768                 qmp_usb_exit(phy);
1769
1770         return ret;
1771 }
1772
1773 static int qmp_usb_disable(struct phy *phy)
1774 {
1775         int ret;
1776
1777         ret = qmp_usb_power_off(phy);
1778         if (ret)
1779                 return ret;
1780         return qmp_usb_exit(phy);
1781 }
1782
1783 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1784 {
1785         struct qmp_usb *qmp = phy_get_drvdata(phy);
1786
1787         qmp->mode = mode;
1788
1789         return 0;
1790 }
1791
1792 static const struct phy_ops qmp_usb_phy_ops = {
1793         .init           = qmp_usb_enable,
1794         .exit           = qmp_usb_disable,
1795         .set_mode       = qmp_usb_set_mode,
1796         .owner          = THIS_MODULE,
1797 };
1798
1799 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
1800 {
1801         const struct qmp_phy_cfg *cfg = qmp->cfg;
1802         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1803         void __iomem *pcs_misc = qmp->pcs_misc;
1804         u32 intr_mask;
1805
1806         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1807             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1808                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1809         else
1810                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1811
1812         /* Clear any pending interrupts status */
1813         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1814         /* Writing 1 followed by 0 clears the interrupt */
1815         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1816
1817         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1818                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1819
1820         /* Enable required PHY autonomous mode interrupts */
1821         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1822
1823         /* Enable i/o clamp_n for autonomous mode */
1824         if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1825                 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1826 }
1827
1828 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
1829 {
1830         const struct qmp_phy_cfg *cfg = qmp->cfg;
1831         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1832         void __iomem *pcs_misc = qmp->pcs_misc;
1833
1834         /* Disable i/o clamp_n on resume for normal mode */
1835         if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1836                 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1837
1838         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1839                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1840
1841         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1842         /* Writing 1 followed by 0 clears the interrupt */
1843         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1844 }
1845
1846 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
1847 {
1848         struct qmp_usb *qmp = dev_get_drvdata(dev);
1849
1850         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1851
1852         if (!qmp->phy->init_count) {
1853                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1854                 return 0;
1855         }
1856
1857         qmp_usb_enable_autonomous_mode(qmp);
1858
1859         clk_disable_unprepare(qmp->pipe_clk);
1860         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1861
1862         return 0;
1863 }
1864
1865 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
1866 {
1867         struct qmp_usb *qmp = dev_get_drvdata(dev);
1868         int ret = 0;
1869
1870         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1871
1872         if (!qmp->phy->init_count) {
1873                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1874                 return 0;
1875         }
1876
1877         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1878         if (ret)
1879                 return ret;
1880
1881         ret = clk_prepare_enable(qmp->pipe_clk);
1882         if (ret) {
1883                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1884                 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1885                 return ret;
1886         }
1887
1888         qmp_usb_disable_autonomous_mode(qmp);
1889
1890         return 0;
1891 }
1892
1893 static const struct dev_pm_ops qmp_usb_pm_ops = {
1894         SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
1895                            qmp_usb_runtime_resume, NULL)
1896 };
1897
1898 static int qmp_usb_vreg_init(struct qmp_usb *qmp)
1899 {
1900         const struct qmp_phy_cfg *cfg = qmp->cfg;
1901         struct device *dev = qmp->dev;
1902         int num = cfg->num_vregs;
1903         int i;
1904
1905         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1906         if (!qmp->vregs)
1907                 return -ENOMEM;
1908
1909         for (i = 0; i < num; i++)
1910                 qmp->vregs[i].supply = cfg->vreg_list[i];
1911
1912         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1913 }
1914
1915 static int qmp_usb_reset_init(struct qmp_usb *qmp,
1916                               const char *const *reset_list,
1917                               int num_resets)
1918 {
1919         struct device *dev = qmp->dev;
1920         int i;
1921         int ret;
1922
1923         qmp->resets = devm_kcalloc(dev, num_resets,
1924                                    sizeof(*qmp->resets), GFP_KERNEL);
1925         if (!qmp->resets)
1926                 return -ENOMEM;
1927
1928         for (i = 0; i < num_resets; i++)
1929                 qmp->resets[i].id = reset_list[i];
1930
1931         qmp->num_resets = num_resets;
1932
1933         ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
1934         if (ret)
1935                 return dev_err_probe(dev, ret, "failed to get resets\n");
1936
1937         return 0;
1938 }
1939
1940 static int qmp_usb_clk_init(struct qmp_usb *qmp)
1941 {
1942         struct device *dev = qmp->dev;
1943         int num = ARRAY_SIZE(qmp_usb_phy_clk_l);
1944         int i;
1945
1946         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1947         if (!qmp->clks)
1948                 return -ENOMEM;
1949
1950         for (i = 0; i < num; i++)
1951                 qmp->clks[i].id = qmp_usb_phy_clk_l[i];
1952
1953         qmp->num_clks = num;
1954
1955         return devm_clk_bulk_get_optional(dev, num, qmp->clks);
1956 }
1957
1958 static void phy_clk_release_provider(void *res)
1959 {
1960         of_clk_del_provider(res);
1961 }
1962
1963 /*
1964  * Register a fixed rate pipe clock.
1965  *
1966  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1967  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1968  * by the PHY driver for its operations.
1969  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1970  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1971  * Below picture shows this relationship.
1972  *
1973  *         +---------------+
1974  *         |   PHY block   |<<---------------------------------------+
1975  *         |               |                                         |
1976  *         |   +-------+   |                   +-----+               |
1977  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1978  *    clk  |   +-------+   |                   +-----+
1979  *         +---------------+
1980  */
1981 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
1982 {
1983         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
1984         struct clk_init_data init = { };
1985         int ret;
1986
1987         ret = of_property_read_string(np, "clock-output-names", &init.name);
1988         if (ret) {
1989                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
1990                 return ret;
1991         }
1992
1993         init.ops = &clk_fixed_rate_ops;
1994
1995         /* controllers using QMP phys use 125MHz pipe clock interface */
1996         fixed->fixed_rate = 125000000;
1997         fixed->hw.init = &init;
1998
1999         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2000         if (ret)
2001                 return ret;
2002
2003         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2004         if (ret)
2005                 return ret;
2006
2007         /*
2008          * Roll a devm action because the clock provider is the child node, but
2009          * the child node is not actually a device.
2010          */
2011         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2012 }
2013
2014 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2015                                         int index, bool exclusive)
2016 {
2017         struct resource res;
2018
2019         if (!exclusive) {
2020                 if (of_address_to_resource(np, index, &res))
2021                         return IOMEM_ERR_PTR(-EINVAL);
2022
2023                 return devm_ioremap(dev, res.start, resource_size(&res));
2024         }
2025
2026         return devm_of_iomap(dev, np, index, NULL);
2027 }
2028
2029 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2030 {
2031         struct platform_device *pdev = to_platform_device(qmp->dev);
2032         const struct qmp_phy_cfg *cfg = qmp->cfg;
2033         struct device *dev = qmp->dev;
2034         bool exclusive = true;
2035         int ret;
2036
2037         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2038         if (IS_ERR(qmp->serdes))
2039                 return PTR_ERR(qmp->serdes);
2040
2041         /*
2042          * FIXME: These bindings should be fixed to not rely on overlapping
2043          *        mappings for PCS.
2044          */
2045         if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2046                 exclusive = false;
2047         if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2048                 exclusive = false;
2049
2050         /*
2051          * Get memory resources for the PHY:
2052          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2053          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2054          * For single lane PHYs: pcs_misc (optional) -> 3.
2055          */
2056         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2057         if (IS_ERR(qmp->tx))
2058                 return PTR_ERR(qmp->tx);
2059
2060         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2061         if (IS_ERR(qmp->rx))
2062                 return PTR_ERR(qmp->rx);
2063
2064         qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2065         if (IS_ERR(qmp->pcs))
2066                 return PTR_ERR(qmp->pcs);
2067
2068         if (cfg->pcs_usb_offset)
2069                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2070
2071         if (cfg->lanes >= 2) {
2072                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2073                 if (IS_ERR(qmp->tx2))
2074                         return PTR_ERR(qmp->tx2);
2075
2076                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2077                 if (IS_ERR(qmp->rx2))
2078                         return PTR_ERR(qmp->rx2);
2079
2080                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2081         } else {
2082                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2083         }
2084
2085         if (IS_ERR(qmp->pcs_misc)) {
2086                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2087                 qmp->pcs_misc = NULL;
2088         }
2089
2090         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2091         if (IS_ERR(qmp->pipe_clk)) {
2092                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2093                                      "failed to get pipe clock\n");
2094         }
2095
2096         ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
2097         if (ret < 0)
2098                 return ret;
2099
2100         qmp->num_clks = ret;
2101
2102         ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,
2103                                  ARRAY_SIZE(usb3phy_legacy_reset_l));
2104         if (ret)
2105                 return ret;
2106
2107         return 0;
2108 }
2109
2110 static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2111 {
2112         struct platform_device *pdev = to_platform_device(qmp->dev);
2113         const struct qmp_phy_cfg *cfg = qmp->cfg;
2114         const struct qmp_usb_offsets *offs = cfg->offsets;
2115         struct device *dev = qmp->dev;
2116         void __iomem *base;
2117         int ret;
2118
2119         if (!offs)
2120                 return -EINVAL;
2121
2122         base = devm_platform_ioremap_resource(pdev, 0);
2123         if (IS_ERR(base))
2124                 return PTR_ERR(base);
2125
2126         qmp->serdes = base + offs->serdes;
2127         qmp->pcs = base + offs->pcs;
2128         if (offs->pcs_usb)
2129                 qmp->pcs_usb = base + offs->pcs_usb;
2130         if (offs->pcs_misc)
2131                 qmp->pcs_misc = base + offs->pcs_misc;
2132         qmp->tx = base + offs->tx;
2133         qmp->rx = base + offs->rx;
2134
2135         if (cfg->lanes >= 2) {
2136                 qmp->tx2 = base + offs->tx2;
2137                 qmp->rx2 = base + offs->rx2;
2138         }
2139
2140         ret = qmp_usb_clk_init(qmp);
2141         if (ret)
2142                 return ret;
2143
2144         qmp->pipe_clk = devm_clk_get(dev, "pipe");
2145         if (IS_ERR(qmp->pipe_clk)) {
2146                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2147                                      "failed to get pipe clock\n");
2148         }
2149
2150         ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,
2151                                  ARRAY_SIZE(usb3phy_reset_l));
2152         if (ret)
2153                 return ret;
2154
2155         return 0;
2156 }
2157
2158 static int qmp_usb_probe(struct platform_device *pdev)
2159 {
2160         struct device *dev = &pdev->dev;
2161         struct phy_provider *phy_provider;
2162         struct device_node *np;
2163         struct qmp_usb *qmp;
2164         int ret;
2165
2166         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2167         if (!qmp)
2168                 return -ENOMEM;
2169
2170         qmp->dev = dev;
2171
2172         qmp->cfg = of_device_get_match_data(dev);
2173         if (!qmp->cfg)
2174                 return -EINVAL;
2175
2176         ret = qmp_usb_vreg_init(qmp);
2177         if (ret)
2178                 return ret;
2179
2180         /* Check for legacy binding with child node. */
2181         np = of_get_next_available_child(dev->of_node, NULL);
2182         if (np) {
2183                 ret = qmp_usb_parse_dt_legacy(qmp, np);
2184         } else {
2185                 np = of_node_get(dev->of_node);
2186                 ret = qmp_usb_parse_dt(qmp);
2187         }
2188         if (ret)
2189                 goto err_node_put;
2190
2191         pm_runtime_set_active(dev);
2192         ret = devm_pm_runtime_enable(dev);
2193         if (ret)
2194                 goto err_node_put;
2195         /*
2196          * Prevent runtime pm from being ON by default. Users can enable
2197          * it using power/control in sysfs.
2198          */
2199         pm_runtime_forbid(dev);
2200
2201         ret = phy_pipe_clk_register(qmp, np);
2202         if (ret)
2203                 goto err_node_put;
2204
2205         qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2206         if (IS_ERR(qmp->phy)) {
2207                 ret = PTR_ERR(qmp->phy);
2208                 dev_err(dev, "failed to create PHY: %d\n", ret);
2209                 goto err_node_put;
2210         }
2211
2212         phy_set_drvdata(qmp->phy, qmp);
2213
2214         of_node_put(np);
2215
2216         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2217
2218         return PTR_ERR_OR_ZERO(phy_provider);
2219
2220 err_node_put:
2221         of_node_put(np);
2222         return ret;
2223 }
2224
2225 static const struct of_device_id qmp_usb_of_match_table[] = {
2226         {
2227                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2228                 .data = &ipq8074_usb3phy_cfg,
2229         }, {
2230                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2231                 .data = &ipq8074_usb3phy_cfg,
2232         }, {
2233                 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2234                 .data = &ipq9574_usb3phy_cfg,
2235         }, {
2236                 .compatible = "qcom,msm8996-qmp-usb3-phy",
2237                 .data = &msm8996_usb3phy_cfg,
2238         }, {
2239                 .compatible = "qcom,msm8998-qmp-usb3-phy",
2240                 .data = &msm8998_usb3phy_cfg,
2241         }, {
2242                 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2243                 .data = &qcm2290_usb3phy_cfg,
2244         }, {
2245                 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2246                 .data = &sa8775p_usb3_uniphy_cfg,
2247         }, {
2248                 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2249                 .data = &sc8280xp_usb3_uniphy_cfg,
2250         }, {
2251                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2252                 .data = &qmp_v3_usb3_uniphy_cfg,
2253         }, {
2254                 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2255                 .data = &sdx55_usb3_uniphy_cfg,
2256         }, {
2257                 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2258                 .data = &sdx65_usb3_uniphy_cfg,
2259         }, {
2260                 .compatible = "qcom,sm6115-qmp-usb3-phy",
2261                 .data = &qcm2290_usb3phy_cfg,
2262         }, {
2263                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2264                 .data = &sm8150_usb3_uniphy_cfg,
2265         }, {
2266                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2267                 .data = &sm8250_usb3_uniphy_cfg,
2268         }, {
2269                 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2270                 .data = &sm8350_usb3_uniphy_cfg,
2271         },
2272         { },
2273 };
2274 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2275
2276 static struct platform_driver qmp_usb_driver = {
2277         .probe          = qmp_usb_probe,
2278         .driver = {
2279                 .name   = "qcom-qmp-usb-phy",
2280                 .pm     = &qmp_usb_pm_ops,
2281                 .of_match_table = qmp_usb_of_match_table,
2282         },
2283 };
2284
2285 module_platform_driver(qmp_usb_driver);
2286
2287 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
2288 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2289 MODULE_LICENSE("GPL v2");