drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include <ufs/unipro.h>
  23 #include "phy-qcom-qmp.h"
  24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
  25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
  26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
  27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
  28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
  29
  30 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
  31
  32 /* QPHY_SW_RESET bit */
  33 #define SW_RESET                                BIT(0)
  34 /* QPHY_POWER_DOWN_CONTROL */
  35 #define SW_PWRDN                                BIT(0)
  36 /* QPHY_START_CONTROL bits */
  37 #define SERDES_START                            BIT(0)
  38 #define PCS_START                               BIT(1)
  39 /* QPHY_PCS_READY_STATUS bit */
  40 #define PCS_READY                               BIT(0)
  41
  42 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  43
  44 struct qmp_phy_init_tbl {
  45         unsigned int offset;
  46         unsigned int val;
  47         /*
  48          * mask of lanes for which this register is written
  49          * for cases when second lane needs different values
  50          */
  51         u8 lane_mask;
  52 };
  53
  54 #define QMP_PHY_INIT_CFG(o, v)          \
  55         {                               \
  56                 .offset = o,            \
  57                 .val = v,               \
  58                 .lane_mask = 0xff,      \
  59         }
  60
  61 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  62         {                               \
  63                 .offset = o,            \
  64                 .val = v,               \
  65                 .lane_mask = l,         \
  66         }
  67
  68 /* set of registers with offsets different per-PHY */
  69 enum qphy_reg_layout {
  70         /* PCS registers */
  71         QPHY_SW_RESET,
  72         QPHY_START_CTRL,
  73         QPHY_PCS_READY_STATUS,
  74         QPHY_PCS_POWER_DOWN_CONTROL,
  75         /* Keep last to ensure regs_layout arrays are properly initialized */
  76         QPHY_LAYOUT_SIZE
  77 };
  78
  79 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
  80         [QPHY_START_CTRL]               = QPHY_V2_PCS_UFS_PHY_START,
  81         [QPHY_PCS_READY_STATUS]         = QPHY_V2_PCS_UFS_READY_STATUS,
  82         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
  83 };
  84
  85 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
  86         [QPHY_START_CTRL]               = QPHY_V3_PCS_UFS_PHY_START,
  87         [QPHY_PCS_READY_STATUS]         = QPHY_V3_PCS_UFS_READY_STATUS,
  88         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
  89 };
  90
  91 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
  92         [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
  93         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
  94         [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
  95         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
  96 };
  97
  98 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
  99         [QPHY_START_CTRL]               = QPHY_V5_PCS_UFS_PHY_START,
 100         [QPHY_PCS_READY_STATUS]         = QPHY_V5_PCS_UFS_READY_STATUS,
 101         [QPHY_SW_RESET]                 = QPHY_V5_PCS_UFS_SW_RESET,
 102         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
 103 };
 104
 105 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
 106         [QPHY_START_CTRL]               = QPHY_V6_PCS_UFS_PHY_START,
 107         [QPHY_PCS_READY_STATUS]         = QPHY_V6_PCS_UFS_READY_STATUS,
 108         [QPHY_SW_RESET]                 = QPHY_V6_PCS_UFS_SW_RESET,
 109         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
 110 };
 111
 112 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
 113         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 114         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 115         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 116         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 117         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 118         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 119         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 120         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 121         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 122         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 123         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 124         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 125         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 126         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 127         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 128         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 129         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 130         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 131         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 132         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 133         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 134         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 135         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 136         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 137         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 138         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 139         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 140         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 141         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 142         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 143         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 144         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 145         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 146         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 147         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 148         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 149         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 150         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 151         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 152         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 153         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 154         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 155         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 156         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 157         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 158         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 159 };
 160
 161 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
 162         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 163         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 164 };
 165
 166 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
 167         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 168         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 169         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 170         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 171         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 172         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 173         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 174         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 175         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 176         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 177         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 178 };
 179
 180 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
 181         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 182         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 183         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 184         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 185         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
 186         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
 187 };
 188
 189 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
 190         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 191         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 192         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 193         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 194         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 195         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 196         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 197         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 198         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
 199         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 200         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 201         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
 202         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 203         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 204         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
 205         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 206         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
 207         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 208         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 209         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
 210         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
 211         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
 212         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
 213         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
 214         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
 215         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
 216         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 217         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 218         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 219         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 220         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 221         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 222         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 223         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 224         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 225 };
 226
 227 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
 228         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 229         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 230         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 231         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 232         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 233         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 234         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 235         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
 236         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
 237         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
 238         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
 239         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
 240         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
 241         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
 242 };
 243
 244 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
 245         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 246         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 247         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 248         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 249         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 250         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 251         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 252         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 253         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 254         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 255         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 256         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 257         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 258         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
 260         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
 261         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 262         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 263         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 264         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 265         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 266         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 267         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 268         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 269         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 270         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
 271         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 272         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 273         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 274         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 275         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 276         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 277         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 278         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 279         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 280         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 281         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 282         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
 283 };
 284
 285 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
 286         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 294         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 295         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 296         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 297         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 302         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 304         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 305         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 306         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 307         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 308         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 309         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 310         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 311         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 312         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
 336 };
 337
 338 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
 339         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
 340 };
 341
 342 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
 343         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 344         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 345 };
 346
 347 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
 348         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 349         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
 350         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
 351         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
 352         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 353         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
 354         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
 355         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
 356         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
 357         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
 358         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
 359         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 360         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 361         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
 362         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
 363 };
 364
 365 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
 366         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
 367         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 368         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 369         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 370         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
 371         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 372         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
 373         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
 374         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
 375 };
 376
 377 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
 378         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 379         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 380         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 381         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 382         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 383         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 385         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 386         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 388         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
 414 };
 415
 416 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
 417         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 418 };
 419
 420 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
 421         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 424 };
 425
 426 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
 427         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 429         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 430         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 443 };
 444
 445 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
 446         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 454 };
 455
 456 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
 457         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 458         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 459         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 460         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 461         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 462         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 463         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 464         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 465         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 466         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 467         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 468         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 469         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
 470         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 471         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 472         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 473 };
 474
 475 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
 476         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
 477         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 478         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 479         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 480         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 481         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
 482         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 483         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 484 };
 485
 486 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
 487         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
 488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
 489         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
 490         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
 491         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 492         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 493         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
 494         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 495         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 496         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 497         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 498         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 499         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
 500         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
 501         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
 502         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 503         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
 504         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 505         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
 508         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
 511 };
 512
 513 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
 514         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
 515 };
 516
 517 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
 518         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 519         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 520         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 521         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
 524 };
 525
 526 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
 527         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
 528 };
 529
 530 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 538         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 539         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
 540         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 541         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 542         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
 543         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 544         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 545         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
 546         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 547         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
 548         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 549         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 550         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
 551         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
 552         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
 553         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
 554         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
 555         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
 556         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
 557         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 558         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 559         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 560         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 561         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 562         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 563         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 564         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 565 };
 566
 567 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
 568         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 569         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 570         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 571         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 572         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 573         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 574         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 575         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 576         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 577         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 578         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 579         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
 580         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 581         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 582         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 583         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 584 };
 585
 586 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
 587         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 588         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 589         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 590         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 591         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 592         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 593         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 594 };
 595
 596 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
 597         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
 598         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 599 };
 600
 601 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
 602         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
 603 };
 604
 605 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
 606         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 608         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 609         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 610         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 611         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 612         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
 613         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
 614         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 615         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 616         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 617         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 618         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 619         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 620         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 621         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 622         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
 623         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 624         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 625         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 626         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 627 };
 628
 629 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
 630         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
 631         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
 632         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
 633         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
 634         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
 635         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
 636         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
 637         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 638         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
 639         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
 640         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
 641         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
 642         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
 643         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
 644         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
 645         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 646         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
 647         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
 648         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
 649         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
 650         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
 651         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
 652         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
 653         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
 654 };
 655
 656 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
 657         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
 658 };
 659
 660 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
 661         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 662         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 663         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 664         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 665         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
 666         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 667         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
 668         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 669         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
 670 };
 671
 672 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
 673         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
 674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
 675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 676         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
 677         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
 680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
 682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
 683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
 684         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
 685         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 686         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 687         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 688         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 689         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 690         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 691         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
 692         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 693         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 694         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
 695         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
 696         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
 697         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
 698         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
 699         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
 700         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
 701         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
 702         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
 703         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
 704         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
 705         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
 706         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
 707         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
 708         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
 709         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 710 };
 711
 712 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
 713         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 714         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 715         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 716         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 717         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 718         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 719         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
 720         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 721 };
 722
 723 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
 724         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
 725 };
 726
 727 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
 728         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
 729         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
 730         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 731         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 732         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 733         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
 734         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 735         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 736         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
 737         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
 738         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
 739         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
 740         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
 741         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
 742         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
 743         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
 744         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
 745 };
 746
 747 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
 748         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 749 };
 750
 751 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
 752         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
 753         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 754         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
 755         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
 756         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
 757         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 758         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 759         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
 760         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 761         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
 762         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
 763         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
 764         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
 765         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
 766         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
 767         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
 768         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
 769         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
 770         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
 771         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
 772 };
 773
 774 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
 775         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
 776         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
 777 };
 778
 779 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
 780         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
 781         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
 782         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
 783
 784         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
 785         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
 786         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
 787         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
 788
 789         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
 790         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
 791
 792         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
 793         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
 794         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
 795         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
 796 };
 797
 798 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
 799         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
 800         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 801         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 802         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
 803         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 804 };
 805
 806 struct qmp_ufs_offsets {
 807         u16 serdes;
 808         u16 pcs;
 809         u16 tx;
 810         u16 rx;
 811         u16 tx2;
 812         u16 rx2;
 813 };
 814
 815 struct qmp_phy_cfg_tbls {
 816         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 817         const struct qmp_phy_init_tbl *serdes;
 818         int serdes_num;
 819         const struct qmp_phy_init_tbl *tx;
 820         int tx_num;
 821         const struct qmp_phy_init_tbl *rx;
 822         int rx_num;
 823         const struct qmp_phy_init_tbl *pcs;
 824         int pcs_num;
 825 };
 826
 827 /* struct qmp_phy_cfg - per-PHY initialization config */
 828 struct qmp_phy_cfg {
 829         int lanes;
 830
 831         const struct qmp_ufs_offsets *offsets;
 832
 833         /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
 834         const struct qmp_phy_cfg_tbls tbls;
 835         /* Additional sequence for HS Series B */
 836         const struct qmp_phy_cfg_tbls tbls_hs_b;
 837         /* Additional sequence for HS G4 */
 838         const struct qmp_phy_cfg_tbls tbls_hs_g4;
 839
 840         /* clock ids to be requested */
 841         const char * const *clk_list;
 842         int num_clks;
 843         /* regulators to be requested */
 844         const char * const *vreg_list;
 845         int num_vregs;
 846
 847         /* array of registers with different offsets */
 848         const unsigned int *regs;
 849
 850         /* true, if PCS block has no separate SW_RESET register */
 851         bool no_pcs_sw_reset;
 852 };
 853
 854 struct qmp_ufs {
 855         struct device *dev;
 856
 857         const struct qmp_phy_cfg *cfg;
 858
 859         void __iomem *serdes;
 860         void __iomem *pcs;
 861         void __iomem *pcs_misc;
 862         void __iomem *tx;
 863         void __iomem *rx;
 864         void __iomem *tx2;
 865         void __iomem *rx2;
 866
 867         struct clk_bulk_data *clks;
 868         struct regulator_bulk_data *vregs;
 869         struct reset_control *ufs_reset;
 870
 871         struct phy *phy;
 872         u32 mode;
 873         u32 submode;
 874 };
 875
 876 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 877 {
 878         u32 reg;
 879
 880         reg = readl(base + offset);
 881         reg |= val;
 882         writel(reg, base + offset);
 883
 884         /* ensure that above write is through */
 885         readl(base + offset);
 886 }
 887
 888 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 889 {
 890         u32 reg;
 891
 892         reg = readl(base + offset);
 893         reg &= ~val;
 894         writel(reg, base + offset);
 895
 896         /* ensure that above write is through */
 897         readl(base + offset);
 898 }
 899
 900 /* list of clocks required by phy */
 901 static const char * const msm8996_ufs_phy_clk_l[] = {
 902         "ref",
 903 };
 904
 905 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
 906 static const char * const sm8450_ufs_phy_clk_l[] = {
 907         "qref", "ref", "ref_aux",
 908 };
 909
 910 static const char * const sdm845_ufs_phy_clk_l[] = {
 911         "ref", "ref_aux",
 912 };
 913
 914 /* list of regulators */
 915 static const char * const qmp_phy_vreg_l[] = {
 916         "vdda-phy", "vdda-pll",
 917 };
 918
 919 static const struct qmp_ufs_offsets qmp_ufs_offsets = {
 920         .serdes         = 0,
 921         .pcs            = 0xc00,
 922         .tx             = 0x400,
 923         .rx             = 0x600,
 924         .tx2            = 0x800,
 925         .rx2            = 0xa00,
 926 };
 927
 928 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
 929         .serdes         = 0,
 930         .pcs            = 0x0400,
 931         .tx             = 0x1000,
 932         .rx             = 0x1200,
 933         .tx2            = 0x1800,
 934         .rx2            = 0x1a00,
 935 };
 936
 937 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
 938         .lanes                  = 1,
 939
 940         .offsets                = &qmp_ufs_offsets,
 941
 942         .tbls = {
 943                 .serdes         = msm8996_ufsphy_serdes,
 944                 .serdes_num     = ARRAY_SIZE(msm8996_ufsphy_serdes),
 945                 .tx             = msm8996_ufsphy_tx,
 946                 .tx_num         = ARRAY_SIZE(msm8996_ufsphy_tx),
 947                 .rx             = msm8996_ufsphy_rx,
 948                 .rx_num         = ARRAY_SIZE(msm8996_ufsphy_rx),
 949         },
 950
 951         .clk_list               = msm8996_ufs_phy_clk_l,
 952         .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
 953
 954         .vreg_list              = qmp_phy_vreg_l,
 955         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 956
 957         .regs                   = ufsphy_v2_regs_layout,
 958
 959         .no_pcs_sw_reset        = true,
 960 };
 961
 962 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
 963         .lanes                  = 2,
 964
 965         .offsets                = &qmp_ufs_offsets,
 966
 967         .tbls = {
 968                 .serdes         = sm8350_ufsphy_serdes,
 969                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
 970                 .tx             = sm8350_ufsphy_tx,
 971                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
 972                 .rx             = sm8350_ufsphy_rx,
 973                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
 974                 .pcs            = sm8350_ufsphy_pcs,
 975                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
 976         },
 977         .tbls_hs_b = {
 978                 .serdes         = sm8350_ufsphy_hs_b_serdes,
 979                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
 980         },
 981         .tbls_hs_g4 = {
 982                 .tx             = sm8350_ufsphy_g4_tx,
 983                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
 984                 .rx             = sm8350_ufsphy_g4_rx,
 985                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
 986                 .pcs            = sm8350_ufsphy_g4_pcs,
 987                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
 988         },
 989         .clk_list               = sm8450_ufs_phy_clk_l,
 990         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
 991         .vreg_list              = qmp_phy_vreg_l,
 992         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 993         .regs                   = ufsphy_v5_regs_layout,
 994 };
 995
 996 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
 997         .lanes                  = 2,
 998
 999         .offsets                = &qmp_ufs_offsets,
1000
1001         .tbls = {
1002                 .serdes         = sm8150_ufsphy_serdes,
1003                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1004                 .tx             = sc7280_ufsphy_tx,
1005                 .tx_num         = ARRAY_SIZE(sc7280_ufsphy_tx),
1006                 .rx             = sc7280_ufsphy_rx,
1007                 .rx_num         = ARRAY_SIZE(sc7280_ufsphy_rx),
1008                 .pcs            = sc7280_ufsphy_pcs,
1009                 .pcs_num        = ARRAY_SIZE(sc7280_ufsphy_pcs),
1010         },
1011         .tbls_hs_b = {
1012                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1013                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1014         },
1015         .tbls_hs_g4 = {
1016                 .tx             = sm8250_ufsphy_hs_g4_tx,
1017                 .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1018                 .rx             = sc7280_ufsphy_hs_g4_rx,
1019                 .rx_num         = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
1020                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1021                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1022         },
1023         .clk_list               = sm8450_ufs_phy_clk_l,
1024         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1025         .vreg_list              = qmp_phy_vreg_l,
1026         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1027         .regs                   = ufsphy_v4_regs_layout,
1028 };
1029
1030 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
1031         .lanes                  = 2,
1032
1033         .offsets                = &qmp_ufs_offsets,
1034
1035         .tbls = {
1036                 .serdes         = sm8350_ufsphy_serdes,
1037                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1038                 .tx             = sm8350_ufsphy_tx,
1039                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1040                 .rx             = sm8350_ufsphy_rx,
1041                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1042                 .pcs            = sm8350_ufsphy_pcs,
1043                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1044         },
1045         .tbls_hs_b = {
1046                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1047                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1048         },
1049         .tbls_hs_g4 = {
1050                 .tx             = sm8350_ufsphy_g4_tx,
1051                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1052                 .rx             = sm8350_ufsphy_g4_rx,
1053                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1054                 .pcs            = sm8350_ufsphy_g4_pcs,
1055                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1056         },
1057         .clk_list               = sdm845_ufs_phy_clk_l,
1058         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1059         .vreg_list              = qmp_phy_vreg_l,
1060         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1061         .regs                   = ufsphy_v5_regs_layout,
1062 };
1063
1064 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1065         .lanes                  = 2,
1066
1067         .offsets                = &qmp_ufs_offsets,
1068
1069         .tbls = {
1070                 .serdes         = sdm845_ufsphy_serdes,
1071                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
1072                 .tx             = sdm845_ufsphy_tx,
1073                 .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
1074                 .rx             = sdm845_ufsphy_rx,
1075                 .rx_num         = ARRAY_SIZE(sdm845_ufsphy_rx),
1076                 .pcs            = sdm845_ufsphy_pcs,
1077                 .pcs_num        = ARRAY_SIZE(sdm845_ufsphy_pcs),
1078         },
1079         .tbls_hs_b = {
1080                 .serdes         = sdm845_ufsphy_hs_b_serdes,
1081                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1082         },
1083         .clk_list               = sdm845_ufs_phy_clk_l,
1084         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1085         .vreg_list              = qmp_phy_vreg_l,
1086         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1087         .regs                   = ufsphy_v3_regs_layout,
1088
1089         .no_pcs_sw_reset        = true,
1090 };
1091
1092 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
1093         .lanes                  = 1,
1094
1095         .offsets                = &qmp_ufs_offsets,
1096
1097         .tbls = {
1098                 .serdes         = sm6115_ufsphy_serdes,
1099                 .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_serdes),
1100                 .tx             = sm6115_ufsphy_tx,
1101                 .tx_num         = ARRAY_SIZE(sm6115_ufsphy_tx),
1102                 .rx             = sm6115_ufsphy_rx,
1103                 .rx_num         = ARRAY_SIZE(sm6115_ufsphy_rx),
1104                 .pcs            = sm6115_ufsphy_pcs,
1105                 .pcs_num        = ARRAY_SIZE(sm6115_ufsphy_pcs),
1106         },
1107         .tbls_hs_b = {
1108                 .serdes         = sm6115_ufsphy_hs_b_serdes,
1109                 .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
1110         },
1111         .clk_list               = sdm845_ufs_phy_clk_l,
1112         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1113         .vreg_list              = qmp_phy_vreg_l,
1114         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1115         .regs                   = ufsphy_v2_regs_layout,
1116
1117         .no_pcs_sw_reset        = true,
1118 };
1119
1120 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
1121         .lanes                  = 1,
1122
1123         .offsets                = &qmp_ufs_offsets,
1124
1125         .tbls = {
1126                 .serdes         = sdm845_ufsphy_serdes,
1127                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
1128                 .tx             = sdm845_ufsphy_tx,
1129                 .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
1130                 .rx             = sm7150_ufsphy_rx,
1131                 .rx_num         = ARRAY_SIZE(sm7150_ufsphy_rx),
1132                 .pcs            = sm7150_ufsphy_pcs,
1133                 .pcs_num        = ARRAY_SIZE(sm7150_ufsphy_pcs),
1134         },
1135         .tbls_hs_b = {
1136                 .serdes         = sdm845_ufsphy_hs_b_serdes,
1137                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1138         },
1139         .clk_list               = sdm845_ufs_phy_clk_l,
1140         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1141         .vreg_list              = qmp_phy_vreg_l,
1142         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1143         .regs                   = ufsphy_v3_regs_layout,
1144
1145         .no_pcs_sw_reset        = true,
1146 };
1147
1148 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1149         .lanes                  = 2,
1150
1151         .offsets                = &qmp_ufs_offsets,
1152
1153         .tbls = {
1154                 .serdes         = sm8150_ufsphy_serdes,
1155                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1156                 .tx             = sm8150_ufsphy_tx,
1157                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
1158                 .rx             = sm8150_ufsphy_rx,
1159                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
1160                 .pcs            = sm8150_ufsphy_pcs,
1161                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
1162         },
1163         .tbls_hs_b = {
1164                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1165                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1166         },
1167         .tbls_hs_g4 = {
1168                 .tx             = sm8150_ufsphy_hs_g4_tx,
1169                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1170                 .rx             = sm8150_ufsphy_hs_g4_rx,
1171                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1172                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1173                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1174         },
1175         .clk_list               = sdm845_ufs_phy_clk_l,
1176         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1177         .vreg_list              = qmp_phy_vreg_l,
1178         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1179         .regs                   = ufsphy_v4_regs_layout,
1180 };
1181
1182 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
1183         .lanes                  = 2,
1184
1185         .offsets                = &qmp_ufs_offsets,
1186
1187         .tbls = {
1188                 .serdes         = sm8150_ufsphy_serdes,
1189                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1190                 .tx             = sm8150_ufsphy_tx,
1191                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
1192                 .rx             = sm8150_ufsphy_rx,
1193                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
1194                 .pcs            = sm8150_ufsphy_pcs,
1195                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
1196         },
1197         .tbls_hs_b = {
1198                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1199                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1200         },
1201         .tbls_hs_g4 = {
1202                 .tx             = sm8250_ufsphy_hs_g4_tx,
1203                 .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1204                 .rx             = sm8250_ufsphy_hs_g4_rx,
1205                 .rx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1206                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1207                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1208         },
1209         .clk_list               = sdm845_ufs_phy_clk_l,
1210         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1211         .vreg_list              = qmp_phy_vreg_l,
1212         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1213         .regs                   = ufsphy_v4_regs_layout,
1214 };
1215
1216 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
1217         .lanes                  = 2,
1218
1219         .offsets                = &qmp_ufs_offsets,
1220
1221         .tbls = {
1222                 .serdes         = sm8350_ufsphy_serdes,
1223                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1224                 .tx             = sm8350_ufsphy_tx,
1225                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1226                 .rx             = sm8350_ufsphy_rx,
1227                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1228                 .pcs            = sm8350_ufsphy_pcs,
1229                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1230         },
1231         .tbls_hs_b = {
1232                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1233                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1234         },
1235         .tbls_hs_g4 = {
1236                 .tx             = sm8350_ufsphy_g4_tx,
1237                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1238                 .rx             = sm8350_ufsphy_g4_rx,
1239                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1240                 .pcs            = sm8350_ufsphy_g4_pcs,
1241                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1242         },
1243         .clk_list               = sdm845_ufs_phy_clk_l,
1244         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1245         .vreg_list              = qmp_phy_vreg_l,
1246         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1247         .regs                   = ufsphy_v5_regs_layout,
1248 };
1249
1250 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
1251         .lanes                  = 2,
1252
1253         .offsets                = &qmp_ufs_offsets,
1254
1255         .tbls = {
1256                 .serdes         = sm8350_ufsphy_serdes,
1257                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1258                 .tx             = sm8350_ufsphy_tx,
1259                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1260                 .rx             = sm8350_ufsphy_rx,
1261                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1262                 .pcs            = sm8350_ufsphy_pcs,
1263                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1264         },
1265         .tbls_hs_b = {
1266                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1267                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1268         },
1269         .tbls_hs_g4 = {
1270                 .tx             = sm8350_ufsphy_g4_tx,
1271                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1272                 .rx             = sm8350_ufsphy_g4_rx,
1273                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1274                 .pcs            = sm8350_ufsphy_g4_pcs,
1275                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1276         },
1277         .clk_list               = sm8450_ufs_phy_clk_l,
1278         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
1279         .vreg_list              = qmp_phy_vreg_l,
1280         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1281         .regs                   = ufsphy_v5_regs_layout,
1282 };
1283
1284 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1285         .lanes                  = 2,
1286
1287         .offsets                = &qmp_ufs_offsets_v6,
1288
1289         .tbls = {
1290                 .serdes         = sm8550_ufsphy_serdes,
1291                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_serdes),
1292                 .tx             = sm8550_ufsphy_tx,
1293                 .tx_num         = ARRAY_SIZE(sm8550_ufsphy_tx),
1294                 .rx             = sm8550_ufsphy_rx,
1295                 .rx_num         = ARRAY_SIZE(sm8550_ufsphy_rx),
1296                 .pcs            = sm8550_ufsphy_pcs,
1297                 .pcs_num        = ARRAY_SIZE(sm8550_ufsphy_pcs),
1298         },
1299         .clk_list               = sdm845_ufs_phy_clk_l,
1300         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
1301         .vreg_list              = qmp_phy_vreg_l,
1302         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1303         .regs                   = ufsphy_v6_regs_layout,
1304 };
1305
1306 static void qmp_ufs_configure_lane(void __iomem *base,
1307                                         const struct qmp_phy_init_tbl tbl[],
1308                                         int num,
1309                                         u8 lane_mask)
1310 {
1311         int i;
1312         const struct qmp_phy_init_tbl *t = tbl;
1313
1314         if (!t)
1315                 return;
1316
1317         for (i = 0; i < num; i++, t++) {
1318                 if (!(t->lane_mask & lane_mask))
1319                         continue;
1320
1321                 writel(t->val, base + t->offset);
1322         }
1323 }
1324
1325 static void qmp_ufs_configure(void __iomem *base,
1326                                    const struct qmp_phy_init_tbl tbl[],
1327                                    int num)
1328 {
1329         qmp_ufs_configure_lane(base, tbl, num, 0xff);
1330 }
1331
1332 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1333 {
1334         void __iomem *serdes = qmp->serdes;
1335
1336         qmp_ufs_configure(serdes, tbls->serdes, tbls->serdes_num);
1337 }
1338
1339 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1340 {
1341         const struct qmp_phy_cfg *cfg = qmp->cfg;
1342         void __iomem *tx = qmp->tx;
1343         void __iomem *rx = qmp->rx;
1344
1345         qmp_ufs_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1346         qmp_ufs_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1347
1348         if (cfg->lanes >= 2) {
1349                 qmp_ufs_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1350                 qmp_ufs_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1351         }
1352 }
1353
1354 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1355 {
1356         void __iomem *pcs = qmp->pcs;
1357
1358         qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
1359 }
1360
1361 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1362 {
1363         qmp_ufs_serdes_init(qmp, &cfg->tbls);
1364         if (qmp->mode == PHY_MODE_UFS_HS_B)
1365                 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1366         qmp_ufs_lanes_init(qmp, &cfg->tbls);
1367         if (qmp->submode == UFS_HS_G4)
1368                 qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
1369         qmp_ufs_pcs_init(qmp, &cfg->tbls);
1370         if (qmp->submode == UFS_HS_G4)
1371                 qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
1372 }
1373
1374 static int qmp_ufs_com_init(struct qmp_ufs *qmp)
1375 {
1376         const struct qmp_phy_cfg *cfg = qmp->cfg;
1377         void __iomem *pcs = qmp->pcs;
1378         int ret;
1379
1380         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1381         if (ret) {
1382                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1383                 return ret;
1384         }
1385
1386         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1387         if (ret)
1388                 goto err_disable_regulators;
1389
1390         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1391
1392         return 0;
1393
1394 err_disable_regulators:
1395         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1396
1397         return ret;
1398 }
1399
1400 static int qmp_ufs_com_exit(struct qmp_ufs *qmp)
1401 {
1402         const struct qmp_phy_cfg *cfg = qmp->cfg;
1403
1404         reset_control_assert(qmp->ufs_reset);
1405
1406         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1407
1408         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1409
1410         return 0;
1411 }
1412
1413 static int qmp_ufs_init(struct phy *phy)
1414 {
1415         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1416         const struct qmp_phy_cfg *cfg = qmp->cfg;
1417         int ret;
1418         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1419
1420         if (cfg->no_pcs_sw_reset) {
1421                 /*
1422                  * Get UFS reset, which is delayed until now to avoid a
1423                  * circular dependency where UFS needs its PHY, but the PHY
1424                  * needs this UFS reset.
1425                  */
1426                 if (!qmp->ufs_reset) {
1427                         qmp->ufs_reset =
1428                                 devm_reset_control_get_exclusive(qmp->dev,
1429                                                                  "ufsphy");
1430
1431                         if (IS_ERR(qmp->ufs_reset)) {
1432                                 ret = PTR_ERR(qmp->ufs_reset);
1433                                 dev_err(qmp->dev,
1434                                         "failed to get UFS reset: %d\n",
1435                                         ret);
1436
1437                                 qmp->ufs_reset = NULL;
1438                                 return ret;
1439                         }
1440                 }
1441
1442                 ret = reset_control_assert(qmp->ufs_reset);
1443                 if (ret)
1444                         return ret;
1445         }
1446
1447         ret = qmp_ufs_com_init(qmp);
1448         if (ret)
1449                 return ret;
1450
1451         return 0;
1452 }
1453
1454 static int qmp_ufs_power_on(struct phy *phy)
1455 {
1456         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1457         const struct qmp_phy_cfg *cfg = qmp->cfg;
1458         void __iomem *pcs = qmp->pcs;
1459         void __iomem *status;
1460         unsigned int val;
1461         int ret;
1462
1463         qmp_ufs_init_registers(qmp, cfg);
1464
1465         ret = reset_control_deassert(qmp->ufs_reset);
1466         if (ret)
1467                 return ret;
1468
1469         /* Pull PHY out of reset state */
1470         if (!cfg->no_pcs_sw_reset)
1471                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1472
1473         /* start SerDes */
1474         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1475
1476         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1477         ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
1478                                  PHY_INIT_COMPLETE_TIMEOUT);
1479         if (ret) {
1480                 dev_err(qmp->dev, "phy initialization timed-out\n");
1481                 return ret;
1482         }
1483
1484         return 0;
1485 }
1486
1487 static int qmp_ufs_power_off(struct phy *phy)
1488 {
1489         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1490         const struct qmp_phy_cfg *cfg = qmp->cfg;
1491
1492         /* PHY reset */
1493         if (!cfg->no_pcs_sw_reset)
1494                 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1495
1496         /* stop SerDes */
1497         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1498
1499         /* Put PHY into POWER DOWN state: active low */
1500         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1501                         SW_PWRDN);
1502
1503         return 0;
1504 }
1505
1506 static int qmp_ufs_exit(struct phy *phy)
1507 {
1508         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1509
1510         qmp_ufs_com_exit(qmp);
1511
1512         return 0;
1513 }
1514
1515 static int qmp_ufs_enable(struct phy *phy)
1516 {
1517         int ret;
1518
1519         ret = qmp_ufs_init(phy);
1520         if (ret)
1521                 return ret;
1522
1523         ret = qmp_ufs_power_on(phy);
1524         if (ret)
1525                 qmp_ufs_exit(phy);
1526
1527         return ret;
1528 }
1529
1530 static int qmp_ufs_disable(struct phy *phy)
1531 {
1532         int ret;
1533
1534         ret = qmp_ufs_power_off(phy);
1535         if (ret)
1536                 return ret;
1537         return qmp_ufs_exit(phy);
1538 }
1539
1540 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1541 {
1542         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1543
1544         qmp->mode = mode;
1545         qmp->submode = submode;
1546
1547         return 0;
1548 }
1549
1550 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
1551         .power_on       = qmp_ufs_enable,
1552         .power_off      = qmp_ufs_disable,
1553         .set_mode       = qmp_ufs_set_mode,
1554         .owner          = THIS_MODULE,
1555 };
1556
1557 static int qmp_ufs_vreg_init(struct qmp_ufs *qmp)
1558 {
1559         const struct qmp_phy_cfg *cfg = qmp->cfg;
1560         struct device *dev = qmp->dev;
1561         int num = cfg->num_vregs;
1562         int i;
1563
1564         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1565         if (!qmp->vregs)
1566                 return -ENOMEM;
1567
1568         for (i = 0; i < num; i++)
1569                 qmp->vregs[i].supply = cfg->vreg_list[i];
1570
1571         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1572 }
1573
1574 static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
1575 {
1576         const struct qmp_phy_cfg *cfg = qmp->cfg;
1577         struct device *dev = qmp->dev;
1578         int num = cfg->num_clks;
1579         int i;
1580
1581         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1582         if (!qmp->clks)
1583                 return -ENOMEM;
1584
1585         for (i = 0; i < num; i++)
1586                 qmp->clks[i].id = cfg->clk_list[i];
1587
1588         return devm_clk_bulk_get(dev, num, qmp->clks);
1589 }
1590
1591 static void qmp_ufs_clk_release_provider(void *res)
1592 {
1593         of_clk_del_provider(res);
1594 }
1595
1596 #define UFS_SYMBOL_CLOCKS 3
1597
1598 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
1599 {
1600         struct clk_hw_onecell_data *clk_data;
1601         struct clk_hw *hw;
1602         char name[64];
1603         int ret;
1604
1605         clk_data = devm_kzalloc(qmp->dev,
1606                                 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
1607                                 GFP_KERNEL);
1608         if (!clk_data)
1609                 return -ENOMEM;
1610
1611         clk_data->num = UFS_SYMBOL_CLOCKS;
1612
1613         snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
1614         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1615         if (IS_ERR(hw))
1616                 return PTR_ERR(hw);
1617
1618         clk_data->hws[0] = hw;
1619
1620         snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
1621         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1622         if (IS_ERR(hw))
1623                 return PTR_ERR(hw);
1624
1625         clk_data->hws[1] = hw;
1626
1627         snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
1628         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1629         if (IS_ERR(hw))
1630                 return PTR_ERR(hw);
1631
1632         clk_data->hws[2] = hw;
1633
1634         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1635         if (ret)
1636                 return ret;
1637
1638         /*
1639          * Roll a devm action because the clock provider can be a child node.
1640          */
1641         return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
1642 }
1643
1644 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
1645 {
1646         struct platform_device *pdev = to_platform_device(qmp->dev);
1647         const struct qmp_phy_cfg *cfg = qmp->cfg;
1648         struct device *dev = qmp->dev;
1649
1650         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
1651         if (IS_ERR(qmp->serdes))
1652                 return PTR_ERR(qmp->serdes);
1653
1654         /*
1655          * Get memory resources for the PHY:
1656          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1657          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1658          * For single lane PHYs: pcs_misc (optional) -> 3.
1659          */
1660         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
1661         if (IS_ERR(qmp->tx))
1662                 return PTR_ERR(qmp->tx);
1663
1664         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
1665         if (IS_ERR(qmp->rx))
1666                 return PTR_ERR(qmp->rx);
1667
1668         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
1669         if (IS_ERR(qmp->pcs))
1670                 return PTR_ERR(qmp->pcs);
1671
1672         if (cfg->lanes >= 2) {
1673                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
1674                 if (IS_ERR(qmp->tx2))
1675                         return PTR_ERR(qmp->tx2);
1676
1677                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
1678                 if (IS_ERR(qmp->rx2))
1679                         return PTR_ERR(qmp->rx2);
1680
1681                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
1682         } else {
1683                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
1684         }
1685
1686         if (IS_ERR(qmp->pcs_misc))
1687                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1688
1689         return 0;
1690 }
1691
1692 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp)
1693 {
1694         struct platform_device *pdev = to_platform_device(qmp->dev);
1695         const struct qmp_phy_cfg *cfg = qmp->cfg;
1696         const struct qmp_ufs_offsets *offs = cfg->offsets;
1697         void __iomem *base;
1698
1699         if (!offs)
1700                 return -EINVAL;
1701
1702         base = devm_platform_ioremap_resource(pdev, 0);
1703         if (IS_ERR(base))
1704                 return PTR_ERR(base);
1705
1706         qmp->serdes = base + offs->serdes;
1707         qmp->pcs = base + offs->pcs;
1708         qmp->tx = base + offs->tx;
1709         qmp->rx = base + offs->rx;
1710
1711         if (cfg->lanes >= 2) {
1712                 qmp->tx2 = base + offs->tx2;
1713                 qmp->rx2 = base + offs->rx2;
1714         }
1715
1716         return 0;
1717 }
1718
1719 static int qmp_ufs_probe(struct platform_device *pdev)
1720 {
1721         struct device *dev = &pdev->dev;
1722         struct phy_provider *phy_provider;
1723         struct device_node *np;
1724         struct qmp_ufs *qmp;
1725         int ret;
1726
1727         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1728         if (!qmp)
1729                 return -ENOMEM;
1730
1731         qmp->dev = dev;
1732
1733         qmp->cfg = of_device_get_match_data(dev);
1734         if (!qmp->cfg)
1735                 return -EINVAL;
1736
1737         ret = qmp_ufs_clk_init(qmp);
1738         if (ret)
1739                 return ret;
1740
1741         ret = qmp_ufs_vreg_init(qmp);
1742         if (ret)
1743                 return ret;
1744
1745         /* Check for legacy binding with child node. */
1746         np = of_get_next_available_child(dev->of_node, NULL);
1747         if (np) {
1748                 ret = qmp_ufs_parse_dt_legacy(qmp, np);
1749         } else {
1750                 np = of_node_get(dev->of_node);
1751                 ret = qmp_ufs_parse_dt(qmp);
1752         }
1753         if (ret)
1754                 goto err_node_put;
1755
1756         ret = qmp_ufs_register_clocks(qmp, np);
1757         if (ret)
1758                 goto err_node_put;
1759
1760         qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
1761         if (IS_ERR(qmp->phy)) {
1762                 ret = PTR_ERR(qmp->phy);
1763                 dev_err(dev, "failed to create PHY: %d\n", ret);
1764                 goto err_node_put;
1765         }
1766
1767         phy_set_drvdata(qmp->phy, qmp);
1768
1769         of_node_put(np);
1770
1771         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1772
1773         return PTR_ERR_OR_ZERO(phy_provider);
1774
1775 err_node_put:
1776         of_node_put(np);
1777         return ret;
1778 }
1779
1780 static const struct of_device_id qmp_ufs_of_match_table[] = {
1781         {
1782                 .compatible = "qcom,msm8996-qmp-ufs-phy",
1783                 .data = &msm8996_ufsphy_cfg,
1784         }, {
1785                 .compatible = "qcom,msm8998-qmp-ufs-phy",
1786                 .data = &sdm845_ufsphy_cfg,
1787         }, {
1788                 .compatible = "qcom,sa8775p-qmp-ufs-phy",
1789                 .data = &sa8775p_ufsphy_cfg,
1790         }, {
1791                 .compatible = "qcom,sc7280-qmp-ufs-phy",
1792                 .data = &sc7280_ufsphy_cfg,
1793         }, {
1794                 .compatible = "qcom,sc8180x-qmp-ufs-phy",
1795                 .data = &sm8150_ufsphy_cfg,
1796         }, {
1797                 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
1798                 .data = &sc8280xp_ufsphy_cfg,
1799         }, {
1800                 .compatible = "qcom,sdm845-qmp-ufs-phy",
1801                 .data = &sdm845_ufsphy_cfg,
1802         }, {
1803                 .compatible = "qcom,sm6115-qmp-ufs-phy",
1804                 .data = &sm6115_ufsphy_cfg,
1805         }, {
1806                 .compatible = "qcom,sm6125-qmp-ufs-phy",
1807                 .data = &sm6115_ufsphy_cfg,
1808         }, {
1809                 .compatible = "qcom,sm6350-qmp-ufs-phy",
1810                 .data = &sdm845_ufsphy_cfg,
1811         }, {
1812                 .compatible = "qcom,sm7150-qmp-ufs-phy",
1813                 .data = &sm7150_ufsphy_cfg,
1814         }, {
1815                 .compatible = "qcom,sm8150-qmp-ufs-phy",
1816                 .data = &sm8150_ufsphy_cfg,
1817         }, {
1818                 .compatible = "qcom,sm8250-qmp-ufs-phy",
1819                 .data = &sm8250_ufsphy_cfg,
1820         }, {
1821                 .compatible = "qcom,sm8350-qmp-ufs-phy",
1822                 .data = &sm8350_ufsphy_cfg,
1823         }, {
1824                 .compatible = "qcom,sm8450-qmp-ufs-phy",
1825                 .data = &sm8450_ufsphy_cfg,
1826         }, {
1827                 .compatible = "qcom,sm8550-qmp-ufs-phy",
1828                 .data = &sm8550_ufsphy_cfg,
1829         },
1830         { },
1831 };
1832 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
1833
1834 static struct platform_driver qmp_ufs_driver = {
1835         .probe          = qmp_ufs_probe,
1836         .driver = {
1837                 .name   = "qcom-qmp-ufs-phy",
1838                 .of_match_table = qmp_ufs_of_match_table,
1839         },
1840 };
1841
1842 module_platform_driver(qmp_ufs_driver);
1843
1844 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
1845 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");
1846 MODULE_LICENSE("GPL v2");