drivers/net/dsa/sja1105/sja1105_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
   3  * Copyright (c) 2018-2019, Vladimir Oltean <[email protected]>
   4  */
   5
   6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   7
   8 #include <linux/delay.h>
   9 #include <linux/module.h>
  10 #include <linux/printk.h>
  11 #include <linux/spi/spi.h>
  12 #include <linux/errno.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/phylink.h>
  15 #include <linux/of.h>
  16 #include <linux/of_net.h>
  17 #include <linux/of_mdio.h>
  18 #include <linux/pcs/pcs-xpcs.h>
  19 #include <linux/netdev_features.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/if_bridge.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/dsa/8021q.h>
  24 #include "sja1105.h"
  25 #include "sja1105_tas.h"
  26
  27 #define SJA1105_UNKNOWN_MULTICAST       0x010000000000ull
  28
  29 /* Configure the optional reset pin and bring up switch */
  30 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
  31                             unsigned int startup_delay)
  32 {
  33         struct gpio_desc *gpio;
  34
  35         gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  36         if (IS_ERR(gpio))
  37                 return PTR_ERR(gpio);
  38
  39         if (!gpio)
  40                 return 0;
  41
  42         gpiod_set_value_cansleep(gpio, 1);
  43         /* Wait for minimum reset pulse length */
  44         msleep(pulse_len);
  45         gpiod_set_value_cansleep(gpio, 0);
  46         /* Wait until chip is ready after reset */
  47         msleep(startup_delay);
  48
  49         gpiod_put(gpio);
  50
  51         return 0;
  52 }
  53
  54 static void
  55 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
  56                            int from, int to, bool allow)
  57 {
  58         if (allow)
  59                 l2_fwd[from].reach_port |= BIT(to);
  60         else
  61                 l2_fwd[from].reach_port &= ~BIT(to);
  62 }
  63
  64 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
  65                                 int from, int to)
  66 {
  67         return !!(l2_fwd[from].reach_port & BIT(to));
  68 }
  69
  70 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
  71 {
  72         struct sja1105_vlan_lookup_entry *vlan;
  73         int count, i;
  74
  75         vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
  76         count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
  77
  78         for (i = 0; i < count; i++)
  79                 if (vlan[i].vlanid == vid)
  80                         return i;
  81
  82         /* Return an invalid entry index if not found */
  83         return -1;
  84 }
  85
  86 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
  87 {
  88         struct sja1105_private *priv = ds->priv;
  89         struct sja1105_mac_config_entry *mac;
  90
  91         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
  92
  93         if (mac[port].drpuntag == drop)
  94                 return 0;
  95
  96         mac[port].drpuntag = drop;
  97
  98         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
  99                                             &mac[port], true);
 100 }
 101
 102 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
 103 {
 104         struct sja1105_mac_config_entry *mac;
 105
 106         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
 107
 108         if (mac[port].vlanid == pvid)
 109                 return 0;
 110
 111         mac[port].vlanid = pvid;
 112
 113         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
 114                                             &mac[port], true);
 115 }
 116
 117 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
 118 {
 119         struct dsa_port *dp = dsa_to_port(ds, port);
 120         struct net_device *br = dsa_port_bridge_dev_get(dp);
 121         struct sja1105_private *priv = ds->priv;
 122         struct sja1105_vlan_lookup_entry *vlan;
 123         bool drop_untagged = false;
 124         int match, rc;
 125         u16 pvid;
 126
 127         if (br && br_vlan_enabled(br))
 128                 pvid = priv->bridge_pvid[port];
 129         else
 130                 pvid = priv->tag_8021q_pvid[port];
 131
 132         rc = sja1105_pvid_apply(priv, port, pvid);
 133         if (rc)
 134                 return rc;
 135
 136         /* Only force dropping of untagged packets when the port is under a
 137          * VLAN-aware bridge. When the tag_8021q pvid is used, we are
 138          * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
 139          * to prevent DSA tag spoofing from the link partner. Untagged packets
 140          * are the only ones that should be received with tag_8021q, so
 141          * definitely don't drop them.
 142          */
 143         if (pvid == priv->bridge_pvid[port]) {
 144                 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
 145
 146                 match = sja1105_is_vlan_configured(priv, pvid);
 147
 148                 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
 149                         drop_untagged = true;
 150         }
 151
 152         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
 153                 drop_untagged = true;
 154
 155         return sja1105_drop_untagged(ds, port, drop_untagged);
 156 }
 157
 158 static int sja1105_init_mac_settings(struct sja1105_private *priv)
 159 {
 160         struct sja1105_mac_config_entry default_mac = {
 161                 /* Enable all 8 priority queues on egress.
 162                  * Every queue i holds top[i] - base[i] frames.
 163                  * Sum of top[i] - base[i] is 511 (max hardware limit).
 164                  */
 165                 .top  = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
 166                 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
 167                 .enabled = {true, true, true, true, true, true, true, true},
 168                 /* Keep standard IFG of 12 bytes on egress. */
 169                 .ifg = 0,
 170                 /* Always put the MAC speed in automatic mode, where it can be
 171                  * adjusted at runtime by PHYLINK.
 172                  */
 173                 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
 174                 /* No static correction for 1-step 1588 events */
 175                 .tp_delin = 0,
 176                 .tp_delout = 0,
 177                 /* Disable aging for critical TTEthernet traffic */
 178                 .maxage = 0xFF,
 179                 /* Internal VLAN (pvid) to apply to untagged ingress */
 180                 .vlanprio = 0,
 181                 .vlanid = 1,
 182                 .ing_mirr = false,
 183                 .egr_mirr = false,
 184                 /* Don't drop traffic with other EtherType than ETH_P_IP */
 185                 .drpnona664 = false,
 186                 /* Don't drop double-tagged traffic */
 187                 .drpdtag = false,
 188                 /* Don't drop untagged traffic */
 189                 .drpuntag = false,
 190                 /* Don't retag 802.1p (VID 0) traffic with the pvid */
 191                 .retag = false,
 192                 /* Disable learning and I/O on user ports by default -
 193                  * STP will enable it.
 194                  */
 195                 .dyn_learn = false,
 196                 .egress = false,
 197                 .ingress = false,
 198         };
 199         struct sja1105_mac_config_entry *mac;
 200         struct dsa_switch *ds = priv->ds;
 201         struct sja1105_table *table;
 202         struct dsa_port *dp;
 203
 204         table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
 205
 206         /* Discard previous MAC Configuration Table */
 207         if (table->entry_count) {
 208                 kfree(table->entries);
 209                 table->entry_count = 0;
 210         }
 211
 212         table->entries = kcalloc(table->ops->max_entry_count,
 213                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 214         if (!table->entries)
 215                 return -ENOMEM;
 216
 217         table->entry_count = table->ops->max_entry_count;
 218
 219         mac = table->entries;
 220
 221         list_for_each_entry(dp, &ds->dst->ports, list) {
 222                 if (dp->ds != ds)
 223                         continue;
 224
 225                 mac[dp->index] = default_mac;
 226
 227                 /* Let sja1105_bridge_stp_state_set() keep address learning
 228                  * enabled for the DSA ports. CPU ports use software-assisted
 229                  * learning to ensure that only FDB entries belonging to the
 230                  * bridge are learned, and that they are learned towards all
 231                  * CPU ports in a cross-chip topology if multiple CPU ports
 232                  * exist.
 233                  */
 234                 if (dsa_port_is_dsa(dp))
 235                         dp->learning = true;
 236
 237                 /* Disallow untagged packets from being received on the
 238                  * CPU and DSA ports.
 239                  */
 240                 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
 241                         mac[dp->index].drpuntag = true;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int sja1105_init_mii_settings(struct sja1105_private *priv)
 248 {
 249         struct device *dev = &priv->spidev->dev;
 250         struct sja1105_xmii_params_entry *mii;
 251         struct dsa_switch *ds = priv->ds;
 252         struct sja1105_table *table;
 253         int i;
 254
 255         table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
 256
 257         /* Discard previous xMII Mode Parameters Table */
 258         if (table->entry_count) {
 259                 kfree(table->entries);
 260                 table->entry_count = 0;
 261         }
 262
 263         table->entries = kcalloc(table->ops->max_entry_count,
 264                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 265         if (!table->entries)
 266                 return -ENOMEM;
 267
 268         /* Override table based on PHYLINK DT bindings */
 269         table->entry_count = table->ops->max_entry_count;
 270
 271         mii = table->entries;
 272
 273         for (i = 0; i < ds->num_ports; i++) {
 274                 sja1105_mii_role_t role = XMII_MAC;
 275
 276                 if (dsa_is_unused_port(priv->ds, i))
 277                         continue;
 278
 279                 switch (priv->phy_mode[i]) {
 280                 case PHY_INTERFACE_MODE_INTERNAL:
 281                         if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
 282                                 goto unsupported;
 283
 284                         mii->xmii_mode[i] = XMII_MODE_MII;
 285                         if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
 286                                 mii->special[i] = true;
 287
 288                         break;
 289                 case PHY_INTERFACE_MODE_REVMII:
 290                         role = XMII_PHY;
 291                         fallthrough;
 292                 case PHY_INTERFACE_MODE_MII:
 293                         if (!priv->info->supports_mii[i])
 294                                 goto unsupported;
 295
 296                         mii->xmii_mode[i] = XMII_MODE_MII;
 297                         break;
 298                 case PHY_INTERFACE_MODE_REVRMII:
 299                         role = XMII_PHY;
 300                         fallthrough;
 301                 case PHY_INTERFACE_MODE_RMII:
 302                         if (!priv->info->supports_rmii[i])
 303                                 goto unsupported;
 304
 305                         mii->xmii_mode[i] = XMII_MODE_RMII;
 306                         break;
 307                 case PHY_INTERFACE_MODE_RGMII:
 308                 case PHY_INTERFACE_MODE_RGMII_ID:
 309                 case PHY_INTERFACE_MODE_RGMII_RXID:
 310                 case PHY_INTERFACE_MODE_RGMII_TXID:
 311                         if (!priv->info->supports_rgmii[i])
 312                                 goto unsupported;
 313
 314                         mii->xmii_mode[i] = XMII_MODE_RGMII;
 315                         break;
 316                 case PHY_INTERFACE_MODE_SGMII:
 317                         if (!priv->info->supports_sgmii[i])
 318                                 goto unsupported;
 319
 320                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 321                         mii->special[i] = true;
 322                         break;
 323                 case PHY_INTERFACE_MODE_2500BASEX:
 324                         if (!priv->info->supports_2500basex[i])
 325                                 goto unsupported;
 326
 327                         mii->xmii_mode[i] = XMII_MODE_SGMII;
 328                         mii->special[i] = true;
 329                         break;
 330 unsupported:
 331                 default:
 332                         dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
 333                                 phy_modes(priv->phy_mode[i]), i);
 334                         return -EINVAL;
 335                 }
 336
 337                 mii->phy_mac[i] = role;
 338         }
 339         return 0;
 340 }
 341
 342 static int sja1105_init_static_fdb(struct sja1105_private *priv)
 343 {
 344         struct sja1105_l2_lookup_entry *l2_lookup;
 345         struct sja1105_table *table;
 346         int port;
 347
 348         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
 349
 350         /* We only populate the FDB table through dynamic L2 Address Lookup
 351          * entries, except for a special entry at the end which is a catch-all
 352          * for unknown multicast and will be used to control flooding domain.
 353          */
 354         if (table->entry_count) {
 355                 kfree(table->entries);
 356                 table->entry_count = 0;
 357         }
 358
 359         if (!priv->info->can_limit_mcast_flood)
 360                 return 0;
 361
 362         table->entries = kcalloc(1, table->ops->unpacked_entry_size,
 363                                  GFP_KERNEL);
 364         if (!table->entries)
 365                 return -ENOMEM;
 366
 367         table->entry_count = 1;
 368         l2_lookup = table->entries;
 369
 370         /* All L2 multicast addresses have an odd first octet */
 371         l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
 372         l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
 373         l2_lookup[0].lockeds = true;
 374         l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
 375
 376         /* Flood multicast to every port by default */
 377         for (port = 0; port < priv->ds->num_ports; port++)
 378                 if (!dsa_is_unused_port(priv->ds, port))
 379                         l2_lookup[0].destports |= BIT(port);
 380
 381         return 0;
 382 }
 383
 384 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
 385 {
 386         struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
 387                 /* Learned FDB entries are forgotten after 300 seconds */
 388                 .maxage = SJA1105_AGEING_TIME_MS(300000),
 389                 /* All entries within a FDB bin are available for learning */
 390                 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
 391                 /* And the P/Q/R/S equivalent setting: */
 392                 .start_dynspc = 0,
 393                 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
 394                 .poly = 0x97,
 395                 /* Always use Independent VLAN Learning (IVL) */
 396                 .shared_learn = false,
 397                 /* Don't discard management traffic based on ENFPORT -
 398                  * we don't perform SMAC port enforcement anyway, so
 399                  * what we are setting here doesn't matter.
 400                  */
 401                 .no_enf_hostprt = false,
 402                 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.
 403                  * Maybe correlate with no_linklocal_learn from bridge driver?
 404                  */
 405                 .no_mgmt_learn = true,
 406                 /* P/Q/R/S only */
 407                 .use_static = true,
 408                 /* Dynamically learned FDB entries can overwrite other (older)
 409                  * dynamic FDB entries
 410                  */
 411                 .owr_dyn = true,
 412                 .drpnolearn = true,
 413         };
 414         struct dsa_switch *ds = priv->ds;
 415         int port, num_used_ports = 0;
 416         struct sja1105_table *table;
 417         u64 max_fdb_entries;
 418
 419         for (port = 0; port < ds->num_ports; port++)
 420                 if (!dsa_is_unused_port(ds, port))
 421                         num_used_ports++;
 422
 423         max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
 424
 425         for (port = 0; port < ds->num_ports; port++) {
 426                 if (dsa_is_unused_port(ds, port))
 427                         continue;
 428
 429                 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
 430         }
 431
 432         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
 433
 434         if (table->entry_count) {
 435                 kfree(table->entries);
 436                 table->entry_count = 0;
 437         }
 438
 439         table->entries = kcalloc(table->ops->max_entry_count,
 440                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 441         if (!table->entries)
 442                 return -ENOMEM;
 443
 444         table->entry_count = table->ops->max_entry_count;
 445
 446         /* This table only has a single entry */
 447         ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
 448                                 default_l2_lookup_params;
 449
 450         return 0;
 451 }
 452
 453 /* Set up a default VLAN for untagged traffic injected from the CPU
 454  * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
 455  * All DT-defined ports are members of this VLAN, and there are no
 456  * restrictions on forwarding (since the CPU selects the destination).
 457  * Frames from this VLAN will always be transmitted as untagged, and
 458  * neither the bridge nor the 8021q module cannot create this VLAN ID.
 459  */
 460 static int sja1105_init_static_vlan(struct sja1105_private *priv)
 461 {
 462         struct sja1105_table *table;
 463         struct sja1105_vlan_lookup_entry pvid = {
 464                 .type_entry = SJA1110_VLAN_D_TAG,
 465                 .ving_mirr = 0,
 466                 .vegr_mirr = 0,
 467                 .vmemb_port = 0,
 468                 .vlan_bc = 0,
 469                 .tag_port = 0,
 470                 .vlanid = SJA1105_DEFAULT_VLAN,
 471         };
 472         struct dsa_switch *ds = priv->ds;
 473         int port;
 474
 475         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
 476
 477         if (table->entry_count) {
 478                 kfree(table->entries);
 479                 table->entry_count = 0;
 480         }
 481
 482         table->entries = kzalloc(table->ops->unpacked_entry_size,
 483                                  GFP_KERNEL);
 484         if (!table->entries)
 485                 return -ENOMEM;
 486
 487         table->entry_count = 1;
 488
 489         for (port = 0; port < ds->num_ports; port++) {
 490                 if (dsa_is_unused_port(ds, port))
 491                         continue;
 492
 493                 pvid.vmemb_port |= BIT(port);
 494                 pvid.vlan_bc |= BIT(port);
 495                 pvid.tag_port &= ~BIT(port);
 496
 497                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
 498                         priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
 499                         priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
 500                 }
 501         }
 502
 503         ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
 504         return 0;
 505 }
 506
 507 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
 508 {
 509         struct sja1105_l2_forwarding_entry *l2fwd;
 510         struct dsa_switch *ds = priv->ds;
 511         struct dsa_switch_tree *dst;
 512         struct sja1105_table *table;
 513         struct dsa_link *dl;
 514         int port, tc;
 515         int from, to;
 516
 517         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
 518
 519         if (table->entry_count) {
 520                 kfree(table->entries);
 521                 table->entry_count = 0;
 522         }
 523
 524         table->entries = kcalloc(table->ops->max_entry_count,
 525                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 526         if (!table->entries)
 527                 return -ENOMEM;
 528
 529         table->entry_count = table->ops->max_entry_count;
 530
 531         l2fwd = table->entries;
 532
 533         /* First 5 entries in the L2 Forwarding Table define the forwarding
 534          * rules and the VLAN PCP to ingress queue mapping.
 535          * Set up the ingress queue mapping first.
 536          */
 537         for (port = 0; port < ds->num_ports; port++) {
 538                 if (dsa_is_unused_port(ds, port))
 539                         continue;
 540
 541                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 542                         l2fwd[port].vlan_pmap[tc] = tc;
 543         }
 544
 545         /* Then manage the forwarding domain for user ports. These can forward
 546          * only to the always-on domain (CPU port and DSA links)
 547          */
 548         for (from = 0; from < ds->num_ports; from++) {
 549                 if (!dsa_is_user_port(ds, from))
 550                         continue;
 551
 552                 for (to = 0; to < ds->num_ports; to++) {
 553                         if (!dsa_is_cpu_port(ds, to) &&
 554                             !dsa_is_dsa_port(ds, to))
 555                                 continue;
 556
 557                         l2fwd[from].bc_domain |= BIT(to);
 558                         l2fwd[from].fl_domain |= BIT(to);
 559
 560                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 561                 }
 562         }
 563
 564         /* Then manage the forwarding domain for DSA links and CPU ports (the
 565          * always-on domain). These can send packets to any enabled port except
 566          * themselves.
 567          */
 568         for (from = 0; from < ds->num_ports; from++) {
 569                 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
 570                         continue;
 571
 572                 for (to = 0; to < ds->num_ports; to++) {
 573                         if (dsa_is_unused_port(ds, to))
 574                                 continue;
 575
 576                         if (from == to)
 577                                 continue;
 578
 579                         l2fwd[from].bc_domain |= BIT(to);
 580                         l2fwd[from].fl_domain |= BIT(to);
 581
 582                         sja1105_port_allow_traffic(l2fwd, from, to, true);
 583                 }
 584         }
 585
 586         /* In odd topologies ("H" connections where there is a DSA link to
 587          * another switch which also has its own CPU port), TX packets can loop
 588          * back into the system (they are flooded from CPU port 1 to the DSA
 589          * link, and from there to CPU port 2). Prevent this from happening by
 590          * cutting RX from DSA links towards our CPU port, if the remote switch
 591          * has its own CPU port and therefore doesn't need ours for network
 592          * stack termination.
 593          */
 594         dst = ds->dst;
 595
 596         list_for_each_entry(dl, &dst->rtable, list) {
 597                 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
 598                         continue;
 599
 600                 from = dl->dp->index;
 601                 to = dsa_upstream_port(ds, from);
 602
 603                 dev_warn(ds->dev,
 604                          "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
 605                          from, to);
 606
 607                 sja1105_port_allow_traffic(l2fwd, from, to, false);
 608
 609                 l2fwd[from].bc_domain &= ~BIT(to);
 610                 l2fwd[from].fl_domain &= ~BIT(to);
 611         }
 612
 613         /* Finally, manage the egress flooding domain. All ports start up with
 614          * flooding enabled, including the CPU port and DSA links.
 615          */
 616         for (port = 0; port < ds->num_ports; port++) {
 617                 if (dsa_is_unused_port(ds, port))
 618                         continue;
 619
 620                 priv->ucast_egress_floods |= BIT(port);
 621                 priv->bcast_egress_floods |= BIT(port);
 622         }
 623
 624         /* Next 8 entries define VLAN PCP mapping from ingress to egress.
 625          * Create a one-to-one mapping.
 626          */
 627         for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
 628                 for (port = 0; port < ds->num_ports; port++) {
 629                         if (dsa_is_unused_port(ds, port))
 630                                 continue;
 631
 632                         l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
 633                 }
 634
 635                 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
 636         }
 637
 638         return 0;
 639 }
 640
 641 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
 642 {
 643         struct sja1110_pcp_remapping_entry *pcp_remap;
 644         struct dsa_switch *ds = priv->ds;
 645         struct sja1105_table *table;
 646         int port, tc;
 647
 648         table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
 649
 650         /* Nothing to do for SJA1105 */
 651         if (!table->ops->max_entry_count)
 652                 return 0;
 653
 654         if (table->entry_count) {
 655                 kfree(table->entries);
 656                 table->entry_count = 0;
 657         }
 658
 659         table->entries = kcalloc(table->ops->max_entry_count,
 660                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 661         if (!table->entries)
 662                 return -ENOMEM;
 663
 664         table->entry_count = table->ops->max_entry_count;
 665
 666         pcp_remap = table->entries;
 667
 668         /* Repeat the configuration done for vlan_pmap */
 669         for (port = 0; port < ds->num_ports; port++) {
 670                 if (dsa_is_unused_port(ds, port))
 671                         continue;
 672
 673                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
 674                         pcp_remap[port].egrpcp[tc] = tc;
 675         }
 676
 677         return 0;
 678 }
 679
 680 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
 681 {
 682         struct sja1105_l2_forwarding_params_entry *l2fwd_params;
 683         struct sja1105_table *table;
 684
 685         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 686
 687         if (table->entry_count) {
 688                 kfree(table->entries);
 689                 table->entry_count = 0;
 690         }
 691
 692         table->entries = kcalloc(table->ops->max_entry_count,
 693                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 694         if (!table->entries)
 695                 return -ENOMEM;
 696
 697         table->entry_count = table->ops->max_entry_count;
 698
 699         /* This table only has a single entry */
 700         l2fwd_params = table->entries;
 701
 702         /* Disallow dynamic reconfiguration of vlan_pmap */
 703         l2fwd_params->max_dynp = 0;
 704         /* Use a single memory partition for all ingress queues */
 705         l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
 706
 707         return 0;
 708 }
 709
 710 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
 711 {
 712         struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
 713         struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
 714         struct sja1105_table *table;
 715
 716         table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
 717         l2_fwd_params = table->entries;
 718         l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
 719
 720         /* If we have any critical-traffic virtual links, we need to reserve
 721          * some frame buffer memory for them. At the moment, hardcode the value
 722          * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
 723          * remaining for best-effort traffic. TODO: figure out a more flexible
 724          * way to perform the frame buffer partitioning.
 725          */
 726         if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
 727                 return;
 728
 729         table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
 730         vl_fwd_params = table->entries;
 731
 732         l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
 733         vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
 734 }
 735
 736 /* SJA1110 TDMACONFIGIDX values:
 737  *
 738  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
 739  * -----+----------------+---------------+---------------+---------------
 740  *   0  |   0, [5:10]    |     [1:2]     |     [3:4]     |     retag
 741  *   1  |0, [5:10], retag|     [1:2]     |     [3:4]     |       -
 742  *   2  |   0, [5:10]    |  [1:3], retag |       4       |       -
 743  *   3  |   0, [5:10]    |[1:2], 4, retag|       3       |       -
 744  *   4  |  0, 2, [5:10]  |    1, retag   |     [3:4]     |       -
 745  *   5  |  0, 1, [5:10]  |    2, retag   |     [3:4]     |       -
 746  *  14  |   0, [5:10]    | [1:4], retag  |       -       |       -
 747  *  15  |     [5:10]     | [0:4], retag  |       -       |       -
 748  */
 749 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
 750 {
 751         struct sja1105_general_params_entry *general_params;
 752         struct sja1105_table *table;
 753         bool port_1_is_base_tx;
 754         bool port_3_is_2500;
 755         bool port_4_is_2500;
 756         u64 tdmaconfigidx;
 757
 758         if (priv->info->device_id != SJA1110_DEVICE_ID)
 759                 return;
 760
 761         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 762         general_params = table->entries;
 763
 764         /* All the settings below are "as opposed to SGMII", which is the
 765          * other pinmuxing option.
 766          */
 767         port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
 768         port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
 769         port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
 770
 771         if (port_1_is_base_tx)
 772                 /* Retagging port will operate at 1 Gbps */
 773                 tdmaconfigidx = 5;
 774         else if (port_3_is_2500 && port_4_is_2500)
 775                 /* Retagging port will operate at 100 Mbps */
 776                 tdmaconfigidx = 1;
 777         else if (port_3_is_2500)
 778                 /* Retagging port will operate at 1 Gbps */
 779                 tdmaconfigidx = 3;
 780         else if (port_4_is_2500)
 781                 /* Retagging port will operate at 1 Gbps */
 782                 tdmaconfigidx = 2;
 783         else
 784                 /* Retagging port will operate at 1 Gbps */
 785                 tdmaconfigidx = 14;
 786
 787         general_params->tdmaconfigidx = tdmaconfigidx;
 788 }
 789
 790 static int sja1105_init_topology(struct sja1105_private *priv,
 791                                  struct sja1105_general_params_entry *general_params)
 792 {
 793         struct dsa_switch *ds = priv->ds;
 794         int port;
 795
 796         /* The host port is the destination for traffic matching mac_fltres1
 797          * and mac_fltres0 on all ports except itself. Default to an invalid
 798          * value.
 799          */
 800         general_params->host_port = ds->num_ports;
 801
 802         /* Link-local traffic received on casc_port will be forwarded
 803          * to host_port without embedding the source port and device ID
 804          * info in the destination MAC address, and no RX timestamps will be
 805          * taken either (presumably because it is a cascaded port and a
 806          * downstream SJA switch already did that).
 807          * To disable the feature, we need to do different things depending on
 808          * switch generation. On SJA1105 we need to set an invalid port, while
 809          * on SJA1110 which support multiple cascaded ports, this field is a
 810          * bitmask so it must be left zero.
 811          */
 812         if (!priv->info->multiple_cascade_ports)
 813                 general_params->casc_port = ds->num_ports;
 814
 815         for (port = 0; port < ds->num_ports; port++) {
 816                 bool is_upstream = dsa_is_upstream_port(ds, port);
 817                 bool is_dsa_link = dsa_is_dsa_port(ds, port);
 818
 819                 /* Upstream ports can be dedicated CPU ports or
 820                  * upstream-facing DSA links
 821                  */
 822                 if (is_upstream) {
 823                         if (general_params->host_port == ds->num_ports) {
 824                                 general_params->host_port = port;
 825                         } else {
 826                                 dev_err(ds->dev,
 827                                         "Port %llu is already a host port, configuring %d as one too is not supported\n",
 828                                         general_params->host_port, port);
 829                                 return -EINVAL;
 830                         }
 831                 }
 832
 833                 /* Cascade ports are downstream-facing DSA links */
 834                 if (is_dsa_link && !is_upstream) {
 835                         if (priv->info->multiple_cascade_ports) {
 836                                 general_params->casc_port |= BIT(port);
 837                         } else if (general_params->casc_port == ds->num_ports) {
 838                                 general_params->casc_port = port;
 839                         } else {
 840                                 dev_err(ds->dev,
 841                                         "Port %llu is already a cascade port, configuring %d as one too is not supported\n",
 842                                         general_params->casc_port, port);
 843                                 return -EINVAL;
 844                         }
 845                 }
 846         }
 847
 848         if (general_params->host_port == ds->num_ports) {
 849                 dev_err(ds->dev, "No host port configured\n");
 850                 return -EINVAL;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int sja1105_init_general_params(struct sja1105_private *priv)
 857 {
 858         struct sja1105_general_params_entry default_general_params = {
 859                 /* Allow dynamic changing of the mirror port */
 860                 .mirr_ptacu = true,
 861                 .switchid = priv->ds->index,
 862                 /* Priority queue for link-local management frames
 863                  * (both ingress to and egress from CPU - PTP, STP etc)
 864                  */
 865                 .hostprio = 7,
 866                 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
 867                 .mac_flt1    = SJA1105_LINKLOCAL_FILTER_A_MASK,
 868                 .incl_srcpt1 = true,
 869                 .send_meta1  = true,
 870                 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
 871                 .mac_flt0    = SJA1105_LINKLOCAL_FILTER_B_MASK,
 872                 .incl_srcpt0 = true,
 873                 .send_meta0  = true,
 874                 /* Default to an invalid value */
 875                 .mirr_port = priv->ds->num_ports,
 876                 /* No TTEthernet */
 877                 .vllupformat = SJA1105_VL_FORMAT_PSFP,
 878                 .vlmarker = 0,
 879                 .vlmask = 0,
 880                 /* Only update correctionField for 1-step PTP (L2 transport) */
 881                 .ignore2stf = 0,
 882                 /* Forcefully disable VLAN filtering by telling
 883                  * the switch that VLAN has a different EtherType.
 884                  */
 885                 .tpid = ETH_P_SJA1105,
 886                 .tpid2 = ETH_P_SJA1105,
 887                 /* Enable the TTEthernet engine on SJA1110 */
 888                 .tte_en = true,
 889                 /* Set up the EtherType for control packets on SJA1110 */
 890                 .header_type = ETH_P_SJA1110,
 891         };
 892         struct sja1105_general_params_entry *general_params;
 893         struct sja1105_table *table;
 894         int rc;
 895
 896         rc = sja1105_init_topology(priv, &default_general_params);
 897         if (rc)
 898                 return rc;
 899
 900         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
 901
 902         if (table->entry_count) {
 903                 kfree(table->entries);
 904                 table->entry_count = 0;
 905         }
 906
 907         table->entries = kcalloc(table->ops->max_entry_count,
 908                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 909         if (!table->entries)
 910                 return -ENOMEM;
 911
 912         table->entry_count = table->ops->max_entry_count;
 913
 914         general_params = table->entries;
 915
 916         /* This table only has a single entry */
 917         general_params[0] = default_general_params;
 918
 919         sja1110_select_tdmaconfigidx(priv);
 920
 921         return 0;
 922 }
 923
 924 static int sja1105_init_avb_params(struct sja1105_private *priv)
 925 {
 926         struct sja1105_avb_params_entry *avb;
 927         struct sja1105_table *table;
 928
 929         table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
 930
 931         /* Discard previous AVB Parameters Table */
 932         if (table->entry_count) {
 933                 kfree(table->entries);
 934                 table->entry_count = 0;
 935         }
 936
 937         table->entries = kcalloc(table->ops->max_entry_count,
 938                                  table->ops->unpacked_entry_size, GFP_KERNEL);
 939         if (!table->entries)
 940                 return -ENOMEM;
 941
 942         table->entry_count = table->ops->max_entry_count;
 943
 944         avb = table->entries;
 945
 946         /* Configure the MAC addresses for meta frames */
 947         avb->destmeta = SJA1105_META_DMAC;
 948         avb->srcmeta  = SJA1105_META_SMAC;
 949         /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
 950          * default. This is because there might be boards with a hardware
 951          * layout where enabling the pin as output might cause an electrical
 952          * clash. On E/T the pin is always an output, which the board designers
 953          * probably already knew, so even if there are going to be electrical
 954          * issues, there's nothing we can do.
 955          */
 956         avb->cas_master = false;
 957
 958         return 0;
 959 }
 960
 961 /* The L2 policing table is 2-stage. The table is looked up for each frame
 962  * according to the ingress port, whether it was broadcast or not, and the
 963  * classified traffic class (given by VLAN PCP). This portion of the lookup is
 964  * fixed, and gives access to the SHARINDX, an indirection register pointing
 965  * within the policing table itself, which is used to resolve the policer that
 966  * will be used for this frame.
 967  *
 968  *  Stage 1                              Stage 2
 969  * +------------+--------+              +---------------------------------+
 970  * |Port 0 TC 0 |SHARINDX|              | Policer 0: Rate, Burst, MTU     |
 971  * +------------+--------+              +---------------------------------+
 972  * |Port 0 TC 1 |SHARINDX|              | Policer 1: Rate, Burst, MTU     |
 973  * +------------+--------+              +---------------------------------+
 974  *    ...                               | Policer 2: Rate, Burst, MTU     |
 975  * +------------+--------+              +---------------------------------+
 976  * |Port 0 TC 7 |SHARINDX|              | Policer 3: Rate, Burst, MTU     |
 977  * +------------+--------+              +---------------------------------+
 978  * |Port 1 TC 0 |SHARINDX|              | Policer 4: Rate, Burst, MTU     |
 979  * +------------+--------+              +---------------------------------+
 980  *    ...                               | Policer 5: Rate, Burst, MTU     |
 981  * +------------+--------+              +---------------------------------+
 982  * |Port 1 TC 7 |SHARINDX|              | Policer 6: Rate, Burst, MTU     |
 983  * +------------+--------+              +---------------------------------+
 984  *    ...                               | Policer 7: Rate, Burst, MTU     |
 985  * +------------+--------+              +---------------------------------+
 986  * |Port 4 TC 7 |SHARINDX|                 ...
 987  * +------------+--------+
 988  * |Port 0 BCAST|SHARINDX|                 ...
 989  * +------------+--------+
 990  * |Port 1 BCAST|SHARINDX|                 ...
 991  * +------------+--------+
 992  *    ...                                  ...
 993  * +------------+--------+              +---------------------------------+
 994  * |Port 4 BCAST|SHARINDX|              | Policer 44: Rate, Burst, MTU    |
 995  * +------------+--------+              +---------------------------------+
 996  *
 997  * In this driver, we shall use policers 0-4 as statically alocated port
 998  * (matchall) policers. So we need to make the SHARINDX for all lookups
 999  * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1000  * lookup) equal.
1001  * The remaining policers (40) shall be dynamically allocated for flower
1002  * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1003  */
1004 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1005
1006 static int sja1105_init_l2_policing(struct sja1105_private *priv)
1007 {
1008         struct sja1105_l2_policing_entry *policing;
1009         struct dsa_switch *ds = priv->ds;
1010         struct sja1105_table *table;
1011         int port, tc;
1012
1013         table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1014
1015         /* Discard previous L2 Policing Table */
1016         if (table->entry_count) {
1017                 kfree(table->entries);
1018                 table->entry_count = 0;
1019         }
1020
1021         table->entries = kcalloc(table->ops->max_entry_count,
1022                                  table->ops->unpacked_entry_size, GFP_KERNEL);
1023         if (!table->entries)
1024                 return -ENOMEM;
1025
1026         table->entry_count = table->ops->max_entry_count;
1027
1028         policing = table->entries;
1029
1030         /* Setup shared indices for the matchall policers */
1031         for (port = 0; port < ds->num_ports; port++) {
1032                 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1033                 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1034
1035                 for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1036                         policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1037
1038                 policing[bcast].sharindx = port;
1039                 /* Only SJA1110 has multicast policers */
1040                 if (mcast < table->ops->max_entry_count)
1041                         policing[mcast].sharindx = port;
1042         }
1043
1044         /* Setup the matchall policer parameters */
1045         for (port = 0; port < ds->num_ports; port++) {
1046                 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1047
1048                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1049                         mtu += VLAN_HLEN;
1050
1051                 policing[port].smax = 65535; /* Burst size in bytes */
1052                 policing[port].rate = SJA1105_RATE_MBPS(1000);
1053                 policing[port].maxlen = mtu;
1054                 policing[port].partition = 0;
1055         }
1056
1057         return 0;
1058 }
1059
1060 static int sja1105_static_config_load(struct sja1105_private *priv)
1061 {
1062         int rc;
1063
1064         sja1105_static_config_free(&priv->static_config);
1065         rc = sja1105_static_config_init(&priv->static_config,
1066                                         priv->info->static_ops,
1067                                         priv->info->device_id);
1068         if (rc)
1069                 return rc;
1070
1071         /* Build static configuration */
1072         rc = sja1105_init_mac_settings(priv);
1073         if (rc < 0)
1074                 return rc;
1075         rc = sja1105_init_mii_settings(priv);
1076         if (rc < 0)
1077                 return rc;
1078         rc = sja1105_init_static_fdb(priv);
1079         if (rc < 0)
1080                 return rc;
1081         rc = sja1105_init_static_vlan(priv);
1082         if (rc < 0)
1083                 return rc;
1084         rc = sja1105_init_l2_lookup_params(priv);
1085         if (rc < 0)
1086                 return rc;
1087         rc = sja1105_init_l2_forwarding(priv);
1088         if (rc < 0)
1089                 return rc;
1090         rc = sja1105_init_l2_forwarding_params(priv);
1091         if (rc < 0)
1092                 return rc;
1093         rc = sja1105_init_l2_policing(priv);
1094         if (rc < 0)
1095                 return rc;
1096         rc = sja1105_init_general_params(priv);
1097         if (rc < 0)
1098                 return rc;
1099         rc = sja1105_init_avb_params(priv);
1100         if (rc < 0)
1101                 return rc;
1102         rc = sja1110_init_pcp_remapping(priv);
1103         if (rc < 0)
1104                 return rc;
1105
1106         /* Send initial configuration to hardware via SPI */
1107         return sja1105_static_config_upload(priv);
1108 }
1109
1110 /* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1111  * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1112  * properties. It has the advantage of working with fixed links and with PHYs
1113  * that apply RGMII delays too, and the MAC driver needs not perform any
1114  * special checks.
1115  *
1116  * Previously we were acting upon the "phy-mode" property when we were
1117  * operating in fixed-link, basically acting as a PHY, but with a reversed
1118  * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1119  * behave as if it is connected to a PHY which has applied RGMII delays in the
1120  * TX direction. So if anything, RX delays should have been added by the MAC,
1121  * but we were adding TX delays.
1122  *
1123  * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1124  * back to the legacy behavior and apply delays on fixed-link ports based on
1125  * the reverse interpretation of the phy-mode. This is a deviation from the
1126  * expected default behavior which is to simply apply no delays. To achieve
1127  * that behavior with the new bindings, it is mandatory to specify
1128  * "{rx,tx}-internal-delay-ps" with a value of 0.
1129  */
1130 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1131                                       struct device_node *port_dn)
1132 {
1133         phy_interface_t phy_mode = priv->phy_mode[port];
1134         struct device *dev = &priv->spidev->dev;
1135         int rx_delay = -1, tx_delay = -1;
1136
1137         if (!phy_interface_mode_is_rgmii(phy_mode))
1138                 return 0;
1139
1140         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1141         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1142
1143         if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1144                 dev_warn(dev,
1145                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1146                          "please update device tree to specify \"rx-internal-delay-ps\" and "
1147                          "\"tx-internal-delay-ps\"",
1148                          port);
1149
1150                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1151                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1152                         rx_delay = 2000;
1153
1154                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1155                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1156                         tx_delay = 2000;
1157         }
1158
1159         if (rx_delay < 0)
1160                 rx_delay = 0;
1161         if (tx_delay < 0)
1162                 tx_delay = 0;
1163
1164         if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1165                 dev_err(dev, "Chip cannot apply RGMII delays\n");
1166                 return -EINVAL;
1167         }
1168
1169         if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1170             (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1171             (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1172             (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1173                 dev_err(dev,
1174                         "port %d RGMII delay values out of range, must be between %d and %d ps\n",
1175                         port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1176                 return -ERANGE;
1177         }
1178
1179         priv->rgmii_rx_delay_ps[port] = rx_delay;
1180         priv->rgmii_tx_delay_ps[port] = tx_delay;
1181
1182         return 0;
1183 }
1184
1185 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1186                                     struct device_node *ports_node)
1187 {
1188         struct device *dev = &priv->spidev->dev;
1189         struct device_node *child;
1190
1191         for_each_available_child_of_node(ports_node, child) {
1192                 struct device_node *phy_node;
1193                 phy_interface_t phy_mode;
1194                 u32 index;
1195                 int err;
1196
1197                 /* Get switch port number from DT */
1198                 if (of_property_read_u32(child, "reg", &index) < 0) {
1199                         dev_err(dev, "Port number not defined in device tree "
1200                                 "(property \"reg\")\n");
1201                         of_node_put(child);
1202                         return -ENODEV;
1203                 }
1204
1205                 /* Get PHY mode from DT */
1206                 err = of_get_phy_mode(child, &phy_mode);
1207                 if (err) {
1208                         dev_err(dev, "Failed to read phy-mode or "
1209                                 "phy-interface-type property for port %d\n",
1210                                 index);
1211                         of_node_put(child);
1212                         return -ENODEV;
1213                 }
1214
1215                 phy_node = of_parse_phandle(child, "phy-handle", 0);
1216                 if (!phy_node) {
1217                         if (!of_phy_is_fixed_link(child)) {
1218                                 dev_err(dev, "phy-handle or fixed-link "
1219                                         "properties missing!\n");
1220                                 of_node_put(child);
1221                                 return -ENODEV;
1222                         }
1223                         /* phy-handle is missing, but fixed-link isn't.
1224                          * So it's a fixed link. Default to PHY role.
1225                          */
1226                         priv->fixed_link[index] = true;
1227                 } else {
1228                         of_node_put(phy_node);
1229                 }
1230
1231                 priv->phy_mode[index] = phy_mode;
1232
1233                 err = sja1105_parse_rgmii_delays(priv, index, child);
1234                 if (err) {
1235                         of_node_put(child);
1236                         return err;
1237                 }
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int sja1105_parse_dt(struct sja1105_private *priv)
1244 {
1245         struct device *dev = &priv->spidev->dev;
1246         struct device_node *switch_node = dev->of_node;
1247         struct device_node *ports_node;
1248         int rc;
1249
1250         ports_node = of_get_child_by_name(switch_node, "ports");
1251         if (!ports_node)
1252                 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1253         if (!ports_node) {
1254                 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1255                 return -ENODEV;
1256         }
1257
1258         rc = sja1105_parse_ports_node(priv, ports_node);
1259         of_node_put(ports_node);
1260
1261         return rc;
1262 }
1263
1264 /* Convert link speed from SJA1105 to ethtool encoding */
1265 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1266                                          u64 speed)
1267 {
1268         if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1269                 return SPEED_10;
1270         if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1271                 return SPEED_100;
1272         if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1273                 return SPEED_1000;
1274         if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1275                 return SPEED_2500;
1276         return SPEED_UNKNOWN;
1277 }
1278
1279 /* Set link speed in the MAC configuration for a specific port. */
1280 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1281                                       int speed_mbps)
1282 {
1283         struct sja1105_mac_config_entry *mac;
1284         struct device *dev = priv->ds->dev;
1285         u64 speed;
1286         int rc;
1287
1288         /* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1289          * tables. On E/T, MAC reconfig tables are not readable, only writable.
1290          * We have to *know* what the MAC looks like.  For the sake of keeping
1291          * the code common, we'll use the static configuration tables as a
1292          * reasonable approximation for both E/T and P/Q/R/S.
1293          */
1294         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1295
1296         switch (speed_mbps) {
1297         case SPEED_UNKNOWN:
1298                 /* PHYLINK called sja1105_mac_config() to inform us about
1299                  * the state->interface, but AN has not completed and the
1300                  * speed is not yet valid. UM10944.pdf says that setting
1301                  * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1302                  * ok for power consumption in case AN will never complete -
1303                  * otherwise PHYLINK should come back with a new update.
1304                  */
1305                 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1306                 break;
1307         case SPEED_10:
1308                 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1309                 break;
1310         case SPEED_100:
1311                 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1312                 break;
1313         case SPEED_1000:
1314                 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1315                 break;
1316         case SPEED_2500:
1317                 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1318                 break;
1319         default:
1320                 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1321                 return -EINVAL;
1322         }
1323
1324         /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1325          * table, since this will be used for the clocking setup, and we no
1326          * longer need to store it in the static config (already told hardware
1327          * we want auto during upload phase).
1328          * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1329          * we need to configure the PCS only (if even that).
1330          */
1331         if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1332                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1333         else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1334                 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1335         else
1336                 mac[port].speed = speed;
1337
1338         /* Write to the dynamic reconfiguration tables */
1339         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1340                                           &mac[port], true);
1341         if (rc < 0) {
1342                 dev_err(dev, "Failed to write MAC config: %d\n", rc);
1343                 return rc;
1344         }
1345
1346         /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1347          * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1348          * RMII no change of the clock setup is required. Actually, changing
1349          * the clock setup does interrupt the clock signal for a certain time
1350          * which causes trouble for all PHYs relying on this signal.
1351          */
1352         if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1353                 return 0;
1354
1355         return sja1105_clocking_setup_port(priv, port);
1356 }
1357
1358 static struct phylink_pcs *
1359 sja1105_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t iface)
1360 {
1361         struct sja1105_private *priv = ds->priv;
1362         struct dw_xpcs *xpcs = priv->xpcs[port];
1363
1364         if (xpcs)
1365                 return &xpcs->pcs;
1366
1367         return NULL;
1368 }
1369
1370 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1371                                   unsigned int mode,
1372                                   phy_interface_t interface)
1373 {
1374         sja1105_inhibit_tx(ds->priv, BIT(port), true);
1375 }
1376
1377 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1378                                 unsigned int mode,
1379                                 phy_interface_t interface,
1380                                 struct phy_device *phydev,
1381                                 int speed, int duplex,
1382                                 bool tx_pause, bool rx_pause)
1383 {
1384         struct sja1105_private *priv = ds->priv;
1385
1386         sja1105_adjust_port_config(priv, port, speed);
1387
1388         sja1105_inhibit_tx(priv, BIT(port), false);
1389 }
1390
1391 static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1392                                      struct phylink_config *config)
1393 {
1394         struct sja1105_private *priv = ds->priv;
1395         struct sja1105_xmii_params_entry *mii;
1396         phy_interface_t phy_mode;
1397
1398         phy_mode = priv->phy_mode[port];
1399         if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
1400             phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
1401                 /* Changing the PHY mode on SERDES ports is possible and makes
1402                  * sense, because that is done through the XPCS. We allow
1403                  * changes between SGMII and 2500base-X.
1404                  */
1405                 if (priv->info->supports_sgmii[port])
1406                         __set_bit(PHY_INTERFACE_MODE_SGMII,
1407                                   config->supported_interfaces);
1408
1409                 if (priv->info->supports_2500basex[port])
1410                         __set_bit(PHY_INTERFACE_MODE_2500BASEX,
1411                                   config->supported_interfaces);
1412         } else {
1413                 /* The SJA1105 MAC programming model is through the static
1414                  * config (the xMII Mode table cannot be dynamically
1415                  * reconfigured), and we have to program that early.
1416                  */
1417                 __set_bit(phy_mode, config->supported_interfaces);
1418         }
1419
1420         /* The MAC does not support pause frames, and also doesn't
1421          * support half-duplex traffic modes.
1422          */
1423         config->mac_capabilities = MAC_10FD | MAC_100FD;
1424
1425         mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1426         if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1427             mii->xmii_mode[port] == XMII_MODE_SGMII)
1428                 config->mac_capabilities |= MAC_1000FD;
1429
1430         if (priv->info->supports_2500basex[port])
1431                 config->mac_capabilities |= MAC_2500FD;
1432 }
1433
1434 static int
1435 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1436                               const struct sja1105_l2_lookup_entry *requested)
1437 {
1438         struct sja1105_l2_lookup_entry *l2_lookup;
1439         struct sja1105_table *table;
1440         int i;
1441
1442         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1443         l2_lookup = table->entries;
1444
1445         for (i = 0; i < table->entry_count; i++)
1446                 if (l2_lookup[i].macaddr == requested->macaddr &&
1447                     l2_lookup[i].vlanid == requested->vlanid &&
1448                     l2_lookup[i].destports & BIT(port))
1449                         return i;
1450
1451         return -1;
1452 }
1453
1454 /* We want FDB entries added statically through the bridge command to persist
1455  * across switch resets, which are a common thing during normal SJA1105
1456  * operation. So we have to back them up in the static configuration tables
1457  * and hence apply them on next static config upload... yay!
1458  */
1459 static int
1460 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1461                           const struct sja1105_l2_lookup_entry *requested,
1462                           bool keep)
1463 {
1464         struct sja1105_l2_lookup_entry *l2_lookup;
1465         struct sja1105_table *table;
1466         int rc, match;
1467
1468         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1469
1470         match = sja1105_find_static_fdb_entry(priv, port, requested);
1471         if (match < 0) {
1472                 /* Can't delete a missing entry. */
1473                 if (!keep)
1474                         return 0;
1475
1476                 /* No match => new entry */
1477                 rc = sja1105_table_resize(table, table->entry_count + 1);
1478                 if (rc)
1479                         return rc;
1480
1481                 match = table->entry_count - 1;
1482         }
1483
1484         /* Assign pointer after the resize (it may be new memory) */
1485         l2_lookup = table->entries;
1486
1487         /* We have a match.
1488          * If the job was to add this FDB entry, it's already done (mostly
1489          * anyway, since the port forwarding mask may have changed, case in
1490          * which we update it).
1491          * Otherwise we have to delete it.
1492          */
1493         if (keep) {
1494                 l2_lookup[match] = *requested;
1495                 return 0;
1496         }
1497
1498         /* To remove, the strategy is to overwrite the element with
1499          * the last one, and then reduce the array size by 1
1500          */
1501         l2_lookup[match] = l2_lookup[table->entry_count - 1];
1502         return sja1105_table_resize(table, table->entry_count - 1);
1503 }
1504
1505 /* First-generation switches have a 4-way set associative TCAM that
1506  * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1507  * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1508  * For the placement of a newly learnt FDB entry, the switch selects the bin
1509  * based on a hash function, and the way within that bin incrementally.
1510  */
1511 static int sja1105et_fdb_index(int bin, int way)
1512 {
1513         return bin * SJA1105ET_FDB_BIN_SIZE + way;
1514 }
1515
1516 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1517                                          const u8 *addr, u16 vid,
1518                                          struct sja1105_l2_lookup_entry *match,
1519                                          int *last_unused)
1520 {
1521         int way;
1522
1523         for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1524                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1525                 int index = sja1105et_fdb_index(bin, way);
1526
1527                 /* Skip unused entries, optionally marking them
1528                  * into the return value
1529                  */
1530                 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1531                                                 index, &l2_lookup)) {
1532                         if (last_unused)
1533                                 *last_unused = way;
1534                         continue;
1535                 }
1536
1537                 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1538                     l2_lookup.vlanid == vid) {
1539                         if (match)
1540                                 *match = l2_lookup;
1541                         return way;
1542                 }
1543         }
1544         /* Return an invalid entry index if not found */
1545         return -1;
1546 }
1547
1548 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1549                       const unsigned char *addr, u16 vid)
1550 {
1551         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1552         struct sja1105_private *priv = ds->priv;
1553         struct device *dev = ds->dev;
1554         int last_unused = -1;
1555         int start, end, i;
1556         int bin, way, rc;
1557
1558         bin = sja1105et_fdb_hash(priv, addr, vid);
1559
1560         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1561                                             &l2_lookup, &last_unused);
1562         if (way >= 0) {
1563                 /* We have an FDB entry. Is our port in the destination
1564                  * mask? If yes, we need to do nothing. If not, we need
1565                  * to rewrite the entry by adding this port to it.
1566                  */
1567                 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1568                         return 0;
1569                 l2_lookup.destports |= BIT(port);
1570         } else {
1571                 int index = sja1105et_fdb_index(bin, way);
1572
1573                 /* We don't have an FDB entry. We construct a new one and
1574                  * try to find a place for it within the FDB table.
1575                  */
1576                 l2_lookup.macaddr = ether_addr_to_u64(addr);
1577                 l2_lookup.destports = BIT(port);
1578                 l2_lookup.vlanid = vid;
1579
1580                 if (last_unused >= 0) {
1581                         way = last_unused;
1582                 } else {
1583                         /* Bin is full, need to evict somebody.
1584                          * Choose victim at random. If you get these messages
1585                          * often, you may need to consider changing the
1586                          * distribution function:
1587                          * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1588                          */
1589                         get_random_bytes(&way, sizeof(u8));
1590                         way %= SJA1105ET_FDB_BIN_SIZE;
1591                         dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1592                                  bin, addr, way);
1593                         /* Evict entry */
1594                         sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1595                                                      index, NULL, false);
1596                 }
1597         }
1598         l2_lookup.lockeds = true;
1599         l2_lookup.index = sja1105et_fdb_index(bin, way);
1600
1601         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1602                                           l2_lookup.index, &l2_lookup,
1603                                           true);
1604         if (rc < 0)
1605                 return rc;
1606
1607         /* Invalidate a dynamically learned entry if that exists */
1608         start = sja1105et_fdb_index(bin, 0);
1609         end = sja1105et_fdb_index(bin, way);
1610
1611         for (i = start; i < end; i++) {
1612                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1613                                                  i, &tmp);
1614                 if (rc == -ENOENT)
1615                         continue;
1616                 if (rc)
1617                         return rc;
1618
1619                 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1620                         continue;
1621
1622                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1623                                                   i, NULL, false);
1624                 if (rc)
1625                         return rc;
1626
1627                 break;
1628         }
1629
1630         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1631 }
1632
1633 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1634                       const unsigned char *addr, u16 vid)
1635 {
1636         struct sja1105_l2_lookup_entry l2_lookup = {0};
1637         struct sja1105_private *priv = ds->priv;
1638         int index, bin, way, rc;
1639         bool keep;
1640
1641         bin = sja1105et_fdb_hash(priv, addr, vid);
1642         way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1643                                             &l2_lookup, NULL);
1644         if (way < 0)
1645                 return 0;
1646         index = sja1105et_fdb_index(bin, way);
1647
1648         /* We have an FDB entry. Is our port in the destination mask? If yes,
1649          * we need to remove it. If the resulting port mask becomes empty, we
1650          * need to completely evict the FDB entry.
1651          * Otherwise we just write it back.
1652          */
1653         l2_lookup.destports &= ~BIT(port);
1654
1655         if (l2_lookup.destports)
1656                 keep = true;
1657         else
1658                 keep = false;
1659
1660         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1661                                           index, &l2_lookup, keep);
1662         if (rc < 0)
1663                 return rc;
1664
1665         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1666 }
1667
1668 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1669                         const unsigned char *addr, u16 vid)
1670 {
1671         struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1672         struct sja1105_private *priv = ds->priv;
1673         int rc, i;
1674
1675         /* Search for an existing entry in the FDB table */
1676         l2_lookup.macaddr = ether_addr_to_u64(addr);
1677         l2_lookup.vlanid = vid;
1678         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1679         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1680         l2_lookup.destports = BIT(port);
1681
1682         tmp = l2_lookup;
1683
1684         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1685                                          SJA1105_SEARCH, &tmp);
1686         if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1687                 /* Found a static entry and this port is already in the entry's
1688                  * port mask => job done
1689                  */
1690                 if ((tmp.destports & BIT(port)) && tmp.lockeds)
1691                         return 0;
1692
1693                 l2_lookup = tmp;
1694
1695                 /* l2_lookup.index is populated by the switch in case it
1696                  * found something.
1697                  */
1698                 l2_lookup.destports |= BIT(port);
1699                 goto skip_finding_an_index;
1700         }
1701
1702         /* Not found, so try to find an unused spot in the FDB.
1703          * This is slightly inefficient because the strategy is knock-knock at
1704          * every possible position from 0 to 1023.
1705          */
1706         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1707                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1708                                                  i, NULL);
1709                 if (rc < 0)
1710                         break;
1711         }
1712         if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1713                 dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1714                 return -EINVAL;
1715         }
1716         l2_lookup.index = i;
1717
1718 skip_finding_an_index:
1719         l2_lookup.lockeds = true;
1720
1721         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1722                                           l2_lookup.index, &l2_lookup,
1723                                           true);
1724         if (rc < 0)
1725                 return rc;
1726
1727         /* The switch learns dynamic entries and looks up the FDB left to
1728          * right. It is possible that our addition was concurrent with the
1729          * dynamic learning of the same address, so now that the static entry
1730          * has been installed, we are certain that address learning for this
1731          * particular address has been turned off, so the dynamic entry either
1732          * is in the FDB at an index smaller than the static one, or isn't (it
1733          * can also be at a larger index, but in that case it is inactive
1734          * because the static FDB entry will match first, and the dynamic one
1735          * will eventually age out). Search for a dynamically learned address
1736          * prior to our static one and invalidate it.
1737          */
1738         tmp = l2_lookup;
1739
1740         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1741                                          SJA1105_SEARCH, &tmp);
1742         if (rc < 0) {
1743                 dev_err(ds->dev,
1744                         "port %d failed to read back entry for %pM vid %d: %pe\n",
1745                         port, addr, vid, ERR_PTR(rc));
1746                 return rc;
1747         }
1748
1749         if (tmp.index < l2_lookup.index) {
1750                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1751                                                   tmp.index, NULL, false);
1752                 if (rc < 0)
1753                         return rc;
1754         }
1755
1756         return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1757 }
1758
1759 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1760                         const unsigned char *addr, u16 vid)
1761 {
1762         struct sja1105_l2_lookup_entry l2_lookup = {0};
1763         struct sja1105_private *priv = ds->priv;
1764         bool keep;
1765         int rc;
1766
1767         l2_lookup.macaddr = ether_addr_to_u64(addr);
1768         l2_lookup.vlanid = vid;
1769         l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1770         l2_lookup.mask_vlanid = VLAN_VID_MASK;
1771         l2_lookup.destports = BIT(port);
1772
1773         rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1774                                          SJA1105_SEARCH, &l2_lookup);
1775         if (rc < 0)
1776                 return 0;
1777
1778         l2_lookup.destports &= ~BIT(port);
1779
1780         /* Decide whether we remove just this port from the FDB entry,
1781          * or if we remove it completely.
1782          */
1783         if (l2_lookup.destports)
1784                 keep = true;
1785         else
1786                 keep = false;
1787
1788         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1789                                           l2_lookup.index, &l2_lookup, keep);
1790         if (rc < 0)
1791                 return rc;
1792
1793         return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1794 }
1795
1796 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1797                            const unsigned char *addr, u16 vid,
1798                            struct dsa_db db)
1799 {
1800         struct sja1105_private *priv = ds->priv;
1801         int rc;
1802
1803         if (!vid) {
1804                 switch (db.type) {
1805                 case DSA_DB_PORT:
1806                         vid = dsa_tag_8021q_standalone_vid(db.dp);
1807                         break;
1808                 case DSA_DB_BRIDGE:
1809                         vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1810                         break;
1811                 default:
1812                         return -EOPNOTSUPP;
1813                 }
1814         }
1815
1816         mutex_lock(&priv->fdb_lock);
1817         rc = priv->info->fdb_add_cmd(ds, port, addr, vid);
1818         mutex_unlock(&priv->fdb_lock);
1819
1820         return rc;
1821 }
1822
1823 static int __sja1105_fdb_del(struct dsa_switch *ds, int port,
1824                              const unsigned char *addr, u16 vid,
1825                              struct dsa_db db)
1826 {
1827         struct sja1105_private *priv = ds->priv;
1828
1829         if (!vid) {
1830                 switch (db.type) {
1831                 case DSA_DB_PORT:
1832                         vid = dsa_tag_8021q_standalone_vid(db.dp);
1833                         break;
1834                 case DSA_DB_BRIDGE:
1835                         vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1836                         break;
1837                 default:
1838                         return -EOPNOTSUPP;
1839                 }
1840         }
1841
1842         return priv->info->fdb_del_cmd(ds, port, addr, vid);
1843 }
1844
1845 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1846                            const unsigned char *addr, u16 vid,
1847                            struct dsa_db db)
1848 {
1849         struct sja1105_private *priv = ds->priv;
1850         int rc;
1851
1852         mutex_lock(&priv->fdb_lock);
1853         rc = __sja1105_fdb_del(ds, port, addr, vid, db);
1854         mutex_unlock(&priv->fdb_lock);
1855
1856         return rc;
1857 }
1858
1859 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1860                             dsa_fdb_dump_cb_t *cb, void *data)
1861 {
1862         struct sja1105_private *priv = ds->priv;
1863         struct device *dev = ds->dev;
1864         int i;
1865
1866         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1867                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1868                 u8 macaddr[ETH_ALEN];
1869                 int rc;
1870
1871                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1872                                                  i, &l2_lookup);
1873                 /* No fdb entry at i, not an issue */
1874                 if (rc == -ENOENT)
1875                         continue;
1876                 if (rc) {
1877                         dev_err(dev, "Failed to dump FDB: %d\n", rc);
1878                         return rc;
1879                 }
1880
1881                 /* FDB dump callback is per port. This means we have to
1882                  * disregard a valid entry if it's not for this port, even if
1883                  * only to revisit it later. This is inefficient because the
1884                  * 1024-sized FDB table needs to be traversed 4 times through
1885                  * SPI during a 'bridge fdb show' command.
1886                  */
1887                 if (!(l2_lookup.destports & BIT(port)))
1888                         continue;
1889
1890                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1891
1892                 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show"
1893                  * only wants to see unicast
1894                  */
1895                 if (is_multicast_ether_addr(macaddr))
1896                         continue;
1897
1898                 /* We need to hide the dsa_8021q VLANs from the user. */
1899                 if (vid_is_dsa_8021q(l2_lookup.vlanid))
1900                         l2_lookup.vlanid = 0;
1901                 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1902                 if (rc)
1903                         return rc;
1904         }
1905         return 0;
1906 }
1907
1908 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1909 {
1910         struct dsa_port *dp = dsa_to_port(ds, port);
1911         struct sja1105_private *priv = ds->priv;
1912         struct dsa_db db = {
1913                 .type = DSA_DB_BRIDGE,
1914                 .bridge = {
1915                         .dev = dsa_port_bridge_dev_get(dp),
1916                         .num = dsa_port_bridge_num_get(dp),
1917                 },
1918         };
1919         int i;
1920
1921         mutex_lock(&priv->fdb_lock);
1922
1923         for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1924                 struct sja1105_l2_lookup_entry l2_lookup = {0};
1925                 u8 macaddr[ETH_ALEN];
1926                 int rc;
1927
1928                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1929                                                  i, &l2_lookup);
1930                 /* No fdb entry at i, not an issue */
1931                 if (rc == -ENOENT)
1932                         continue;
1933                 if (rc) {
1934                         dev_err(ds->dev, "Failed to read FDB: %pe\n",
1935                                 ERR_PTR(rc));
1936                         break;
1937                 }
1938
1939                 if (!(l2_lookup.destports & BIT(port)))
1940                         continue;
1941
1942                 /* Don't delete static FDB entries */
1943                 if (l2_lookup.lockeds)
1944                         continue;
1945
1946                 u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1947
1948                 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);
1949                 if (rc) {
1950                         dev_err(ds->dev,
1951                                 "Failed to delete FDB entry %pM vid %lld: %pe\n",
1952                                 macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1953                         break;
1954                 }
1955         }
1956
1957         mutex_unlock(&priv->fdb_lock);
1958 }
1959
1960 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1961                            const struct switchdev_obj_port_mdb *mdb,
1962                            struct dsa_db db)
1963 {
1964         return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);
1965 }
1966
1967 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1968                            const struct switchdev_obj_port_mdb *mdb,
1969                            struct dsa_db db)
1970 {
1971         return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);
1972 }
1973
1974 /* Common function for unicast and broadcast flood configuration.
1975  * Flooding is configured between each {ingress, egress} port pair, and since
1976  * the bridge's semantics are those of "egress flooding", it means we must
1977  * enable flooding towards this port from all ingress ports that are in the
1978  * same forwarding domain.
1979  */
1980 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1981 {
1982         struct sja1105_l2_forwarding_entry *l2_fwd;
1983         struct dsa_switch *ds = priv->ds;
1984         int from, to, rc;
1985
1986         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1987
1988         for (from = 0; from < ds->num_ports; from++) {
1989                 u64 fl_domain = 0, bc_domain = 0;
1990
1991                 for (to = 0; to < priv->ds->num_ports; to++) {
1992                         if (!sja1105_can_forward(l2_fwd, from, to))
1993                                 continue;
1994
1995                         if (priv->ucast_egress_floods & BIT(to))
1996                                 fl_domain |= BIT(to);
1997                         if (priv->bcast_egress_floods & BIT(to))
1998                                 bc_domain |= BIT(to);
1999                 }
2000
2001                 /* Nothing changed, nothing to do */
2002                 if (l2_fwd[from].fl_domain == fl_domain &&
2003                     l2_fwd[from].bc_domain == bc_domain)
2004                         continue;
2005
2006                 l2_fwd[from].fl_domain = fl_domain;
2007                 l2_fwd[from].bc_domain = bc_domain;
2008
2009                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2010                                                   from, &l2_fwd[from], true);
2011                 if (rc < 0)
2012                         return rc;
2013         }
2014
2015         return 0;
2016 }
2017
2018 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
2019                                  struct dsa_bridge bridge, bool member)
2020 {
2021         struct sja1105_l2_forwarding_entry *l2_fwd;
2022         struct sja1105_private *priv = ds->priv;
2023         int i, rc;
2024
2025         l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
2026
2027         for (i = 0; i < ds->num_ports; i++) {
2028                 /* Add this port to the forwarding matrix of the
2029                  * other ports in the same bridge, and viceversa.
2030                  */
2031                 if (!dsa_is_user_port(ds, i))
2032                         continue;
2033                 /* For the ports already under the bridge, only one thing needs
2034                  * to be done, and that is to add this port to their
2035                  * reachability domain. So we can perform the SPI write for
2036                  * them immediately. However, for this port itself (the one
2037                  * that is new to the bridge), we need to add all other ports
2038                  * to its reachability domain. So we do that incrementally in
2039                  * this loop, and perform the SPI write only at the end, once
2040                  * the domain contains all other bridge ports.
2041                  */
2042                 if (i == port)
2043                         continue;
2044                 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2045                         continue;
2046                 sja1105_port_allow_traffic(l2_fwd, i, port, member);
2047                 sja1105_port_allow_traffic(l2_fwd, port, i, member);
2048
2049                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2050                                                   i, &l2_fwd[i], true);
2051                 if (rc < 0)
2052                         return rc;
2053         }
2054
2055         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2056                                           port, &l2_fwd[port], true);
2057         if (rc)
2058                 return rc;
2059
2060         rc = sja1105_commit_pvid(ds, port);
2061         if (rc)
2062                 return rc;
2063
2064         return sja1105_manage_flood_domains(priv);
2065 }
2066
2067 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2068                                          u8 state)
2069 {
2070         struct dsa_port *dp = dsa_to_port(ds, port);
2071         struct sja1105_private *priv = ds->priv;
2072         struct sja1105_mac_config_entry *mac;
2073
2074         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2075
2076         switch (state) {
2077         case BR_STATE_DISABLED:
2078         case BR_STATE_BLOCKING:
2079                 /* From UM10944 description of DRPDTAG (why put this there?):
2080                  * "Management traffic flows to the port regardless of the state
2081                  * of the INGRESS flag". So BPDUs are still be allowed to pass.
2082                  * At the moment no difference between DISABLED and BLOCKING.
2083                  */
2084                 mac[port].ingress   = false;
2085                 mac[port].egress    = false;
2086                 mac[port].dyn_learn = false;
2087                 break;
2088         case BR_STATE_LISTENING:
2089                 mac[port].ingress   = true;
2090                 mac[port].egress    = false;
2091                 mac[port].dyn_learn = false;
2092                 break;
2093         case BR_STATE_LEARNING:
2094                 mac[port].ingress   = true;
2095                 mac[port].egress    = false;
2096                 mac[port].dyn_learn = dp->learning;
2097                 break;
2098         case BR_STATE_FORWARDING:
2099                 mac[port].ingress   = true;
2100                 mac[port].egress    = true;
2101                 mac[port].dyn_learn = dp->learning;
2102                 break;
2103         default:
2104                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2105                 return;
2106         }
2107
2108         sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2109                                      &mac[port], true);
2110 }
2111
2112 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2113                                struct dsa_bridge bridge,
2114                                bool *tx_fwd_offload,
2115                                struct netlink_ext_ack *extack)
2116 {
2117         int rc;
2118
2119         rc = sja1105_bridge_member(ds, port, bridge, true);
2120         if (rc)
2121                 return rc;
2122
2123         rc = dsa_tag_8021q_bridge_join(ds, port, bridge);
2124         if (rc) {
2125                 sja1105_bridge_member(ds, port, bridge, false);
2126                 return rc;
2127         }
2128
2129         *tx_fwd_offload = true;
2130
2131         return 0;
2132 }
2133
2134 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2135                                  struct dsa_bridge bridge)
2136 {
2137         dsa_tag_8021q_bridge_leave(ds, port, bridge);
2138         sja1105_bridge_member(ds, port, bridge, false);
2139 }
2140
2141 #define BYTES_PER_KBIT (1000LL / 8)
2142 /* Port 0 (the uC port) does not have CBS shapers */
2143 #define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio))
2144
2145 static int sja1105_find_cbs_shaper(struct sja1105_private *priv,
2146                                    int port, int prio)
2147 {
2148         int i;
2149
2150         if (priv->info->fixed_cbs_mapping) {
2151                 i = SJA1110_FIXED_CBS(port, prio);
2152                 if (i >= 0 && i < priv->info->num_cbs_shapers)
2153                         return i;
2154
2155                 return -1;
2156         }
2157
2158         for (i = 0; i < priv->info->num_cbs_shapers; i++)
2159                 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio)
2160                         return i;
2161
2162         return -1;
2163 }
2164
2165 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2166 {
2167         int i;
2168
2169         if (priv->info->fixed_cbs_mapping)
2170                 return -1;
2171
2172         for (i = 0; i < priv->info->num_cbs_shapers; i++)
2173                 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2174                         return i;
2175
2176         return -1;
2177 }
2178
2179 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2180                                      int prio)
2181 {
2182         int i;
2183
2184         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2185                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2186
2187                 if (cbs->port == port && cbs->prio == prio) {
2188                         memset(cbs, 0, sizeof(*cbs));
2189                         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2190                                                             i, cbs, true);
2191                 }
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2198                                 struct tc_cbs_qopt_offload *offload)
2199 {
2200         struct sja1105_private *priv = ds->priv;
2201         struct sja1105_cbs_entry *cbs;
2202         s64 port_transmit_rate_kbps;
2203         int index;
2204
2205         if (!offload->enable)
2206                 return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2207
2208         /* The user may be replacing an existing shaper */
2209         index = sja1105_find_cbs_shaper(priv, port, offload->queue);
2210         if (index < 0) {
2211                 /* That isn't the case - see if we can allocate a new one */
2212                 index = sja1105_find_unused_cbs_shaper(priv);
2213                 if (index < 0)
2214                         return -ENOSPC;
2215         }
2216
2217         cbs = &priv->cbs[index];
2218         cbs->port = port;
2219         cbs->prio = offload->queue;
2220         /* locredit and sendslope are negative by definition. In hardware,
2221          * positive values must be provided, and the negative sign is implicit.
2222          */
2223         cbs->credit_hi = offload->hicredit;
2224         cbs->credit_lo = abs(offload->locredit);
2225         /* User space is in kbits/sec, while the hardware in bytes/sec times
2226          * link speed. Since the given offload->sendslope is good only for the
2227          * current link speed anyway, and user space is likely to reprogram it
2228          * when that changes, don't even bother to track the port's link speed,
2229          * but deduce the port transmit rate from idleslope - sendslope.
2230          */
2231         port_transmit_rate_kbps = offload->idleslope - offload->sendslope;
2232         cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT,
2233                                   port_transmit_rate_kbps);
2234         cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT),
2235                                   port_transmit_rate_kbps);
2236         /* Convert the negative values from 64-bit 2's complement
2237          * to 32-bit 2's complement (for the case of 0x80000000 whose
2238          * negative is still negative).
2239          */
2240         cbs->credit_lo &= GENMASK_ULL(31, 0);
2241         cbs->send_slope &= GENMASK_ULL(31, 0);
2242
2243         return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2244                                             true);
2245 }
2246
2247 static int sja1105_reload_cbs(struct sja1105_private *priv)
2248 {
2249         int rc = 0, i;
2250
2251         /* The credit based shapers are only allocated if
2252          * CONFIG_NET_SCH_CBS is enabled.
2253          */
2254         if (!priv->cbs)
2255                 return 0;
2256
2257         for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2258                 struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2259
2260                 if (!cbs->idle_slope && !cbs->send_slope)
2261                         continue;
2262
2263                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2264                                                   true);
2265                 if (rc)
2266                         break;
2267         }
2268
2269         return rc;
2270 }
2271
2272 static const char * const sja1105_reset_reasons[] = {
2273         [SJA1105_VLAN_FILTERING] = "VLAN filtering",
2274         [SJA1105_AGEING_TIME] = "Ageing time",
2275         [SJA1105_SCHEDULING] = "Time-aware scheduling",
2276         [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2277         [SJA1105_VIRTUAL_LINKS] = "Virtual links",
2278 };
2279
2280 /* For situations where we need to change a setting at runtime that is only
2281  * available through the static configuration, resetting the switch in order
2282  * to upload the new static config is unavoidable. Back up the settings we
2283  * modify at runtime (currently only MAC) and restore them after uploading,
2284  * such that this operation is relatively seamless.
2285  */
2286 int sja1105_static_config_reload(struct sja1105_private *priv,
2287                                  enum sja1105_reset_reason reason)
2288 {
2289         struct ptp_system_timestamp ptp_sts_before;
2290         struct ptp_system_timestamp ptp_sts_after;
2291         int speed_mbps[SJA1105_MAX_NUM_PORTS];
2292         u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2293         struct sja1105_mac_config_entry *mac;
2294         struct dsa_switch *ds = priv->ds;
2295         s64 t1, t2, t3, t4;
2296         s64 t12, t34;
2297         int rc, i;
2298         s64 now;
2299
2300         mutex_lock(&priv->fdb_lock);
2301         mutex_lock(&priv->mgmt_lock);
2302
2303         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2304
2305         /* Back up the dynamic link speed changed by sja1105_adjust_port_config
2306          * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2307          * switch wants to see in the static config in order to allow us to
2308          * change it through the dynamic interface later.
2309          */
2310         for (i = 0; i < ds->num_ports; i++) {
2311                 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2312                                                               mac[i].speed);
2313                 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2314
2315                 if (priv->xpcs[i])
2316                         bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,
2317                                                    MDIO_MMD_VEND2, MDIO_CTRL1);
2318         }
2319
2320         /* No PTP operations can run right now */
2321         mutex_lock(&priv->ptp_data.lock);
2322
2323         rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2324         if (rc < 0) {
2325                 mutex_unlock(&priv->ptp_data.lock);
2326                 goto out;
2327         }
2328
2329         /* Reset switch and send updated static configuration */
2330         rc = sja1105_static_config_upload(priv);
2331         if (rc < 0) {
2332                 mutex_unlock(&priv->ptp_data.lock);
2333                 goto out;
2334         }
2335
2336         rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2337         if (rc < 0) {
2338                 mutex_unlock(&priv->ptp_data.lock);
2339                 goto out;
2340         }
2341
2342         t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2343         t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2344         t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2345         t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2346         /* Mid point, corresponds to pre-reset PTPCLKVAL */
2347         t12 = t1 + (t2 - t1) / 2;
2348         /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2349         t34 = t3 + (t4 - t3) / 2;
2350         /* Advance PTPCLKVAL by the time it took since its readout */
2351         now += (t34 - t12);
2352
2353         __sja1105_ptp_adjtime(ds, now);
2354
2355         mutex_unlock(&priv->ptp_data.lock);
2356
2357         dev_info(priv->ds->dev,
2358                  "Reset switch and programmed static config. Reason: %s\n",
2359                  sja1105_reset_reasons[reason]);
2360
2361         /* Configure the CGU (PLLs) for MII and RMII PHYs.
2362          * For these interfaces there is no dynamic configuration
2363          * needed, since PLLs have same settings at all speeds.
2364          */
2365         if (priv->info->clocking_setup) {
2366                 rc = priv->info->clocking_setup(priv);
2367                 if (rc < 0)
2368                         goto out;
2369         }
2370
2371         for (i = 0; i < ds->num_ports; i++) {
2372                 struct dw_xpcs *xpcs = priv->xpcs[i];
2373                 unsigned int neg_mode;
2374
2375                 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2376                 if (rc < 0)
2377                         goto out;
2378
2379                 if (!xpcs)
2380                         continue;
2381
2382                 if (bmcr[i] & BMCR_ANENABLE)
2383                         neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
2384                 else
2385                         neg_mode = PHYLINK_PCS_NEG_OUTBAND;
2386
2387                 rc = xpcs_do_config(xpcs, priv->phy_mode[i], NULL, neg_mode);
2388                 if (rc < 0)
2389                         goto out;
2390
2391                 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) {
2392                         int speed = SPEED_UNKNOWN;
2393
2394                         if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2395                                 speed = SPEED_2500;
2396                         else if (bmcr[i] & BMCR_SPEED1000)
2397                                 speed = SPEED_1000;
2398                         else if (bmcr[i] & BMCR_SPEED100)
2399                                 speed = SPEED_100;
2400                         else
2401                                 speed = SPEED_10;
2402
2403                         xpcs_link_up(&xpcs->pcs, neg_mode, priv->phy_mode[i],
2404                                      speed, DUPLEX_FULL);
2405                 }
2406         }
2407
2408         rc = sja1105_reload_cbs(priv);
2409         if (rc < 0)
2410                 goto out;
2411 out:
2412         mutex_unlock(&priv->mgmt_lock);
2413         mutex_unlock(&priv->fdb_lock);
2414
2415         return rc;
2416 }
2417
2418 static enum dsa_tag_protocol
2419 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2420                          enum dsa_tag_protocol mp)
2421 {
2422         struct sja1105_private *priv = ds->priv;
2423
2424         return priv->info->tag_proto;
2425 }
2426
2427 /* The TPID setting belongs to the General Parameters table,
2428  * which can only be partially reconfigured at runtime (and not the TPID).
2429  * So a switch reset is required.
2430  */
2431 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2432                            struct netlink_ext_ack *extack)
2433 {
2434         struct sja1105_general_params_entry *general_params;
2435         struct sja1105_private *priv = ds->priv;
2436         struct sja1105_table *table;
2437         struct sja1105_rule *rule;
2438         u16 tpid, tpid2;
2439         int rc;
2440
2441         list_for_each_entry(rule, &priv->flow_block.rules, list) {
2442                 if (rule->type == SJA1105_RULE_VL) {
2443                         NL_SET_ERR_MSG_MOD(extack,
2444                                            "Cannot change VLAN filtering with active VL rules");
2445                         return -EBUSY;
2446                 }
2447         }
2448
2449         if (enabled) {
2450                 /* Enable VLAN filtering. */
2451                 tpid  = ETH_P_8021Q;
2452                 tpid2 = ETH_P_8021AD;
2453         } else {
2454                 /* Disable VLAN filtering. */
2455                 tpid  = ETH_P_SJA1105;
2456                 tpid2 = ETH_P_SJA1105;
2457         }
2458
2459         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2460         general_params = table->entries;
2461         /* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2462         general_params->tpid = tpid;
2463         /* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2464         general_params->tpid2 = tpid2;
2465
2466         for (port = 0; port < ds->num_ports; port++) {
2467                 if (dsa_is_unused_port(ds, port))
2468                         continue;
2469
2470                 rc = sja1105_commit_pvid(ds, port);
2471                 if (rc)
2472                         return rc;
2473         }
2474
2475         rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2476         if (rc)
2477                 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2478
2479         return rc;
2480 }
2481
2482 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2483                             u16 flags, bool allowed_ingress)
2484 {
2485         struct sja1105_vlan_lookup_entry *vlan;
2486         struct sja1105_table *table;
2487         int match, rc;
2488
2489         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2490
2491         match = sja1105_is_vlan_configured(priv, vid);
2492         if (match < 0) {
2493                 rc = sja1105_table_resize(table, table->entry_count + 1);
2494                 if (rc)
2495                         return rc;
2496                 match = table->entry_count - 1;
2497         }
2498
2499         /* Assign pointer after the resize (it's new memory) */
2500         vlan = table->entries;
2501
2502         vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2503         vlan[match].vlanid = vid;
2504         vlan[match].vlan_bc |= BIT(port);
2505
2506         if (allowed_ingress)
2507                 vlan[match].vmemb_port |= BIT(port);
2508         else
2509                 vlan[match].vmemb_port &= ~BIT(port);
2510
2511         if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2512                 vlan[match].tag_port &= ~BIT(port);
2513         else
2514                 vlan[match].tag_port |= BIT(port);
2515
2516         return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2517                                             &vlan[match], true);
2518 }
2519
2520 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2521 {
2522         struct sja1105_vlan_lookup_entry *vlan;
2523         struct sja1105_table *table;
2524         bool keep = true;
2525         int match, rc;
2526
2527         table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2528
2529         match = sja1105_is_vlan_configured(priv, vid);
2530         /* Can't delete a missing entry. */
2531         if (match < 0)
2532                 return 0;
2533
2534         /* Assign pointer after the resize (it's new memory) */
2535         vlan = table->entries;
2536
2537         vlan[match].vlanid = vid;
2538         vlan[match].vlan_bc &= ~BIT(port);
2539         vlan[match].vmemb_port &= ~BIT(port);
2540         /* Also unset tag_port, just so we don't have a confusing bitmap
2541          * (no practical purpose).
2542          */
2543         vlan[match].tag_port &= ~BIT(port);
2544
2545         /* If there's no port left as member of this VLAN,
2546          * it's time for it to go.
2547          */
2548         if (!vlan[match].vmemb_port)
2549                 keep = false;
2550
2551         rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2552                                           &vlan[match], keep);
2553         if (rc < 0)
2554                 return rc;
2555
2556         if (!keep)
2557                 return sja1105_table_delete_entry(table, match);
2558
2559         return 0;
2560 }
2561
2562 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2563                                    const struct switchdev_obj_port_vlan *vlan,
2564                                    struct netlink_ext_ack *extack)
2565 {
2566         struct sja1105_private *priv = ds->priv;
2567         u16 flags = vlan->flags;
2568         int rc;
2569
2570         /* Be sure to deny alterations to the configuration done by tag_8021q.
2571          */
2572         if (vid_is_dsa_8021q(vlan->vid)) {
2573                 NL_SET_ERR_MSG_MOD(extack,
2574                                    "Range 3072-4095 reserved for dsa_8021q operation");
2575                 return -EBUSY;
2576         }
2577
2578         /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2579         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2580                 flags = 0;
2581
2582         rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2583         if (rc)
2584                 return rc;
2585
2586         if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2587                 priv->bridge_pvid[port] = vlan->vid;
2588
2589         return sja1105_commit_pvid(ds, port);
2590 }
2591
2592 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2593                                    const struct switchdev_obj_port_vlan *vlan)
2594 {
2595         struct sja1105_private *priv = ds->priv;
2596         int rc;
2597
2598         rc = sja1105_vlan_del(priv, port, vlan->vid);
2599         if (rc)
2600                 return rc;
2601
2602         /* In case the pvid was deleted, make sure that untagged packets will
2603          * be dropped.
2604          */
2605         return sja1105_commit_pvid(ds, port);
2606 }
2607
2608 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2609                                       u16 flags)
2610 {
2611         struct sja1105_private *priv = ds->priv;
2612         bool allowed_ingress = true;
2613         int rc;
2614
2615         /* Prevent attackers from trying to inject a DSA tag from
2616          * the outside world.
2617          */
2618         if (dsa_is_user_port(ds, port))
2619                 allowed_ingress = false;
2620
2621         rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2622         if (rc)
2623                 return rc;
2624
2625         if (flags & BRIDGE_VLAN_INFO_PVID)
2626                 priv->tag_8021q_pvid[port] = vid;
2627
2628         return sja1105_commit_pvid(ds, port);
2629 }
2630
2631 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2632 {
2633         struct sja1105_private *priv = ds->priv;
2634
2635         return sja1105_vlan_del(priv, port, vid);
2636 }
2637
2638 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2639                                   struct netdev_notifier_changeupper_info *info)
2640 {
2641         struct netlink_ext_ack *extack = info->info.extack;
2642         struct net_device *upper = info->upper_dev;
2643         struct dsa_switch_tree *dst = ds->dst;
2644         struct dsa_port *dp;
2645
2646         if (is_vlan_dev(upper)) {
2647                 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2648                 return -EBUSY;
2649         }
2650
2651         if (netif_is_bridge_master(upper)) {
2652                 list_for_each_entry(dp, &dst->ports, list) {
2653                         struct net_device *br = dsa_port_bridge_dev_get(dp);
2654
2655                         if (br && br != upper && br_vlan_enabled(br)) {
2656                                 NL_SET_ERR_MSG_MOD(extack,
2657                                                    "Only one VLAN-aware bridge is supported");
2658                                 return -EBUSY;
2659                         }
2660                 }
2661         }
2662
2663         return 0;
2664 }
2665
2666 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2667                              struct sk_buff *skb, bool takets)
2668 {
2669         struct sja1105_mgmt_entry mgmt_route = {0};
2670         struct sja1105_private *priv = ds->priv;
2671         struct ethhdr *hdr;
2672         int timeout = 10;
2673         int rc;
2674
2675         hdr = eth_hdr(skb);
2676
2677         mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2678         mgmt_route.destports = BIT(port);
2679         mgmt_route.enfport = 1;
2680         mgmt_route.tsreg = 0;
2681         mgmt_route.takets = takets;
2682
2683         rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2684                                           slot, &mgmt_route, true);
2685         if (rc < 0) {
2686                 kfree_skb(skb);
2687                 return rc;
2688         }
2689
2690         /* Transfer skb to the host port. */
2691         dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user);
2692
2693         /* Wait until the switch has processed the frame */
2694         do {
2695                 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2696                                                  slot, &mgmt_route);
2697                 if (rc < 0) {
2698                         dev_err_ratelimited(priv->ds->dev,
2699                                             "failed to poll for mgmt route\n");
2700                         continue;
2701                 }
2702
2703                 /* UM10944: The ENFPORT flag of the respective entry is
2704                  * cleared when a match is found. The host can use this
2705                  * flag as an acknowledgment.
2706                  */
2707                 cpu_relax();
2708         } while (mgmt_route.enfport && --timeout);
2709
2710         if (!timeout) {
2711                 /* Clean up the management route so that a follow-up
2712                  * frame may not match on it by mistake.
2713                  * This is only hardware supported on P/Q/R/S - on E/T it is
2714                  * a no-op and we are silently discarding the -EOPNOTSUPP.
2715                  */
2716                 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2717                                              slot, &mgmt_route, false);
2718                 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2719         }
2720
2721         return NETDEV_TX_OK;
2722 }
2723
2724 #define work_to_xmit_work(w) \
2725                 container_of((w), struct sja1105_deferred_xmit_work, work)
2726
2727 /* Deferred work is unfortunately necessary because setting up the management
2728  * route cannot be done from atomit context (SPI transfer takes a sleepable
2729  * lock on the bus)
2730  */
2731 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2732 {
2733         struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2734         struct sk_buff *clone, *skb = xmit_work->skb;
2735         struct dsa_switch *ds = xmit_work->dp->ds;
2736         struct sja1105_private *priv = ds->priv;
2737         int port = xmit_work->dp->index;
2738
2739         clone = SJA1105_SKB_CB(skb)->clone;
2740
2741         mutex_lock(&priv->mgmt_lock);
2742
2743         sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2744
2745         /* The clone, if there, was made by dsa_skb_tx_timestamp */
2746         if (clone)
2747                 sja1105_ptp_txtstamp_skb(ds, port, clone);
2748
2749         mutex_unlock(&priv->mgmt_lock);
2750
2751         kfree(xmit_work);
2752 }
2753
2754 static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2755                                         enum dsa_tag_protocol proto)
2756 {
2757         struct sja1105_private *priv = ds->priv;
2758         struct sja1105_tagger_data *tagger_data;
2759
2760         if (proto != priv->info->tag_proto)
2761                 return -EPROTONOSUPPORT;
2762
2763         tagger_data = sja1105_tagger_data(ds);
2764         tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2765         tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2766
2767         return 0;
2768 }
2769
2770 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2771  * which cannot be reconfigured at runtime. So a switch reset is required.
2772  */
2773 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2774                                    unsigned int ageing_time)
2775 {
2776         struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2777         struct sja1105_private *priv = ds->priv;
2778         struct sja1105_table *table;
2779         unsigned int maxage;
2780
2781         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2782         l2_lookup_params = table->entries;
2783
2784         maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2785
2786         if (l2_lookup_params->maxage == maxage)
2787                 return 0;
2788
2789         l2_lookup_params->maxage = maxage;
2790
2791         return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2792 }
2793
2794 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2795 {
2796         struct sja1105_l2_policing_entry *policing;
2797         struct sja1105_private *priv = ds->priv;
2798
2799         new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2800
2801         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2802                 new_mtu += VLAN_HLEN;
2803
2804         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2805
2806         if (policing[port].maxlen == new_mtu)
2807                 return 0;
2808
2809         policing[port].maxlen = new_mtu;
2810
2811         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2812 }
2813
2814 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2815 {
2816         return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2817 }
2818
2819 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2820                                  enum tc_setup_type type,
2821                                  void *type_data)
2822 {
2823         switch (type) {
2824         case TC_SETUP_QDISC_TAPRIO:
2825                 return sja1105_setup_tc_taprio(ds, port, type_data);
2826         case TC_SETUP_QDISC_CBS:
2827                 return sja1105_setup_tc_cbs(ds, port, type_data);
2828         default:
2829                 return -EOPNOTSUPP;
2830         }
2831 }
2832
2833 /* We have a single mirror (@to) port, but can configure ingress and egress
2834  * mirroring on all other (@from) ports.
2835  * We need to allow mirroring rules only as long as the @to port is always the
2836  * same, and we need to unset the @to port from mirr_port only when there is no
2837  * mirroring rule that references it.
2838  */
2839 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2840                                 bool ingress, bool enabled)
2841 {
2842         struct sja1105_general_params_entry *general_params;
2843         struct sja1105_mac_config_entry *mac;
2844         struct dsa_switch *ds = priv->ds;
2845         struct sja1105_table *table;
2846         bool already_enabled;
2847         u64 new_mirr_port;
2848         int rc;
2849
2850         table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2851         general_params = table->entries;
2852
2853         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2854
2855         already_enabled = (general_params->mirr_port != ds->num_ports);
2856         if (already_enabled && enabled && general_params->mirr_port != to) {
2857                 dev_err(priv->ds->dev,
2858                         "Delete mirroring rules towards port %llu first\n",
2859                         general_params->mirr_port);
2860                 return -EBUSY;
2861         }
2862
2863         new_mirr_port = to;
2864         if (!enabled) {
2865                 bool keep = false;
2866                 int port;
2867
2868                 /* Anybody still referencing mirr_port? */
2869                 for (port = 0; port < ds->num_ports; port++) {
2870                         if (mac[port].ing_mirr || mac[port].egr_mirr) {
2871                                 keep = true;
2872                                 break;
2873                         }
2874                 }
2875                 /* Unset already_enabled for next time */
2876                 if (!keep)
2877                         new_mirr_port = ds->num_ports;
2878         }
2879         if (new_mirr_port != general_params->mirr_port) {
2880                 general_params->mirr_port = new_mirr_port;
2881
2882                 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2883                                                   0, general_params, true);
2884                 if (rc < 0)
2885                         return rc;
2886         }
2887
2888         if (ingress)
2889                 mac[from].ing_mirr = enabled;
2890         else
2891                 mac[from].egr_mirr = enabled;
2892
2893         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2894                                             &mac[from], true);
2895 }
2896
2897 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2898                               struct dsa_mall_mirror_tc_entry *mirror,
2899                               bool ingress, struct netlink_ext_ack *extack)
2900 {
2901         return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2902                                     ingress, true);
2903 }
2904
2905 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2906                                struct dsa_mall_mirror_tc_entry *mirror)
2907 {
2908         sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2909                              mirror->ingress, false);
2910 }
2911
2912 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2913                                     struct dsa_mall_policer_tc_entry *policer)
2914 {
2915         struct sja1105_l2_policing_entry *policing;
2916         struct sja1105_private *priv = ds->priv;
2917
2918         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2919
2920         /* In hardware, every 8 microseconds the credit level is incremented by
2921          * the value of RATE bytes divided by 64, up to a maximum of SMAX
2922          * bytes.
2923          */
2924         policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2925                                       1000000);
2926         policing[port].smax = policer->burst;
2927
2928         return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2929 }
2930
2931 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2932 {
2933         struct sja1105_l2_policing_entry *policing;
2934         struct sja1105_private *priv = ds->priv;
2935
2936         policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2937
2938         policing[port].rate = SJA1105_RATE_MBPS(1000);
2939         policing[port].smax = 65535;
2940
2941         sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2942 }
2943
2944 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2945                                      bool enabled)
2946 {
2947         struct sja1105_mac_config_entry *mac;
2948
2949         mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2950
2951         mac[port].dyn_learn = enabled;
2952
2953         return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2954                                             &mac[port], true);
2955 }
2956
2957 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2958                                           struct switchdev_brport_flags flags)
2959 {
2960         if (flags.mask & BR_FLOOD) {
2961                 if (flags.val & BR_FLOOD)
2962                         priv->ucast_egress_floods |= BIT(to);
2963                 else
2964                         priv->ucast_egress_floods &= ~BIT(to);
2965         }
2966
2967         if (flags.mask & BR_BCAST_FLOOD) {
2968                 if (flags.val & BR_BCAST_FLOOD)
2969                         priv->bcast_egress_floods |= BIT(to);
2970                 else
2971                         priv->bcast_egress_floods &= ~BIT(to);
2972         }
2973
2974         return sja1105_manage_flood_domains(priv);
2975 }
2976
2977 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2978                                     struct switchdev_brport_flags flags,
2979                                     struct netlink_ext_ack *extack)
2980 {
2981         struct sja1105_l2_lookup_entry *l2_lookup;
2982         struct sja1105_table *table;
2983         int match, rc;
2984
2985         mutex_lock(&priv->fdb_lock);
2986
2987         table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2988         l2_lookup = table->entries;
2989
2990         for (match = 0; match < table->entry_count; match++)
2991                 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2992                     l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2993                         break;
2994
2995         if (match == table->entry_count) {
2996                 NL_SET_ERR_MSG_MOD(extack,
2997                                    "Could not find FDB entry for unknown multicast");
2998                 rc = -ENOSPC;
2999                 goto out;
3000         }
3001
3002         if (flags.val & BR_MCAST_FLOOD)
3003                 l2_lookup[match].destports |= BIT(to);
3004         else
3005                 l2_lookup[match].destports &= ~BIT(to);
3006
3007         rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
3008                                           l2_lookup[match].index,
3009                                           &l2_lookup[match], true);
3010 out:
3011         mutex_unlock(&priv->fdb_lock);
3012
3013         return rc;
3014 }
3015
3016 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3017                                          struct switchdev_brport_flags flags,
3018                                          struct netlink_ext_ack *extack)
3019 {
3020         struct sja1105_private *priv = ds->priv;
3021
3022         if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
3023                            BR_BCAST_FLOOD))
3024                 return -EINVAL;
3025
3026         if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
3027             !priv->info->can_limit_mcast_flood) {
3028                 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
3029                 bool unicast = !!(flags.val & BR_FLOOD);
3030
3031                 if (unicast != multicast) {
3032                         NL_SET_ERR_MSG_MOD(extack,
3033                                            "This chip cannot configure multicast flooding independently of unicast");
3034                         return -EINVAL;
3035                 }
3036         }
3037
3038         return 0;
3039 }
3040
3041 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
3042                                      struct switchdev_brport_flags flags,
3043                                      struct netlink_ext_ack *extack)
3044 {
3045         struct sja1105_private *priv = ds->priv;
3046         int rc;
3047
3048         if (flags.mask & BR_LEARNING) {
3049                 bool learn_ena = !!(flags.val & BR_LEARNING);
3050
3051                 rc = sja1105_port_set_learning(priv, port, learn_ena);
3052                 if (rc)
3053                         return rc;
3054         }
3055
3056         if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
3057                 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
3058                 if (rc)
3059                         return rc;
3060         }
3061
3062         /* For chips that can't offload BR_MCAST_FLOOD independently, there
3063          * is nothing to do here, we ensured the configuration is in sync by
3064          * offloading BR_FLOOD.
3065          */
3066         if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3067                 rc = sja1105_port_mcast_flood(priv, port, flags,
3068                                               extack);
3069                 if (rc)
3070                         return rc;
3071         }
3072
3073         return 0;
3074 }
3075
3076 /* The programming model for the SJA1105 switch is "all-at-once" via static
3077  * configuration tables. Some of these can be dynamically modified at runtime,
3078  * but not the xMII mode parameters table.
3079  * Furthermode, some PHYs may not have crystals for generating their clocks
3080  * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3081  * ref_clk pin. So port clocking needs to be initialized early, before
3082  * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3083  * Setting correct PHY link speed does not matter now.
3084  * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY
3085  * bindings are not yet parsed by DSA core. We need to parse early so that we
3086  * can populate the xMII mode parameters table.
3087  */
3088 static int sja1105_setup(struct dsa_switch *ds)
3089 {
3090         struct sja1105_private *priv = ds->priv;
3091         int rc;
3092
3093         if (priv->info->disable_microcontroller) {
3094                 rc = priv->info->disable_microcontroller(priv);
3095                 if (rc < 0) {
3096                         dev_err(ds->dev,
3097                                 "Failed to disable microcontroller: %pe\n",
3098                                 ERR_PTR(rc));
3099                         return rc;
3100                 }
3101         }
3102
3103         /* Create and send configuration down to device */
3104         rc = sja1105_static_config_load(priv);
3105         if (rc < 0) {
3106                 dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3107                 return rc;
3108         }
3109
3110         /* Configure the CGU (PHY link modes and speeds) */
3111         if (priv->info->clocking_setup) {
3112                 rc = priv->info->clocking_setup(priv);
3113                 if (rc < 0) {
3114                         dev_err(ds->dev,
3115                                 "Failed to configure MII clocking: %pe\n",
3116                                 ERR_PTR(rc));
3117                         goto out_static_config_free;
3118                 }
3119         }
3120
3121         sja1105_tas_setup(ds);
3122         sja1105_flower_setup(ds);
3123
3124         rc = sja1105_ptp_clock_register(ds);
3125         if (rc < 0) {
3126                 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3127                 goto out_flower_teardown;
3128         }
3129
3130         rc = sja1105_mdiobus_register(ds);
3131         if (rc < 0) {
3132                 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3133                         ERR_PTR(rc));
3134                 goto out_ptp_clock_unregister;
3135         }
3136
3137         rc = sja1105_devlink_setup(ds);
3138         if (rc < 0)
3139                 goto out_mdiobus_unregister;
3140
3141         rtnl_lock();
3142         rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3143         rtnl_unlock();
3144         if (rc)
3145                 goto out_devlink_teardown;
3146
3147         /* On SJA1105, VLAN filtering per se is always enabled in hardware.
3148          * The only thing we can do to disable it is lie about what the 802.1Q
3149          * EtherType is.
3150          * So it will still try to apply VLAN filtering, but all ingress
3151          * traffic (except frames received with EtherType of ETH_P_SJA1105)
3152          * will be internally tagged with a distorted VLAN header where the
3153          * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3154          */
3155         ds->vlan_filtering_is_global = true;
3156         ds->untag_bridge_pvid = true;
3157         ds->fdb_isolation = true;
3158         /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3159         ds->max_num_bridges = 7;
3160
3161         /* Advertise the 8 egress queues */
3162         ds->num_tx_queues = SJA1105_NUM_TC;
3163
3164         ds->mtu_enforcement_ingress = true;
3165         ds->assisted_learning_on_cpu_port = true;
3166
3167         return 0;
3168
3169 out_devlink_teardown:
3170         sja1105_devlink_teardown(ds);
3171 out_mdiobus_unregister:
3172         sja1105_mdiobus_unregister(ds);
3173 out_ptp_clock_unregister:
3174         sja1105_ptp_clock_unregister(ds);
3175 out_flower_teardown:
3176         sja1105_flower_teardown(ds);
3177         sja1105_tas_teardown(ds);
3178 out_static_config_free:
3179         sja1105_static_config_free(&priv->static_config);
3180
3181         return rc;
3182 }
3183
3184 static void sja1105_teardown(struct dsa_switch *ds)
3185 {
3186         struct sja1105_private *priv = ds->priv;
3187
3188         rtnl_lock();
3189         dsa_tag_8021q_unregister(ds);
3190         rtnl_unlock();
3191
3192         sja1105_devlink_teardown(ds);
3193         sja1105_mdiobus_unregister(ds);
3194         sja1105_ptp_clock_unregister(ds);
3195         sja1105_flower_teardown(ds);
3196         sja1105_tas_teardown(ds);
3197         sja1105_static_config_free(&priv->static_config);
3198 }
3199
3200 static const struct dsa_switch_ops sja1105_switch_ops = {
3201         .get_tag_protocol       = sja1105_get_tag_protocol,
3202         .connect_tag_protocol   = sja1105_connect_tag_protocol,
3203         .setup                  = sja1105_setup,
3204         .teardown               = sja1105_teardown,
3205         .set_ageing_time        = sja1105_set_ageing_time,
3206         .port_change_mtu        = sja1105_change_mtu,
3207         .port_max_mtu           = sja1105_get_max_mtu,
3208         .phylink_get_caps       = sja1105_phylink_get_caps,
3209         .phylink_mac_select_pcs = sja1105_mac_select_pcs,
3210         .phylink_mac_link_up    = sja1105_mac_link_up,
3211         .phylink_mac_link_down  = sja1105_mac_link_down,
3212         .get_strings            = sja1105_get_strings,
3213         .get_ethtool_stats      = sja1105_get_ethtool_stats,
3214         .get_sset_count         = sja1105_get_sset_count,
3215         .get_ts_info            = sja1105_get_ts_info,
3216         .port_fdb_dump          = sja1105_fdb_dump,
3217         .port_fdb_add           = sja1105_fdb_add,
3218         .port_fdb_del           = sja1105_fdb_del,
3219         .port_fast_age          = sja1105_fast_age,
3220         .port_bridge_join       = sja1105_bridge_join,
3221         .port_bridge_leave      = sja1105_bridge_leave,
3222         .port_pre_bridge_flags  = sja1105_port_pre_bridge_flags,
3223         .port_bridge_flags      = sja1105_port_bridge_flags,
3224         .port_stp_state_set     = sja1105_bridge_stp_state_set,
3225         .port_vlan_filtering    = sja1105_vlan_filtering,
3226         .port_vlan_add          = sja1105_bridge_vlan_add,
3227         .port_vlan_del          = sja1105_bridge_vlan_del,
3228         .port_mdb_add           = sja1105_mdb_add,
3229         .port_mdb_del           = sja1105_mdb_del,
3230         .port_hwtstamp_get      = sja1105_hwtstamp_get,
3231         .port_hwtstamp_set      = sja1105_hwtstamp_set,
3232         .port_rxtstamp          = sja1105_port_rxtstamp,
3233         .port_txtstamp          = sja1105_port_txtstamp,
3234         .port_setup_tc          = sja1105_port_setup_tc,
3235         .port_mirror_add        = sja1105_mirror_add,
3236         .port_mirror_del        = sja1105_mirror_del,
3237         .port_policer_add       = sja1105_port_policer_add,
3238         .port_policer_del       = sja1105_port_policer_del,
3239         .cls_flower_add         = sja1105_cls_flower_add,
3240         .cls_flower_del         = sja1105_cls_flower_del,
3241         .cls_flower_stats       = sja1105_cls_flower_stats,
3242         .devlink_info_get       = sja1105_devlink_info_get,
3243         .tag_8021q_vlan_add     = sja1105_dsa_8021q_vlan_add,
3244         .tag_8021q_vlan_del     = sja1105_dsa_8021q_vlan_del,
3245         .port_prechangeupper    = sja1105_prechangeupper,
3246 };
3247
3248 static const struct of_device_id sja1105_dt_ids[];
3249
3250 static int sja1105_check_device_id(struct sja1105_private *priv)
3251 {
3252         const struct sja1105_regs *regs = priv->info->regs;
3253         u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3254         struct device *dev = &priv->spidev->dev;
3255         const struct of_device_id *match;
3256         u32 device_id;
3257         u64 part_no;
3258         int rc;
3259
3260         rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3261                               NULL);
3262         if (rc < 0)
3263                 return rc;
3264
3265         rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3266                               SJA1105_SIZE_DEVICE_ID);
3267         if (rc < 0)
3268                 return rc;
3269
3270         sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3271
3272         for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3273                 const struct sja1105_info *info = match->data;
3274
3275                 /* Is what's been probed in our match table at all? */
3276                 if (info->device_id != device_id || info->part_no != part_no)
3277                         continue;
3278
3279                 /* But is it what's in the device tree? */
3280                 if (priv->info->device_id != device_id ||
3281                     priv->info->part_no != part_no) {
3282                         dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3283                                  priv->info->name, info->name);
3284                         /* It isn't. No problem, pick that up. */
3285                         priv->info = info;
3286                 }
3287
3288                 return 0;
3289         }
3290
3291         dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3292                 device_id, part_no);
3293
3294         return -ENODEV;
3295 }
3296
3297 static int sja1105_probe(struct spi_device *spi)
3298 {
3299         struct device *dev = &spi->dev;
3300         struct sja1105_private *priv;
3301         size_t max_xfer, max_msg;
3302         struct dsa_switch *ds;
3303         int rc;
3304
3305         if (!dev->of_node) {
3306                 dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3307                 return -EINVAL;
3308         }
3309
3310         rc = sja1105_hw_reset(dev, 1, 1);
3311         if (rc)
3312                 return rc;
3313
3314         priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3315         if (!priv)
3316                 return -ENOMEM;
3317
3318         /* Populate our driver private structure (priv) based on
3319          * the device tree node that was probed (spi)
3320          */
3321         priv->spidev = spi;
3322         spi_set_drvdata(spi, priv);
3323
3324         /* Configure the SPI bus */
3325         spi->bits_per_word = 8;
3326         rc = spi_setup(spi);
3327         if (rc < 0) {
3328                 dev_err(dev, "Could not init SPI\n");
3329                 return rc;
3330         }
3331
3332         /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3333          * a small one for the message header and another one for the current
3334          * chunk of the packed buffer.
3335          * Check that the restrictions imposed by the SPI controller are
3336          * respected: the chunk buffer is smaller than the max transfer size,
3337          * and the total length of the chunk plus its message header is smaller
3338          * than the max message size.
3339          * We do that during probe time since the maximum transfer size is a
3340          * runtime invariant.
3341          */
3342         max_xfer = spi_max_transfer_size(spi);
3343         max_msg = spi_max_message_size(spi);
3344
3345         /* We need to send at least one 64-bit word of SPI payload per message
3346          * in order to be able to make useful progress.
3347          */
3348         if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3349                 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3350                 return -EINVAL;
3351         }
3352
3353         priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3354         if (priv->max_xfer_len > max_xfer)
3355                 priv->max_xfer_len = max_xfer;
3356         if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3357                 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3358
3359         priv->info = of_device_get_match_data(dev);
3360
3361         /* Detect hardware device */
3362         rc = sja1105_check_device_id(priv);
3363         if (rc < 0) {
3364                 dev_err(dev, "Device ID check failed: %d\n", rc);
3365                 return rc;
3366         }
3367
3368         dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3369
3370         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3371         if (!ds)
3372                 return -ENOMEM;
3373
3374         ds->dev = dev;
3375         ds->num_ports = priv->info->num_ports;
3376         ds->ops = &sja1105_switch_ops;
3377         ds->priv = priv;
3378         priv->ds = ds;
3379
3380         mutex_init(&priv->ptp_data.lock);
3381         mutex_init(&priv->dynamic_config_lock);
3382         mutex_init(&priv->mgmt_lock);
3383         mutex_init(&priv->fdb_lock);
3384         spin_lock_init(&priv->ts_id_lock);
3385
3386         rc = sja1105_parse_dt(priv);
3387         if (rc < 0) {
3388                 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3389                 return rc;
3390         }
3391
3392         if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3393                 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3394                                          sizeof(struct sja1105_cbs_entry),
3395                                          GFP_KERNEL);
3396                 if (!priv->cbs)
3397                         return -ENOMEM;
3398         }
3399
3400         return dsa_register_switch(priv->ds);
3401 }
3402
3403 static void sja1105_remove(struct spi_device *spi)
3404 {
3405         struct sja1105_private *priv = spi_get_drvdata(spi);
3406
3407         if (!priv)
3408                 return;
3409
3410         dsa_unregister_switch(priv->ds);
3411 }
3412
3413 static void sja1105_shutdown(struct spi_device *spi)
3414 {
3415         struct sja1105_private *priv = spi_get_drvdata(spi);
3416
3417         if (!priv)
3418                 return;
3419
3420         dsa_switch_shutdown(priv->ds);
3421
3422         spi_set_drvdata(spi, NULL);
3423 }
3424
3425 static const struct of_device_id sja1105_dt_ids[] = {
3426         { .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3427         { .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3428         { .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3429         { .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3430         { .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3431         { .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3432         { .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3433         { .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3434         { .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3435         { .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3436         { /* sentinel */ },
3437 };
3438 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3439
3440 static const struct spi_device_id sja1105_spi_ids[] = {
3441         { "sja1105e" },
3442         { "sja1105t" },
3443         { "sja1105p" },
3444         { "sja1105q" },
3445         { "sja1105r" },
3446         { "sja1105s" },
3447         { "sja1110a" },
3448         { "sja1110b" },
3449         { "sja1110c" },
3450         { "sja1110d" },
3451         { },
3452 };
3453 MODULE_DEVICE_TABLE(spi, sja1105_spi_ids);
3454
3455 static struct spi_driver sja1105_driver = {
3456         .driver = {
3457                 .name  = "sja1105",
3458                 .owner = THIS_MODULE,
3459                 .of_match_table = of_match_ptr(sja1105_dt_ids),
3460         },
3461         .id_table = sja1105_spi_ids,
3462         .probe  = sja1105_probe,
3463         .remove = sja1105_remove,
3464         .shutdown = sja1105_shutdown,
3465 };
3466
3467 module_spi_driver(sja1105_driver);
3468
3469 MODULE_AUTHOR("Vladimir Oltean <[email protected]>");
3470 MODULE_AUTHOR("Georg Waibel <[email protected]>");
3471 MODULE_DESCRIPTION("SJA1105 Driver");
3472 MODULE_LICENSE("GPL v2");