drivers/gpu/drm/tegra/sor.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/io.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/reset.h>
  16
  17 #include <soc/tegra/pmc.h>
  18
  19 #include <drm/display/drm_dp_helper.h>
  20 #include <drm/display/drm_scdc_helper.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_debugfs.h>
  23 #include <drm/drm_file.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_simple_kms_helper.h>
  26
  27 #include "dc.h"
  28 #include "dp.h"
  29 #include "drm.h"
  30 #include "hda.h"
  31 #include "sor.h"
  32 #include "trace.h"
  33
  34 #define SOR_REKEY 0x38
  35
  36 struct tegra_sor_hdmi_settings {
  37         unsigned long frequency;
  38
  39         u8 vcocap;
  40         u8 filter;
  41         u8 ichpmp;
  42         u8 loadadj;
  43         u8 tmds_termadj;
  44         u8 tx_pu_value;
  45         u8 bg_temp_coef;
  46         u8 bg_vref_level;
  47         u8 avdd10_level;
  48         u8 avdd14_level;
  49         u8 sparepll;
  50
  51         u8 drive_current[4];
  52         u8 preemphasis[4];
  53 };
  54
  55 #if 1
  56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57         {
  58                 .frequency = 54000000,
  59                 .vcocap = 0x0,
  60                 .filter = 0x0,
  61                 .ichpmp = 0x1,
  62                 .loadadj = 0x3,
  63                 .tmds_termadj = 0x9,
  64                 .tx_pu_value = 0x10,
  65                 .bg_temp_coef = 0x3,
  66                 .bg_vref_level = 0x8,
  67                 .avdd10_level = 0x4,
  68                 .avdd14_level = 0x4,
  69                 .sparepll = 0x0,
  70                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72         }, {
  73                 .frequency = 75000000,
  74                 .vcocap = 0x3,
  75                 .filter = 0x0,
  76                 .ichpmp = 0x1,
  77                 .loadadj = 0x3,
  78                 .tmds_termadj = 0x9,
  79                 .tx_pu_value = 0x40,
  80                 .bg_temp_coef = 0x3,
  81                 .bg_vref_level = 0x8,
  82                 .avdd10_level = 0x4,
  83                 .avdd14_level = 0x4,
  84                 .sparepll = 0x0,
  85                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87         }, {
  88                 .frequency = 150000000,
  89                 .vcocap = 0x3,
  90                 .filter = 0x0,
  91                 .ichpmp = 0x1,
  92                 .loadadj = 0x3,
  93                 .tmds_termadj = 0x9,
  94                 .tx_pu_value = 0x66,
  95                 .bg_temp_coef = 0x3,
  96                 .bg_vref_level = 0x8,
  97                 .avdd10_level = 0x4,
  98                 .avdd14_level = 0x4,
  99                 .sparepll = 0x0,
 100                 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102         }, {
 103                 .frequency = 300000000,
 104                 .vcocap = 0x3,
 105                 .filter = 0x0,
 106                 .ichpmp = 0x1,
 107                 .loadadj = 0x3,
 108                 .tmds_termadj = 0x9,
 109                 .tx_pu_value = 0x66,
 110                 .bg_temp_coef = 0x3,
 111                 .bg_vref_level = 0xa,
 112                 .avdd10_level = 0x4,
 113                 .avdd14_level = 0x4,
 114                 .sparepll = 0x0,
 115                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116                 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117         }, {
 118                 .frequency = 600000000,
 119                 .vcocap = 0x3,
 120                 .filter = 0x0,
 121                 .ichpmp = 0x1,
 122                 .loadadj = 0x3,
 123                 .tmds_termadj = 0x9,
 124                 .tx_pu_value = 0x66,
 125                 .bg_temp_coef = 0x3,
 126                 .bg_vref_level = 0x8,
 127                 .avdd10_level = 0x4,
 128                 .avdd14_level = 0x4,
 129                 .sparepll = 0x0,
 130                 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132         },
 133 };
 134 #else
 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136         {
 137                 .frequency = 75000000,
 138                 .vcocap = 0x3,
 139                 .filter = 0x0,
 140                 .ichpmp = 0x1,
 141                 .loadadj = 0x3,
 142                 .tmds_termadj = 0x9,
 143                 .tx_pu_value = 0x40,
 144                 .bg_temp_coef = 0x3,
 145                 .bg_vref_level = 0x8,
 146                 .avdd10_level = 0x4,
 147                 .avdd14_level = 0x4,
 148                 .sparepll = 0x0,
 149                 .drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151         }, {
 152                 .frequency = 150000000,
 153                 .vcocap = 0x3,
 154                 .filter = 0x0,
 155                 .ichpmp = 0x1,
 156                 .loadadj = 0x3,
 157                 .tmds_termadj = 0x9,
 158                 .tx_pu_value = 0x66,
 159                 .bg_temp_coef = 0x3,
 160                 .bg_vref_level = 0x8,
 161                 .avdd10_level = 0x4,
 162                 .avdd14_level = 0x4,
 163                 .sparepll = 0x0,
 164                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165                 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166         }, {
 167                 .frequency = 300000000,
 168                 .vcocap = 0x3,
 169                 .filter = 0x0,
 170                 .ichpmp = 0x6,
 171                 .loadadj = 0x3,
 172                 .tmds_termadj = 0x9,
 173                 .tx_pu_value = 0x66,
 174                 .bg_temp_coef = 0x3,
 175                 .bg_vref_level = 0xf,
 176                 .avdd10_level = 0x4,
 177                 .avdd14_level = 0x4,
 178                 .sparepll = 0x0,
 179                 .drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180                 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181         }, {
 182                 .frequency = 600000000,
 183                 .vcocap = 0x3,
 184                 .filter = 0x0,
 185                 .ichpmp = 0xa,
 186                 .loadadj = 0x3,
 187                 .tmds_termadj = 0xb,
 188                 .tx_pu_value = 0x66,
 189                 .bg_temp_coef = 0x3,
 190                 .bg_vref_level = 0xe,
 191                 .avdd10_level = 0x4,
 192                 .avdd14_level = 0x4,
 193                 .sparepll = 0x0,
 194                 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195                 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196         },
 197 };
 198 #endif
 199
 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201         {
 202                 .frequency = 54000000,
 203                 .vcocap = 0,
 204                 .filter = 5,
 205                 .ichpmp = 5,
 206                 .loadadj = 3,
 207                 .tmds_termadj = 0xf,
 208                 .tx_pu_value = 0,
 209                 .bg_temp_coef = 3,
 210                 .bg_vref_level = 8,
 211                 .avdd10_level = 4,
 212                 .avdd14_level = 4,
 213                 .sparepll = 0x54,
 214                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216         }, {
 217                 .frequency = 75000000,
 218                 .vcocap = 1,
 219                 .filter = 5,
 220                 .ichpmp = 5,
 221                 .loadadj = 3,
 222                 .tmds_termadj = 0xf,
 223                 .tx_pu_value = 0,
 224                 .bg_temp_coef = 3,
 225                 .bg_vref_level = 8,
 226                 .avdd10_level = 4,
 227                 .avdd14_level = 4,
 228                 .sparepll = 0x44,
 229                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231         }, {
 232                 .frequency = 150000000,
 233                 .vcocap = 3,
 234                 .filter = 5,
 235                 .ichpmp = 5,
 236                 .loadadj = 3,
 237                 .tmds_termadj = 15,
 238                 .tx_pu_value = 0x66 /* 0 */,
 239                 .bg_temp_coef = 3,
 240                 .bg_vref_level = 8,
 241                 .avdd10_level = 4,
 242                 .avdd14_level = 4,
 243                 .sparepll = 0x00, /* 0x34 */
 244                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246         }, {
 247                 .frequency = 300000000,
 248                 .vcocap = 3,
 249                 .filter = 5,
 250                 .ichpmp = 5,
 251                 .loadadj = 3,
 252                 .tmds_termadj = 15,
 253                 .tx_pu_value = 64,
 254                 .bg_temp_coef = 3,
 255                 .bg_vref_level = 8,
 256                 .avdd10_level = 4,
 257                 .avdd14_level = 4,
 258                 .sparepll = 0x34,
 259                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261         }, {
 262                 .frequency = 600000000,
 263                 .vcocap = 3,
 264                 .filter = 5,
 265                 .ichpmp = 5,
 266                 .loadadj = 3,
 267                 .tmds_termadj = 12,
 268                 .tx_pu_value = 96,
 269                 .bg_temp_coef = 3,
 270                 .bg_vref_level = 8,
 271                 .avdd10_level = 4,
 272                 .avdd14_level = 4,
 273                 .sparepll = 0x34,
 274                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276         }
 277 };
 278
 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280         {
 281                 .frequency = 54000000,
 282                 .vcocap = 0,
 283                 .filter = 5,
 284                 .ichpmp = 5,
 285                 .loadadj = 3,
 286                 .tmds_termadj = 0xf,
 287                 .tx_pu_value = 0,
 288                 .bg_temp_coef = 3,
 289                 .bg_vref_level = 8,
 290                 .avdd10_level = 4,
 291                 .avdd14_level = 4,
 292                 .sparepll = 0x54,
 293                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295         }, {
 296                 .frequency = 75000000,
 297                 .vcocap = 1,
 298                 .filter = 5,
 299                 .ichpmp = 5,
 300                 .loadadj = 3,
 301                 .tmds_termadj = 0xf,
 302                 .tx_pu_value = 0,
 303                 .bg_temp_coef = 3,
 304                 .bg_vref_level = 8,
 305                 .avdd10_level = 4,
 306                 .avdd14_level = 4,
 307                 .sparepll = 0x44,
 308                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310         }, {
 311                 .frequency = 150000000,
 312                 .vcocap = 3,
 313                 .filter = 5,
 314                 .ichpmp = 5,
 315                 .loadadj = 3,
 316                 .tmds_termadj = 15,
 317                 .tx_pu_value = 0x66 /* 0 */,
 318                 .bg_temp_coef = 3,
 319                 .bg_vref_level = 8,
 320                 .avdd10_level = 4,
 321                 .avdd14_level = 4,
 322                 .sparepll = 0x00, /* 0x34 */
 323                 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325         }, {
 326                 .frequency = 300000000,
 327                 .vcocap = 3,
 328                 .filter = 5,
 329                 .ichpmp = 5,
 330                 .loadadj = 3,
 331                 .tmds_termadj = 15,
 332                 .tx_pu_value = 64,
 333                 .bg_temp_coef = 3,
 334                 .bg_vref_level = 8,
 335                 .avdd10_level = 4,
 336                 .avdd14_level = 4,
 337                 .sparepll = 0x34,
 338                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340         }, {
 341                 .frequency = 600000000,
 342                 .vcocap = 3,
 343                 .filter = 5,
 344                 .ichpmp = 5,
 345                 .loadadj = 3,
 346                 .tmds_termadj = 12,
 347                 .tx_pu_value = 96,
 348                 .bg_temp_coef = 3,
 349                 .bg_vref_level = 8,
 350                 .avdd10_level = 4,
 351                 .avdd14_level = 4,
 352                 .sparepll = 0x34,
 353                 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354                 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355         }
 356 };
 357
 358 struct tegra_sor_regs {
 359         unsigned int head_state0;
 360         unsigned int head_state1;
 361         unsigned int head_state2;
 362         unsigned int head_state3;
 363         unsigned int head_state4;
 364         unsigned int head_state5;
 365         unsigned int pll0;
 366         unsigned int pll1;
 367         unsigned int pll2;
 368         unsigned int pll3;
 369         unsigned int dp_padctl0;
 370         unsigned int dp_padctl2;
 371 };
 372
 373 struct tegra_sor_soc {
 374         bool supports_lvds;
 375         bool supports_hdmi;
 376         bool supports_dp;
 377         bool supports_audio;
 378         bool supports_hdcp;
 379
 380         const struct tegra_sor_regs *regs;
 381         bool has_nvdisplay;
 382
 383         const struct tegra_sor_hdmi_settings *settings;
 384         unsigned int num_settings;
 385
 386         const u8 *xbar_cfg;
 387         const u8 *lane_map;
 388
 389         const u8 (*voltage_swing)[4][4];
 390         const u8 (*pre_emphasis)[4][4];
 391         const u8 (*post_cursor)[4][4];
 392         const u8 (*tx_pu)[4][4];
 393 };
 394
 395 struct tegra_sor;
 396
 397 struct tegra_sor_ops {
 398         const char *name;
 399         int (*probe)(struct tegra_sor *sor);
 400         void (*audio_enable)(struct tegra_sor *sor);
 401         void (*audio_disable)(struct tegra_sor *sor);
 402 };
 403
 404 struct tegra_sor {
 405         struct host1x_client client;
 406         struct tegra_output output;
 407         struct device *dev;
 408
 409         const struct tegra_sor_soc *soc;
 410         void __iomem *regs;
 411         unsigned int index;
 412         unsigned int irq;
 413
 414         struct reset_control *rst;
 415         struct clk *clk_parent;
 416         struct clk *clk_safe;
 417         struct clk *clk_out;
 418         struct clk *clk_pad;
 419         struct clk *clk_dp;
 420         struct clk *clk;
 421
 422         u8 xbar_cfg[5];
 423
 424         struct drm_dp_link link;
 425         struct drm_dp_aux *aux;
 426
 427         struct drm_info_list *debugfs_files;
 428
 429         const struct tegra_sor_ops *ops;
 430         enum tegra_io_pad pad;
 431
 432         /* for HDMI 2.0 */
 433         struct tegra_sor_hdmi_settings *settings;
 434         unsigned int num_settings;
 435
 436         struct regulator *avdd_io_supply;
 437         struct regulator *vdd_pll_supply;
 438         struct regulator *hdmi_supply;
 439
 440         struct delayed_work scdc;
 441         bool scdc_enabled;
 442
 443         struct tegra_hda_format format;
 444 };
 445
 446 struct tegra_sor_state {
 447         struct drm_connector_state base;
 448
 449         unsigned int link_speed;
 450         unsigned long pclk;
 451         unsigned int bpc;
 452 };
 453
 454 static inline struct tegra_sor_state *
 455 to_sor_state(struct drm_connector_state *state)
 456 {
 457         return container_of(state, struct tegra_sor_state, base);
 458 }
 459
 460 struct tegra_sor_config {
 461         u32 bits_per_pixel;
 462
 463         u32 active_polarity;
 464         u32 active_count;
 465         u32 tu_size;
 466         u32 active_frac;
 467         u32 watermark;
 468
 469         u32 hblank_symbols;
 470         u32 vblank_symbols;
 471 };
 472
 473 static inline struct tegra_sor *
 474 host1x_client_to_sor(struct host1x_client *client)
 475 {
 476         return container_of(client, struct tegra_sor, client);
 477 }
 478
 479 static inline struct tegra_sor *to_sor(struct tegra_output *output)
 480 {
 481         return container_of(output, struct tegra_sor, output);
 482 }
 483
 484 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 485 {
 486         u32 value = readl(sor->regs + (offset << 2));
 487
 488         trace_sor_readl(sor->dev, offset, value);
 489
 490         return value;
 491 }
 492
 493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 494                                     unsigned int offset)
 495 {
 496         trace_sor_writel(sor->dev, offset, value);
 497         writel(value, sor->regs + (offset << 2));
 498 }
 499
 500 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 501 {
 502         int err;
 503
 504         clk_disable_unprepare(sor->clk);
 505
 506         err = clk_set_parent(sor->clk_out, parent);
 507         if (err < 0)
 508                 return err;
 509
 510         err = clk_prepare_enable(sor->clk);
 511         if (err < 0)
 512                 return err;
 513
 514         return 0;
 515 }
 516
 517 struct tegra_clk_sor_pad {
 518         struct clk_hw hw;
 519         struct tegra_sor *sor;
 520 };
 521
 522 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 523 {
 524         return container_of(hw, struct tegra_clk_sor_pad, hw);
 525 }
 526
 527 static const char * const tegra_clk_sor_pad_parents[2][2] = {
 528         { "pll_d_out0", "pll_dp" },
 529         { "pll_d2_out0", "pll_dp" },
 530 };
 531
 532 /*
 533  * Implementing ->set_parent() here isn't really required because the parent
 534  * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
 535  * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
 536  * Tegra186 and later SoC generations where the BPMP implements this clock
 537  * and doesn't expose the mux via the common clock framework.
 538  */
 539
 540 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 541 {
 542         struct tegra_clk_sor_pad *pad = to_pad(hw);
 543         struct tegra_sor *sor = pad->sor;
 544         u32 value;
 545
 546         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 547         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 548
 549         switch (index) {
 550         case 0:
 551                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 552                 break;
 553
 554         case 1:
 555                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 556                 break;
 557         }
 558
 559         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 560
 561         return 0;
 562 }
 563
 564 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 565 {
 566         struct tegra_clk_sor_pad *pad = to_pad(hw);
 567         struct tegra_sor *sor = pad->sor;
 568         u8 parent = U8_MAX;
 569         u32 value;
 570
 571         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 572
 573         switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 574         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 575         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 576                 parent = 0;
 577                 break;
 578
 579         case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 580         case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 581                 parent = 1;
 582                 break;
 583         }
 584
 585         return parent;
 586 }
 587
 588 static const struct clk_ops tegra_clk_sor_pad_ops = {
 589         .determine_rate = clk_hw_determine_rate_no_reparent,
 590         .set_parent = tegra_clk_sor_pad_set_parent,
 591         .get_parent = tegra_clk_sor_pad_get_parent,
 592 };
 593
 594 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 595                                               const char *name)
 596 {
 597         struct tegra_clk_sor_pad *pad;
 598         struct clk_init_data init;
 599         struct clk *clk;
 600
 601         pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 602         if (!pad)
 603                 return ERR_PTR(-ENOMEM);
 604
 605         pad->sor = sor;
 606
 607         init.name = name;
 608         init.flags = 0;
 609         init.parent_names = tegra_clk_sor_pad_parents[sor->index];
 610         init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
 611         init.ops = &tegra_clk_sor_pad_ops;
 612
 613         pad->hw.init = &init;
 614
 615         clk = devm_clk_register(sor->dev, &pad->hw);
 616
 617         return clk;
 618 }
 619
 620 static void tegra_sor_filter_rates(struct tegra_sor *sor)
 621 {
 622         struct drm_dp_link *link = &sor->link;
 623         unsigned int i;
 624
 625         /* Tegra only supports RBR, HBR and HBR2 */
 626         for (i = 0; i < link->num_rates; i++) {
 627                 switch (link->rates[i]) {
 628                 case 1620000:
 629                 case 2700000:
 630                 case 5400000:
 631                         break;
 632
 633                 default:
 634                         DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 635                                       link->rates[i]);
 636                         link->rates[i] = 0;
 637                         break;
 638                 }
 639         }
 640
 641         drm_dp_link_update_rates(link);
 642 }
 643
 644 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 645 {
 646         unsigned long timeout;
 647         u32 value;
 648
 649         /*
 650          * Clear or set the PD_TXD bit corresponding to each lane, depending
 651          * on whether it is used or not.
 652          */
 653         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 654
 655         if (lanes <= 2)
 656                 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 657                            SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 658         else
 659                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 660                          SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 661
 662         if (lanes <= 1)
 663                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 664         else
 665                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 666
 667         if (lanes == 0)
 668                 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 669         else
 670                 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 671
 672         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 673
 674         /* start lane sequencer */
 675         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 676                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 677         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 678
 679         timeout = jiffies + msecs_to_jiffies(250);
 680
 681         while (time_before(jiffies, timeout)) {
 682                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 683                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 684                         break;
 685
 686                 usleep_range(250, 1000);
 687         }
 688
 689         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 690                 return -ETIMEDOUT;
 691
 692         return 0;
 693 }
 694
 695 static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 696 {
 697         unsigned long timeout;
 698         u32 value;
 699
 700         /* power down all lanes */
 701         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 702         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 703                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 704         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 705
 706         /* start lane sequencer */
 707         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 708                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 709         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 710
 711         timeout = jiffies + msecs_to_jiffies(250);
 712
 713         while (time_before(jiffies, timeout)) {
 714                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 715                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 716                         break;
 717
 718                 usleep_range(25, 100);
 719         }
 720
 721         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 722                 return -ETIMEDOUT;
 723
 724         return 0;
 725 }
 726
 727 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 728 {
 729         u32 value;
 730
 731         /* pre-charge all used lanes */
 732         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 733
 734         if (lanes <= 2)
 735                 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 736                            SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 737         else
 738                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 739                          SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 740
 741         if (lanes <= 1)
 742                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 743         else
 744                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 745
 746         if (lanes == 0)
 747                 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 748         else
 749                 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 750
 751         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 752
 753         usleep_range(15, 100);
 754
 755         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 756         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 757                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 758         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 759 }
 760
 761 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 762 {
 763         u32 mask = 0x08, adj = 0, value;
 764
 765         /* enable pad calibration logic */
 766         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 767         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 768         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 769
 770         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 771         value |= SOR_PLL1_TMDS_TERM;
 772         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 773
 774         while (mask) {
 775                 adj |= mask;
 776
 777                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 778                 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 779                 value |= SOR_PLL1_TMDS_TERMADJ(adj);
 780                 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 781
 782                 usleep_range(100, 200);
 783
 784                 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 785                 if (value & SOR_PLL1_TERM_COMPOUT)
 786                         adj &= ~mask;
 787
 788                 mask >>= 1;
 789         }
 790
 791         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 792         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 793         value |= SOR_PLL1_TMDS_TERMADJ(adj);
 794         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 795
 796         /* disable pad calibration logic */
 797         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 798         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 799         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 800 }
 801
 802 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 803 {
 804         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 805         u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 806         const struct tegra_sor_soc *soc = sor->soc;
 807         u32 pattern = 0, tx_pu = 0, value;
 808         unsigned int i;
 809
 810         for (value = 0, i = 0; i < link->lanes; i++) {
 811                 u8 vs = link->train.request.voltage_swing[i];
 812                 u8 pe = link->train.request.pre_emphasis[i];
 813                 u8 pc = link->train.request.post_cursor[i];
 814                 u8 shift = sor->soc->lane_map[i] << 3;
 815
 816                 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 817                 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 818                 post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 819
 820                 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 821                         tx_pu = sor->soc->tx_pu[pc][vs][pe];
 822
 823                 switch (link->train.pattern) {
 824                 case DP_TRAINING_PATTERN_DISABLE:
 825                         value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 826                                 SOR_DP_TPG_PATTERN_NONE;
 827                         break;
 828
 829                 case DP_TRAINING_PATTERN_1:
 830                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 831                                 SOR_DP_TPG_PATTERN_TRAIN1;
 832                         break;
 833
 834                 case DP_TRAINING_PATTERN_2:
 835                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 836                                 SOR_DP_TPG_PATTERN_TRAIN2;
 837                         break;
 838
 839                 case DP_TRAINING_PATTERN_3:
 840                         value = SOR_DP_TPG_SCRAMBLER_NONE |
 841                                 SOR_DP_TPG_PATTERN_TRAIN3;
 842                         break;
 843
 844                 default:
 845                         return -EINVAL;
 846                 }
 847
 848                 if (link->caps.channel_coding)
 849                         value |= SOR_DP_TPG_CHANNEL_CODING;
 850
 851                 pattern = pattern << 8 | value;
 852         }
 853
 854         tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 855         tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 856
 857         if (link->caps.tps3_supported)
 858                 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 859
 860         tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 861
 862         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 863         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 864         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 865         value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 866         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 867
 868         usleep_range(20, 100);
 869
 870         return 0;
 871 }
 872
 873 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 874 {
 875         struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 876         unsigned int rate, lanes;
 877         u32 value;
 878         int err;
 879
 880         rate = drm_dp_link_rate_to_bw_code(link->rate);
 881         lanes = link->lanes;
 882
 883         /* configure link speed and lane count */
 884         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 885         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 886         value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 887         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 888
 889         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 890         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 891         value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 892
 893         if (link->caps.enhanced_framing)
 894                 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 895
 896         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 897
 898         usleep_range(400, 1000);
 899
 900         /* configure load pulse position adjustment */
 901         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 902         value &= ~SOR_PLL1_LOADADJ_MASK;
 903
 904         switch (rate) {
 905         case DP_LINK_BW_1_62:
 906                 value |= SOR_PLL1_LOADADJ(0x3);
 907                 break;
 908
 909         case DP_LINK_BW_2_7:
 910                 value |= SOR_PLL1_LOADADJ(0x4);
 911                 break;
 912
 913         case DP_LINK_BW_5_4:
 914                 value |= SOR_PLL1_LOADADJ(0x6);
 915                 break;
 916         }
 917
 918         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 919
 920         /* use alternate scrambler reset for eDP */
 921         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 922
 923         if (link->edp == 0)
 924                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 925         else
 926                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
 927
 928         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 929
 930         err = tegra_sor_power_down_lanes(sor);
 931         if (err < 0) {
 932                 dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 933                 return err;
 934         }
 935
 936         /* power up and pre-charge lanes */
 937         err = tegra_sor_power_up_lanes(sor, lanes);
 938         if (err < 0) {
 939                 dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 940                         lanes, (lanes != 1) ? "s" : "", err);
 941                 return err;
 942         }
 943
 944         tegra_sor_dp_precharge(sor, lanes);
 945
 946         return 0;
 947 }
 948
 949 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 950         .apply_training = tegra_sor_dp_link_apply_training,
 951         .configure = tegra_sor_dp_link_configure,
 952 };
 953
 954 static void tegra_sor_super_update(struct tegra_sor *sor)
 955 {
 956         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 957         tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 958         tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 959 }
 960
 961 static void tegra_sor_update(struct tegra_sor *sor)
 962 {
 963         tegra_sor_writel(sor, 0, SOR_STATE0);
 964         tegra_sor_writel(sor, 1, SOR_STATE0);
 965         tegra_sor_writel(sor, 0, SOR_STATE0);
 966 }
 967
 968 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 969 {
 970         u32 value;
 971
 972         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 973         value &= ~SOR_PWM_DIV_MASK;
 974         value |= 0x400; /* period */
 975         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 976
 977         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 978         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 979         value |= 0x400; /* duty cycle */
 980         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 981         value |= SOR_PWM_CTL_TRIGGER;
 982         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 983
 984         timeout = jiffies + msecs_to_jiffies(timeout);
 985
 986         while (time_before(jiffies, timeout)) {
 987                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 988                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 989                         return 0;
 990
 991                 usleep_range(25, 100);
 992         }
 993
 994         return -ETIMEDOUT;
 995 }
 996
 997 static int tegra_sor_attach(struct tegra_sor *sor)
 998 {
 999         unsigned long value, timeout;
1000
1001         /* wake up in normal mode */
1002         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1003         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1004         value |= SOR_SUPER_STATE_MODE_NORMAL;
1005         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1006         tegra_sor_super_update(sor);
1007
1008         /* attach */
1009         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1010         value |= SOR_SUPER_STATE_ATTACHED;
1011         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1012         tegra_sor_super_update(sor);
1013
1014         timeout = jiffies + msecs_to_jiffies(250);
1015
1016         while (time_before(jiffies, timeout)) {
1017                 value = tegra_sor_readl(sor, SOR_TEST);
1018                 if ((value & SOR_TEST_ATTACHED) != 0)
1019                         return 0;
1020
1021                 usleep_range(25, 100);
1022         }
1023
1024         return -ETIMEDOUT;
1025 }
1026
1027 static int tegra_sor_wakeup(struct tegra_sor *sor)
1028 {
1029         unsigned long value, timeout;
1030
1031         timeout = jiffies + msecs_to_jiffies(250);
1032
1033         /* wait for head to wake up */
1034         while (time_before(jiffies, timeout)) {
1035                 value = tegra_sor_readl(sor, SOR_TEST);
1036                 value &= SOR_TEST_HEAD_MODE_MASK;
1037
1038                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1039                         return 0;
1040
1041                 usleep_range(25, 100);
1042         }
1043
1044         return -ETIMEDOUT;
1045 }
1046
1047 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1048 {
1049         u32 value;
1050
1051         value = tegra_sor_readl(sor, SOR_PWR);
1052         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1053         tegra_sor_writel(sor, value, SOR_PWR);
1054
1055         timeout = jiffies + msecs_to_jiffies(timeout);
1056
1057         while (time_before(jiffies, timeout)) {
1058                 value = tegra_sor_readl(sor, SOR_PWR);
1059                 if ((value & SOR_PWR_TRIGGER) == 0)
1060                         return 0;
1061
1062                 usleep_range(25, 100);
1063         }
1064
1065         return -ETIMEDOUT;
1066 }
1067
1068 struct tegra_sor_params {
1069         /* number of link clocks per line */
1070         unsigned int num_clocks;
1071         /* ratio between input and output */
1072         u64 ratio;
1073         /* precision factor */
1074         u64 precision;
1075
1076         unsigned int active_polarity;
1077         unsigned int active_count;
1078         unsigned int active_frac;
1079         unsigned int tu_size;
1080         unsigned int error;
1081 };
1082
1083 static int tegra_sor_compute_params(struct tegra_sor *sor,
1084                                     struct tegra_sor_params *params,
1085                                     unsigned int tu_size)
1086 {
1087         u64 active_sym, active_count, frac, approx;
1088         u32 active_polarity, active_frac = 0;
1089         const u64 f = params->precision;
1090         s64 error;
1091
1092         active_sym = params->ratio * tu_size;
1093         active_count = div_u64(active_sym, f) * f;
1094         frac = active_sym - active_count;
1095
1096         /* fraction < 0.5 */
1097         if (frac >= (f / 2)) {
1098                 active_polarity = 1;
1099                 frac = f - frac;
1100         } else {
1101                 active_polarity = 0;
1102         }
1103
1104         if (frac != 0) {
1105                 frac = div_u64(f * f,  frac); /* 1/fraction */
1106                 if (frac <= (15 * f)) {
1107                         active_frac = div_u64(frac, f);
1108
1109                         /* round up */
1110                         if (active_polarity)
1111                                 active_frac++;
1112                 } else {
1113                         active_frac = active_polarity ? 1 : 15;
1114                 }
1115         }
1116
1117         if (active_frac == 1)
1118                 active_polarity = 0;
1119
1120         if (active_polarity == 1) {
1121                 if (active_frac) {
1122                         approx = active_count + (active_frac * (f - 1)) * f;
1123                         approx = div_u64(approx, active_frac * f);
1124                 } else {
1125                         approx = active_count + f;
1126                 }
1127         } else {
1128                 if (active_frac)
1129                         approx = active_count + div_u64(f, active_frac);
1130                 else
1131                         approx = active_count;
1132         }
1133
1134         error = div_s64(active_sym - approx, tu_size);
1135         error *= params->num_clocks;
1136
1137         if (error <= 0 && abs(error) < params->error) {
1138                 params->active_count = div_u64(active_count, f);
1139                 params->active_polarity = active_polarity;
1140                 params->active_frac = active_frac;
1141                 params->error = abs(error);
1142                 params->tu_size = tu_size;
1143
1144                 if (error == 0)
1145                         return true;
1146         }
1147
1148         return false;
1149 }
1150
1151 static int tegra_sor_compute_config(struct tegra_sor *sor,
1152                                     const struct drm_display_mode *mode,
1153                                     struct tegra_sor_config *config,
1154                                     struct drm_dp_link *link)
1155 {
1156         const u64 f = 100000, link_rate = link->rate * 1000;
1157         const u64 pclk = (u64)mode->clock * 1000;
1158         u64 input, output, watermark, num;
1159         struct tegra_sor_params params;
1160         u32 num_syms_per_line;
1161         unsigned int i;
1162
1163         if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1164                 return -EINVAL;
1165
1166         input = pclk * config->bits_per_pixel;
1167         output = link_rate * 8 * link->lanes;
1168
1169         if (input >= output)
1170                 return -ERANGE;
1171
1172         memset(&params, 0, sizeof(params));
1173         params.ratio = div64_u64(input * f, output);
1174         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1175         params.precision = f;
1176         params.error = 64 * f;
1177         params.tu_size = 64;
1178
1179         for (i = params.tu_size; i >= 32; i--)
1180                 if (tegra_sor_compute_params(sor, &params, i))
1181                         break;
1182
1183         if (params.active_frac == 0) {
1184                 config->active_polarity = 0;
1185                 config->active_count = params.active_count;
1186
1187                 if (!params.active_polarity)
1188                         config->active_count--;
1189
1190                 config->tu_size = params.tu_size;
1191                 config->active_frac = 1;
1192         } else {
1193                 config->active_polarity = params.active_polarity;
1194                 config->active_count = params.active_count;
1195                 config->active_frac = params.active_frac;
1196                 config->tu_size = params.tu_size;
1197         }
1198
1199         dev_dbg(sor->dev,
1200                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
1201                 config->active_polarity, config->active_count,
1202                 config->tu_size, config->active_frac);
1203
1204         watermark = params.ratio * config->tu_size * (f - params.ratio);
1205         watermark = div_u64(watermark, f);
1206
1207         watermark = div_u64(watermark + params.error, f);
1208         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1209         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1210                             (link->lanes * 8);
1211
1212         if (config->watermark > 30) {
1213                 config->watermark = 30;
1214                 dev_err(sor->dev,
1215                         "unable to compute TU size, forcing watermark to %u\n",
1216                         config->watermark);
1217         } else if (config->watermark > num_syms_per_line) {
1218                 config->watermark = num_syms_per_line;
1219                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
1220                         config->watermark);
1221         }
1222
1223         /* compute the number of symbols per horizontal blanking interval */
1224         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1225         config->hblank_symbols = div_u64(num, pclk);
1226
1227         if (link->caps.enhanced_framing)
1228                 config->hblank_symbols -= 3;
1229
1230         config->hblank_symbols -= 12 / link->lanes;
1231
1232         /* compute the number of symbols per vertical blanking interval */
1233         num = (mode->hdisplay - 25) * link_rate;
1234         config->vblank_symbols = div_u64(num, pclk);
1235         config->vblank_symbols -= 36 / link->lanes + 4;
1236
1237         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1238                 config->vblank_symbols);
1239
1240         return 0;
1241 }
1242
1243 static void tegra_sor_apply_config(struct tegra_sor *sor,
1244                                    const struct tegra_sor_config *config)
1245 {
1246         u32 value;
1247
1248         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1249         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1250         value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1251         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1252
1253         value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1254         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1255         value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1256
1257         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1258         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1259
1260         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1261         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1262
1263         if (config->active_polarity)
1264                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1265         else
1266                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1267
1268         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1269         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1270         tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1271
1272         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1273         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1274         value |= config->hblank_symbols & 0xffff;
1275         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1276
1277         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1278         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1279         value |= config->vblank_symbols & 0xffff;
1280         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1281 }
1282
1283 static void tegra_sor_mode_set(struct tegra_sor *sor,
1284                                const struct drm_display_mode *mode,
1285                                struct tegra_sor_state *state)
1286 {
1287         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1288         unsigned int vbe, vse, hbe, hse, vbs, hbs;
1289         u32 value;
1290
1291         value = tegra_sor_readl(sor, SOR_STATE1);
1292         value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1293         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1294         value &= ~SOR_STATE_ASY_OWNER_MASK;
1295
1296         value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1297                  SOR_STATE_ASY_OWNER(dc->pipe + 1);
1298
1299         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1300                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1301
1302         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1303                 value |= SOR_STATE_ASY_HSYNCPOL;
1304
1305         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1306                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1307
1308         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1309                 value |= SOR_STATE_ASY_VSYNCPOL;
1310
1311         switch (state->bpc) {
1312         case 16:
1313                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1314                 break;
1315
1316         case 12:
1317                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1318                 break;
1319
1320         case 10:
1321                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1322                 break;
1323
1324         case 8:
1325                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1326                 break;
1327
1328         case 6:
1329                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1330                 break;
1331
1332         default:
1333                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1334                 break;
1335         }
1336
1337         tegra_sor_writel(sor, value, SOR_STATE1);
1338
1339         /*
1340          * TODO: The video timing programming below doesn't seem to match the
1341          * register definitions.
1342          */
1343
1344         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1345         tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1346
1347         /* sync end = sync width - 1 */
1348         vse = mode->vsync_end - mode->vsync_start - 1;
1349         hse = mode->hsync_end - mode->hsync_start - 1;
1350
1351         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1352         tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1353
1354         /* blank end = sync end + back porch */
1355         vbe = vse + (mode->vtotal - mode->vsync_end);
1356         hbe = hse + (mode->htotal - mode->hsync_end);
1357
1358         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1359         tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1360
1361         /* blank start = blank end + active */
1362         vbs = vbe + mode->vdisplay;
1363         hbs = hbe + mode->hdisplay;
1364
1365         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1366         tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1367
1368         /* XXX interlacing support */
1369         tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1370 }
1371
1372 static int tegra_sor_detach(struct tegra_sor *sor)
1373 {
1374         unsigned long value, timeout;
1375
1376         /* switch to safe mode */
1377         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1378         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1379         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1380         tegra_sor_super_update(sor);
1381
1382         timeout = jiffies + msecs_to_jiffies(250);
1383
1384         while (time_before(jiffies, timeout)) {
1385                 value = tegra_sor_readl(sor, SOR_PWR);
1386                 if (value & SOR_PWR_MODE_SAFE)
1387                         break;
1388         }
1389
1390         if ((value & SOR_PWR_MODE_SAFE) == 0)
1391                 return -ETIMEDOUT;
1392
1393         /* go to sleep */
1394         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1395         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1396         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1397         tegra_sor_super_update(sor);
1398
1399         /* detach */
1400         value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1401         value &= ~SOR_SUPER_STATE_ATTACHED;
1402         tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1403         tegra_sor_super_update(sor);
1404
1405         timeout = jiffies + msecs_to_jiffies(250);
1406
1407         while (time_before(jiffies, timeout)) {
1408                 value = tegra_sor_readl(sor, SOR_TEST);
1409                 if ((value & SOR_TEST_ATTACHED) == 0)
1410                         break;
1411
1412                 usleep_range(25, 100);
1413         }
1414
1415         if ((value & SOR_TEST_ATTACHED) != 0)
1416                 return -ETIMEDOUT;
1417
1418         return 0;
1419 }
1420
1421 static int tegra_sor_power_down(struct tegra_sor *sor)
1422 {
1423         unsigned long value, timeout;
1424         int err;
1425
1426         value = tegra_sor_readl(sor, SOR_PWR);
1427         value &= ~SOR_PWR_NORMAL_STATE_PU;
1428         value |= SOR_PWR_TRIGGER;
1429         tegra_sor_writel(sor, value, SOR_PWR);
1430
1431         timeout = jiffies + msecs_to_jiffies(250);
1432
1433         while (time_before(jiffies, timeout)) {
1434                 value = tegra_sor_readl(sor, SOR_PWR);
1435                 if ((value & SOR_PWR_TRIGGER) == 0)
1436                         return 0;
1437
1438                 usleep_range(25, 100);
1439         }
1440
1441         if ((value & SOR_PWR_TRIGGER) != 0)
1442                 return -ETIMEDOUT;
1443
1444         /* switch to safe parent clock */
1445         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1446         if (err < 0) {
1447                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1448                 return err;
1449         }
1450
1451         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1452         value |= SOR_PLL2_PORT_POWERDOWN;
1453         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1454
1455         usleep_range(20, 100);
1456
1457         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1458         value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1459         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1460
1461         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1462         value |= SOR_PLL2_SEQ_PLLCAPPD;
1463         value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1464         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1465
1466         usleep_range(20, 100);
1467
1468         return 0;
1469 }
1470
1471 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1472 {
1473         u32 value;
1474
1475         timeout = jiffies + msecs_to_jiffies(timeout);
1476
1477         while (time_before(jiffies, timeout)) {
1478                 value = tegra_sor_readl(sor, SOR_CRCA);
1479                 if (value & SOR_CRCA_VALID)
1480                         return 0;
1481
1482                 usleep_range(100, 200);
1483         }
1484
1485         return -ETIMEDOUT;
1486 }
1487
1488 static int tegra_sor_show_crc(struct seq_file *s, void *data)
1489 {
1490         struct drm_info_node *node = s->private;
1491         struct tegra_sor *sor = node->info_ent->data;
1492         struct drm_crtc *crtc = sor->output.encoder.crtc;
1493         struct drm_device *drm = node->minor->dev;
1494         int err = 0;
1495         u32 value;
1496
1497         drm_modeset_lock_all(drm);
1498
1499         if (!crtc || !crtc->state->active) {
1500                 err = -EBUSY;
1501                 goto unlock;
1502         }
1503
1504         value = tegra_sor_readl(sor, SOR_STATE1);
1505         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1506         tegra_sor_writel(sor, value, SOR_STATE1);
1507
1508         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1509         value |= SOR_CRC_CNTRL_ENABLE;
1510         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1511
1512         value = tegra_sor_readl(sor, SOR_TEST);
1513         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1514         tegra_sor_writel(sor, value, SOR_TEST);
1515
1516         err = tegra_sor_crc_wait(sor, 100);
1517         if (err < 0)
1518                 goto unlock;
1519
1520         tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1521         value = tegra_sor_readl(sor, SOR_CRCB);
1522
1523         seq_printf(s, "%08x\n", value);
1524
1525 unlock:
1526         drm_modeset_unlock_all(drm);
1527         return err;
1528 }
1529
1530 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1531
1532 static const struct debugfs_reg32 tegra_sor_regs[] = {
1533         DEBUGFS_REG32(SOR_CTXSW),
1534         DEBUGFS_REG32(SOR_SUPER_STATE0),
1535         DEBUGFS_REG32(SOR_SUPER_STATE1),
1536         DEBUGFS_REG32(SOR_STATE0),
1537         DEBUGFS_REG32(SOR_STATE1),
1538         DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1539         DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1540         DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1541         DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1542         DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1543         DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1544         DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1545         DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1546         DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1547         DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1548         DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1549         DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1550         DEBUGFS_REG32(SOR_CRC_CNTRL),
1551         DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1552         DEBUGFS_REG32(SOR_CLK_CNTRL),
1553         DEBUGFS_REG32(SOR_CAP),
1554         DEBUGFS_REG32(SOR_PWR),
1555         DEBUGFS_REG32(SOR_TEST),
1556         DEBUGFS_REG32(SOR_PLL0),
1557         DEBUGFS_REG32(SOR_PLL1),
1558         DEBUGFS_REG32(SOR_PLL2),
1559         DEBUGFS_REG32(SOR_PLL3),
1560         DEBUGFS_REG32(SOR_CSTM),
1561         DEBUGFS_REG32(SOR_LVDS),
1562         DEBUGFS_REG32(SOR_CRCA),
1563         DEBUGFS_REG32(SOR_CRCB),
1564         DEBUGFS_REG32(SOR_BLANK),
1565         DEBUGFS_REG32(SOR_SEQ_CTL),
1566         DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1567         DEBUGFS_REG32(SOR_SEQ_INST(0)),
1568         DEBUGFS_REG32(SOR_SEQ_INST(1)),
1569         DEBUGFS_REG32(SOR_SEQ_INST(2)),
1570         DEBUGFS_REG32(SOR_SEQ_INST(3)),
1571         DEBUGFS_REG32(SOR_SEQ_INST(4)),
1572         DEBUGFS_REG32(SOR_SEQ_INST(5)),
1573         DEBUGFS_REG32(SOR_SEQ_INST(6)),
1574         DEBUGFS_REG32(SOR_SEQ_INST(7)),
1575         DEBUGFS_REG32(SOR_SEQ_INST(8)),
1576         DEBUGFS_REG32(SOR_SEQ_INST(9)),
1577         DEBUGFS_REG32(SOR_SEQ_INST(10)),
1578         DEBUGFS_REG32(SOR_SEQ_INST(11)),
1579         DEBUGFS_REG32(SOR_SEQ_INST(12)),
1580         DEBUGFS_REG32(SOR_SEQ_INST(13)),
1581         DEBUGFS_REG32(SOR_SEQ_INST(14)),
1582         DEBUGFS_REG32(SOR_SEQ_INST(15)),
1583         DEBUGFS_REG32(SOR_PWM_DIV),
1584         DEBUGFS_REG32(SOR_PWM_CTL),
1585         DEBUGFS_REG32(SOR_VCRC_A0),
1586         DEBUGFS_REG32(SOR_VCRC_A1),
1587         DEBUGFS_REG32(SOR_VCRC_B0),
1588         DEBUGFS_REG32(SOR_VCRC_B1),
1589         DEBUGFS_REG32(SOR_CCRC_A0),
1590         DEBUGFS_REG32(SOR_CCRC_A1),
1591         DEBUGFS_REG32(SOR_CCRC_B0),
1592         DEBUGFS_REG32(SOR_CCRC_B1),
1593         DEBUGFS_REG32(SOR_EDATA_A0),
1594         DEBUGFS_REG32(SOR_EDATA_A1),
1595         DEBUGFS_REG32(SOR_EDATA_B0),
1596         DEBUGFS_REG32(SOR_EDATA_B1),
1597         DEBUGFS_REG32(SOR_COUNT_A0),
1598         DEBUGFS_REG32(SOR_COUNT_A1),
1599         DEBUGFS_REG32(SOR_COUNT_B0),
1600         DEBUGFS_REG32(SOR_COUNT_B1),
1601         DEBUGFS_REG32(SOR_DEBUG_A0),
1602         DEBUGFS_REG32(SOR_DEBUG_A1),
1603         DEBUGFS_REG32(SOR_DEBUG_B0),
1604         DEBUGFS_REG32(SOR_DEBUG_B1),
1605         DEBUGFS_REG32(SOR_TRIG),
1606         DEBUGFS_REG32(SOR_MSCHECK),
1607         DEBUGFS_REG32(SOR_XBAR_CTRL),
1608         DEBUGFS_REG32(SOR_XBAR_POL),
1609         DEBUGFS_REG32(SOR_DP_LINKCTL0),
1610         DEBUGFS_REG32(SOR_DP_LINKCTL1),
1611         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1612         DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1613         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1614         DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1615         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1616         DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1617         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1618         DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1619         DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1620         DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1621         DEBUGFS_REG32(SOR_DP_CONFIG0),
1622         DEBUGFS_REG32(SOR_DP_CONFIG1),
1623         DEBUGFS_REG32(SOR_DP_MN0),
1624         DEBUGFS_REG32(SOR_DP_MN1),
1625         DEBUGFS_REG32(SOR_DP_PADCTL0),
1626         DEBUGFS_REG32(SOR_DP_PADCTL1),
1627         DEBUGFS_REG32(SOR_DP_PADCTL2),
1628         DEBUGFS_REG32(SOR_DP_DEBUG0),
1629         DEBUGFS_REG32(SOR_DP_DEBUG1),
1630         DEBUGFS_REG32(SOR_DP_SPARE0),
1631         DEBUGFS_REG32(SOR_DP_SPARE1),
1632         DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1633         DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1634         DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1635         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1636         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1637         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1638         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1639         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1640         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1641         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1642         DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1643         DEBUGFS_REG32(SOR_DP_TPG),
1644         DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1645         DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1646         DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1647         DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1648 };
1649
1650 static int tegra_sor_show_regs(struct seq_file *s, void *data)
1651 {
1652         struct drm_info_node *node = s->private;
1653         struct tegra_sor *sor = node->info_ent->data;
1654         struct drm_crtc *crtc = sor->output.encoder.crtc;
1655         struct drm_device *drm = node->minor->dev;
1656         unsigned int i;
1657         int err = 0;
1658
1659         drm_modeset_lock_all(drm);
1660
1661         if (!crtc || !crtc->state->active) {
1662                 err = -EBUSY;
1663                 goto unlock;
1664         }
1665
1666         for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1667                 unsigned int offset = tegra_sor_regs[i].offset;
1668
1669                 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1670                            offset, tegra_sor_readl(sor, offset));
1671         }
1672
1673 unlock:
1674         drm_modeset_unlock_all(drm);
1675         return err;
1676 }
1677
1678 static const struct drm_info_list debugfs_files[] = {
1679         { "crc", tegra_sor_show_crc, 0, NULL },
1680         { "regs", tegra_sor_show_regs, 0, NULL },
1681 };
1682
1683 static int tegra_sor_late_register(struct drm_connector *connector)
1684 {
1685         struct tegra_output *output = connector_to_output(connector);
1686         unsigned int i, count = ARRAY_SIZE(debugfs_files);
1687         struct drm_minor *minor = connector->dev->primary;
1688         struct dentry *root = connector->debugfs_entry;
1689         struct tegra_sor *sor = to_sor(output);
1690
1691         sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1692                                      GFP_KERNEL);
1693         if (!sor->debugfs_files)
1694                 return -ENOMEM;
1695
1696         for (i = 0; i < count; i++)
1697                 sor->debugfs_files[i].data = sor;
1698
1699         drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
1700
1701         return 0;
1702 }
1703
1704 static void tegra_sor_early_unregister(struct drm_connector *connector)
1705 {
1706         struct tegra_output *output = connector_to_output(connector);
1707         unsigned int count = ARRAY_SIZE(debugfs_files);
1708         struct tegra_sor *sor = to_sor(output);
1709
1710         drm_debugfs_remove_files(sor->debugfs_files, count,
1711                                  connector->debugfs_entry,
1712                                  connector->dev->primary);
1713         kfree(sor->debugfs_files);
1714         sor->debugfs_files = NULL;
1715 }
1716
1717 static void tegra_sor_connector_reset(struct drm_connector *connector)
1718 {
1719         struct tegra_sor_state *state;
1720
1721         state = kzalloc(sizeof(*state), GFP_KERNEL);
1722         if (!state)
1723                 return;
1724
1725         if (connector->state) {
1726                 __drm_atomic_helper_connector_destroy_state(connector->state);
1727                 kfree(connector->state);
1728         }
1729
1730         __drm_atomic_helper_connector_reset(connector, &state->base);
1731 }
1732
1733 static enum drm_connector_status
1734 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1735 {
1736         struct tegra_output *output = connector_to_output(connector);
1737         struct tegra_sor *sor = to_sor(output);
1738
1739         if (sor->aux)
1740                 return drm_dp_aux_detect(sor->aux);
1741
1742         return tegra_output_connector_detect(connector, force);
1743 }
1744
1745 static struct drm_connector_state *
1746 tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1747 {
1748         struct tegra_sor_state *state = to_sor_state(connector->state);
1749         struct tegra_sor_state *copy;
1750
1751         copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1752         if (!copy)
1753                 return NULL;
1754
1755         __drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1756
1757         return &copy->base;
1758 }
1759
1760 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1761         .reset = tegra_sor_connector_reset,
1762         .detect = tegra_sor_connector_detect,
1763         .fill_modes = drm_helper_probe_single_connector_modes,
1764         .destroy = tegra_output_connector_destroy,
1765         .atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1766         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1767         .late_register = tegra_sor_late_register,
1768         .early_unregister = tegra_sor_early_unregister,
1769 };
1770
1771 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1772 {
1773         struct tegra_output *output = connector_to_output(connector);
1774         struct tegra_sor *sor = to_sor(output);
1775         int err;
1776
1777         if (sor->aux)
1778                 drm_dp_aux_enable(sor->aux);
1779
1780         err = tegra_output_connector_get_modes(connector);
1781
1782         if (sor->aux)
1783                 drm_dp_aux_disable(sor->aux);
1784
1785         return err;
1786 }
1787
1788 static enum drm_mode_status
1789 tegra_sor_connector_mode_valid(struct drm_connector *connector,
1790                                struct drm_display_mode *mode)
1791 {
1792         return MODE_OK;
1793 }
1794
1795 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1796         .get_modes = tegra_sor_connector_get_modes,
1797         .mode_valid = tegra_sor_connector_mode_valid,
1798 };
1799
1800 static int
1801 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1802                                struct drm_crtc_state *crtc_state,
1803                                struct drm_connector_state *conn_state)
1804 {
1805         struct tegra_output *output = encoder_to_output(encoder);
1806         struct tegra_sor_state *state = to_sor_state(conn_state);
1807         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1808         unsigned long pclk = crtc_state->mode.clock * 1000;
1809         struct tegra_sor *sor = to_sor(output);
1810         struct drm_display_info *info;
1811         int err;
1812
1813         info = &output->connector.display_info;
1814
1815         /*
1816          * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1817          * the pixel clock must be corrected accordingly.
1818          */
1819         if (pclk >= 340000000) {
1820                 state->link_speed = 20;
1821                 state->pclk = pclk / 2;
1822         } else {
1823                 state->link_speed = 10;
1824                 state->pclk = pclk;
1825         }
1826
1827         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1828                                          pclk, 0);
1829         if (err < 0) {
1830                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1831                 return err;
1832         }
1833
1834         switch (info->bpc) {
1835         case 8:
1836         case 6:
1837                 state->bpc = info->bpc;
1838                 break;
1839
1840         default:
1841                 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1842                 state->bpc = 8;
1843                 break;
1844         }
1845
1846         return 0;
1847 }
1848
1849 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1850 {
1851         u32 value = 0;
1852         size_t i;
1853
1854         for (i = size; i > 0; i--)
1855                 value = (value << 8) | ptr[i - 1];
1856
1857         return value;
1858 }
1859
1860 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1861                                           const void *data, size_t size)
1862 {
1863         const u8 *ptr = data;
1864         unsigned long offset;
1865         size_t i, j;
1866         u32 value;
1867
1868         switch (ptr[0]) {
1869         case HDMI_INFOFRAME_TYPE_AVI:
1870                 offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1871                 break;
1872
1873         case HDMI_INFOFRAME_TYPE_AUDIO:
1874                 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1875                 break;
1876
1877         case HDMI_INFOFRAME_TYPE_VENDOR:
1878                 offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1879                 break;
1880
1881         default:
1882                 dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1883                         ptr[0]);
1884                 return;
1885         }
1886
1887         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1888                 INFOFRAME_HEADER_VERSION(ptr[1]) |
1889                 INFOFRAME_HEADER_LEN(ptr[2]);
1890         tegra_sor_writel(sor, value, offset);
1891         offset++;
1892
1893         /*
1894          * Each subpack contains 7 bytes, divided into:
1895          * - subpack_low: bytes 0 - 3
1896          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1897          */
1898         for (i = 3, j = 0; i < size; i += 7, j += 8) {
1899                 size_t rem = size - i, num = min_t(size_t, rem, 4);
1900
1901                 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1902                 tegra_sor_writel(sor, value, offset++);
1903
1904                 num = min_t(size_t, rem - num, 3);
1905
1906                 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1907                 tegra_sor_writel(sor, value, offset++);
1908         }
1909 }
1910
1911 static int
1912 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1913                                    const struct drm_display_mode *mode)
1914 {
1915         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1916         struct hdmi_avi_infoframe frame;
1917         u32 value;
1918         int err;
1919
1920         /* disable AVI infoframe */
1921         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1922         value &= ~INFOFRAME_CTRL_SINGLE;
1923         value &= ~INFOFRAME_CTRL_OTHER;
1924         value &= ~INFOFRAME_CTRL_ENABLE;
1925         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1926
1927         err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1928                                                        &sor->output.connector, mode);
1929         if (err < 0) {
1930                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1931                 return err;
1932         }
1933
1934         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1935         if (err < 0) {
1936                 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1937                 return err;
1938         }
1939
1940         tegra_sor_hdmi_write_infopack(sor, buffer, err);
1941
1942         /* enable AVI infoframe */
1943         value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1944         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1945         value |= INFOFRAME_CTRL_ENABLE;
1946         tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1947
1948         return 0;
1949 }
1950
1951 static void tegra_sor_write_eld(struct tegra_sor *sor)
1952 {
1953         size_t length = drm_eld_size(sor->output.connector.eld), i;
1954
1955         for (i = 0; i < length; i++)
1956                 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1957                                  SOR_AUDIO_HDA_ELD_BUFWR);
1958
1959         /*
1960          * The HDA codec will always report an ELD buffer size of 96 bytes and
1961          * the HDA codec driver will check that each byte read from the buffer
1962          * is valid. Therefore every byte must be written, even if no 96 bytes
1963          * were parsed from EDID.
1964          */
1965         for (i = length; i < 96; i++)
1966                 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1967 }
1968
1969 static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1970 {
1971         u32 value;
1972
1973         /*
1974          * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1975          * is used for interoperability between the HDA codec driver and the
1976          * HDMI/DP driver.
1977          */
1978         value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1979         tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1980         tegra_sor_writel(sor, value, SOR_INT_MASK);
1981
1982         tegra_sor_write_eld(sor);
1983
1984         value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1985         tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1986 }
1987
1988 static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1989 {
1990         tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1991         tegra_sor_writel(sor, 0, SOR_INT_MASK);
1992         tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1993 }
1994
1995 static void tegra_sor_audio_enable(struct tegra_sor *sor)
1996 {
1997         u32 value;
1998
1999         value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2000
2001         /* select HDA audio input */
2002         value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2003         value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2004
2005         /* inject null samples */
2006         if (sor->format.channels != 2)
2007                 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2008         else
2009                 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2010
2011         value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2012
2013         tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2014
2015         /* enable advertising HBR capability */
2016         tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2017 }
2018
2019 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2020 {
2021         u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2022         struct hdmi_audio_infoframe frame;
2023         u32 value;
2024         int err;
2025
2026         err = hdmi_audio_infoframe_init(&frame);
2027         if (err < 0) {
2028                 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2029                 return err;
2030         }
2031
2032         frame.channels = sor->format.channels;
2033
2034         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2035         if (err < 0) {
2036                 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2037                 return err;
2038         }
2039
2040         tegra_sor_hdmi_write_infopack(sor, buffer, err);
2041
2042         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2043         value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2044         value |= INFOFRAME_CTRL_ENABLE;
2045         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2046
2047         return 0;
2048 }
2049
2050 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2051 {
2052         u32 value;
2053
2054         tegra_sor_audio_enable(sor);
2055
2056         tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2057
2058         value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2059                 SOR_HDMI_SPARE_CTS_RESET(1) |
2060                 SOR_HDMI_SPARE_HW_CTS_ENABLE;
2061         tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2062
2063         /* enable HW CTS */
2064         value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2065         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2066
2067         /* allow packet to be sent */
2068         value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2069         tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2070
2071         /* reset N counter and enable lookup */
2072         value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2073         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2074
2075         value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2076         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2077         tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2078
2079         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2080         tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2081
2082         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2083         tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2084
2085         tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2086         tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2087
2088         value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2089         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2090         tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2091
2092         value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2093         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2094         tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2095
2096         value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2097         tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2098         tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2099
2100         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2101         value &= ~SOR_HDMI_AUDIO_N_RESET;
2102         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2103
2104         tegra_sor_hdmi_enable_audio_infoframe(sor);
2105 }
2106
2107 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2108 {
2109         u32 value;
2110
2111         value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2112         value &= ~INFOFRAME_CTRL_ENABLE;
2113         tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2114 }
2115
2116 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2117 {
2118         tegra_sor_hdmi_disable_audio_infoframe(sor);
2119 }
2120
2121 static struct tegra_sor_hdmi_settings *
2122 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2123 {
2124         unsigned int i;
2125
2126         for (i = 0; i < sor->num_settings; i++)
2127                 if (frequency <= sor->settings[i].frequency)
2128                         return &sor->settings[i];
2129
2130         return NULL;
2131 }
2132
2133 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2134 {
2135         u32 value;
2136
2137         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2138         value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2139         value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2140         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2141 }
2142
2143 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2144 {
2145         drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false);
2146         drm_scdc_set_scrambling(&sor->output.connector, false);
2147
2148         tegra_sor_hdmi_disable_scrambling(sor);
2149 }
2150
2151 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2152 {
2153         if (sor->scdc_enabled) {
2154                 cancel_delayed_work_sync(&sor->scdc);
2155                 tegra_sor_hdmi_scdc_disable(sor);
2156         }
2157 }
2158
2159 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2160 {
2161         u32 value;
2162
2163         value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2164         value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2165         value |= SOR_HDMI2_CTRL_SCRAMBLE;
2166         tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2167 }
2168
2169 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2170 {
2171         drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true);
2172         drm_scdc_set_scrambling(&sor->output.connector, true);
2173
2174         tegra_sor_hdmi_enable_scrambling(sor);
2175 }
2176
2177 static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2178 {
2179         struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2180
2181         if (!drm_scdc_get_scrambling_status(&sor->output.connector)) {
2182                 DRM_DEBUG_KMS("SCDC not scrambled\n");
2183                 tegra_sor_hdmi_scdc_enable(sor);
2184         }
2185
2186         schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2187 }
2188
2189 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2190 {
2191         struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2192         struct drm_display_mode *mode;
2193
2194         mode = &sor->output.encoder.crtc->state->adjusted_mode;
2195
2196         if (mode->clock >= 340000 && scdc->supported) {
2197                 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2198                 tegra_sor_hdmi_scdc_enable(sor);
2199                 sor->scdc_enabled = true;
2200         }
2201 }
2202
2203 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2204 {
2205         struct tegra_output *output = encoder_to_output(encoder);
2206         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2207         struct tegra_sor *sor = to_sor(output);
2208         u32 value;
2209         int err;
2210
2211         tegra_sor_audio_unprepare(sor);
2212         tegra_sor_hdmi_scdc_stop(sor);
2213
2214         err = tegra_sor_detach(sor);
2215         if (err < 0)
2216                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2217
2218         tegra_sor_writel(sor, 0, SOR_STATE1);
2219         tegra_sor_update(sor);
2220
2221         /* disable display to SOR clock */
2222         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2223
2224         if (!sor->soc->has_nvdisplay)
2225                 value &= ~SOR1_TIMING_CYA;
2226
2227         value &= ~SOR_ENABLE(sor->index);
2228
2229         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2230
2231         tegra_dc_commit(dc);
2232
2233         err = tegra_sor_power_down(sor);
2234         if (err < 0)
2235                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2236
2237         err = tegra_io_pad_power_disable(sor->pad);
2238         if (err < 0)
2239                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2240
2241         host1x_client_suspend(&sor->client);
2242 }
2243
2244 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2245 {
2246         struct tegra_output *output = encoder_to_output(encoder);
2247         unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2248         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2249         struct tegra_sor_hdmi_settings *settings;
2250         struct tegra_sor *sor = to_sor(output);
2251         struct tegra_sor_state *state;
2252         struct drm_display_mode *mode;
2253         unsigned long rate, pclk;
2254         unsigned int div, i;
2255         u32 value;
2256         int err;
2257
2258         state = to_sor_state(output->connector.state);
2259         mode = &encoder->crtc->state->adjusted_mode;
2260         pclk = mode->clock * 1000;
2261
2262         err = host1x_client_resume(&sor->client);
2263         if (err < 0) {
2264                 dev_err(sor->dev, "failed to resume: %d\n", err);
2265                 return;
2266         }
2267
2268         /* switch to safe parent clock */
2269         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2270         if (err < 0) {
2271                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2272                 return;
2273         }
2274
2275         div = clk_get_rate(sor->clk) / 1000000 * 4;
2276
2277         err = tegra_io_pad_power_enable(sor->pad);
2278         if (err < 0)
2279                 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2280
2281         usleep_range(20, 100);
2282
2283         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2284         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2285         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2286
2287         usleep_range(20, 100);
2288
2289         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2290         value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2291         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2292
2293         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2294         value &= ~SOR_PLL0_VCOPD;
2295         value &= ~SOR_PLL0_PWR;
2296         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2297
2298         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2299         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2300         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2301
2302         usleep_range(200, 400);
2303
2304         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2305         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2306         value &= ~SOR_PLL2_PORT_POWERDOWN;
2307         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2308
2309         usleep_range(20, 100);
2310
2311         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2312         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2313                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2314         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2315
2316         while (true) {
2317                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2318                 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2319                         break;
2320
2321                 usleep_range(250, 1000);
2322         }
2323
2324         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2325                 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2326         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2327
2328         while (true) {
2329                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2330                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2331                         break;
2332
2333                 usleep_range(250, 1000);
2334         }
2335
2336         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2337         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2338         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2339
2340         if (mode->clock < 340000) {
2341                 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2342                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2343         } else {
2344                 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2345                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2346         }
2347
2348         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2349         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2350
2351         /* SOR pad PLL stabilization time */
2352         usleep_range(250, 1000);
2353
2354         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2355         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2356         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2357         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2358
2359         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2360         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2361         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2362         value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2363         value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2364         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2365
2366         value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2367                 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2368         tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2369
2370         value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2371                 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2372         tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2373         tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2374
2375         if (!sor->soc->has_nvdisplay) {
2376                 /* program the reference clock */
2377                 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2378                 tegra_sor_writel(sor, value, SOR_REFCLK);
2379         }
2380
2381         /* XXX not in TRM */
2382         for (value = 0, i = 0; i < 5; i++)
2383                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2384                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2385
2386         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2387         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2388
2389         /*
2390          * Switch the pad clock to the DP clock. Note that we cannot actually
2391          * do this because Tegra186 and later don't support clk_set_parent()
2392          * on the sorX_pad_clkout clocks. We already do the equivalent above
2393          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2394          */
2395 #if 0
2396         err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2397         if (err < 0) {
2398                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2399                         err);
2400                 return;
2401         }
2402 #endif
2403
2404         /* switch the SOR clock to the pad clock */
2405         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2406         if (err < 0) {
2407                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2408                         err);
2409                 return;
2410         }
2411
2412         /* switch the output clock to the parent pixel clock */
2413         err = clk_set_parent(sor->clk, sor->clk_parent);
2414         if (err < 0) {
2415                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2416                         err);
2417                 return;
2418         }
2419
2420         /* adjust clock rate for HDMI 2.0 modes */
2421         rate = clk_get_rate(sor->clk_parent);
2422
2423         if (mode->clock >= 340000)
2424                 rate /= 2;
2425
2426         DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2427
2428         clk_set_rate(sor->clk, rate);
2429
2430         if (!sor->soc->has_nvdisplay) {
2431                 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2432
2433                 /* XXX is this the proper check? */
2434                 if (mode->clock < 75000)
2435                         value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2436
2437                 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2438         }
2439
2440         max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2441
2442         value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2443                 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2444         tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2445
2446         if (!dc->soc->has_nvdisplay) {
2447                 /* H_PULSE2 setup */
2448                 pulse_start = h_ref_to_sync +
2449                               (mode->hsync_end - mode->hsync_start) +
2450                               (mode->htotal - mode->hsync_end) - 10;
2451
2452                 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2453                         PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2454                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2455
2456                 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2457                 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2458
2459                 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2460                 value |= H_PULSE2_ENABLE;
2461                 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2462         }
2463
2464         /* infoframe setup */
2465         err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2466         if (err < 0)
2467                 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2468
2469         /* XXX HDMI audio support not implemented yet */
2470         tegra_sor_hdmi_disable_audio_infoframe(sor);
2471
2472         /* use single TMDS protocol */
2473         value = tegra_sor_readl(sor, SOR_STATE1);
2474         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2475         value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2476         tegra_sor_writel(sor, value, SOR_STATE1);
2477
2478         /* power up pad calibration */
2479         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2480         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2481         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2482
2483         /* production settings */
2484         settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2485         if (!settings) {
2486                 dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2487                         mode->clock * 1000);
2488                 return;
2489         }
2490
2491         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2492         value &= ~SOR_PLL0_ICHPMP_MASK;
2493         value &= ~SOR_PLL0_FILTER_MASK;
2494         value &= ~SOR_PLL0_VCOCAP_MASK;
2495         value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2496         value |= SOR_PLL0_FILTER(settings->filter);
2497         value |= SOR_PLL0_VCOCAP(settings->vcocap);
2498         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2499
2500         /* XXX not in TRM */
2501         value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2502         value &= ~SOR_PLL1_LOADADJ_MASK;
2503         value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2504         value |= SOR_PLL1_LOADADJ(settings->loadadj);
2505         value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2506         value |= SOR_PLL1_TMDS_TERM;
2507         tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2508
2509         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2510         value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2511         value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2512         value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2513         value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2514         value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2515         value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2516         value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2517         value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2518         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2519
2520         value = settings->drive_current[3] << 24 |
2521                 settings->drive_current[2] << 16 |
2522                 settings->drive_current[1] <<  8 |
2523                 settings->drive_current[0] <<  0;
2524         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2525
2526         value = settings->preemphasis[3] << 24 |
2527                 settings->preemphasis[2] << 16 |
2528                 settings->preemphasis[1] <<  8 |
2529                 settings->preemphasis[0] <<  0;
2530         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2531
2532         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2533         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2534         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2535         value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2536         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2537
2538         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2539         value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2540         value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2541         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2542
2543         /* power down pad calibration */
2544         value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2545         value |= SOR_DP_PADCTL_PAD_CAL_PD;
2546         tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2547
2548         if (!dc->soc->has_nvdisplay) {
2549                 /* miscellaneous display controller settings */
2550                 value = VSYNC_H_POSITION(1);
2551                 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2552         }
2553
2554         value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2555         value &= ~DITHER_CONTROL_MASK;
2556         value &= ~BASE_COLOR_SIZE_MASK;
2557
2558         switch (state->bpc) {
2559         case 6:
2560                 value |= BASE_COLOR_SIZE_666;
2561                 break;
2562
2563         case 8:
2564                 value |= BASE_COLOR_SIZE_888;
2565                 break;
2566
2567         case 10:
2568                 value |= BASE_COLOR_SIZE_101010;
2569                 break;
2570
2571         case 12:
2572                 value |= BASE_COLOR_SIZE_121212;
2573                 break;
2574
2575         default:
2576                 WARN(1, "%u bits-per-color not supported\n", state->bpc);
2577                 value |= BASE_COLOR_SIZE_888;
2578                 break;
2579         }
2580
2581         tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2582
2583         /* XXX set display head owner */
2584         value = tegra_sor_readl(sor, SOR_STATE1);
2585         value &= ~SOR_STATE_ASY_OWNER_MASK;
2586         value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2587         tegra_sor_writel(sor, value, SOR_STATE1);
2588
2589         err = tegra_sor_power_up(sor, 250);
2590         if (err < 0)
2591                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2592
2593         /* configure dynamic range of output */
2594         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2595         value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2596         value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2597         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2598
2599         /* configure colorspace */
2600         value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2601         value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2602         value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2603         tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2604
2605         tegra_sor_mode_set(sor, mode, state);
2606
2607         tegra_sor_update(sor);
2608
2609         /* program preamble timing in SOR (XXX) */
2610         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2611         value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2612         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2613
2614         err = tegra_sor_attach(sor);
2615         if (err < 0)
2616                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2617
2618         /* enable display to SOR clock and generate HDMI preamble */
2619         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2620
2621         if (!sor->soc->has_nvdisplay)
2622                 value |= SOR1_TIMING_CYA;
2623
2624         value |= SOR_ENABLE(sor->index);
2625
2626         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2627
2628         if (dc->soc->has_nvdisplay) {
2629                 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2630                 value &= ~PROTOCOL_MASK;
2631                 value |= PROTOCOL_SINGLE_TMDS_A;
2632                 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2633         }
2634
2635         tegra_dc_commit(dc);
2636
2637         err = tegra_sor_wakeup(sor);
2638         if (err < 0)
2639                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2640
2641         tegra_sor_hdmi_scdc_start(sor);
2642         tegra_sor_audio_prepare(sor);
2643 }
2644
2645 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2646         .disable = tegra_sor_hdmi_disable,
2647         .enable = tegra_sor_hdmi_enable,
2648         .atomic_check = tegra_sor_encoder_atomic_check,
2649 };
2650
2651 static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2652 {
2653         struct tegra_output *output = encoder_to_output(encoder);
2654         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2655         struct tegra_sor *sor = to_sor(output);
2656         u32 value;
2657         int err;
2658
2659         if (output->panel)
2660                 drm_panel_disable(output->panel);
2661
2662         /*
2663          * Do not attempt to power down a DP link if we're not connected since
2664          * the AUX transactions would just be timing out.
2665          */
2666         if (output->connector.status != connector_status_disconnected) {
2667                 err = drm_dp_link_power_down(sor->aux, &sor->link);
2668                 if (err < 0)
2669                         dev_err(sor->dev, "failed to power down link: %d\n",
2670                                 err);
2671         }
2672
2673         err = tegra_sor_detach(sor);
2674         if (err < 0)
2675                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2676
2677         tegra_sor_writel(sor, 0, SOR_STATE1);
2678         tegra_sor_update(sor);
2679
2680         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2681         value &= ~SOR_ENABLE(sor->index);
2682         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2683         tegra_dc_commit(dc);
2684
2685         value = tegra_sor_readl(sor, SOR_STATE1);
2686         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2687         value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2688         value &= ~SOR_STATE_ASY_OWNER_MASK;
2689         tegra_sor_writel(sor, value, SOR_STATE1);
2690         tegra_sor_update(sor);
2691
2692         /* switch to safe parent clock */
2693         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2694         if (err < 0)
2695                 dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2696
2697         err = tegra_sor_power_down(sor);
2698         if (err < 0)
2699                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2700
2701         err = tegra_io_pad_power_disable(sor->pad);
2702         if (err < 0)
2703                 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2704
2705         err = drm_dp_aux_disable(sor->aux);
2706         if (err < 0)
2707                 dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2708
2709         if (output->panel)
2710                 drm_panel_unprepare(output->panel);
2711
2712         host1x_client_suspend(&sor->client);
2713 }
2714
2715 static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2716 {
2717         struct tegra_output *output = encoder_to_output(encoder);
2718         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2719         struct tegra_sor *sor = to_sor(output);
2720         struct tegra_sor_config config;
2721         struct tegra_sor_state *state;
2722         struct drm_display_mode *mode;
2723         struct drm_display_info *info;
2724         unsigned int i;
2725         u32 value;
2726         int err;
2727
2728         state = to_sor_state(output->connector.state);
2729         mode = &encoder->crtc->state->adjusted_mode;
2730         info = &output->connector.display_info;
2731
2732         err = host1x_client_resume(&sor->client);
2733         if (err < 0) {
2734                 dev_err(sor->dev, "failed to resume: %d\n", err);
2735                 return;
2736         }
2737
2738         /* switch to safe parent clock */
2739         err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2740         if (err < 0)
2741                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2742
2743         err = tegra_io_pad_power_enable(sor->pad);
2744         if (err < 0)
2745                 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2746
2747         usleep_range(20, 100);
2748
2749         err = drm_dp_aux_enable(sor->aux);
2750         if (err < 0)
2751                 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2752
2753         err = drm_dp_link_probe(sor->aux, &sor->link);
2754         if (err < 0)
2755                 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2756
2757         tegra_sor_filter_rates(sor);
2758
2759         err = drm_dp_link_choose(&sor->link, mode, info);
2760         if (err < 0)
2761                 dev_err(sor->dev, "failed to choose link: %d\n", err);
2762
2763         if (output->panel)
2764                 drm_panel_prepare(output->panel);
2765
2766         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2767         value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2768         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2769
2770         usleep_range(20, 40);
2771
2772         value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2773         value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2774         tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2775
2776         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2777         value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2778         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2779
2780         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2781         value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2782         value |= SOR_PLL2_SEQ_PLLCAPPD;
2783         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2784
2785         usleep_range(200, 400);
2786
2787         value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2788         value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2789         value &= ~SOR_PLL2_PORT_POWERDOWN;
2790         tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2791
2792         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2793         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2794
2795         if (output->panel)
2796                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2797         else
2798                 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2799
2800         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2801
2802         usleep_range(200, 400);
2803
2804         value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2805         /* XXX not in TRM */
2806         if (output->panel)
2807                 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2808         else
2809                 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2810
2811         value |= SOR_DP_SPARE_SEQ_ENABLE;
2812         tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2813
2814         /* XXX not in TRM */
2815         tegra_sor_writel(sor, 0, SOR_LVDS);
2816
2817         value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2818         value &= ~SOR_PLL0_ICHPMP_MASK;
2819         value &= ~SOR_PLL0_VCOCAP_MASK;
2820         value |= SOR_PLL0_ICHPMP(0x1);
2821         value |= SOR_PLL0_VCOCAP(0x3);
2822         value |= SOR_PLL0_RESISTOR_EXT;
2823         tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2824
2825         /* XXX not in TRM */
2826         for (value = 0, i = 0; i < 5; i++)
2827                 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2828                          SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2829
2830         tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2831         tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2832
2833         /*
2834          * Switch the pad clock to the DP clock. Note that we cannot actually
2835          * do this because Tegra186 and later don't support clk_set_parent()
2836          * on the sorX_pad_clkout clocks. We already do the equivalent above
2837          * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2838          */
2839 #if 0
2840         err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2841         if (err < 0) {
2842                 dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2843                         err);
2844                 return;
2845         }
2846 #endif
2847
2848         /* switch the SOR clock to the pad clock */
2849         err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2850         if (err < 0) {
2851                 dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2852                         err);
2853                 return;
2854         }
2855
2856         /* switch the output clock to the parent pixel clock */
2857         err = clk_set_parent(sor->clk, sor->clk_parent);
2858         if (err < 0) {
2859                 dev_err(sor->dev, "failed to select output parent clock: %d\n",
2860                         err);
2861                 return;
2862         }
2863
2864         /* use DP-A protocol */
2865         value = tegra_sor_readl(sor, SOR_STATE1);
2866         value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2867         value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2868         tegra_sor_writel(sor, value, SOR_STATE1);
2869
2870         /* enable port */
2871         value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2872         value |= SOR_DP_LINKCTL_ENABLE;
2873         tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2874
2875         tegra_sor_dp_term_calibrate(sor);
2876
2877         err = drm_dp_link_train(&sor->link);
2878         if (err < 0)
2879                 dev_err(sor->dev, "link training failed: %d\n", err);
2880         else
2881                 dev_dbg(sor->dev, "link training succeeded\n");
2882
2883         err = drm_dp_link_power_up(sor->aux, &sor->link);
2884         if (err < 0)
2885                 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2886
2887         /* compute configuration */
2888         memset(&config, 0, sizeof(config));
2889         config.bits_per_pixel = state->bpc * 3;
2890
2891         err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2892         if (err < 0)
2893                 dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2894
2895         tegra_sor_apply_config(sor, &config);
2896         tegra_sor_mode_set(sor, mode, state);
2897
2898         if (output->panel) {
2899                 /* CSTM (LVDS, link A/B, upper) */
2900                 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2901                         SOR_CSTM_UPPER;
2902                 tegra_sor_writel(sor, value, SOR_CSTM);
2903
2904                 /* PWM setup */
2905                 err = tegra_sor_setup_pwm(sor, 250);
2906                 if (err < 0)
2907                         dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2908         }
2909
2910         tegra_sor_update(sor);
2911
2912         err = tegra_sor_power_up(sor, 250);
2913         if (err < 0)
2914                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2915
2916         /* attach and wake up */
2917         err = tegra_sor_attach(sor);
2918         if (err < 0)
2919                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2920
2921         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2922         value |= SOR_ENABLE(sor->index);
2923         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2924
2925         tegra_dc_commit(dc);
2926
2927         err = tegra_sor_wakeup(sor);
2928         if (err < 0)
2929                 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2930
2931         if (output->panel)
2932                 drm_panel_enable(output->panel);
2933 }
2934
2935 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2936         .disable = tegra_sor_dp_disable,
2937         .enable = tegra_sor_dp_enable,
2938         .atomic_check = tegra_sor_encoder_atomic_check,
2939 };
2940
2941 static void tegra_sor_disable_regulator(void *data)
2942 {
2943         struct regulator *reg = data;
2944
2945         regulator_disable(reg);
2946 }
2947
2948 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg)
2949 {
2950         int err;
2951
2952         err = regulator_enable(reg);
2953         if (err)
2954                 return err;
2955
2956         return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg);
2957 }
2958
2959 static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2960 {
2961         int err;
2962
2963         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2964         if (IS_ERR(sor->avdd_io_supply))
2965                 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply),
2966                                      "cannot get AVDD I/O supply\n");
2967
2968         err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
2969         if (err < 0) {
2970                 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2971                         err);
2972                 return err;
2973         }
2974
2975         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2976         if (IS_ERR(sor->vdd_pll_supply))
2977                 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply),
2978                                      "cannot get VDD PLL supply\n");
2979
2980         err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
2981         if (err < 0) {
2982                 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2983                         err);
2984                 return err;
2985         }
2986
2987         sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2988         if (IS_ERR(sor->hdmi_supply))
2989                 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply),
2990                                      "cannot get HDMI supply\n");
2991
2992         err = tegra_sor_enable_regulator(sor, sor->hdmi_supply);
2993         if (err < 0) {
2994                 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2995                 return err;
2996         }
2997
2998         INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
2999
3000         return 0;
3001 }
3002
3003 static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3004         .name = "HDMI",
3005         .probe = tegra_sor_hdmi_probe,
3006         .audio_enable = tegra_sor_hdmi_audio_enable,
3007         .audio_disable = tegra_sor_hdmi_audio_disable,
3008 };
3009
3010 static int tegra_sor_dp_probe(struct tegra_sor *sor)
3011 {
3012         int err;
3013
3014         sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3015         if (IS_ERR(sor->avdd_io_supply))
3016                 return PTR_ERR(sor->avdd_io_supply);
3017
3018         err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply);
3019         if (err < 0)
3020                 return err;
3021
3022         sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3023         if (IS_ERR(sor->vdd_pll_supply))
3024                 return PTR_ERR(sor->vdd_pll_supply);
3025
3026         err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply);
3027         if (err < 0)
3028                 return err;
3029
3030         return 0;
3031 }
3032
3033 static const struct tegra_sor_ops tegra_sor_dp_ops = {
3034         .name = "DP",
3035         .probe = tegra_sor_dp_probe,
3036 };
3037
3038 static int tegra_sor_init(struct host1x_client *client)
3039 {
3040         struct drm_device *drm = dev_get_drvdata(client->host);
3041         const struct drm_encoder_helper_funcs *helpers = NULL;
3042         struct tegra_sor *sor = host1x_client_to_sor(client);
3043         int connector = DRM_MODE_CONNECTOR_Unknown;
3044         int encoder = DRM_MODE_ENCODER_NONE;
3045         int err;
3046
3047         if (!sor->aux) {
3048                 if (sor->ops == &tegra_sor_hdmi_ops) {
3049                         connector = DRM_MODE_CONNECTOR_HDMIA;
3050                         encoder = DRM_MODE_ENCODER_TMDS;
3051                         helpers = &tegra_sor_hdmi_helpers;
3052                 } else if (sor->soc->supports_lvds) {
3053                         connector = DRM_MODE_CONNECTOR_LVDS;
3054                         encoder = DRM_MODE_ENCODER_LVDS;
3055                 }
3056         } else {
3057                 if (sor->output.panel) {
3058                         connector = DRM_MODE_CONNECTOR_eDP;
3059                         encoder = DRM_MODE_ENCODER_TMDS;
3060                         helpers = &tegra_sor_dp_helpers;
3061                 } else {
3062                         connector = DRM_MODE_CONNECTOR_DisplayPort;
3063                         encoder = DRM_MODE_ENCODER_TMDS;
3064                         helpers = &tegra_sor_dp_helpers;
3065                 }
3066
3067                 sor->link.ops = &tegra_sor_dp_link_ops;
3068                 sor->link.aux = sor->aux;
3069         }
3070
3071         sor->output.dev = sor->dev;
3072
3073         drm_connector_init_with_ddc(drm, &sor->output.connector,
3074                                     &tegra_sor_connector_funcs,
3075                                     connector,
3076                                     sor->output.ddc);
3077         drm_connector_helper_add(&sor->output.connector,
3078                                  &tegra_sor_connector_helper_funcs);
3079         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3080
3081         drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
3082         drm_encoder_helper_add(&sor->output.encoder, helpers);
3083
3084         drm_connector_attach_encoder(&sor->output.connector,
3085                                           &sor->output.encoder);
3086         drm_connector_register(&sor->output.connector);
3087
3088         err = tegra_output_init(drm, &sor->output);
3089         if (err < 0) {
3090                 dev_err(client->dev, "failed to initialize output: %d\n", err);
3091                 return err;
3092         }
3093
3094         tegra_output_find_possible_crtcs(&sor->output, drm);
3095
3096         if (sor->aux) {
3097                 err = drm_dp_aux_attach(sor->aux, &sor->output);
3098                 if (err < 0) {
3099                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
3100                         return err;
3101                 }
3102         }
3103
3104         /*
3105          * XXX: Remove this reset once proper hand-over from firmware to
3106          * kernel is possible.
3107          */
3108         if (sor->rst) {
3109                 err = pm_runtime_resume_and_get(sor->dev);
3110                 if (err < 0) {
3111                         dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
3112                         return err;
3113                 }
3114
3115                 err = reset_control_acquire(sor->rst);
3116                 if (err < 0) {
3117                         dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3118                                 err);
3119                         goto rpm_put;
3120                 }
3121
3122                 err = reset_control_assert(sor->rst);
3123                 if (err < 0) {
3124                         dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3125                                 err);
3126                         goto rpm_put;
3127                 }
3128         }
3129
3130         err = clk_prepare_enable(sor->clk);
3131         if (err < 0) {
3132                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
3133                 goto rpm_put;
3134         }
3135
3136         usleep_range(1000, 3000);
3137
3138         if (sor->rst) {
3139                 err = reset_control_deassert(sor->rst);
3140                 if (err < 0) {
3141                         dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3142                                 err);
3143                         clk_disable_unprepare(sor->clk);
3144                         goto rpm_put;
3145                 }
3146
3147                 reset_control_release(sor->rst);
3148                 pm_runtime_put(sor->dev);
3149         }
3150
3151         err = clk_prepare_enable(sor->clk_safe);
3152         if (err < 0) {
3153                 clk_disable_unprepare(sor->clk);
3154                 return err;
3155         }
3156
3157         err = clk_prepare_enable(sor->clk_dp);
3158         if (err < 0) {
3159                 clk_disable_unprepare(sor->clk_safe);
3160                 clk_disable_unprepare(sor->clk);
3161                 return err;
3162         }
3163
3164         return 0;
3165
3166 rpm_put:
3167         if (sor->rst)
3168                 pm_runtime_put(sor->dev);
3169
3170         return err;
3171 }
3172
3173 static int tegra_sor_exit(struct host1x_client *client)
3174 {
3175         struct tegra_sor *sor = host1x_client_to_sor(client);
3176         int err;
3177
3178         tegra_output_exit(&sor->output);
3179
3180         if (sor->aux) {
3181                 err = drm_dp_aux_detach(sor->aux);
3182                 if (err < 0) {
3183                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
3184                         return err;
3185                 }
3186         }
3187
3188         clk_disable_unprepare(sor->clk_safe);
3189         clk_disable_unprepare(sor->clk_dp);
3190         clk_disable_unprepare(sor->clk);
3191
3192         return 0;
3193 }
3194
3195 static int tegra_sor_runtime_suspend(struct host1x_client *client)
3196 {
3197         struct tegra_sor *sor = host1x_client_to_sor(client);
3198         struct device *dev = client->dev;
3199         int err;
3200
3201         if (sor->rst) {
3202                 err = reset_control_assert(sor->rst);
3203                 if (err < 0) {
3204                         dev_err(dev, "failed to assert reset: %d\n", err);
3205                         return err;
3206                 }
3207
3208                 reset_control_release(sor->rst);
3209         }
3210
3211         usleep_range(1000, 2000);
3212
3213         clk_disable_unprepare(sor->clk);
3214         pm_runtime_put_sync(dev);
3215
3216         return 0;
3217 }
3218
3219 static int tegra_sor_runtime_resume(struct host1x_client *client)
3220 {
3221         struct tegra_sor *sor = host1x_client_to_sor(client);
3222         struct device *dev = client->dev;
3223         int err;
3224
3225         err = pm_runtime_resume_and_get(dev);
3226         if (err < 0) {
3227                 dev_err(dev, "failed to get runtime PM: %d\n", err);
3228                 return err;
3229         }
3230
3231         err = clk_prepare_enable(sor->clk);
3232         if (err < 0) {
3233                 dev_err(dev, "failed to enable clock: %d\n", err);
3234                 goto put_rpm;
3235         }
3236
3237         usleep_range(1000, 2000);
3238
3239         if (sor->rst) {
3240                 err = reset_control_acquire(sor->rst);
3241                 if (err < 0) {
3242                         dev_err(dev, "failed to acquire reset: %d\n", err);
3243                         goto disable_clk;
3244                 }
3245
3246                 err = reset_control_deassert(sor->rst);
3247                 if (err < 0) {
3248                         dev_err(dev, "failed to deassert reset: %d\n", err);
3249                         goto release_reset;
3250                 }
3251         }
3252
3253         return 0;
3254
3255 release_reset:
3256         reset_control_release(sor->rst);
3257 disable_clk:
3258         clk_disable_unprepare(sor->clk);
3259 put_rpm:
3260         pm_runtime_put_sync(dev);
3261         return err;
3262 }
3263
3264 static const struct host1x_client_ops sor_client_ops = {
3265         .init = tegra_sor_init,
3266         .exit = tegra_sor_exit,
3267         .suspend = tegra_sor_runtime_suspend,
3268         .resume = tegra_sor_runtime_resume,
3269 };
3270
3271 static const u8 tegra124_sor_xbar_cfg[5] = {
3272         0, 1, 2, 3, 4
3273 };
3274
3275 static const struct tegra_sor_regs tegra124_sor_regs = {
3276         .head_state0 = 0x05,
3277         .head_state1 = 0x07,
3278         .head_state2 = 0x09,
3279         .head_state3 = 0x0b,
3280         .head_state4 = 0x0d,
3281         .head_state5 = 0x0f,
3282         .pll0 = 0x17,
3283         .pll1 = 0x18,
3284         .pll2 = 0x19,
3285         .pll3 = 0x1a,
3286         .dp_padctl0 = 0x5c,
3287         .dp_padctl2 = 0x73,
3288 };
3289
3290 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3291 static const u8 tegra124_sor_lane_map[4] = {
3292         2, 1, 0, 3,
3293 };
3294
3295 static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3296         {
3297                 { 0x13, 0x19, 0x1e, 0x28 },
3298                 { 0x1e, 0x25, 0x2d, },
3299                 { 0x28, 0x32, },
3300                 { 0x3c, },
3301         }, {
3302                 { 0x12, 0x17, 0x1b, 0x25 },
3303                 { 0x1c, 0x23, 0x2a, },
3304                 { 0x25, 0x2f, },
3305                 { 0x39, }
3306         }, {
3307                 { 0x12, 0x16, 0x1a, 0x22 },
3308                 { 0x1b, 0x20, 0x27, },
3309                 { 0x24, 0x2d, },
3310                 { 0x36, },
3311         }, {
3312                 { 0x11, 0x14, 0x17, 0x1f },
3313                 { 0x19, 0x1e, 0x24, },
3314                 { 0x22, 0x2a, },
3315                 { 0x32, },
3316         },
3317 };
3318
3319 static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3320         {
3321                 { 0x00, 0x09, 0x13, 0x25 },
3322                 { 0x00, 0x0f, 0x1e, },
3323                 { 0x00, 0x14, },
3324                 { 0x00, },
3325         }, {
3326                 { 0x00, 0x0a, 0x14, 0x28 },
3327                 { 0x00, 0x0f, 0x1e, },
3328                 { 0x00, 0x14, },
3329                 { 0x00 },
3330         }, {
3331                 { 0x00, 0x0a, 0x14, 0x28 },
3332                 { 0x00, 0x0f, 0x1e, },
3333                 { 0x00, 0x14, },
3334                 { 0x00, },
3335         }, {
3336                 { 0x00, 0x0a, 0x14, 0x28 },
3337                 { 0x00, 0x0f, 0x1e, },
3338                 { 0x00, 0x14, },
3339                 { 0x00, },
3340         },
3341 };
3342
3343 static const u8 tegra124_sor_post_cursor[4][4][4] = {
3344         {
3345                 { 0x00, 0x00, 0x00, 0x00 },
3346                 { 0x00, 0x00, 0x00, },
3347                 { 0x00, 0x00, },
3348                 { 0x00, },
3349         }, {
3350                 { 0x02, 0x02, 0x04, 0x05 },
3351                 { 0x02, 0x04, 0x05, },
3352                 { 0x04, 0x05, },
3353                 { 0x05, },
3354         }, {
3355                 { 0x04, 0x05, 0x08, 0x0b },
3356                 { 0x05, 0x09, 0x0b, },
3357                 { 0x08, 0x0a, },
3358                 { 0x0b, },
3359         }, {
3360                 { 0x05, 0x09, 0x0b, 0x12 },
3361                 { 0x09, 0x0d, 0x12, },
3362                 { 0x0b, 0x0f, },
3363                 { 0x12, },
3364         },
3365 };
3366
3367 static const u8 tegra124_sor_tx_pu[4][4][4] = {
3368         {
3369                 { 0x20, 0x30, 0x40, 0x60 },
3370                 { 0x30, 0x40, 0x60, },
3371                 { 0x40, 0x60, },
3372                 { 0x60, },
3373         }, {
3374                 { 0x20, 0x20, 0x30, 0x50 },
3375                 { 0x30, 0x40, 0x50, },
3376                 { 0x40, 0x50, },
3377                 { 0x60, },
3378         }, {
3379                 { 0x20, 0x20, 0x30, 0x40, },
3380                 { 0x30, 0x30, 0x40, },
3381                 { 0x40, 0x50, },
3382                 { 0x60, },
3383         }, {
3384                 { 0x20, 0x20, 0x20, 0x40, },
3385                 { 0x30, 0x30, 0x40, },
3386                 { 0x40, 0x40, },
3387                 { 0x60, },
3388         },
3389 };
3390
3391 static const struct tegra_sor_soc tegra124_sor = {
3392         .supports_lvds = true,
3393         .supports_hdmi = false,
3394         .supports_dp = true,
3395         .supports_audio = false,
3396         .supports_hdcp = false,
3397         .regs = &tegra124_sor_regs,
3398         .has_nvdisplay = false,
3399         .xbar_cfg = tegra124_sor_xbar_cfg,
3400         .lane_map = tegra124_sor_lane_map,
3401         .voltage_swing = tegra124_sor_voltage_swing,
3402         .pre_emphasis = tegra124_sor_pre_emphasis,
3403         .post_cursor = tegra124_sor_post_cursor,
3404         .tx_pu = tegra124_sor_tx_pu,
3405 };
3406
3407 static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3408         {
3409                 { 0x00, 0x08, 0x12, 0x24 },
3410                 { 0x01, 0x0e, 0x1d, },
3411                 { 0x01, 0x13, },
3412                 { 0x00, },
3413         }, {
3414                 { 0x00, 0x08, 0x12, 0x24 },
3415                 { 0x00, 0x0e, 0x1d, },
3416                 { 0x00, 0x13, },
3417                 { 0x00 },
3418         }, {
3419                 { 0x00, 0x08, 0x12, 0x24 },
3420                 { 0x00, 0x0e, 0x1d, },
3421                 { 0x00, 0x13, },
3422                 { 0x00, },
3423         }, {
3424                 { 0x00, 0x08, 0x12, 0x24 },
3425                 { 0x00, 0x0e, 0x1d, },
3426                 { 0x00, 0x13, },
3427                 { 0x00, },
3428         },
3429 };
3430
3431 static const struct tegra_sor_soc tegra132_sor = {
3432         .supports_lvds = true,
3433         .supports_hdmi = false,
3434         .supports_dp = true,
3435         .supports_audio = false,
3436         .supports_hdcp = false,
3437         .regs = &tegra124_sor_regs,
3438         .has_nvdisplay = false,
3439         .xbar_cfg = tegra124_sor_xbar_cfg,
3440         .lane_map = tegra124_sor_lane_map,
3441         .voltage_swing = tegra124_sor_voltage_swing,
3442         .pre_emphasis = tegra132_sor_pre_emphasis,
3443         .post_cursor = tegra124_sor_post_cursor,
3444         .tx_pu = tegra124_sor_tx_pu,
3445 };
3446
3447 static const struct tegra_sor_regs tegra210_sor_regs = {
3448         .head_state0 = 0x05,
3449         .head_state1 = 0x07,
3450         .head_state2 = 0x09,
3451         .head_state3 = 0x0b,
3452         .head_state4 = 0x0d,
3453         .head_state5 = 0x0f,
3454         .pll0 = 0x17,
3455         .pll1 = 0x18,
3456         .pll2 = 0x19,
3457         .pll3 = 0x1a,
3458         .dp_padctl0 = 0x5c,
3459         .dp_padctl2 = 0x73,
3460 };
3461
3462 static const u8 tegra210_sor_xbar_cfg[5] = {
3463         2, 1, 0, 3, 4
3464 };
3465
3466 static const u8 tegra210_sor_lane_map[4] = {
3467         0, 1, 2, 3,
3468 };
3469
3470 static const struct tegra_sor_soc tegra210_sor = {
3471         .supports_lvds = false,
3472         .supports_hdmi = false,
3473         .supports_dp = true,
3474         .supports_audio = false,
3475         .supports_hdcp = false,
3476
3477         .regs = &tegra210_sor_regs,
3478         .has_nvdisplay = false,
3479
3480         .xbar_cfg = tegra210_sor_xbar_cfg,
3481         .lane_map = tegra210_sor_lane_map,
3482         .voltage_swing = tegra124_sor_voltage_swing,
3483         .pre_emphasis = tegra124_sor_pre_emphasis,
3484         .post_cursor = tegra124_sor_post_cursor,
3485         .tx_pu = tegra124_sor_tx_pu,
3486 };
3487
3488 static const struct tegra_sor_soc tegra210_sor1 = {
3489         .supports_lvds = false,
3490         .supports_hdmi = true,
3491         .supports_dp = true,
3492         .supports_audio = true,
3493         .supports_hdcp = true,
3494
3495         .regs = &tegra210_sor_regs,
3496         .has_nvdisplay = false,
3497
3498         .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3499         .settings = tegra210_sor_hdmi_defaults,
3500         .xbar_cfg = tegra210_sor_xbar_cfg,
3501         .lane_map = tegra210_sor_lane_map,
3502         .voltage_swing = tegra124_sor_voltage_swing,
3503         .pre_emphasis = tegra124_sor_pre_emphasis,
3504         .post_cursor = tegra124_sor_post_cursor,
3505         .tx_pu = tegra124_sor_tx_pu,
3506 };
3507
3508 static const struct tegra_sor_regs tegra186_sor_regs = {
3509         .head_state0 = 0x151,
3510         .head_state1 = 0x154,
3511         .head_state2 = 0x157,
3512         .head_state3 = 0x15a,
3513         .head_state4 = 0x15d,
3514         .head_state5 = 0x160,
3515         .pll0 = 0x163,
3516         .pll1 = 0x164,
3517         .pll2 = 0x165,
3518         .pll3 = 0x166,
3519         .dp_padctl0 = 0x168,
3520         .dp_padctl2 = 0x16a,
3521 };
3522
3523 static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3524         {
3525                 { 0x13, 0x19, 0x1e, 0x28 },
3526                 { 0x1e, 0x25, 0x2d, },
3527                 { 0x28, 0x32, },
3528                 { 0x39, },
3529         }, {
3530                 { 0x12, 0x16, 0x1b, 0x25 },
3531                 { 0x1c, 0x23, 0x2a, },
3532                 { 0x25, 0x2f, },
3533                 { 0x37, }
3534         }, {
3535                 { 0x12, 0x16, 0x1a, 0x22 },
3536                 { 0x1b, 0x20, 0x27, },
3537                 { 0x24, 0x2d, },
3538                 { 0x35, },
3539         }, {
3540                 { 0x11, 0x14, 0x17, 0x1f },
3541                 { 0x19, 0x1e, 0x24, },
3542                 { 0x22, 0x2a, },
3543                 { 0x32, },
3544         },
3545 };
3546
3547 static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3548         {
3549                 { 0x00, 0x08, 0x12, 0x24 },
3550                 { 0x01, 0x0e, 0x1d, },
3551                 { 0x01, 0x13, },
3552                 { 0x00, },
3553         }, {
3554                 { 0x00, 0x08, 0x12, 0x24 },
3555                 { 0x00, 0x0e, 0x1d, },
3556                 { 0x00, 0x13, },
3557                 { 0x00 },
3558         }, {
3559                 { 0x00, 0x08, 0x14, 0x24 },
3560                 { 0x00, 0x0e, 0x1d, },
3561                 { 0x00, 0x13, },
3562                 { 0x00, },
3563         }, {
3564                 { 0x00, 0x08, 0x12, 0x24 },
3565                 { 0x00, 0x0e, 0x1d, },
3566                 { 0x00, 0x13, },
3567                 { 0x00, },
3568         },
3569 };
3570
3571 static const struct tegra_sor_soc tegra186_sor = {
3572         .supports_lvds = false,
3573         .supports_hdmi = true,
3574         .supports_dp = true,
3575         .supports_audio = true,
3576         .supports_hdcp = true,
3577
3578         .regs = &tegra186_sor_regs,
3579         .has_nvdisplay = true,
3580
3581         .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3582         .settings = tegra186_sor_hdmi_defaults,
3583         .xbar_cfg = tegra124_sor_xbar_cfg,
3584         .lane_map = tegra124_sor_lane_map,
3585         .voltage_swing = tegra186_sor_voltage_swing,
3586         .pre_emphasis = tegra186_sor_pre_emphasis,
3587         .post_cursor = tegra124_sor_post_cursor,
3588         .tx_pu = tegra124_sor_tx_pu,
3589 };
3590
3591 static const struct tegra_sor_regs tegra194_sor_regs = {
3592         .head_state0 = 0x151,
3593         .head_state1 = 0x155,
3594         .head_state2 = 0x159,
3595         .head_state3 = 0x15d,
3596         .head_state4 = 0x161,
3597         .head_state5 = 0x165,
3598         .pll0 = 0x169,
3599         .pll1 = 0x16a,
3600         .pll2 = 0x16b,
3601         .pll3 = 0x16c,
3602         .dp_padctl0 = 0x16e,
3603         .dp_padctl2 = 0x16f,
3604 };
3605
3606 static const struct tegra_sor_soc tegra194_sor = {
3607         .supports_lvds = false,
3608         .supports_hdmi = true,
3609         .supports_dp = true,
3610         .supports_audio = true,
3611         .supports_hdcp = true,
3612
3613         .regs = &tegra194_sor_regs,
3614         .has_nvdisplay = true,
3615
3616         .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3617         .settings = tegra194_sor_hdmi_defaults,
3618
3619         .xbar_cfg = tegra210_sor_xbar_cfg,
3620         .lane_map = tegra124_sor_lane_map,
3621         .voltage_swing = tegra186_sor_voltage_swing,
3622         .pre_emphasis = tegra186_sor_pre_emphasis,
3623         .post_cursor = tegra124_sor_post_cursor,
3624         .tx_pu = tegra124_sor_tx_pu,
3625 };
3626
3627 static const struct of_device_id tegra_sor_of_match[] = {
3628         { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3629         { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3630         { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3631         { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3632         { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3633         { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3634         { },
3635 };
3636 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3637
3638 static int tegra_sor_parse_dt(struct tegra_sor *sor)
3639 {
3640         struct device_node *np = sor->dev->of_node;
3641         u32 xbar_cfg[5];
3642         unsigned int i;
3643         u32 value;
3644         int err;
3645
3646         if (sor->soc->has_nvdisplay) {
3647                 err = of_property_read_u32(np, "nvidia,interface", &value);
3648                 if (err < 0)
3649                         return err;
3650
3651                 sor->index = value;
3652
3653                 /*
3654                  * override the default that we already set for Tegra210 and
3655                  * earlier
3656                  */
3657                 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3658         } else {
3659                 if (!sor->soc->supports_audio)
3660                         sor->index = 0;
3661                 else
3662                         sor->index = 1;
3663         }
3664
3665         err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3666         if (err < 0) {
3667                 /* fall back to default per-SoC XBAR configuration */
3668                 for (i = 0; i < 5; i++)
3669                         sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3670         } else {
3671                 /* copy cells to SOR XBAR configuration */
3672                 for (i = 0; i < 5; i++)
3673                         sor->xbar_cfg[i] = xbar_cfg[i];
3674         }
3675
3676         return 0;
3677 }
3678
3679 static irqreturn_t tegra_sor_irq(int irq, void *data)
3680 {
3681         struct tegra_sor *sor = data;
3682         u32 value;
3683
3684         value = tegra_sor_readl(sor, SOR_INT_STATUS);
3685         tegra_sor_writel(sor, value, SOR_INT_STATUS);
3686
3687         if (value & SOR_INT_CODEC_SCRATCH0) {
3688                 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3689
3690                 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3691                         unsigned int format;
3692
3693                         format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3694
3695                         tegra_hda_parse_format(format, &sor->format);
3696
3697                         if (sor->ops->audio_enable)
3698                                 sor->ops->audio_enable(sor);
3699                 } else {
3700                         if (sor->ops->audio_disable)
3701                                 sor->ops->audio_disable(sor);
3702                 }
3703         }
3704
3705         return IRQ_HANDLED;
3706 }
3707
3708 static int tegra_sor_probe(struct platform_device *pdev)
3709 {
3710         struct device_node *np;
3711         struct tegra_sor *sor;
3712         int err;
3713
3714         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3715         if (!sor)
3716                 return -ENOMEM;
3717
3718         sor->soc = of_device_get_match_data(&pdev->dev);
3719         sor->output.dev = sor->dev = &pdev->dev;
3720
3721         sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3722                                      sor->soc->num_settings *
3723                                         sizeof(*sor->settings),
3724                                      GFP_KERNEL);
3725         if (!sor->settings)
3726                 return -ENOMEM;
3727
3728         sor->num_settings = sor->soc->num_settings;
3729
3730         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3731         if (np) {
3732                 sor->aux = drm_dp_aux_find_by_of_node(np);
3733                 of_node_put(np);
3734
3735                 if (!sor->aux)
3736                         return -EPROBE_DEFER;
3737
3738                 if (get_device(sor->aux->dev))
3739                         sor->output.ddc = &sor->aux->ddc;
3740         }
3741
3742         if (!sor->aux) {
3743                 if (sor->soc->supports_hdmi) {
3744                         sor->ops = &tegra_sor_hdmi_ops;
3745                         sor->pad = TEGRA_IO_PAD_HDMI;
3746                 } else if (sor->soc->supports_lvds) {
3747                         dev_err(&pdev->dev, "LVDS not supported yet\n");
3748                         return -ENODEV;
3749                 } else {
3750                         dev_err(&pdev->dev, "unknown (non-DP) support\n");
3751                         return -ENODEV;
3752                 }
3753         } else {
3754                 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3755                 /*
3756                  * No need to keep this around since we only use it as a check
3757                  * to see if a panel is connected (eDP) or not (DP).
3758                  */
3759                 of_node_put(np);
3760
3761                 sor->ops = &tegra_sor_dp_ops;
3762                 sor->pad = TEGRA_IO_PAD_LVDS;
3763         }
3764
3765         err = tegra_sor_parse_dt(sor);
3766         if (err < 0)
3767                 goto put_aux;
3768
3769         err = tegra_output_probe(&sor->output);
3770         if (err < 0) {
3771                 dev_err_probe(&pdev->dev, err, "failed to probe output\n");
3772                 goto put_aux;
3773         }
3774
3775         if (sor->ops && sor->ops->probe) {
3776                 err = sor->ops->probe(sor);
3777                 if (err < 0) {
3778                         dev_err(&pdev->dev, "failed to probe %s: %d\n",
3779                                 sor->ops->name, err);
3780                         goto remove;
3781                 }
3782         }
3783
3784         sor->regs = devm_platform_ioremap_resource(pdev, 0);
3785         if (IS_ERR(sor->regs)) {
3786                 err = PTR_ERR(sor->regs);
3787                 goto remove;
3788         }
3789
3790         err = platform_get_irq(pdev, 0);
3791         if (err < 0)
3792                 goto remove;
3793
3794         sor->irq = err;
3795
3796         err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3797                                dev_name(sor->dev), sor);
3798         if (err < 0) {
3799                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3800                 goto remove;
3801         }
3802
3803         sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3804         if (IS_ERR(sor->rst)) {
3805                 err = PTR_ERR(sor->rst);
3806
3807                 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3808                         dev_err(&pdev->dev, "failed to get reset control: %d\n",
3809                                 err);
3810                         goto remove;
3811                 }
3812
3813                 /*
3814                  * At this point, the reset control is most likely being used
3815                  * by the generic power domain implementation. With any luck
3816                  * the power domain will have taken care of resetting the SOR
3817                  * and we don't have to do anything.
3818                  */
3819                 sor->rst = NULL;
3820         }
3821
3822         sor->clk = devm_clk_get(&pdev->dev, NULL);
3823         if (IS_ERR(sor->clk)) {
3824                 err = PTR_ERR(sor->clk);
3825                 dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3826                 goto remove;
3827         }
3828
3829         if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3830                 struct device_node *np = pdev->dev.of_node;
3831                 const char *name;
3832
3833                 /*
3834                  * For backwards compatibility with Tegra210 device trees,
3835                  * fall back to the old clock name "source" if the new "out"
3836                  * clock is not available.
3837                  */
3838                 if (of_property_match_string(np, "clock-names", "out") < 0)
3839                         name = "source";
3840                 else
3841                         name = "out";
3842
3843                 sor->clk_out = devm_clk_get(&pdev->dev, name);
3844                 if (IS_ERR(sor->clk_out)) {
3845                         err = PTR_ERR(sor->clk_out);
3846                         dev_err(sor->dev, "failed to get %s clock: %d\n",
3847                                 name, err);
3848                         goto remove;
3849                 }
3850         } else {
3851                 /* fall back to the module clock on SOR0 (eDP/LVDS only) */
3852                 sor->clk_out = sor->clk;
3853         }
3854
3855         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3856         if (IS_ERR(sor->clk_parent)) {
3857                 err = PTR_ERR(sor->clk_parent);
3858                 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3859                 goto remove;
3860         }
3861
3862         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3863         if (IS_ERR(sor->clk_safe)) {
3864                 err = PTR_ERR(sor->clk_safe);
3865                 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3866                 goto remove;
3867         }
3868
3869         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3870         if (IS_ERR(sor->clk_dp)) {
3871                 err = PTR_ERR(sor->clk_dp);
3872                 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3873                 goto remove;
3874         }
3875
3876         /*
3877          * Starting with Tegra186, the BPMP provides an implementation for
3878          * the pad output clock, so we have to look it up from device tree.
3879          */
3880         sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3881         if (IS_ERR(sor->clk_pad)) {
3882                 if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3883                         err = PTR_ERR(sor->clk_pad);
3884                         goto remove;
3885                 }
3886
3887                 /*
3888                  * If the pad output clock is not available, then we assume
3889                  * we're on Tegra210 or earlier and have to provide our own
3890                  * implementation.
3891                  */
3892                 sor->clk_pad = NULL;
3893         }
3894
3895         /*
3896          * The bootloader may have set up the SOR such that it's module clock
3897          * is sourced by one of the display PLLs. However, that doesn't work
3898          * without properly having set up other bits of the SOR.
3899          */
3900         err = clk_set_parent(sor->clk_out, sor->clk_safe);
3901         if (err < 0) {
3902                 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3903                 goto remove;
3904         }
3905
3906         platform_set_drvdata(pdev, sor);
3907         pm_runtime_enable(&pdev->dev);
3908
3909         host1x_client_init(&sor->client);
3910         sor->client.ops = &sor_client_ops;
3911         sor->client.dev = &pdev->dev;
3912
3913         /*
3914          * On Tegra210 and earlier, provide our own implementation for the
3915          * pad output clock.
3916          */
3917         if (!sor->clk_pad) {
3918                 char *name;
3919
3920                 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3921                                       sor->index);
3922                 if (!name) {
3923                         err = -ENOMEM;
3924                         goto uninit;
3925                 }
3926
3927                 err = host1x_client_resume(&sor->client);
3928                 if (err < 0) {
3929                         dev_err(sor->dev, "failed to resume: %d\n", err);
3930                         goto uninit;
3931                 }
3932
3933                 sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3934                 host1x_client_suspend(&sor->client);
3935         }
3936
3937         if (IS_ERR(sor->clk_pad)) {
3938                 err = PTR_ERR(sor->clk_pad);
3939                 dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
3940                         err);
3941                 goto uninit;
3942         }
3943
3944         err = __host1x_client_register(&sor->client);
3945         if (err < 0) {
3946                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3947                         err);
3948                 goto uninit;
3949         }
3950
3951         return 0;
3952
3953 uninit:
3954         host1x_client_exit(&sor->client);
3955         pm_runtime_disable(&pdev->dev);
3956 remove:
3957         if (sor->aux)
3958                 sor->output.ddc = NULL;
3959
3960         tegra_output_remove(&sor->output);
3961 put_aux:
3962         if (sor->aux)
3963                 put_device(sor->aux->dev);
3964
3965         return err;
3966 }
3967
3968 static void tegra_sor_remove(struct platform_device *pdev)
3969 {
3970         struct tegra_sor *sor = platform_get_drvdata(pdev);
3971
3972         host1x_client_unregister(&sor->client);
3973
3974         pm_runtime_disable(&pdev->dev);
3975
3976         if (sor->aux) {
3977                 put_device(sor->aux->dev);
3978                 sor->output.ddc = NULL;
3979         }
3980
3981         tegra_output_remove(&sor->output);
3982 }
3983
3984 static int __maybe_unused tegra_sor_suspend(struct device *dev)
3985 {
3986         struct tegra_sor *sor = dev_get_drvdata(dev);
3987         int err;
3988
3989         err = tegra_output_suspend(&sor->output);
3990         if (err < 0) {
3991                 dev_err(dev, "failed to suspend output: %d\n", err);
3992                 return err;
3993         }
3994
3995         if (sor->hdmi_supply) {
3996                 err = regulator_disable(sor->hdmi_supply);
3997                 if (err < 0) {
3998                         tegra_output_resume(&sor->output);
3999                         return err;
4000                 }
4001         }
4002
4003         return 0;
4004 }
4005
4006 static int __maybe_unused tegra_sor_resume(struct device *dev)
4007 {
4008         struct tegra_sor *sor = dev_get_drvdata(dev);
4009         int err;
4010
4011         if (sor->hdmi_supply) {
4012                 err = regulator_enable(sor->hdmi_supply);
4013                 if (err < 0)
4014                         return err;
4015         }
4016
4017         err = tegra_output_resume(&sor->output);
4018         if (err < 0) {
4019                 dev_err(dev, "failed to resume output: %d\n", err);
4020
4021                 if (sor->hdmi_supply)
4022                         regulator_disable(sor->hdmi_supply);
4023
4024                 return err;
4025         }
4026
4027         return 0;
4028 }
4029
4030 static const struct dev_pm_ops tegra_sor_pm_ops = {
4031         SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4032 };
4033
4034 struct platform_driver tegra_sor_driver = {
4035         .driver = {
4036                 .name = "tegra-sor",
4037                 .of_match_table = tegra_sor_of_match,
4038                 .pm = &tegra_sor_pm_ops,
4039         },
4040         .probe = tegra_sor_probe,
4041         .remove_new = tegra_sor_remove,
4042 };