drivers/gpu/drm/i915/display/intel_psr_regs.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_PSR_REGS_H__
   7 #define __INTEL_PSR_REGS_H__
   8
   9 #include "intel_display_reg_defs.h"
  10 #include "intel_dp_aux_regs.h"
  11
  12 #define TRANS_EXITLINE(trans)   _MMIO_TRANS2((trans), _TRANS_EXITLINE_A)
  13 #define   EXITLINE_ENABLE       REG_BIT(31)
  14 #define   EXITLINE_MASK         REG_GENMASK(12, 0)
  15 #define   EXITLINE_SHIFT        0
  16
  17 /*
  18  * HSW+ eDP PSR registers
  19  *
  20  * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one
  21  * instance of it
  22  */
  23 #define HSW_SRD_CTL                             _MMIO(0x64800)
  24 #define _SRD_CTL_A                              0x60800
  25 #define _SRD_CTL_EDP                            0x6f800
  26 #define EDP_PSR_CTL(tran)                       _MMIO_TRANS2(tran, _SRD_CTL_A)
  27 #define   EDP_PSR_ENABLE                        REG_BIT(31)
  28 #define   BDW_PSR_SINGLE_FRAME                  REG_BIT(30)
  29 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK   REG_BIT(29) /* SW can't modify */
  30 #define   EDP_PSR_LINK_STANDBY                  REG_BIT(27)
  31 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK      REG_GENMASK(26, 25)
  32 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0)
  33 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES   REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1)
  34 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES   REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2)
  35 #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES   REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3)
  36 #define   EDP_PSR_MAX_SLEEP_TIME_MASK           REG_GENMASK(24, 20)
  37 #define   EDP_PSR_MAX_SLEEP_TIME(x)             REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x))
  38 #define   EDP_PSR_SKIP_AUX_EXIT                 REG_BIT(12)
  39 #define   EDP_PSR_TP_MASK                       REG_BIT(11)
  40 #define   EDP_PSR_TP_TP1_TP2                    REG_FIELD_PREP(EDP_PSR_TP_MASK, 0)
  41 #define   EDP_PSR_TP_TP1_TP3                    REG_FIELD_PREP(EDP_PSR_TP_MASK, 1)
  42 #define   EDP_PSR_CRC_ENABLE                    REG_BIT(10) /* BDW+ */
  43 #define   EDP_PSR_TP2_TP3_TIME_MASK             REG_GENMASK(9, 8)
  44 #define   EDP_PSR_TP2_TP3_TIME_500us            REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0)
  45 #define   EDP_PSR_TP2_TP3_TIME_100us            REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1)
  46 #define   EDP_PSR_TP2_TP3_TIME_2500us           REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2)
  47 #define   EDP_PSR_TP2_TP3_TIME_0us              REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3)
  48 #define   EDP_PSR_TP4_TIME_MASK                 REG_GENMASK(7, 6)
  49 #define   EDP_PSR_TP4_TIME_0us                  REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */
  50 #define   EDP_PSR_TP1_TIME_MASK                 REG_GENMASK(5, 4)
  51 #define   EDP_PSR_TP1_TIME_500us                REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0)
  52 #define   EDP_PSR_TP1_TIME_100us                REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1)
  53 #define   EDP_PSR_TP1_TIME_2500us               REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2)
  54 #define   EDP_PSR_TP1_TIME_0us                  REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3)
  55 #define   EDP_PSR_IDLE_FRAMES_MASK              REG_GENMASK(3, 0)
  56 #define   EDP_PSR_IDLE_FRAMES(x)                REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x))
  57
  58 /*
  59  * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative
  60  * to transcoder and bits defined for each one as if using no shift (i.e. as if
  61  * it was for TRANSCODER_EDP)
  62  */
  63 #define EDP_PSR_IMR                             _MMIO(0x64834)
  64 #define EDP_PSR_IIR                             _MMIO(0x64838)
  65 #define _PSR_IMR_A                              0x60814
  66 #define _PSR_IIR_A                              0x60818
  67 #define TRANS_PSR_IMR(tran)                     _MMIO_TRANS2(tran, _PSR_IMR_A)
  68 #define TRANS_PSR_IIR(tran)                     _MMIO_TRANS2(tran, _PSR_IIR_A)
  69 #define   _EDP_PSR_TRANS_SHIFT(trans)           ((trans) == TRANSCODER_EDP ? \
  70                                                  0 : ((trans) - TRANSCODER_A + 1) * 8)
  71 #define   TGL_PSR_MASK                  REG_GENMASK(2, 0)
  72 #define   TGL_PSR_ERROR                 REG_BIT(2)
  73 #define   TGL_PSR_POST_EXIT             REG_BIT(1)
  74 #define   TGL_PSR_PRE_ENTRY             REG_BIT(0)
  75 #define   EDP_PSR_MASK(trans)           (TGL_PSR_MASK <<                \
  76                                          _EDP_PSR_TRANS_SHIFT(trans))
  77 #define   EDP_PSR_ERROR(trans)          (TGL_PSR_ERROR <<               \
  78                                          _EDP_PSR_TRANS_SHIFT(trans))
  79 #define   EDP_PSR_POST_EXIT(trans)      (TGL_PSR_POST_EXIT <<           \
  80                                          _EDP_PSR_TRANS_SHIFT(trans))
  81 #define   EDP_PSR_PRE_ENTRY(trans)      (TGL_PSR_PRE_ENTRY <<           \
  82                                          _EDP_PSR_TRANS_SHIFT(trans))
  83
  84 #define HSW_SRD_AUX_CTL                         _MMIO(0x64810)
  85 #define _SRD_AUX_CTL_A                          0x60810
  86 #define _SRD_AUX_CTL_EDP                        0x6f810
  87 #define EDP_PSR_AUX_CTL(tran)                   _MMIO_TRANS2(tran, _SRD_AUX_CTL_A)
  88 #define   EDP_PSR_AUX_CTL_TIME_OUT_MASK         DP_AUX_CH_CTL_TIME_OUT_MASK
  89 #define   EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK     DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
  90 #define   EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK    DP_AUX_CH_CTL_PRECHARGE_2US_MASK
  91 #define   EDP_PSR_AUX_CTL_ERROR_INTERRUPT       REG_BIT(11)
  92 #define   EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK     DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK
  93
  94 #define HSW_SRD_AUX_DATA(i)                     _MMIO(0x64814 + (i) * 4) /* 5 registers */
  95 #define _SRD_AUX_DATA_A                         0x60814
  96 #define _SRD_AUX_DATA_EDP                       0x6f814
  97 #define EDP_PSR_AUX_DATA(tran, i)               _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
  98
  99 #define HSW_SRD_STATUS                          _MMIO(0x64840)
 100 #define _SRD_STATUS_A                           0x60840
 101 #define _SRD_STATUS_EDP                         0x6f840
 102 #define EDP_PSR_STATUS(tran)                    _MMIO_TRANS2(tran, _SRD_STATUS_A)
 103 #define   EDP_PSR_STATUS_STATE_MASK             REG_GENMASK(31, 29)
 104 #define   EDP_PSR_STATUS_STATE_IDLE             REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)
 105 #define   EDP_PSR_STATUS_STATE_SRDONACK         REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)
 106 #define   EDP_PSR_STATUS_STATE_SRDENT           REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2)
 107 #define   EDP_PSR_STATUS_STATE_BUFOFF           REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3)
 108 #define   EDP_PSR_STATUS_STATE_BUFON            REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4)
 109 #define   EDP_PSR_STATUS_STATE_AUXACK           REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5)
 110 #define   EDP_PSR_STATUS_STATE_SRDOFFACK        REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6)
 111 #define   EDP_PSR_STATUS_LINK_MASK              REG_GENMASK(27, 26)
 112 #define   EDP_PSR_STATUS_LINK_FULL_OFF          REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0)
 113 #define   EDP_PSR_STATUS_LINK_FULL_ON           REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1)
 114 #define   EDP_PSR_STATUS_LINK_STANDBY           REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2)
 115 #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK   REG_GENMASK(24, 20)
 116 #define   EDP_PSR_STATUS_COUNT_MASK             REG_GENMASK(19, 16)
 117 #define   EDP_PSR_STATUS_AUX_ERROR              REG_BIT(15)
 118 #define   EDP_PSR_STATUS_AUX_SENDING            REG_BIT(12)
 119 #define   EDP_PSR_STATUS_SENDING_IDLE           REG_BIT(9)
 120 #define   EDP_PSR_STATUS_SENDING_TP2_TP3        REG_BIT(8)
 121 #define   EDP_PSR_STATUS_SENDING_TP1            REG_BIT(4)
 122 #define   EDP_PSR_STATUS_IDLE_MASK              REG_GENMASK(3, 0)
 123
 124 #define HSW_SRD_PERF_CNT                _MMIO(0x64844)
 125 #define _SRD_PERF_CNT_A                 0x60844
 126 #define _SRD_PERF_CNT_EDP               0x6f844
 127 #define EDP_PSR_PERF_CNT(tran)          _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
 128 #define   EDP_PSR_PERF_CNT_MASK         REG_GENMASK(23, 0)
 129
 130 /* PSR_MASK on SKL+ */
 131 #define HSW_SRD_DEBUG                           _MMIO(0x64860)
 132 #define _SRD_DEBUG_A                            0x60860
 133 #define _SRD_DEBUG_EDP                          0x6f860
 134 #define EDP_PSR_DEBUG(tran)                     _MMIO_TRANS2(tran, _SRD_DEBUG_A)
 135 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP          REG_BIT(28)
 136 #define   EDP_PSR_DEBUG_MASK_LPSP               REG_BIT(27)
 137 #define   EDP_PSR_DEBUG_MASK_MEMUP              REG_BIT(26)
 138 #define   EDP_PSR_DEBUG_MASK_HPD                REG_BIT(25)
 139 #define   EDP_PSR_DEBUG_MASK_FBC_MODIFY         REG_BIT(24)
 140 #define   EDP_PSR_DEBUG_MASK_PRIMARY_FLIP       REG_BIT(23)  /* hsw */
 141 #define   EDP_PSR_DEBUG_MASK_HDCP_ENABLE        REG_BIT(22)  /* hsw/bdw */
 142 #define   EDP_PSR_DEBUG_MASK_SPRITE_ENABLE      REG_BIT(21)  /* hsw */
 143 #define   EDP_PSR_DEBUG_MASK_CURSOR_MOVE        REG_BIT(20)  /* hsw */
 144 #define   EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT   REG_BIT(19)  /* hsw */
 145 #define   EDP_PSR_DEBUG_MASK_DPST_PHASE_IN      REG_BIT(18)  /* hsw */
 146 #define   EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN    REG_BIT(17)
 147 #define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE     REG_BIT(16)  /* hsw-skl */
 148 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN  REG_BIT(15)  /* skl+ */
 149 #define   EDP_PSR_DEBUG_RFB_UPDATE_SENT         REG_BIT(2)  /* bdw */
 150 #define   EDP_PSR_DEBUG_ENTRY_COMPLETION        REG_BIT(1)  /* hsw/bdw */
 151
 152 #define _PSR2_CTL_A                             0x60900
 153 #define _PSR2_CTL_EDP                           0x6f900
 154 #define EDP_PSR2_CTL(tran)                      _MMIO_TRANS2(tran, _PSR2_CTL_A)
 155 #define   EDP_PSR2_ENABLE                       REG_BIT(31)
 156 #define   EDP_SU_TRACK_ENABLE                   REG_BIT(30) /* up to adl-p */
 157 #define   TGL_EDP_PSR2_BLOCK_COUNT_MASK         REG_BIT(28)
 158 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2        REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0)
 159 #define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3        REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1)
 160 #define   EDP_Y_COORDINATE_ENABLE               REG_BIT(25) /* display 10, 11 and 12 */
 161 #define   EDP_PSR2_SU_SDP_SCANLINE              REG_BIT(25) /* display 13+ */
 162 #define   EDP_MAX_SU_DISABLE_TIME_MASK          REG_GENMASK(24, 20)
 163 #define   EDP_MAX_SU_DISABLE_TIME(t)            REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t))
 164 #define   EDP_PSR2_IO_BUFFER_WAKE_MASK          REG_GENMASK(14, 13)
 165 #define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES     8
 166 #define   EDP_PSR2_IO_BUFFER_WAKE(lines)        REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \
 167                                                                EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines))
 168 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK      REG_GENMASK(15, 13)
 169 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5
 170 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)    REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
 171                                                                (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
 172 #define   EDP_PSR2_FAST_WAKE_MASK               REG_GENMASK(12, 11)
 173 #define   EDP_PSR2_FAST_WAKE_MAX_LINES          8
 174 #define   EDP_PSR2_FAST_WAKE(lines)             REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \
 175                                                                EDP_PSR2_FAST_WAKE_MAX_LINES - (lines))
 176 #define   TGL_EDP_PSR2_FAST_WAKE_MASK           REG_GENMASK(12, 10)
 177 #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES      5
 178 #define   TGL_EDP_PSR2_FAST_WAKE(lines)         REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \
 179                                                                (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES)
 180 #define   EDP_PSR2_TP2_TIME_MASK                REG_GENMASK(9, 8)
 181 #define   EDP_PSR2_TP2_TIME_500us               REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0)
 182 #define   EDP_PSR2_TP2_TIME_100us               REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1)
 183 #define   EDP_PSR2_TP2_TIME_2500us              REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2)
 184 #define   EDP_PSR2_TP2_TIME_50us                REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3)
 185 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK         REG_GENMASK(7, 4)
 186 #define   EDP_PSR2_FRAME_BEFORE_SU(a)           REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a))
 187 #define   EDP_PSR2_IDLE_FRAMES_MASK             REG_GENMASK(3, 0)
 188 #define   EDP_PSR2_IDLE_FRAMES(x)               REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x))
 189
 190 #define _PSR_EVENT_TRANS_A                      0x60848
 191 #define _PSR_EVENT_TRANS_B                      0x61848
 192 #define _PSR_EVENT_TRANS_C                      0x62848
 193 #define _PSR_EVENT_TRANS_D                      0x63848
 194 #define _PSR_EVENT_TRANS_EDP                    0x6f848
 195 #define PSR_EVENT(tran)                         _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A)
 196 #define  PSR_EVENT_PSR2_WD_TIMER_EXPIRE         REG_BIT(17)
 197 #define  PSR_EVENT_PSR2_DISABLED                REG_BIT(16)
 198 #define  PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN       REG_BIT(15)
 199 #define  PSR_EVENT_SU_CRC_FIFO_UNDERRUN         REG_BIT(14)
 200 #define  PSR_EVENT_GRAPHICS_RESET               REG_BIT(12)
 201 #define  PSR_EVENT_PCH_INTERRUPT                REG_BIT(11)
 202 #define  PSR_EVENT_MEMORY_UP                    REG_BIT(10)
 203 #define  PSR_EVENT_FRONT_BUFFER_MODIFY          REG_BIT(9)
 204 #define  PSR_EVENT_WD_TIMER_EXPIRE              REG_BIT(8)
 205 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE        REG_BIT(6)
 206 #define  PSR_EVENT_REGISTER_UPDATE              REG_BIT(5) /* Reserved in ICL+ */
 207 #define  PSR_EVENT_HDCP_ENABLE                  REG_BIT(4)
 208 #define  PSR_EVENT_KVMR_SESSION_ENABLE          REG_BIT(3)
 209 #define  PSR_EVENT_VBI_ENABLE                   REG_BIT(2)
 210 #define  PSR_EVENT_LPSP_MODE_EXIT               REG_BIT(1)
 211 #define  PSR_EVENT_PSR_DISABLE                  REG_BIT(0)
 212
 213 #define _PSR2_STATUS_A                          0x60940
 214 #define _PSR2_STATUS_EDP                        0x6f940
 215 #define EDP_PSR2_STATUS(tran)                   _MMIO_TRANS2(tran, _PSR2_STATUS_A)
 216 #define EDP_PSR2_STATUS_STATE_MASK              REG_GENMASK(31, 28)
 217 #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP        REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8)
 218
 219 #define _PSR2_SU_STATUS_A               0x60914
 220 #define _PSR2_SU_STATUS_EDP             0x6f914
 221 #define _PSR2_SU_STATUS(tran, index)    _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
 222 #define PSR2_SU_STATUS(tran, frame)     (_PSR2_SU_STATUS(tran, (frame) / 3))
 223 #define PSR2_SU_STATUS_SHIFT(frame)     (((frame) % 3) * 10)
 224 #define PSR2_SU_STATUS_MASK(frame)      (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
 225 #define PSR2_SU_STATUS_FRAMES           8
 226
 227 #define _PSR2_MAN_TRK_CTL_A                                     0x60910
 228 #define _PSR2_MAN_TRK_CTL_EDP                                   0x6f910
 229 #define PSR2_MAN_TRK_CTL(tran)                                  _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)
 230 #define  PSR2_MAN_TRK_CTL_ENABLE                                REG_BIT(31)
 231 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK             REG_GENMASK(30, 21)
 232 #define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)             REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 233 #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK               REG_GENMASK(20, 11)
 234 #define  PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)               REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
 235 #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME                  REG_BIT(3)
 236 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME               REG_BIT(2)
 237 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE               REG_BIT(1)
 238 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK        REG_GENMASK(28, 16)
 239 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)        REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 240 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK          REG_GENMASK(12, 0)
 241 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)          REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)
 242 #define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE          REG_BIT(31)
 243 #define  ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME             REG_BIT(14)
 244 #define  ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME          REG_BIT(13)
 245
 246 #define _SEL_FETCH_PLANE_BASE_1_A               0x70890
 247 #define _SEL_FETCH_PLANE_BASE_2_A               0x708B0
 248 #define _SEL_FETCH_PLANE_BASE_3_A               0x708D0
 249 #define _SEL_FETCH_PLANE_BASE_4_A               0x708F0
 250 #define _SEL_FETCH_PLANE_BASE_5_A               0x70920
 251 #define _SEL_FETCH_PLANE_BASE_6_A               0x70940
 252 #define _SEL_FETCH_PLANE_BASE_7_A               0x70960
 253 #define _SEL_FETCH_PLANE_BASE_CUR_A             0x70880
 254 #define _SEL_FETCH_PLANE_BASE_1_B               0x71890
 255
 256 #define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
 257                                              _SEL_FETCH_PLANE_BASE_1_A, \
 258                                              _SEL_FETCH_PLANE_BASE_2_A, \
 259                                              _SEL_FETCH_PLANE_BASE_3_A, \
 260                                              _SEL_FETCH_PLANE_BASE_4_A, \
 261                                              _SEL_FETCH_PLANE_BASE_5_A, \
 262                                              _SEL_FETCH_PLANE_BASE_6_A, \
 263                                              _SEL_FETCH_PLANE_BASE_7_A, \
 264                                              _SEL_FETCH_PLANE_BASE_CUR_A)
 265 #define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
 266 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
 267                                             _SEL_FETCH_PLANE_BASE_1_A + \
 268                                             _SEL_FETCH_PLANE_BASE_A(plane))
 269
 270 #define _SEL_FETCH_PLANE_CTL_1_A                0x70890
 271 #define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
 272                                                _SEL_FETCH_PLANE_CTL_1_A - \
 273                                                _SEL_FETCH_PLANE_BASE_1_A)
 274 #define PLANE_SEL_FETCH_CTL_ENABLE              REG_BIT(31)
 275
 276 #define _SEL_FETCH_PLANE_POS_1_A                0x70894
 277 #define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
 278                                                _SEL_FETCH_PLANE_POS_1_A - \
 279                                                _SEL_FETCH_PLANE_BASE_1_A)
 280
 281 #define _SEL_FETCH_PLANE_SIZE_1_A               0x70898
 282 #define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
 283                                                 _SEL_FETCH_PLANE_SIZE_1_A - \
 284                                                 _SEL_FETCH_PLANE_BASE_1_A)
 285
 286 #define _SEL_FETCH_PLANE_OFFSET_1_A             0x7089C
 287 #define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
 288                                                   _SEL_FETCH_PLANE_OFFSET_1_A - \
 289                                                   _SEL_FETCH_PLANE_BASE_1_A)
 290
 291 #endif /* __INTEL_PSR_REGS_H__ */