drivers/gpu/drm/i915/display/intel_dp_mst.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *             2014 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_probe_helper.h>
  30
  31 #include "i915_drv.h"
  32 #include "i915_reg.h"
  33 #include "intel_atomic.h"
  34 #include "intel_audio.h"
  35 #include "intel_connector.h"
  36 #include "intel_crtc.h"
  37 #include "intel_ddi.h"
  38 #include "intel_de.h"
  39 #include "intel_display_types.h"
  40 #include "intel_dp.h"
  41 #include "intel_dp_hdcp.h"
  42 #include "intel_dp_mst.h"
  43 #include "intel_dpio_phy.h"
  44 #include "intel_hdcp.h"
  45 #include "intel_hotplug.h"
  46 #include "skl_scaler.h"
  47
  48 static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
  49                                           const struct drm_display_mode *adjusted_mode,
  50                                           struct intel_crtc_state *crtc_state,
  51                                           bool dsc)
  52 {
  53         if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) <= 13 && dsc) {
  54                 int output_bpp = bpp;
  55                 /* DisplayPort 2 128b/132b, bits per lane is always 32 */
  56                 int symbol_clock = crtc_state->port_clock / 32;
  57
  58                 if (output_bpp * adjusted_mode->crtc_clock >=
  59                     symbol_clock * 72) {
  60                         drm_dbg_kms(&i915->drm, "UHBR check failed(required bw %d available %d)\n",
  61                                     output_bpp * adjusted_mode->crtc_clock, symbol_clock * 72);
  62                         return -EINVAL;
  63                 }
  64         }
  65
  66         return 0;
  67 }
  68
  69 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
  70                                                 struct intel_crtc_state *crtc_state,
  71                                                 int max_bpp,
  72                                                 int min_bpp,
  73                                                 struct link_config_limits *limits,
  74                                                 struct drm_connector_state *conn_state,
  75                                                 int step,
  76                                                 bool dsc)
  77 {
  78         struct drm_atomic_state *state = crtc_state->uapi.state;
  79         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
  80         struct intel_dp *intel_dp = &intel_mst->primary->dp;
  81         struct drm_dp_mst_topology_state *mst_state;
  82         struct intel_connector *connector =
  83                 to_intel_connector(conn_state->connector);
  84         struct drm_i915_private *i915 = to_i915(connector->base.dev);
  85         const struct drm_display_mode *adjusted_mode =
  86                 &crtc_state->hw.adjusted_mode;
  87         int bpp, slots = -EINVAL;
  88         int ret = 0;
  89
  90         mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
  91         if (IS_ERR(mst_state))
  92                 return PTR_ERR(mst_state);
  93
  94         crtc_state->lane_count = limits->max_lane_count;
  95         crtc_state->port_clock = limits->max_rate;
  96
  97         mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
  98                                                       crtc_state->port_clock,
  99                                                       crtc_state->lane_count);
 100
 101         for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
 102                 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
 103
 104                 ret = intel_dp_mst_check_constraints(i915, bpp, adjusted_mode, crtc_state, dsc);
 105                 if (ret)
 106                         continue;
 107
 108                 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
 109                                                        dsc ? bpp << 4 : bpp,
 110                                                        dsc);
 111
 112                 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
 113                                                       connector->port,
 114                                                       crtc_state->pbn);
 115                 if (slots == -EDEADLK)
 116                         return slots;
 117
 118                 if (slots >= 0) {
 119                         ret = drm_dp_mst_atomic_check(state);
 120                         /*
 121                          * If we got slots >= 0 and we can fit those based on check
 122                          * then we can exit the loop. Otherwise keep trying.
 123                          */
 124                         if (!ret)
 125                                 break;
 126                 }
 127         }
 128
 129         /* We failed to find a proper bpp/timeslots, return error */
 130         if (ret)
 131                 slots = ret;
 132
 133         if (slots < 0) {
 134                 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 135                             slots);
 136         } else {
 137                 if (!dsc)
 138                         crtc_state->pipe_bpp = bpp;
 139                 else
 140                         crtc_state->dsc.compressed_bpp = bpp;
 141                 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 142         }
 143
 144         return slots;
 145 }
 146
 147 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 148                                             struct intel_crtc_state *crtc_state,
 149                                             struct drm_connector_state *conn_state,
 150                                             struct link_config_limits *limits)
 151 {
 152         const struct drm_display_mode *adjusted_mode =
 153                 &crtc_state->hw.adjusted_mode;
 154         int slots = -EINVAL;
 155         int link_bpp;
 156
 157         /*
 158          * FIXME: allocate the BW according to link_bpp, which in the case of
 159          * YUV420 is only half of the pipe bpp value.
 160          */
 161         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 162                                                      to_bpp_int(limits->link.max_bpp_x16),
 163                                                      to_bpp_int(limits->link.min_bpp_x16),
 164                                                      limits,
 165                                                      conn_state, 2 * 3, false);
 166
 167         if (slots < 0)
 168                 return slots;
 169
 170         link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp);
 171
 172         intel_link_compute_m_n(link_bpp,
 173                                crtc_state->lane_count,
 174                                adjusted_mode->crtc_clock,
 175                                crtc_state->port_clock,
 176                                &crtc_state->dp_m_n,
 177                                crtc_state->fec_enable);
 178         crtc_state->dp_m_n.tu = slots;
 179
 180         return 0;
 181 }
 182
 183 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 184                                                 struct intel_crtc_state *crtc_state,
 185                                                 struct drm_connector_state *conn_state,
 186                                                 struct link_config_limits *limits)
 187 {
 188         struct intel_connector *connector =
 189                 to_intel_connector(conn_state->connector);
 190         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 191         const struct drm_display_mode *adjusted_mode =
 192                 &crtc_state->hw.adjusted_mode;
 193         int slots = -EINVAL;
 194         int i, num_bpc;
 195         u8 dsc_bpc[3] = {};
 196         int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 197         u8 dsc_max_bpc;
 198         bool need_timeslot_recalc = false;
 199         u32 last_compressed_bpp;
 200
 201         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 202         if (DISPLAY_VER(i915) >= 12)
 203                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
 204         else
 205                 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
 206
 207         max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
 208         min_bpp = limits->pipe.min_bpp;
 209
 210         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
 211                                                        dsc_bpc);
 212
 213         drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
 214                     min_bpp, max_bpp);
 215
 216         sink_max_bpp = dsc_bpc[0] * 3;
 217         sink_min_bpp = sink_max_bpp;
 218
 219         for (i = 1; i < num_bpc; i++) {
 220                 if (sink_min_bpp > dsc_bpc[i] * 3)
 221                         sink_min_bpp = dsc_bpc[i] * 3;
 222                 if (sink_max_bpp < dsc_bpc[i] * 3)
 223                         sink_max_bpp = dsc_bpc[i] * 3;
 224         }
 225
 226         drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
 227                     sink_min_bpp, sink_max_bpp);
 228
 229         if (min_bpp < sink_min_bpp)
 230                 min_bpp = sink_min_bpp;
 231
 232         if (max_bpp > sink_max_bpp)
 233                 max_bpp = sink_max_bpp;
 234
 235         min_bpp = max(min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
 236         max_bpp = min(max_bpp, to_bpp_int(limits->link.max_bpp_x16));
 237
 238         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
 239                                                      min_bpp, limits,
 240                                                      conn_state, 2 * 3, true);
 241
 242         if (slots < 0)
 243                 return slots;
 244
 245         last_compressed_bpp = crtc_state->dsc.compressed_bpp;
 246
 247         crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915,
 248                                                                         last_compressed_bpp,
 249                                                                         crtc_state->pipe_bpp);
 250
 251         if (crtc_state->dsc.compressed_bpp != last_compressed_bpp)
 252                 need_timeslot_recalc = true;
 253
 254         /*
 255          * Apparently some MST hubs dislike if vcpi slots are not matching precisely
 256          * the actual compressed bpp we use.
 257          */
 258         if (need_timeslot_recalc) {
 259                 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 260                                                              crtc_state->dsc.compressed_bpp,
 261                                                              crtc_state->dsc.compressed_bpp,
 262                                                              limits, conn_state, 2 * 3, true);
 263                 if (slots < 0)
 264                         return slots;
 265         }
 266
 267         intel_link_compute_m_n(crtc_state->dsc.compressed_bpp,
 268                                crtc_state->lane_count,
 269                                adjusted_mode->crtc_clock,
 270                                crtc_state->port_clock,
 271                                &crtc_state->dp_m_n,
 272                                crtc_state->fec_enable);
 273         crtc_state->dp_m_n.tu = slots;
 274
 275         return 0;
 276 }
 277 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 278                                      struct intel_crtc_state *crtc_state,
 279                                      struct drm_connector_state *conn_state)
 280 {
 281         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 282         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 283         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 284         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 285         struct drm_dp_mst_topology_state *topology_state;
 286         u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
 287                 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 288
 289         topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
 290         if (IS_ERR(topology_state)) {
 291                 drm_dbg_kms(&i915->drm, "slot update failed\n");
 292                 return PTR_ERR(topology_state);
 293         }
 294
 295         drm_dp_mst_update_slots(topology_state, link_coding_cap);
 296
 297         return 0;
 298 }
 299
 300 static bool
 301 intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
 302                                    struct intel_crtc_state *crtc_state,
 303                                    bool dsc,
 304                                    struct link_config_limits *limits)
 305 {
 306         /*
 307          * for MST we always configure max link bw - the spec doesn't
 308          * seem to suggest we should do otherwise.
 309          */
 310         limits->min_rate = limits->max_rate =
 311                 intel_dp_max_link_rate(intel_dp);
 312
 313         limits->min_lane_count = limits->max_lane_count =
 314                 intel_dp_max_lane_count(intel_dp);
 315
 316         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 317         /*
 318          * FIXME: If all the streams can't fit into the link with
 319          * their current pipe_bpp we should reduce pipe_bpp across
 320          * the board until things start to fit. Until then we
 321          * limit to <= 8bpc since that's what was hardcoded for all
 322          * MST streams previously. This hack should be removed once
 323          * we have the proper retry logic in place.
 324          */
 325         limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
 326
 327         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
 328
 329         return intel_dp_compute_config_link_bpp_limits(intel_dp,
 330                                                        crtc_state,
 331                                                        dsc,
 332                                                        limits);
 333 }
 334
 335 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 336                                        struct intel_crtc_state *pipe_config,
 337                                        struct drm_connector_state *conn_state)
 338 {
 339         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 340         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 341         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 342         const struct drm_display_mode *adjusted_mode =
 343                 &pipe_config->hw.adjusted_mode;
 344         struct link_config_limits limits;
 345         bool dsc_needed;
 346         int ret = 0;
 347
 348         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 349                 return -EINVAL;
 350
 351         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 352         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 353         pipe_config->has_pch_encoder = false;
 354
 355         dsc_needed = intel_dp->force_dsc_en ||
 356                      !intel_dp_mst_compute_config_limits(intel_dp,
 357                                                          pipe_config,
 358                                                          false,
 359                                                          &limits);
 360
 361         if (!dsc_needed) {
 362                 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
 363                                                        conn_state, &limits);
 364
 365                 if (ret == -EDEADLK)
 366                         return ret;
 367
 368                 if (ret)
 369                         dsc_needed = true;
 370         }
 371
 372         /* enable compression if the mode doesn't fit available BW */
 373         if (dsc_needed) {
 374                 drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
 375                             str_yes_no(ret),
 376                             str_yes_no(intel_dp->force_dsc_en));
 377
 378                 if (!intel_dp_mst_compute_config_limits(intel_dp,
 379                                                         pipe_config,
 380                                                         true,
 381                                                         &limits))
 382                         return -EINVAL;
 383
 384                 /*
 385                  * FIXME: As bpc is hardcoded to 8, as mentioned above,
 386                  * WARN and ignore the debug flag force_dsc_bpc for now.
 387                  */
 388                 drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
 389                 /*
 390                  * Try to get at least some timeslots and then see, if
 391                  * we can fit there with DSC.
 392                  */
 393                 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
 394
 395                 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
 396                                                            conn_state, &limits);
 397                 if (ret < 0)
 398                         return ret;
 399
 400                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
 401                                                   conn_state, &limits,
 402                                                   pipe_config->dp_m_n.tu, false);
 403         }
 404
 405         if (ret)
 406                 return ret;
 407
 408         ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
 409         if (ret)
 410                 return ret;
 411
 412         pipe_config->limited_color_range =
 413                 intel_dp_limited_color_range(pipe_config, conn_state);
 414
 415         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 416                 pipe_config->lane_lat_optim_mask =
 417                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 418
 419         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 420
 421         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 422
 423         return 0;
 424 }
 425
 426 /*
 427  * Iterate over all connectors and return a mask of
 428  * all CPU transcoders streaming over the same DP link.
 429  */
 430 static unsigned int
 431 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
 432                              struct intel_dp *mst_port)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 435         const struct intel_digital_connector_state *conn_state;
 436         struct intel_connector *connector;
 437         u8 transcoders = 0;
 438         int i;
 439
 440         if (DISPLAY_VER(dev_priv) < 12)
 441                 return 0;
 442
 443         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 444                 const struct intel_crtc_state *crtc_state;
 445                 struct intel_crtc *crtc;
 446
 447                 if (connector->mst_port != mst_port || !conn_state->base.crtc)
 448                         continue;
 449
 450                 crtc = to_intel_crtc(conn_state->base.crtc);
 451                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 452
 453                 if (!crtc_state->hw.active)
 454                         continue;
 455
 456                 transcoders |= BIT(crtc_state->cpu_transcoder);
 457         }
 458
 459         return transcoders;
 460 }
 461
 462 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
 463                                             struct intel_crtc_state *crtc_state,
 464                                             struct drm_connector_state *conn_state)
 465 {
 466         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 467         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 468         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 469
 470         /* lowest numbered transcoder will be designated master */
 471         crtc_state->mst_master_transcoder =
 472                 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
 473
 474         return 0;
 475 }
 476
 477 /*
 478  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
 479  * that shares the same MST stream as mode changed,
 480  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
 481  * a fastset when possible.
 482  */
 483 static int
 484 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
 485                                        struct intel_atomic_state *state)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 488         struct drm_connector_list_iter connector_list_iter;
 489         struct intel_connector *connector_iter;
 490         int ret = 0;
 491
 492         if (DISPLAY_VER(dev_priv) < 12)
 493                 return  0;
 494
 495         if (!intel_connector_needs_modeset(state, &connector->base))
 496                 return 0;
 497
 498         drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
 499         for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
 500                 struct intel_digital_connector_state *conn_iter_state;
 501                 struct intel_crtc_state *crtc_state;
 502                 struct intel_crtc *crtc;
 503
 504                 if (connector_iter->mst_port != connector->mst_port ||
 505                     connector_iter == connector)
 506                         continue;
 507
 508                 conn_iter_state = intel_atomic_get_digital_connector_state(state,
 509                                                                            connector_iter);
 510                 if (IS_ERR(conn_iter_state)) {
 511                         ret = PTR_ERR(conn_iter_state);
 512                         break;
 513                 }
 514
 515                 if (!conn_iter_state->base.crtc)
 516                         continue;
 517
 518                 crtc = to_intel_crtc(conn_iter_state->base.crtc);
 519                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 520                 if (IS_ERR(crtc_state)) {
 521                         ret = PTR_ERR(crtc_state);
 522                         break;
 523                 }
 524
 525                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 526                 if (ret)
 527                         break;
 528                 crtc_state->uapi.mode_changed = true;
 529         }
 530         drm_connector_list_iter_end(&connector_list_iter);
 531
 532         return ret;
 533 }
 534
 535 static int
 536 intel_dp_mst_atomic_check(struct drm_connector *connector,
 537                           struct drm_atomic_state *_state)
 538 {
 539         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 540         struct intel_connector *intel_connector =
 541                 to_intel_connector(connector);
 542         int ret;
 543
 544         ret = intel_digital_connector_atomic_check(connector, &state->base);
 545         if (ret)
 546                 return ret;
 547
 548         ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state);
 549         if (ret)
 550                 return ret;
 551
 552         return drm_dp_atomic_release_time_slots(&state->base,
 553                                                 &intel_connector->mst_port->mst_mgr,
 554                                                 intel_connector->port);
 555 }
 556
 557 static void clear_act_sent(struct intel_encoder *encoder,
 558                            const struct intel_crtc_state *crtc_state)
 559 {
 560         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 561
 562         intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 563                        DP_TP_STATUS_ACT_SENT);
 564 }
 565
 566 static void wait_for_act_sent(struct intel_encoder *encoder,
 567                               const struct intel_crtc_state *crtc_state)
 568 {
 569         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 570         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 571         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 572
 573         if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 574                                   DP_TP_STATUS_ACT_SENT, 1))
 575                 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 576
 577         drm_dp_check_act_status(&intel_dp->mst_mgr);
 578 }
 579
 580 static void intel_mst_disable_dp(struct intel_atomic_state *state,
 581                                  struct intel_encoder *encoder,
 582                                  const struct intel_crtc_state *old_crtc_state,
 583                                  const struct drm_connector_state *old_conn_state)
 584 {
 585         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 586         struct intel_digital_port *dig_port = intel_mst->primary;
 587         struct intel_dp *intel_dp = &dig_port->dp;
 588         struct intel_connector *connector =
 589                 to_intel_connector(old_conn_state->connector);
 590         struct drm_dp_mst_topology_state *new_mst_state =
 591                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 592         struct drm_dp_mst_atomic_payload *new_payload =
 593                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
 594         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 595
 596         drm_dbg_kms(&i915->drm, "active links %d\n",
 597                     intel_dp->active_mst_links);
 598
 599         intel_hdcp_disable(intel_mst->connector);
 600
 601         drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);
 602
 603         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
 604 }
 605
 606 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 607                                       struct intel_encoder *encoder,
 608                                       const struct intel_crtc_state *old_crtc_state,
 609                                       const struct drm_connector_state *old_conn_state)
 610 {
 611         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 612         struct intel_digital_port *dig_port = intel_mst->primary;
 613         struct intel_dp *intel_dp = &dig_port->dp;
 614         struct intel_connector *connector =
 615                 to_intel_connector(old_conn_state->connector);
 616         struct drm_dp_mst_topology_state *old_mst_state =
 617                 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 618         struct drm_dp_mst_topology_state *new_mst_state =
 619                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 620         const struct drm_dp_mst_atomic_payload *old_payload =
 621                 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
 622         struct drm_dp_mst_atomic_payload *new_payload =
 623                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
 624         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 625         bool last_mst_stream;
 626
 627         intel_dp->active_mst_links--;
 628         last_mst_stream = intel_dp->active_mst_links == 0;
 629         drm_WARN_ON(&dev_priv->drm,
 630                     DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
 631                     !intel_dp_mst_is_master_trans(old_crtc_state));
 632
 633         intel_crtc_vblank_off(old_crtc_state);
 634
 635         intel_disable_transcoder(old_crtc_state);
 636
 637         clear_act_sent(encoder, old_crtc_state);
 638
 639         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
 640                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
 641
 642         wait_for_act_sent(encoder, old_crtc_state);
 643
 644         drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,
 645                                     old_payload, new_payload);
 646
 647         intel_ddi_disable_transcoder_func(old_crtc_state);
 648
 649         if (DISPLAY_VER(dev_priv) >= 9)
 650                 skl_scaler_disable(old_crtc_state);
 651         else
 652                 ilk_pfit_disable(old_crtc_state);
 653
 654         /*
 655          * Power down mst path before disabling the port, otherwise we end
 656          * up getting interrupts from the sink upon detecting link loss.
 657          */
 658         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
 659                                      false);
 660
 661         /*
 662          * BSpec 4287: disable DIP after the transcoder is disabled and before
 663          * the transcoder clock select is set to none.
 664          */
 665         if (last_mst_stream)
 666                 intel_dp_set_infoframes(&dig_port->base, false,
 667                                         old_crtc_state, NULL);
 668         /*
 669          * From TGL spec: "If multi-stream slave transcoder: Configure
 670          * Transcoder Clock Select to direct no clock to the transcoder"
 671          *
 672          * From older GENs spec: "Configure Transcoder Clock Select to direct
 673          * no clock to the transcoder"
 674          */
 675         if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
 676                 intel_ddi_disable_transcoder_clock(old_crtc_state);
 677
 678
 679         intel_mst->connector = NULL;
 680         if (last_mst_stream)
 681                 dig_port->base.post_disable(state, &dig_port->base,
 682                                                   old_crtc_state, NULL);
 683
 684         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 685                     intel_dp->active_mst_links);
 686 }
 687
 688 static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
 689                                           struct intel_encoder *encoder,
 690                                           const struct intel_crtc_state *old_crtc_state,
 691                                           const struct drm_connector_state *old_conn_state)
 692 {
 693         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 694         struct intel_digital_port *dig_port = intel_mst->primary;
 695         struct intel_dp *intel_dp = &dig_port->dp;
 696
 697         if (intel_dp->active_mst_links == 0 &&
 698             dig_port->base.post_pll_disable)
 699                 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
 700 }
 701
 702 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
 703                                         struct intel_encoder *encoder,
 704                                         const struct intel_crtc_state *pipe_config,
 705                                         const struct drm_connector_state *conn_state)
 706 {
 707         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 708         struct intel_digital_port *dig_port = intel_mst->primary;
 709         struct intel_dp *intel_dp = &dig_port->dp;
 710
 711         if (intel_dp->active_mst_links == 0)
 712                 dig_port->base.pre_pll_enable(state, &dig_port->base,
 713                                                     pipe_config, NULL);
 714         else
 715                 /*
 716                  * The port PLL state needs to get updated for secondary
 717                  * streams as for the primary stream.
 718                  */
 719                 intel_ddi_update_active_dpll(state, &dig_port->base,
 720                                              to_intel_crtc(pipe_config->uapi.crtc));
 721 }
 722
 723 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
 724                                     struct intel_encoder *encoder,
 725                                     const struct intel_crtc_state *pipe_config,
 726                                     const struct drm_connector_state *conn_state)
 727 {
 728         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 729         struct intel_digital_port *dig_port = intel_mst->primary;
 730         struct intel_dp *intel_dp = &dig_port->dp;
 731         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 732         struct intel_connector *connector =
 733                 to_intel_connector(conn_state->connector);
 734         struct drm_dp_mst_topology_state *mst_state =
 735                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 736         int ret;
 737         bool first_mst_stream;
 738
 739         /* MST encoders are bound to a crtc, not to a connector,
 740          * force the mapping here for get_hw_state.
 741          */
 742         connector->encoder = encoder;
 743         intel_mst->connector = connector;
 744         first_mst_stream = intel_dp->active_mst_links == 0;
 745         drm_WARN_ON(&dev_priv->drm,
 746                     DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
 747                     !intel_dp_mst_is_master_trans(pipe_config));
 748
 749         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 750                     intel_dp->active_mst_links);
 751
 752         if (first_mst_stream)
 753                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
 754
 755         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 756
 757         if (first_mst_stream)
 758                 dig_port->base.pre_enable(state, &dig_port->base,
 759                                                 pipe_config, NULL);
 760
 761         intel_dp->active_mst_links++;
 762
 763         ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
 764                                        drm_atomic_get_mst_payload_state(mst_state, connector->port));
 765         if (ret < 0)
 766                 drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
 767                             connector->base.name, ret);
 768
 769         /*
 770          * Before Gen 12 this is not done as part of
 771          * dig_port->base.pre_enable() and should be done here. For
 772          * Gen 12+ the step in which this should be done is different for the
 773          * first MST stream, so it's done on the DDI for the first stream and
 774          * here for the following ones.
 775          */
 776         if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
 777                 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
 778
 779         intel_ddi_set_dp_msa(pipe_config, conn_state);
 780 }
 781
 782 static void intel_mst_enable_dp(struct intel_atomic_state *state,
 783                                 struct intel_encoder *encoder,
 784                                 const struct intel_crtc_state *pipe_config,
 785                                 const struct drm_connector_state *conn_state)
 786 {
 787         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 788         struct intel_digital_port *dig_port = intel_mst->primary;
 789         struct intel_dp *intel_dp = &dig_port->dp;
 790         struct intel_connector *connector = to_intel_connector(conn_state->connector);
 791         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 792         struct drm_dp_mst_topology_state *mst_state =
 793                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 794         enum transcoder trans = pipe_config->cpu_transcoder;
 795
 796         drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
 797
 798         clear_act_sent(encoder, pipe_config);
 799
 800         if (intel_dp_is_uhbr(pipe_config)) {
 801                 const struct drm_display_mode *adjusted_mode =
 802                         &pipe_config->hw.adjusted_mode;
 803                 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
 804
 805                 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
 806                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
 807                 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
 808                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
 809         }
 810
 811         intel_ddi_enable_transcoder_func(encoder, pipe_config);
 812
 813         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
 814                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 815
 816         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
 817                     intel_dp->active_mst_links);
 818
 819         wait_for_act_sent(encoder, pipe_config);
 820
 821         drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
 822                                  drm_atomic_get_mst_payload_state(mst_state, connector->port));
 823
 824         if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
 825                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
 826                              FECSTALL_DIS_DPTSTREAM_DPTTG);
 827         else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
 828                 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
 829                              FECSTALL_DIS_DPTSTREAM_DPTTG);
 830
 831         intel_audio_sdp_split_update(pipe_config);
 832
 833         intel_enable_transcoder(pipe_config);
 834
 835         intel_crtc_vblank_on(pipe_config);
 836
 837         intel_audio_codec_enable(encoder, pipe_config, conn_state);
 838
 839         /* Enable hdcp if it's desired */
 840         if (conn_state->content_protection ==
 841             DRM_MODE_CONTENT_PROTECTION_DESIRED)
 842                 intel_hdcp_enable(state, encoder, pipe_config, conn_state);
 843 }
 844
 845 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
 846                                       enum pipe *pipe)
 847 {
 848         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 849         *pipe = intel_mst->pipe;
 850         if (intel_mst->connector)
 851                 return true;
 852         return false;
 853 }
 854
 855 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
 856                                         struct intel_crtc_state *pipe_config)
 857 {
 858         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 859         struct intel_digital_port *dig_port = intel_mst->primary;
 860
 861         dig_port->base.get_config(&dig_port->base, pipe_config);
 862 }
 863
 864 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
 865                                                struct intel_crtc_state *crtc_state)
 866 {
 867         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 868         struct intel_digital_port *dig_port = intel_mst->primary;
 869
 870         return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
 871 }
 872
 873 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
 874 {
 875         struct intel_connector *intel_connector = to_intel_connector(connector);
 876         struct intel_dp *intel_dp = intel_connector->mst_port;
 877         const struct drm_edid *drm_edid;
 878         int ret;
 879
 880         if (drm_connector_is_unregistered(connector))
 881                 return intel_connector_update_modes(connector, NULL);
 882
 883         drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
 884
 885         ret = intel_connector_update_modes(connector, drm_edid);
 886
 887         drm_edid_free(drm_edid);
 888
 889         return ret;
 890 }
 891
 892 static int
 893 intel_dp_mst_connector_late_register(struct drm_connector *connector)
 894 {
 895         struct intel_connector *intel_connector = to_intel_connector(connector);
 896         int ret;
 897
 898         ret = drm_dp_mst_connector_late_register(connector,
 899                                                  intel_connector->port);
 900         if (ret < 0)
 901                 return ret;
 902
 903         ret = intel_connector_register(connector);
 904         if (ret < 0)
 905                 drm_dp_mst_connector_early_unregister(connector,
 906                                                       intel_connector->port);
 907
 908         return ret;
 909 }
 910
 911 static void
 912 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
 913 {
 914         struct intel_connector *intel_connector = to_intel_connector(connector);
 915
 916         intel_connector_unregister(connector);
 917         drm_dp_mst_connector_early_unregister(connector,
 918                                               intel_connector->port);
 919 }
 920
 921 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
 922         .fill_modes = drm_helper_probe_single_connector_modes,
 923         .atomic_get_property = intel_digital_connector_atomic_get_property,
 924         .atomic_set_property = intel_digital_connector_atomic_set_property,
 925         .late_register = intel_dp_mst_connector_late_register,
 926         .early_unregister = intel_dp_mst_connector_early_unregister,
 927         .destroy = intel_connector_destroy,
 928         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 929         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 930 };
 931
 932 static int intel_dp_mst_get_modes(struct drm_connector *connector)
 933 {
 934         return intel_dp_mst_get_ddc_modes(connector);
 935 }
 936
 937 static int
 938 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
 939                             struct drm_display_mode *mode,
 940                             struct drm_modeset_acquire_ctx *ctx,
 941                             enum drm_mode_status *status)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 944         struct intel_connector *intel_connector = to_intel_connector(connector);
 945         struct intel_dp *intel_dp = intel_connector->mst_port;
 946         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 947         struct drm_dp_mst_port *port = intel_connector->port;
 948         const int min_bpp = 18;
 949         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 950         int max_rate, mode_rate, max_lanes, max_link_clock;
 951         int ret;
 952         bool dsc = false, bigjoiner = false;
 953         u16 dsc_max_compressed_bpp = 0;
 954         u8 dsc_slice_count = 0;
 955         int target_clock = mode->clock;
 956
 957         if (drm_connector_is_unregistered(connector)) {
 958                 *status = MODE_ERROR;
 959                 return 0;
 960         }
 961
 962         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 963                 *status = MODE_NO_DBLESCAN;
 964                 return 0;
 965         }
 966
 967         max_link_clock = intel_dp_max_link_rate(intel_dp);
 968         max_lanes = intel_dp_max_lane_count(intel_dp);
 969
 970         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 971         mode_rate = intel_dp_link_required(mode->clock, min_bpp);
 972
 973         ret = drm_modeset_lock(&mgr->base.lock, ctx);
 974         if (ret)
 975                 return ret;
 976
 977         if (mode_rate > max_rate || mode->clock > max_dotclk ||
 978             drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
 979                 *status = MODE_CLOCK_HIGH;
 980                 return 0;
 981         }
 982
 983         if (mode->clock < 10000) {
 984                 *status = MODE_CLOCK_LOW;
 985                 return 0;
 986         }
 987
 988         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 989                 *status = MODE_H_ILLEGAL;
 990                 return 0;
 991         }
 992
 993         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
 994                 bigjoiner = true;
 995                 max_dotclk *= 2;
 996         }
 997
 998         if (DISPLAY_VER(dev_priv) >= 10 &&
 999             drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
1000                 /*
1001                  * TBD pass the connector BPC,
1002                  * for now U8_MAX so that max BPC on that platform would be picked
1003                  */
1004                 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);
1005
1006                 if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1007                         dsc_max_compressed_bpp =
1008                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1009                                                                     max_link_clock,
1010                                                                     max_lanes,
1011                                                                     target_clock,
1012                                                                     mode->hdisplay,
1013                                                                     bigjoiner,
1014                                                                     INTEL_OUTPUT_FORMAT_RGB,
1015                                                                     pipe_bpp, 64);
1016                         dsc_slice_count =
1017                                 intel_dp_dsc_get_slice_count(intel_connector,
1018                                                              target_clock,
1019                                                              mode->hdisplay,
1020                                                              bigjoiner);
1021                 }
1022
1023                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1024         }
1025
1026         /*
1027          * Big joiner configuration needs DSC for TGL which is not true for
1028          * XE_LPD where uncompressed joiner is supported.
1029          */
1030         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1031                 return MODE_CLOCK_HIGH;
1032
1033         if (mode_rate > max_rate && !dsc)
1034                 return MODE_CLOCK_HIGH;
1035
1036         *status = intel_mode_valid_max_plane_size(dev_priv, mode, false);
1037         return 0;
1038 }
1039
1040 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1041                                                          struct drm_atomic_state *state)
1042 {
1043         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1044                                                                                          connector);
1045         struct intel_connector *intel_connector = to_intel_connector(connector);
1046         struct intel_dp *intel_dp = intel_connector->mst_port;
1047         struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1048
1049         return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1050 }
1051
1052 static int
1053 intel_dp_mst_detect(struct drm_connector *connector,
1054                     struct drm_modeset_acquire_ctx *ctx, bool force)
1055 {
1056         struct drm_i915_private *i915 = to_i915(connector->dev);
1057         struct intel_connector *intel_connector = to_intel_connector(connector);
1058         struct intel_dp *intel_dp = intel_connector->mst_port;
1059
1060         if (!intel_display_device_enabled(i915))
1061                 return connector_status_disconnected;
1062
1063         if (drm_connector_is_unregistered(connector))
1064                 return connector_status_disconnected;
1065
1066         return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1067                                       intel_connector->port);
1068 }
1069
1070 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1071         .get_modes = intel_dp_mst_get_modes,
1072         .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1073         .atomic_best_encoder = intel_mst_atomic_best_encoder,
1074         .atomic_check = intel_dp_mst_atomic_check,
1075         .detect_ctx = intel_dp_mst_detect,
1076 };
1077
1078 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1079 {
1080         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1081
1082         drm_encoder_cleanup(encoder);
1083         kfree(intel_mst);
1084 }
1085
1086 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1087         .destroy = intel_dp_mst_encoder_destroy,
1088 };
1089
1090 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1091 {
1092         if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1093                 enum pipe pipe;
1094                 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1095                         return false;
1096                 return true;
1097         }
1098         return false;
1099 }
1100
1101 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1102                                        struct drm_connector *connector,
1103                                        const char *pathprop)
1104 {
1105         struct drm_i915_private *i915 = to_i915(connector->dev);
1106
1107         drm_object_attach_property(&connector->base,
1108                                    i915->drm.mode_config.path_property, 0);
1109         drm_object_attach_property(&connector->base,
1110                                    i915->drm.mode_config.tile_property, 0);
1111
1112         intel_attach_force_audio_property(connector);
1113         intel_attach_broadcast_rgb_property(connector);
1114
1115         /*
1116          * Reuse the prop from the SST connector because we're
1117          * not allowed to create new props after device registration.
1118          */
1119         connector->max_bpc_property =
1120                 intel_dp->attached_connector->base.max_bpc_property;
1121         if (connector->max_bpc_property)
1122                 drm_connector_attach_max_bpc_property(connector, 6, 12);
1123
1124         return drm_connector_set_path_property(connector, pathprop);
1125 }
1126
1127 static void
1128 intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
1129                                               struct intel_connector *connector)
1130 {
1131         u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
1132
1133         if (!connector->dp.dsc_decompression_aux)
1134                 return;
1135
1136         if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
1137                 return;
1138
1139         intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
1140 }
1141
1142 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1143                                                         struct drm_dp_mst_port *port,
1144                                                         const char *pathprop)
1145 {
1146         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1147         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1148         struct drm_device *dev = dig_port->base.base.dev;
1149         struct drm_i915_private *dev_priv = to_i915(dev);
1150         struct intel_connector *intel_connector;
1151         struct drm_connector *connector;
1152         enum pipe pipe;
1153         int ret;
1154
1155         intel_connector = intel_connector_alloc();
1156         if (!intel_connector)
1157                 return NULL;
1158
1159         intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1160         intel_connector->mst_port = intel_dp;
1161         intel_connector->port = port;
1162         drm_dp_mst_get_port_malloc(port);
1163
1164         connector = &intel_connector->base;
1165         ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1166                                  DRM_MODE_CONNECTOR_DisplayPort);
1167         if (ret) {
1168                 drm_dp_mst_put_port_malloc(port);
1169                 intel_connector_free(intel_connector);
1170                 return NULL;
1171         }
1172
1173         drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1174
1175         /*
1176          * TODO: set the AUX for the actual MST port decompressing the stream.
1177          * At the moment the driver only supports enabling this globally in the
1178          * first downstream MST branch, via intel_dp's (root port) AUX.
1179          */
1180         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
1181         intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
1182
1183         for_each_pipe(dev_priv, pipe) {
1184                 struct drm_encoder *enc =
1185                         &intel_dp->mst_encoders[pipe]->base.base;
1186
1187                 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1188                 if (ret)
1189                         goto err;
1190         }
1191
1192         ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1193         if (ret)
1194                 goto err;
1195
1196         ret = intel_dp_hdcp_init(dig_port, intel_connector);
1197         if (ret)
1198                 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1199                             connector->name, connector->base.id);
1200
1201         return connector;
1202
1203 err:
1204         drm_connector_cleanup(connector);
1205         return NULL;
1206 }
1207
1208 static void
1209 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1210 {
1211         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1212
1213         intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1214 }
1215
1216 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1217         .add_connector = intel_dp_add_mst_connector,
1218         .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1219 };
1220
1221 static struct intel_dp_mst_encoder *
1222 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1223 {
1224         struct intel_dp_mst_encoder *intel_mst;
1225         struct intel_encoder *intel_encoder;
1226         struct drm_device *dev = dig_port->base.base.dev;
1227
1228         intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1229
1230         if (!intel_mst)
1231                 return NULL;
1232
1233         intel_mst->pipe = pipe;
1234         intel_encoder = &intel_mst->base;
1235         intel_mst->primary = dig_port;
1236
1237         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1238                          DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1239
1240         intel_encoder->type = INTEL_OUTPUT_DP_MST;
1241         intel_encoder->power_domain = dig_port->base.power_domain;
1242         intel_encoder->port = dig_port->base.port;
1243         intel_encoder->cloneable = 0;
1244         /*
1245          * This is wrong, but broken userspace uses the intersection
1246          * of possible_crtcs of all the encoders of a given connector
1247          * to figure out which crtcs can drive said connector. What
1248          * should be used instead is the union of possible_crtcs.
1249          * To keep such userspace functioning we must misconfigure
1250          * this to make sure the intersection is not empty :(
1251          */
1252         intel_encoder->pipe_mask = ~0;
1253
1254         intel_encoder->compute_config = intel_dp_mst_compute_config;
1255         intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1256         intel_encoder->disable = intel_mst_disable_dp;
1257         intel_encoder->post_disable = intel_mst_post_disable_dp;
1258         intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1259         intel_encoder->update_pipe = intel_ddi_update_pipe;
1260         intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1261         intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1262         intel_encoder->enable = intel_mst_enable_dp;
1263         intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1264         intel_encoder->get_config = intel_dp_mst_enc_get_config;
1265         intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1266
1267         return intel_mst;
1268
1269 }
1270
1271 static bool
1272 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1273 {
1274         struct intel_dp *intel_dp = &dig_port->dp;
1275         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1276         enum pipe pipe;
1277
1278         for_each_pipe(dev_priv, pipe)
1279                 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1280         return true;
1281 }
1282
1283 int
1284 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1285 {
1286         return dig_port->dp.active_mst_links;
1287 }
1288
1289 int
1290 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1291 {
1292         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1293         struct intel_dp *intel_dp = &dig_port->dp;
1294         enum port port = dig_port->base.port;
1295         int ret;
1296
1297         if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1298                 return 0;
1299
1300         if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1301                 return 0;
1302
1303         if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1304                 return 0;
1305
1306         intel_dp->mst_mgr.cbs = &mst_cbs;
1307
1308         /* create encoders */
1309         intel_dp_create_fake_mst_encoders(dig_port);
1310         ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1311                                            &intel_dp->aux, 16, 3, conn_base_id);
1312         if (ret) {
1313                 intel_dp->mst_mgr.cbs = NULL;
1314                 return ret;
1315         }
1316
1317         return 0;
1318 }
1319
1320 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1321 {
1322         return intel_dp->mst_mgr.cbs;
1323 }
1324
1325 void
1326 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1327 {
1328         struct intel_dp *intel_dp = &dig_port->dp;
1329
1330         if (!intel_dp_mst_source_support(intel_dp))
1331                 return;
1332
1333         drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1334         /* encoders will get killed by normal cleanup */
1335
1336         intel_dp->mst_mgr.cbs = NULL;
1337 }
1338
1339 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1340 {
1341         return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1342 }
1343
1344 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1345 {
1346         return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1347                crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1348 }
1349
1350 /**
1351  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1352  * @state: atomic state
1353  * @connector: connector to add the state for
1354  * @crtc: the CRTC @connector is attached to
1355  *
1356  * Add the MST topology state for @connector to @state.
1357  *
1358  * Returns 0 on success, negative error code on failure.
1359  */
1360 static int
1361 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1362                                               struct intel_connector *connector,
1363                                               struct intel_crtc *crtc)
1364 {
1365         struct drm_dp_mst_topology_state *mst_state;
1366
1367         if (!connector->mst_port)
1368                 return 0;
1369
1370         mst_state = drm_atomic_get_mst_topology_state(&state->base,
1371                                                       &connector->mst_port->mst_mgr);
1372         if (IS_ERR(mst_state))
1373                 return PTR_ERR(mst_state);
1374
1375         mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1376
1377         return 0;
1378 }
1379
1380 /**
1381  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1382  * @state: atomic state
1383  * @crtc: CRTC to add the state for
1384  *
1385  * Add the MST topology state for @crtc to @state.
1386  *
1387  * Returns 0 on success, negative error code on failure.
1388  */
1389 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1390                                              struct intel_crtc *crtc)
1391 {
1392         struct drm_connector *_connector;
1393         struct drm_connector_state *conn_state;
1394         int i;
1395
1396         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1397                 struct intel_connector *connector = to_intel_connector(_connector);
1398                 int ret;
1399
1400                 if (conn_state->crtc != &crtc->base)
1401                         continue;
1402
1403                 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1404                 if (ret)
1405                         return ret;
1406         }
1407
1408         return 0;
1409 }