drivers/gpu/drm/i915/display/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "i915_drv.h"
  25 #include "intel_display_types.h"
  26 #include "intel_dp.h"
  27 #include "intel_dp_link_training.h"
  28
  29 #define LT_MSG_PREFIX                   "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
  30 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \
  31                                         (_intel_dp)->attached_connector->base.name, \
  32                                         dp_to_dig_port(_intel_dp)->base.base.base.id, \
  33                                         dp_to_dig_port(_intel_dp)->base.base.name, \
  34                                         drm_dp_phy_name(_dp_phy)
  35
  36 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \
  37         drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \
  38                     LT_MSG_PREFIX _format, \
  39                     LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__)
  40
  41 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
  42         if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
  43                 drm_err(&dp_to_i915(_intel_dp)->drm, \
  44                         LT_MSG_PREFIX _format, \
  45                         LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
  46         else \
  47                 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \
  48 } while (0)
  49
  50 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
  51 {
  52         memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
  53 }
  54
  55 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
  56 {
  57         intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
  58                                     DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
  59 }
  60
  61 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
  62                                    enum drm_dp_phy dp_phy)
  63 {
  64         return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
  65 }
  66
  67 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
  68                                          const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  69                                          enum drm_dp_phy dp_phy)
  70 {
  71         u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
  72
  73         if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
  74                 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");
  75                 return;
  76         }
  77
  78         lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",
  79                (int)sizeof(intel_dp->lttpr_phy_caps[0]),
  80                phy_caps);
  81 }
  82
  83 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,
  84                                             const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  85 {
  86         int ret;
  87
  88         ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
  89                                             intel_dp->lttpr_common_caps);
  90         if (ret < 0)
  91                 goto reset_caps;
  92
  93         lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",
  94                (int)sizeof(intel_dp->lttpr_common_caps),
  95                intel_dp->lttpr_common_caps);
  96
  97         /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
  98         if (intel_dp->lttpr_common_caps[0] < 0x14)
  99                 goto reset_caps;
 100
 101         return true;
 102
 103 reset_caps:
 104         intel_dp_reset_lttpr_common_caps(intel_dp);
 105         return false;
 106 }
 107
 108 static bool
 109 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
 110 {
 111         u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
 112                           DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
 113
 114         return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
 115 }
 116
 117 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 118 {
 119         int lttpr_count;
 120         int i;
 121
 122         if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
 123                 return 0;
 124
 125         lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
 126         /*
 127          * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
 128          * detected as this breaks link training at least on the Dell WD19TB
 129          * dock.
 130          */
 131         if (lttpr_count == 0)
 132                 return 0;
 133
 134         /*
 135          * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
 136          * non-transparent mode and the disable->enable non-transparent mode
 137          * sequence.
 138          */
 139         intel_dp_set_lttpr_transparent_mode(intel_dp, true);
 140
 141         /*
 142          * In case of unsupported number of LTTPRs or failing to switch to
 143          * non-transparent mode fall-back to transparent link training mode,
 144          * still taking into account any LTTPR common lane- rate/count limits.
 145          */
 146         if (lttpr_count < 0)
 147                 return 0;
 148
 149         if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
 150                 lt_dbg(intel_dp, DP_PHY_DPRX,
 151                        "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
 152
 153                 intel_dp_set_lttpr_transparent_mode(intel_dp, true);
 154                 intel_dp_reset_lttpr_count(intel_dp);
 155
 156                 return 0;
 157         }
 158
 159         for (i = 0; i < lttpr_count; i++)
 160                 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
 161
 162         return lttpr_count;
 163 }
 164
 165 /**
 166  * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
 167  * @intel_dp: Intel DP struct
 168  *
 169  * Read the LTTPR common and DPRX capabilities and switch to non-transparent
 170  * link training mode if any is detected and read the PHY capabilities for all
 171  * detected LTTPRs. In case of an LTTPR detection error or if the number of
 172  * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
 173  * transparent mode link training mode.
 174  *
 175  * Returns:
 176  *   >0  if LTTPRs were detected and the non-transparent LT mode was set. The
 177  *       DPRX capabilities are read out.
 178  *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
 179  *       detection failure and the transparent LT mode was set. The DPRX
 180  *       capabilities are read out.
 181  *   <0  Reading out the DPRX capabilities failed.
 182  */
 183 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
 184 {
 185         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 186         int lttpr_count = 0;
 187
 188         /*
 189          * Detecting LTTPRs must be avoided on platforms with an AUX timeout
 190          * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
 191          */
 192         if (!intel_dp_is_edp(intel_dp) &&
 193             (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))) {
 194                 u8 dpcd[DP_RECEIVER_CAP_SIZE];
 195
 196                 if (drm_dp_dpcd_probe(&intel_dp->aux, DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
 197                         return -EIO;
 198
 199                 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
 200                         return -EIO;
 201
 202                 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
 203         }
 204
 205         /*
 206          * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
 207          * it here.
 208          */
 209         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
 210                 intel_dp_reset_lttpr_common_caps(intel_dp);
 211                 return -EIO;
 212         }
 213
 214         return lttpr_count;
 215 }
 216
 217 static u8 dp_voltage_max(u8 preemph)
 218 {
 219         switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
 220         case DP_TRAIN_PRE_EMPH_LEVEL_0:
 221                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 222         case DP_TRAIN_PRE_EMPH_LEVEL_1:
 223                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 224         case DP_TRAIN_PRE_EMPH_LEVEL_2:
 225                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
 226         case DP_TRAIN_PRE_EMPH_LEVEL_3:
 227         default:
 228                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 229         }
 230 }
 231
 232 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
 233                                      enum drm_dp_phy dp_phy)
 234 {
 235         const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 236
 237         if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
 238                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 239         else
 240                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 241 }
 242
 243 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
 244                                      enum drm_dp_phy dp_phy)
 245 {
 246         const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 247
 248         if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
 249                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
 250         else
 251                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
 252 }
 253
 254 static bool
 255 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
 256                                      enum drm_dp_phy dp_phy)
 257 {
 258         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 259         int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
 260
 261         drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
 262
 263         return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
 264 }
 265
 266 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
 267                                    const struct intel_crtc_state *crtc_state,
 268                                    enum drm_dp_phy dp_phy)
 269 {
 270         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 271         u8 voltage_max;
 272
 273         /*
 274          * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
 275          * the DPRX_PHY we train.
 276          */
 277         if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 278                 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
 279         else
 280                 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
 281
 282         drm_WARN_ON_ONCE(&i915->drm,
 283                          voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
 284                          voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
 285
 286         return voltage_max;
 287 }
 288
 289 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
 290                                    enum drm_dp_phy dp_phy)
 291 {
 292         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 293         u8 preemph_max;
 294
 295         /*
 296          * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
 297          * the DPRX_PHY we train.
 298          */
 299         if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 300                 preemph_max = intel_dp->preemph_max(intel_dp);
 301         else
 302                 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
 303
 304         drm_WARN_ON_ONCE(&i915->drm,
 305                          preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
 306                          preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
 307
 308         return preemph_max;
 309 }
 310
 311 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
 312                                        enum drm_dp_phy dp_phy)
 313 {
 314         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 315
 316         return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
 317                 DISPLAY_VER(i915) >= 11;
 318 }
 319
 320 /* 128b/132b */
 321 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,
 322                                                  const struct intel_crtc_state *crtc_state,
 323                                                  enum drm_dp_phy dp_phy,
 324                                                  const u8 link_status[DP_LINK_STATUS_SIZE],
 325                                                  int lane)
 326 {
 327         u8 tx_ffe = 0;
 328
 329         if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
 330                 lane = min(lane, crtc_state->lane_count - 1);
 331                 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane);
 332         } else {
 333                 for (lane = 0; lane < crtc_state->lane_count; lane++)
 334                         tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
 335         }
 336
 337         return tx_ffe;
 338 }
 339
 340 /* 8b/10b */
 341 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
 342                                                   const struct intel_crtc_state *crtc_state,
 343                                                   enum drm_dp_phy dp_phy,
 344                                                   const u8 link_status[DP_LINK_STATUS_SIZE],
 345                                                   int lane)
 346 {
 347         u8 v = 0;
 348         u8 p = 0;
 349         u8 voltage_max;
 350         u8 preemph_max;
 351
 352         if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
 353                 lane = min(lane, crtc_state->lane_count - 1);
 354
 355                 v = drm_dp_get_adjust_request_voltage(link_status, lane);
 356                 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 357         } else {
 358                 for (lane = 0; lane < crtc_state->lane_count; lane++) {
 359                         v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 360                         p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 361                 }
 362         }
 363
 364         preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
 365         if (p >= preemph_max)
 366                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 367
 368         v = min(v, dp_voltage_max(p));
 369
 370         voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
 371         if (v >= voltage_max)
 372                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 373
 374         return v | p;
 375 }
 376
 377 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
 378                                          const struct intel_crtc_state *crtc_state,
 379                                          enum drm_dp_phy dp_phy,
 380                                          const u8 link_status[DP_LINK_STATUS_SIZE],
 381                                          int lane)
 382 {
 383         if (intel_dp_is_uhbr(crtc_state))
 384                 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
 385                                                               dp_phy, link_status, lane);
 386         else
 387                 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,
 388                                                                dp_phy, link_status, lane);
 389 }
 390
 391 #define TRAIN_REQ_FMT "%d/%d/%d/%d"
 392 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
 393         (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
 394 #define TRAIN_REQ_VSWING_ARGS(link_status) \
 395         _TRAIN_REQ_VSWING_ARGS(link_status, 0), \
 396         _TRAIN_REQ_VSWING_ARGS(link_status, 1), \
 397         _TRAIN_REQ_VSWING_ARGS(link_status, 2), \
 398         _TRAIN_REQ_VSWING_ARGS(link_status, 3)
 399 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
 400         (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
 401 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \
 402         _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
 403         _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
 404         _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
 405         _TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
 406 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \
 407         drm_dp_get_adjust_tx_ffe_preset((link_status), (lane))
 408 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \
 409         _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
 410         _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
 411         _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
 412         _TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
 413
 414 void
 415 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 416                           const struct intel_crtc_state *crtc_state,
 417                           enum drm_dp_phy dp_phy,
 418                           const u8 link_status[DP_LINK_STATUS_SIZE])
 419 {
 420         int lane;
 421
 422         if (intel_dp_is_uhbr(crtc_state)) {
 423                 lt_dbg(intel_dp, dp_phy,
 424                        "128b/132b, lanes: %d, "
 425                        "TX FFE request: " TRAIN_REQ_FMT "\n",
 426                        crtc_state->lane_count,
 427                        TRAIN_REQ_TX_FFE_ARGS(link_status));
 428         } else {
 429                 lt_dbg(intel_dp, dp_phy,
 430                        "8b/10b, lanes: %d, "
 431                        "vswing request: " TRAIN_REQ_FMT ", "
 432                        "pre-emphasis request: " TRAIN_REQ_FMT "\n",
 433                        crtc_state->lane_count,
 434                        TRAIN_REQ_VSWING_ARGS(link_status),
 435                        TRAIN_REQ_PREEMPH_ARGS(link_status));
 436         }
 437
 438         for (lane = 0; lane < 4; lane++)
 439                 intel_dp->train_set[lane] =
 440                         intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
 441                                                        dp_phy, link_status, lane);
 442 }
 443
 444 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
 445                                              enum drm_dp_phy dp_phy)
 446 {
 447         return dp_phy == DP_PHY_DPRX ?
 448                 DP_TRAINING_PATTERN_SET :
 449                 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
 450 }
 451
 452 static bool
 453 intel_dp_set_link_train(struct intel_dp *intel_dp,
 454                         const struct intel_crtc_state *crtc_state,
 455                         enum drm_dp_phy dp_phy,
 456                         u8 dp_train_pat)
 457 {
 458         int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
 459         u8 buf[sizeof(intel_dp->train_set) + 1];
 460         int len;
 461
 462         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
 463                                                dp_phy, dp_train_pat);
 464
 465         buf[0] = dp_train_pat;
 466         /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
 467         memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
 468         len = crtc_state->lane_count + 1;
 469
 470         return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 471 }
 472
 473 static char dp_training_pattern_name(u8 train_pat)
 474 {
 475         switch (train_pat) {
 476         case DP_TRAINING_PATTERN_1:
 477         case DP_TRAINING_PATTERN_2:
 478         case DP_TRAINING_PATTERN_3:
 479                 return '0' + train_pat;
 480         case DP_TRAINING_PATTERN_4:
 481                 return '4';
 482         default:
 483                 MISSING_CASE(train_pat);
 484                 return '?';
 485         }
 486 }
 487
 488 void
 489 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 490                                        const struct intel_crtc_state *crtc_state,
 491                                        enum drm_dp_phy dp_phy,
 492                                        u8 dp_train_pat)
 493 {
 494         u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
 495
 496         if (train_pat != DP_TRAINING_PATTERN_DISABLE)
 497                 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",
 498                        dp_training_pattern_name(train_pat));
 499
 500         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 501 }
 502
 503 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s"
 504 #define _TRAIN_SET_VSWING_ARGS(train_set) \
 505         ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
 506         (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""
 507 #define TRAIN_SET_VSWING_ARGS(train_set) \
 508         _TRAIN_SET_VSWING_ARGS((train_set)[0]), \
 509         _TRAIN_SET_VSWING_ARGS((train_set)[1]), \
 510         _TRAIN_SET_VSWING_ARGS((train_set)[2]), \
 511         _TRAIN_SET_VSWING_ARGS((train_set)[3])
 512 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \
 513         ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \
 514         (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : ""
 515 #define TRAIN_SET_PREEMPH_ARGS(train_set) \
 516         _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \
 517         _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \
 518         _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \
 519         _TRAIN_SET_PREEMPH_ARGS((train_set)[3])
 520 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \
 521         ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), ""
 522 #define TRAIN_SET_TX_FFE_ARGS(train_set) \
 523         _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
 524         _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
 525         _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
 526         _TRAIN_SET_TX_FFE_ARGS((train_set)[3])
 527
 528 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
 529                                 const struct intel_crtc_state *crtc_state,
 530                                 enum drm_dp_phy dp_phy)
 531 {
 532         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 533
 534         if (intel_dp_is_uhbr(crtc_state)) {
 535                 lt_dbg(intel_dp, dp_phy,
 536                        "128b/132b, lanes: %d, "
 537                        "TX FFE presets: " TRAIN_SET_FMT "\n",
 538                        crtc_state->lane_count,
 539                        TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
 540         } else {
 541                 lt_dbg(intel_dp, dp_phy,
 542                        "8b/10b, lanes: %d, "
 543                        "vswing levels: " TRAIN_SET_FMT ", "
 544                        "pre-emphasis levels: " TRAIN_SET_FMT "\n",
 545                        crtc_state->lane_count,
 546                        TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
 547                        TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
 548         }
 549
 550         if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 551                 encoder->set_signal_levels(encoder, crtc_state);
 552 }
 553
 554 static bool
 555 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 556                           const struct intel_crtc_state *crtc_state,
 557                           enum drm_dp_phy dp_phy,
 558                           u8 dp_train_pat)
 559 {
 560         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 561         intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 562         return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
 563 }
 564
 565 static bool
 566 intel_dp_update_link_train(struct intel_dp *intel_dp,
 567                            const struct intel_crtc_state *crtc_state,
 568                            enum drm_dp_phy dp_phy)
 569 {
 570         int reg = dp_phy == DP_PHY_DPRX ?
 571                             DP_TRAINING_LANE0_SET :
 572                             DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
 573         int ret;
 574
 575         intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 576
 577         ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
 578                                 intel_dp->train_set, crtc_state->lane_count);
 579
 580         return ret == crtc_state->lane_count;
 581 }
 582
 583 /* 128b/132b */
 584 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)
 585 {
 586         return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) ==
 587                 DP_TX_FFE_PRESET_VALUE_MASK;
 588 }
 589
 590 /*
 591  * 8b/10b
 592  *
 593  * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to
 594  * have self contradicting tests around this area.
 595  *
 596  * In lieu of better ideas let's just stop when we've reached the max supported
 597  * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on
 598  * whether vswing level 3 is supported or not.
 599  */
 600 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)
 601 {
 602         u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
 603                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
 604         u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 605                 DP_TRAIN_PRE_EMPHASIS_SHIFT;
 606
 607         if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0)
 608                 return false;
 609
 610         if (v + p != 3)
 611                 return false;
 612
 613         return true;
 614 }
 615
 616 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 617                                              const struct intel_crtc_state *crtc_state)
 618 {
 619         int lane;
 620
 621         for (lane = 0; lane < crtc_state->lane_count; lane++) {
 622                 u8 train_set_lane = intel_dp->train_set[lane];
 623
 624                 if (intel_dp_is_uhbr(crtc_state)) {
 625                         if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
 626                                 return false;
 627                 } else {
 628                         if (!intel_dp_lane_max_vswing_reached(train_set_lane))
 629                                 return false;
 630                 }
 631         }
 632
 633         return true;
 634 }
 635
 636 static void
 637 intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 638                                 const struct intel_crtc_state *crtc_state)
 639 {
 640         u8 link_config[2];
 641
 642         link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
 643         link_config[1] = intel_dp_is_uhbr(crtc_state) ?
 644                          DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 645         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 646 }
 647
 648 static void
 649 intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
 650                             const struct intel_crtc_state *crtc_state,
 651                             u8 link_bw, u8 rate_select)
 652 {
 653         u8 link_config[2];
 654
 655         /* Write the link configuration data */
 656         link_config[0] = link_bw;
 657         link_config[1] = crtc_state->lane_count;
 658         if (crtc_state->enhanced_framing)
 659                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 660         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 661
 662         /* eDP 1.4 rate select method. */
 663         if (!link_bw)
 664                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 665                                   &rate_select, 1);
 666 }
 667
 668 /*
 669  * Prepare link training by configuring the link parameters. On DDI platforms
 670  * also enable the port here.
 671  */
 672 static bool
 673 intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 674                             const struct intel_crtc_state *crtc_state)
 675 {
 676         u8 link_bw, rate_select;
 677
 678         if (intel_dp->prepare_link_retrain)
 679                 intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 680
 681         intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
 682                               &link_bw, &rate_select);
 683
 684         /*
 685          * WaEdpLinkRateDataReload
 686          *
 687          * Parade PS8461E MUX (used on varius TGL+ laptops) needs
 688          * to snoop the link rates reported by the sink when we
 689          * use LINK_RATE_SET in order to operate in jitter cleaning
 690          * mode (as opposed to redriver mode). Unfortunately it
 691          * loses track of the snooped link rates when powered down,
 692          * so we need to make it re-snoop often. Without this high
 693          * link rates are not stable.
 694          */
 695         if (!link_bw) {
 696                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 697
 698                 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");
 699
 700                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
 701                                  sink_rates, sizeof(sink_rates));
 702         }
 703
 704         if (link_bw)
 705                 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",
 706                        link_bw);
 707         else
 708                 lt_dbg(intel_dp, DP_PHY_DPRX,
 709                        "Using LINK_RATE_SET value %02x\n",
 710                        rate_select);
 711         /*
 712          * Spec DP2.1 Section 3.5.2.16
 713          * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
 714          */
 715         intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
 716         intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
 717                                     rate_select);
 718
 719         return true;
 720 }
 721
 722 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
 723                                             const u8 old_link_status[DP_LINK_STATUS_SIZE],
 724                                             const u8 new_link_status[DP_LINK_STATUS_SIZE])
 725 {
 726         int lane;
 727
 728         for (lane = 0; lane < crtc_state->lane_count; lane++) {
 729                 u8 old, new;
 730
 731                 if (intel_dp_is_uhbr(crtc_state)) {
 732                         old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
 733                         new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
 734                 } else {
 735                         old = drm_dp_get_adjust_request_voltage(old_link_status, lane) |
 736                                 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane);
 737                         new = drm_dp_get_adjust_request_voltage(new_link_status, lane) |
 738                                 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane);
 739                 }
 740
 741                 if (old != new)
 742                         return true;
 743         }
 744
 745         return false;
 746 }
 747
 748 void
 749 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
 750                           const u8 link_status[DP_LINK_STATUS_SIZE])
 751 {
 752         lt_dbg(intel_dp, dp_phy,
 753                "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
 754                link_status[0], link_status[1], link_status[2],
 755                link_status[3], link_status[4], link_status[5]);
 756 }
 757
 758 /*
 759  * Perform the link training clock recovery phase on the given DP PHY using
 760  * training pattern 1.
 761  */
 762 static bool
 763 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 764                                       const struct intel_crtc_state *crtc_state,
 765                                       enum drm_dp_phy dp_phy)
 766 {
 767         u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
 768         int voltage_tries, cr_tries, max_cr_tries;
 769         u8 link_status[DP_LINK_STATUS_SIZE];
 770         bool max_vswing_reached = false;
 771         int delay_us;
 772
 773         delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
 774                                                     intel_dp->dpcd, dp_phy,
 775                                                     intel_dp_is_uhbr(crtc_state));
 776
 777         /* clock recovery */
 778         if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
 779                                        DP_TRAINING_PATTERN_1 |
 780                                        DP_LINK_SCRAMBLING_DISABLE)) {
 781                 lt_err(intel_dp, dp_phy, "Failed to enable link training\n");
 782                 return false;
 783         }
 784
 785         /*
 786          * The DP 1.4 spec defines the max clock recovery retries value
 787          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 788          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 789          * x 5 identical voltage retries). Since the previous specs didn't
 790          * define a limit and created the possibility of an infinite loop
 791          * we want to prevent any sync from triggering that corner case.
 792          */
 793         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 794                 max_cr_tries = 10;
 795         else
 796                 max_cr_tries = 80;
 797
 798         voltage_tries = 1;
 799         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 800                 usleep_range(delay_us, 2 * delay_us);
 801
 802                 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 803                                                      link_status) < 0) {
 804                         lt_err(intel_dp, dp_phy, "Failed to get link status\n");
 805                         return false;
 806                 }
 807
 808                 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
 809                         lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
 810                         return true;
 811                 }
 812
 813                 if (voltage_tries == 5) {
 814                         intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 815                         lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");
 816                         return false;
 817                 }
 818
 819                 if (max_vswing_reached) {
 820                         intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 821                         lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");
 822                         return false;
 823                 }
 824
 825                 /* Update training set as requested by target */
 826                 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
 827                                           link_status);
 828                 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 829                         lt_err(intel_dp, dp_phy, "Failed to update link training\n");
 830                         return false;
 831                 }
 832
 833                 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
 834                         ++voltage_tries;
 835                 else
 836                         voltage_tries = 1;
 837
 838                 memcpy(old_link_status, link_status, sizeof(link_status));
 839
 840                 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
 841                         max_vswing_reached = true;
 842         }
 843
 844         intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 845         lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",
 846                max_cr_tries);
 847
 848         return false;
 849 }
 850
 851 /*
 852  * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
 853  * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
 854  * 1.2 devices that support it, TPS2 otherwise.
 855  */
 856 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 857                                      const struct intel_crtc_state *crtc_state,
 858                                      enum drm_dp_phy dp_phy)
 859 {
 860         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 861         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 862
 863         /* UHBR+ use separate 128b/132b TPS2 */
 864         if (intel_dp_is_uhbr(crtc_state))
 865                 return DP_TRAINING_PATTERN_2;
 866
 867         /*
 868          * TPS4 support is mandatory for all downstream devices that
 869          * support HBR3. There are no known eDP panels that support
 870          * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
 871          * LTTPRs must support TPS4.
 872          */
 873         source_tps4 = intel_dp_source_supports_tps4(i915);
 874         sink_tps4 = dp_phy != DP_PHY_DPRX ||
 875                     drm_dp_tps4_supported(intel_dp->dpcd);
 876         if (source_tps4 && sink_tps4) {
 877                 return DP_TRAINING_PATTERN_4;
 878         } else if (crtc_state->port_clock == 810000) {
 879                 if (!source_tps4)
 880                         lt_dbg(intel_dp, dp_phy,
 881                                "8.1 Gbps link rate without source TPS4 support\n");
 882                 if (!sink_tps4)
 883                         lt_dbg(intel_dp, dp_phy,
 884                                "8.1 Gbps link rate without sink TPS4 support\n");
 885         }
 886
 887         /*
 888          * TPS3 support is mandatory for downstream devices that
 889          * support HBR2. However, not all sinks follow the spec.
 890          */
 891         source_tps3 = intel_dp_source_supports_tps3(i915);
 892         sink_tps3 = dp_phy != DP_PHY_DPRX ||
 893                     drm_dp_tps3_supported(intel_dp->dpcd);
 894         if (source_tps3 && sink_tps3) {
 895                 return  DP_TRAINING_PATTERN_3;
 896         } else if (crtc_state->port_clock >= 540000) {
 897                 if (!source_tps3)
 898                         lt_dbg(intel_dp, dp_phy,
 899                                ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
 900                 if (!sink_tps3)
 901                         lt_dbg(intel_dp, dp_phy,
 902                                ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 903         }
 904
 905         return DP_TRAINING_PATTERN_2;
 906 }
 907
 908 /*
 909  * Perform the link training channel equalization phase on the given DP PHY
 910  * using one of training pattern 2, 3 or 4 depending on the source and
 911  * sink capabilities.
 912  */
 913 static bool
 914 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 915                                             const struct intel_crtc_state *crtc_state,
 916                                             enum drm_dp_phy dp_phy)
 917 {
 918         int tries;
 919         u32 training_pattern;
 920         u8 link_status[DP_LINK_STATUS_SIZE];
 921         bool channel_eq = false;
 922         int delay_us;
 923
 924         delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
 925                                                 intel_dp->dpcd, dp_phy,
 926                                                 intel_dp_is_uhbr(crtc_state));
 927
 928         training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
 929         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 930         if (training_pattern != DP_TRAINING_PATTERN_4)
 931                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 932
 933         /* channel equalization */
 934         if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
 935                                      training_pattern)) {
 936                 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");
 937                 return false;
 938         }
 939
 940         for (tries = 0; tries < 5; tries++) {
 941                 usleep_range(delay_us, 2 * delay_us);
 942
 943                 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 944                                                      link_status) < 0) {
 945                         lt_err(intel_dp, dp_phy, "Failed to get link status\n");
 946                         break;
 947                 }
 948
 949                 /* Make sure clock is still ok */
 950                 if (!drm_dp_clock_recovery_ok(link_status,
 951                                               crtc_state->lane_count)) {
 952                         intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 953                         lt_dbg(intel_dp, dp_phy,
 954                                "Clock recovery check failed, cannot continue channel equalization\n");
 955                         break;
 956                 }
 957
 958                 if (drm_dp_channel_eq_ok(link_status,
 959                                          crtc_state->lane_count)) {
 960                         channel_eq = true;
 961                         lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
 962                         break;
 963                 }
 964
 965                 /* Update training set as requested by target */
 966                 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
 967                                           link_status);
 968                 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 969                         lt_err(intel_dp, dp_phy, "Failed to update link training\n");
 970                         break;
 971                 }
 972         }
 973
 974         /* Try 5 times, else fail and try at lower BW */
 975         if (tries == 5) {
 976                 intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 977                 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");
 978         }
 979
 980         return channel_eq;
 981 }
 982
 983 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
 984                                                    enum drm_dp_phy dp_phy)
 985 {
 986         int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
 987         u8 val = DP_TRAINING_PATTERN_DISABLE;
 988
 989         return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
 990 }
 991
 992 static int
 993 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,
 994                             const struct intel_crtc_state *crtc_state)
 995 {
 996         u8 sink_status;
 997         int ret;
 998
 999         ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);
1000         if (ret != 1) {
1001                 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");
1002                 return ret < 0 ? ret : -EIO;
1003         }
1004
1005         return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0;
1006 }
1007
1008 /**
1009  * intel_dp_stop_link_train - stop link training
1010  * @intel_dp: DP struct
1011  * @crtc_state: state for CRTC attached to the encoder
1012  *
1013  * Stop the link training of the @intel_dp port, disabling the training
1014  * pattern in the sink's DPCD, and disabling the test pattern symbol
1015  * generation on the port.
1016  *
1017  * What symbols are output on the port after this point is
1018  * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
1019  * with the pipe being disabled, on older platforms it's HW specific if/how an
1020  * idle pattern is generated, as the pipe is already enabled here for those.
1021  *
1022  * This function must be called after intel_dp_start_link_train().
1023  */
1024 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
1025                               const struct intel_crtc_state *crtc_state)
1026 {
1027         intel_dp->link_trained = true;
1028
1029         intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
1030         intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
1031                                                DP_TRAINING_PATTERN_DISABLE);
1032
1033         if (intel_dp_is_uhbr(crtc_state) &&
1034             wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1035                 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
1036         }
1037 }
1038
1039 static bool
1040 intel_dp_link_train_phy(struct intel_dp *intel_dp,
1041                         const struct intel_crtc_state *crtc_state,
1042                         enum drm_dp_phy dp_phy)
1043 {
1044         bool ret = false;
1045
1046         if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
1047                 goto out;
1048
1049         if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
1050                 goto out;
1051
1052         ret = true;
1053
1054 out:
1055         lt_dbg(intel_dp, dp_phy,
1056                "Link Training %s at link rate = %d, lane count = %d\n",
1057                ret ? "passed" : "failed",
1058                crtc_state->port_clock, crtc_state->lane_count);
1059
1060         return ret;
1061 }
1062
1063 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
1064                                                      const struct intel_crtc_state *crtc_state)
1065 {
1066         struct intel_connector *intel_connector = intel_dp->attached_connector;
1067         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1068
1069         if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
1070                 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
1071                 return;
1072         }
1073
1074         if (intel_dp->hobl_active) {
1075                 lt_dbg(intel_dp, DP_PHY_DPRX,
1076                        "Link Training failed with HOBL active, not enabling it from now on\n");
1077                 intel_dp->hobl_failed = true;
1078         } else if (intel_dp_get_link_train_fallback_values(intel_dp,
1079                                                            crtc_state->port_clock,
1080                                                            crtc_state->lane_count)) {
1081                 return;
1082         }
1083
1084         /* Schedule a Hotplug Uevent to userspace to start modeset */
1085         queue_work(i915->unordered_wq, &intel_connector->modeset_retry_work);
1086 }
1087
1088 /* Perform the link training on all LTTPRs and the DPRX on a link. */
1089 static bool
1090 intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
1091                              const struct intel_crtc_state *crtc_state,
1092                              int lttpr_count)
1093 {
1094         bool ret = true;
1095         int i;
1096
1097         for (i = lttpr_count - 1; i >= 0; i--) {
1098                 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
1099
1100                 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
1101                 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
1102
1103                 if (!ret)
1104                         break;
1105         }
1106
1107         if (ret)
1108                 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
1109
1110         if (intel_dp->set_idle_link_train)
1111                 intel_dp->set_idle_link_train(intel_dp, crtc_state);
1112
1113         return ret;
1114 }
1115
1116 /*
1117  * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1)
1118  */
1119 static bool
1120 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
1121                           const struct intel_crtc_state *crtc_state)
1122 {
1123         u8 link_status[DP_LINK_STATUS_SIZE];
1124         int delay_us;
1125         int try, max_tries = 20;
1126         unsigned long deadline;
1127         bool timeout = false;
1128
1129         /*
1130          * Reset signal levels. Start transmitting 128b/132b TPS1.
1131          *
1132          * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1
1133          * in DP_TRAINING_PATTERN_SET.
1134          */
1135         if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
1136                                        DP_TRAINING_PATTERN_1)) {
1137                 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");
1138                 return false;
1139         }
1140
1141         delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
1142
1143         /* Read the initial TX FFE settings. */
1144         if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1145                 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");
1146                 return false;
1147         }
1148
1149         /* Update signal levels and training set as requested. */
1150         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1151         if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
1152                 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");
1153                 return false;
1154         }
1155
1156         /* Start transmitting 128b/132b TPS2. */
1157         if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
1158                                      DP_TRAINING_PATTERN_2)) {
1159                 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");
1160                 return false;
1161         }
1162
1163         /* Time budget for the LANEx_EQ_DONE Sequence */
1164         deadline = jiffies + msecs_to_jiffies_timeout(400);
1165
1166         for (try = 0; try < max_tries; try++) {
1167                 usleep_range(delay_us, 2 * delay_us);
1168
1169                 /*
1170                  * The delay may get updated. The transmitter shall read the
1171                  * delay before link status during link training.
1172                  */
1173                 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
1174
1175                 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1176                         lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1177                         return false;
1178                 }
1179
1180                 if (drm_dp_128b132b_link_training_failed(link_status)) {
1181                         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1182                         lt_err(intel_dp, DP_PHY_DPRX,
1183                                "Downstream link training failure\n");
1184                         return false;
1185                 }
1186
1187                 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
1188                         lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
1189                         break;
1190                 }
1191
1192                 if (timeout) {
1193                         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1194                         lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");
1195                         return false;
1196                 }
1197
1198                 if (time_after(jiffies, deadline))
1199                         timeout = true; /* try one last time after deadline */
1200
1201                 /* Update signal levels and training set as requested. */
1202                 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1203                 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
1204                         lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
1205                         return false;
1206                 }
1207         }
1208
1209         if (try == max_tries) {
1210                 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1211                 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");
1212                 return false;
1213         }
1214
1215         for (;;) {
1216                 if (time_after(jiffies, deadline))
1217                         timeout = true; /* try one last time after deadline */
1218
1219                 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1220                         lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1221                         return false;
1222                 }
1223
1224                 if (drm_dp_128b132b_link_training_failed(link_status)) {
1225                         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1226                         lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
1227                         return false;
1228                 }
1229
1230                 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) {
1231                         lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");
1232                         break;
1233                 }
1234
1235                 if (timeout) {
1236                         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1237                         lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");
1238                         return false;
1239                 }
1240
1241                 usleep_range(2000, 3000);
1242         }
1243
1244         return true;
1245 }
1246
1247 /*
1248  * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2)
1249  */
1250 static bool
1251 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
1252                            const struct intel_crtc_state *crtc_state,
1253                            int lttpr_count)
1254 {
1255         u8 link_status[DP_LINK_STATUS_SIZE];
1256         unsigned long deadline;
1257
1258         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
1259                                DP_TRAINING_PATTERN_2_CDS) != 1) {
1260                 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");
1261                 return false;
1262         }
1263
1264         /* Time budget for the LANEx_CDS_DONE Sequence */
1265         deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20);
1266
1267         for (;;) {
1268                 bool timeout = false;
1269
1270                 if (time_after(jiffies, deadline))
1271                         timeout = true; /* try one last time after deadline */
1272
1273                 usleep_range(2000, 3000);
1274
1275                 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1276                         lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1277                         return false;
1278                 }
1279
1280                 if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
1281                     drm_dp_128b132b_cds_interlane_align_done(link_status) &&
1282                     drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
1283                         lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
1284                         break;
1285                 }
1286
1287                 if (drm_dp_128b132b_link_training_failed(link_status)) {
1288                         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1289                         lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
1290                         return false;
1291                 }
1292
1293                 if (timeout) {
1294                         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1295                         lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");
1296                         return false;
1297                 }
1298         }
1299
1300         return true;
1301 }
1302
1303 /*
1304  * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.)
1305  */
1306 static bool
1307 intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
1308                              const struct intel_crtc_state *crtc_state,
1309                              int lttpr_count)
1310 {
1311         bool passed = false;
1312
1313         if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1314                 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
1315                 return false;
1316         }
1317
1318         if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
1319             intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))
1320                 passed = true;
1321
1322         lt_dbg(intel_dp, DP_PHY_DPRX,
1323                "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
1324                passed ? "passed" : "failed",
1325                crtc_state->port_clock, crtc_state->lane_count);
1326
1327         return passed;
1328 }
1329
1330 /**
1331  * intel_dp_start_link_train - start link training
1332  * @intel_dp: DP struct
1333  * @crtc_state: state for CRTC attached to the encoder
1334  *
1335  * Start the link training of the @intel_dp port, scheduling a fallback
1336  * retraining with reduced link rate/lane parameters if the link training
1337  * fails.
1338  * After calling this function intel_dp_stop_link_train() must be called.
1339  */
1340 void intel_dp_start_link_train(struct intel_dp *intel_dp,
1341                                const struct intel_crtc_state *crtc_state)
1342 {
1343         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1344         bool passed;
1345
1346         /*
1347          * TODO: Reiniting LTTPRs here won't be needed once proper connector
1348          * HW state readout is added.
1349          */
1350         int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
1351
1352         if (lttpr_count < 0)
1353                 /* Still continue with enabling the port and link training. */
1354                 lttpr_count = 0;
1355
1356         intel_dp_prepare_link_train(intel_dp, crtc_state);
1357
1358         if (intel_dp_is_uhbr(crtc_state))
1359                 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
1360         else
1361                 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
1362
1363         /*
1364          * Ignore the link failure in CI
1365          *
1366          * In fixed enviroments like CI, sometimes unexpected long HPDs are
1367          * generated by the displays. If ignore_long_hpd flag is set, such long
1368          * HPDs are ignored. And probably as a consequence of these ignored
1369          * long HPDs, subsequent link trainings are failed resulting into CI
1370          * execution failures.
1371          *
1372          * For test cases which rely on the link training or processing of HPDs
1373          * ignore_long_hpd flag can unset from the testcase.
1374          */
1375         if (!passed && i915->display.hotplug.ignore_long_hpd) {
1376                 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
1377                 return;
1378         }
1379
1380         if (!passed)
1381                 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
1382 }
1383
1384 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
1385                                  const struct intel_crtc_state *crtc_state)
1386 {
1387         /*
1388          * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
1389          * disable SDP CRC. This is applicable for Display version 13.
1390          * Default value of bit 31 is '0' hence discarding the write
1391          * TODO: Corrective actions on SDP corruption yet to be defined
1392          */
1393         if (!intel_dp_is_uhbr(crtc_state))
1394                 return;
1395
1396         /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
1397         drm_dp_dpcd_writeb(&intel_dp->aux,
1398                            DP_SDP_ERROR_DETECTION_CONFIGURATION,
1399                            DP_SDP_CRC16_128B132B_EN);
1400
1401         lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
1402 }