drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/string_helpers.h>
  33 #include <linux/timekeeping.h>
  34 #include <linux/types.h>
  35
  36 #include <asm/byteorder.h>
  37
  38 #include <drm/display/drm_dp_helper.h>
  39 #include <drm/display/drm_dsc_helper.h>
  40 #include <drm/display/drm_hdmi_helper.h>
  41 #include <drm/drm_atomic_helper.h>
  42 #include <drm/drm_crtc.h>
  43 #include <drm/drm_edid.h>
  44 #include <drm/drm_probe_helper.h>
  45
  46 #include "g4x_dp.h"
  47 #include "i915_drv.h"
  48 #include "i915_irq.h"
  49 #include "i915_reg.h"
  50 #include "intel_atomic.h"
  51 #include "intel_audio.h"
  52 #include "intel_backlight.h"
  53 #include "intel_combo_phy_regs.h"
  54 #include "intel_connector.h"
  55 #include "intel_crtc.h"
  56 #include "intel_cx0_phy.h"
  57 #include "intel_ddi.h"
  58 #include "intel_de.h"
  59 #include "intel_display_types.h"
  60 #include "intel_dp.h"
  61 #include "intel_dp_aux.h"
  62 #include "intel_dp_hdcp.h"
  63 #include "intel_dp_link_training.h"
  64 #include "intel_dp_mst.h"
  65 #include "intel_dpio_phy.h"
  66 #include "intel_dpll.h"
  67 #include "intel_fifo_underrun.h"
  68 #include "intel_hdcp.h"
  69 #include "intel_hdmi.h"
  70 #include "intel_hotplug.h"
  71 #include "intel_hotplug_irq.h"
  72 #include "intel_lspcon.h"
  73 #include "intel_lvds.h"
  74 #include "intel_panel.h"
  75 #include "intel_pch_display.h"
  76 #include "intel_pps.h"
  77 #include "intel_psr.h"
  78 #include "intel_tc.h"
  79 #include "intel_vdsc.h"
  80 #include "intel_vrr.h"
  81 #include "intel_crtc_state_dump.h"
  82
  83 /* DP DSC throughput values used for slice count calculations KPixels/s */
  84 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  85 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  86 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  87
  88 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  89 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  90
  91 /* Compliance test status bits  */
  92 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  93 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  94 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  95 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  96
  97
  98 /* Constants for DP DSC configurations */
  99 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 100
 101 /* With Single pipe configuration, HW is capable of supporting maximum
 102  * of 4 slices per line.
 103  */
 104 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  *
 113  * This function is not safe to use prior to encoder type being set.
 114  */
 115 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 116 {
 117         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 118
 119         return dig_port->base.type == INTEL_OUTPUT_EDP;
 120 }
 121
 122 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 123
 124 /* Is link rate UHBR and thus 128b/132b? */
 125 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
 126 {
 127         return crtc_state->port_clock >= 1000000;
 128 }
 129
 130 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
 131 {
 132         intel_dp->sink_rates[0] = 162000;
 133         intel_dp->num_sink_rates = 1;
 134 }
 135
 136 /* update sink rates from dpcd */
 137 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
 138 {
 139         static const int dp_rates[] = {
 140                 162000, 270000, 540000, 810000
 141         };
 142         int i, max_rate;
 143         int max_lttpr_rate;
 144
 145         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 146                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 147                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 148
 149                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 150                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 151
 152                 return;
 153         }
 154
 155         /*
 156          * Sink rates for 8b/10b.
 157          */
 158         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 159         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 160         if (max_lttpr_rate)
 161                 max_rate = min(max_rate, max_lttpr_rate);
 162
 163         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 164                 if (dp_rates[i] > max_rate)
 165                         break;
 166                 intel_dp->sink_rates[i] = dp_rates[i];
 167         }
 168
 169         /*
 170          * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 171          * rates and 10 Gbps.
 172          */
 173         if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) {
 174                 u8 uhbr_rates = 0;
 175
 176                 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
 177
 178                 drm_dp_dpcd_readb(&intel_dp->aux,
 179                                   DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
 180
 181                 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
 182                         /* We have a repeater */
 183                         if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
 184                             intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
 185                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
 186                             DP_PHY_REPEATER_128B132B_SUPPORTED) {
 187                                 /* Repeater supports 128b/132b, valid UHBR rates */
 188                                 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
 189                                                                           DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
 190                         } else {
 191                                 /* Does not support 128b/132b */
 192                                 uhbr_rates = 0;
 193                         }
 194                 }
 195
 196                 if (uhbr_rates & DP_UHBR10)
 197                         intel_dp->sink_rates[i++] = 1000000;
 198                 if (uhbr_rates & DP_UHBR13_5)
 199                         intel_dp->sink_rates[i++] = 1350000;
 200                 if (uhbr_rates & DP_UHBR20)
 201                         intel_dp->sink_rates[i++] = 2000000;
 202         }
 203
 204         intel_dp->num_sink_rates = i;
 205 }
 206
 207 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 208 {
 209         struct intel_connector *connector = intel_dp->attached_connector;
 210         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 211         struct intel_encoder *encoder = &intel_dig_port->base;
 212
 213         intel_dp_set_dpcd_sink_rates(intel_dp);
 214
 215         if (intel_dp->num_sink_rates)
 216                 return;
 217
 218         drm_err(&dp_to_i915(intel_dp)->drm,
 219                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
 220                 connector->base.base.id, connector->base.name,
 221                 encoder->base.base.id, encoder->base.name);
 222
 223         intel_dp_set_default_sink_rates(intel_dp);
 224 }
 225
 226 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
 227 {
 228         intel_dp->max_sink_lane_count = 1;
 229 }
 230
 231 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
 232 {
 233         struct intel_connector *connector = intel_dp->attached_connector;
 234         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 235         struct intel_encoder *encoder = &intel_dig_port->base;
 236
 237         intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 238
 239         switch (intel_dp->max_sink_lane_count) {
 240         case 1:
 241         case 2:
 242         case 4:
 243                 return;
 244         }
 245
 246         drm_err(&dp_to_i915(intel_dp)->drm,
 247                 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
 248                 connector->base.base.id, connector->base.name,
 249                 encoder->base.base.id, encoder->base.name,
 250                 intel_dp->max_sink_lane_count);
 251
 252         intel_dp_set_default_max_sink_lane_count(intel_dp);
 253 }
 254
 255 /* Get length of rates array potentially limited by max_rate. */
 256 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 257 {
 258         int i;
 259
 260         /* Limit results by potentially reduced max rate */
 261         for (i = 0; i < len; i++) {
 262                 if (rates[len - i - 1] <= max_rate)
 263                         return len - i;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /* Get length of common rates array potentially limited by max_rate. */
 270 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 271                                           int max_rate)
 272 {
 273         return intel_dp_rate_limit_len(intel_dp->common_rates,
 274                                        intel_dp->num_common_rates, max_rate);
 275 }
 276
 277 static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
 278 {
 279         if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,
 280                         index < 0 || index >= intel_dp->num_common_rates))
 281                 return 162000;
 282
 283         return intel_dp->common_rates[index];
 284 }
 285
 286 /* Theoretical max between source and sink */
 287 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 288 {
 289         return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
 290 }
 291
 292 static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
 293 {
 294         int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
 295         int max_lanes = dig_port->max_lanes;
 296
 297         if (vbt_max_lanes)
 298                 max_lanes = min(max_lanes, vbt_max_lanes);
 299
 300         return max_lanes;
 301 }
 302
 303 /* Theoretical max between source and sink */
 304 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 305 {
 306         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 307         int source_max = intel_dp_max_source_lane_count(dig_port);
 308         int sink_max = intel_dp->max_sink_lane_count;
 309         int lane_max = intel_tc_port_max_lane_count(dig_port);
 310         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 311
 312         if (lttpr_max)
 313                 sink_max = min(sink_max, lttpr_max);
 314
 315         return min3(source_max, sink_max, lane_max);
 316 }
 317
 318 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 319 {
 320         switch (intel_dp->max_link_lane_count) {
 321         case 1:
 322         case 2:
 323         case 4:
 324                 return intel_dp->max_link_lane_count;
 325         default:
 326                 MISSING_CASE(intel_dp->max_link_lane_count);
 327                 return 1;
 328         }
 329 }
 330
 331 /*
 332  * The required data bandwidth for a mode with given pixel clock and bpp. This
 333  * is the required net bandwidth independent of the data bandwidth efficiency.
 334  */
 335 int
 336 intel_dp_link_required(int pixel_clock, int bpp)
 337 {
 338         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 339         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 340 }
 341
 342 /*
 343  * Given a link rate and lanes, get the data bandwidth.
 344  *
 345  * Data bandwidth is the actual payload rate, which depends on the data
 346  * bandwidth efficiency and the link rate.
 347  *
 348  * For 8b/10b channel encoding, SST and non-FEC, the data bandwidth efficiency
 349  * is 80%. For example, for a 1.62 Gbps link, 1.62*10^9 bps * 0.80 * (1/8) =
 350  * 162000 kBps. With 8-bit symbols, we have 162000 kHz symbol clock. Just by
 351  * coincidence, the port clock in kHz matches the data bandwidth in kBps, and
 352  * they equal the link bit rate in Gbps multiplied by 100000. (Note that this no
 353  * longer holds for data bandwidth as soon as FEC or MST is taken into account!)
 354  *
 355  * For 128b/132b channel encoding, the data bandwidth efficiency is 96.71%. For
 356  * example, for a 10 Gbps link, 10*10^9 bps * 0.9671 * (1/8) = 1208875
 357  * kBps. With 32-bit symbols, we have 312500 kHz symbol clock. The value 1000000
 358  * does not match the symbol clock, the port clock (not even if you think in
 359  * terms of a byte clock), nor the data bandwidth. It only matches the link bit
 360  * rate in units of 10000 bps.
 361  */
 362 int
 363 intel_dp_max_data_rate(int max_link_rate, int max_lanes)
 364 {
 365         if (max_link_rate >= 1000000) {
 366                 /*
 367                  * UHBR rates always use 128b/132b channel encoding, and have
 368                  * 97.71% data bandwidth efficiency. Consider max_link_rate the
 369                  * link bit rate in units of 10000 bps.
 370                  */
 371                 int max_link_rate_kbps = max_link_rate * 10;
 372
 373                 max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000);
 374                 max_link_rate = max_link_rate_kbps / 8;
 375         }
 376
 377         /*
 378          * Lower than UHBR rates always use 8b/10b channel encoding, and have
 379          * 80% data bandwidth efficiency for SST non-FEC. However, this turns
 380          * out to be a nop by coincidence, and can be skipped:
 381          *
 382          *      int max_link_rate_kbps = max_link_rate * 10;
 383          *      max_link_rate_kbps = DIV_ROUND_CLOSEST_ULL(max_link_rate_kbps * 8, 10);
 384          *      max_link_rate = max_link_rate_kbps / 8;
 385          */
 386
 387         return max_link_rate * max_lanes;
 388 }
 389
 390 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 391 {
 392         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 393         struct intel_encoder *encoder = &intel_dig_port->base;
 394         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 395
 396         return DISPLAY_VER(dev_priv) >= 12 ||
 397                 (DISPLAY_VER(dev_priv) == 11 &&
 398                  encoder->port != PORT_A);
 399 }
 400
 401 static int dg2_max_source_rate(struct intel_dp *intel_dp)
 402 {
 403         return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
 404 }
 405
 406 static int icl_max_source_rate(struct intel_dp *intel_dp)
 407 {
 408         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 409         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 410         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 411
 412         if (intel_phy_is_combo(dev_priv, phy) && !intel_dp_is_edp(intel_dp))
 413                 return 540000;
 414
 415         return 810000;
 416 }
 417
 418 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 419 {
 420         if (intel_dp_is_edp(intel_dp))
 421                 return 540000;
 422
 423         return 810000;
 424 }
 425
 426 static int mtl_max_source_rate(struct intel_dp *intel_dp)
 427 {
 428         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 429         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 430         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 431
 432         if (intel_is_c10phy(i915, phy))
 433                 return 810000;
 434
 435         return 2000000;
 436 }
 437
 438 static int vbt_max_link_rate(struct intel_dp *intel_dp)
 439 {
 440         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 441         int max_rate;
 442
 443         max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
 444
 445         if (intel_dp_is_edp(intel_dp)) {
 446                 struct intel_connector *connector = intel_dp->attached_connector;
 447                 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
 448
 449                 if (max_rate && edp_max_rate)
 450                         max_rate = min(max_rate, edp_max_rate);
 451                 else if (edp_max_rate)
 452                         max_rate = edp_max_rate;
 453         }
 454
 455         return max_rate;
 456 }
 457
 458 static void
 459 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 460 {
 461         /* The values must be in increasing order */
 462         static const int mtl_rates[] = {
 463                 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
 464                 810000, 1000000, 1350000, 2000000,
 465         };
 466         static const int icl_rates[] = {
 467                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
 468                 1000000, 1350000,
 469         };
 470         static const int bxt_rates[] = {
 471                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 472         };
 473         static const int skl_rates[] = {
 474                 162000, 216000, 270000, 324000, 432000, 540000
 475         };
 476         static const int hsw_rates[] = {
 477                 162000, 270000, 540000
 478         };
 479         static const int g4x_rates[] = {
 480                 162000, 270000
 481         };
 482         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 483         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 484         const int *source_rates;
 485         int size, max_rate = 0, vbt_max_rate;
 486
 487         /* This should only be done once */
 488         drm_WARN_ON(&dev_priv->drm,
 489                     intel_dp->source_rates || intel_dp->num_source_rates);
 490
 491         if (DISPLAY_VER(dev_priv) >= 14) {
 492                 source_rates = mtl_rates;
 493                 size = ARRAY_SIZE(mtl_rates);
 494                 max_rate = mtl_max_source_rate(intel_dp);
 495         } else if (DISPLAY_VER(dev_priv) >= 11) {
 496                 source_rates = icl_rates;
 497                 size = ARRAY_SIZE(icl_rates);
 498                 if (IS_DG2(dev_priv))
 499                         max_rate = dg2_max_source_rate(intel_dp);
 500                 else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 501                          IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 502                         max_rate = 810000;
 503                 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
 504                         max_rate = ehl_max_source_rate(intel_dp);
 505                 else
 506                         max_rate = icl_max_source_rate(intel_dp);
 507         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
 508                 source_rates = bxt_rates;
 509                 size = ARRAY_SIZE(bxt_rates);
 510         } else if (DISPLAY_VER(dev_priv) == 9) {
 511                 source_rates = skl_rates;
 512                 size = ARRAY_SIZE(skl_rates);
 513         } else if ((IS_HASWELL(dev_priv) && !IS_HASWELL_ULX(dev_priv)) ||
 514                    IS_BROADWELL(dev_priv)) {
 515                 source_rates = hsw_rates;
 516                 size = ARRAY_SIZE(hsw_rates);
 517         } else {
 518                 source_rates = g4x_rates;
 519                 size = ARRAY_SIZE(g4x_rates);
 520         }
 521
 522         vbt_max_rate = vbt_max_link_rate(intel_dp);
 523         if (max_rate && vbt_max_rate)
 524                 max_rate = min(max_rate, vbt_max_rate);
 525         else if (vbt_max_rate)
 526                 max_rate = vbt_max_rate;
 527
 528         if (max_rate)
 529                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 530
 531         intel_dp->source_rates = source_rates;
 532         intel_dp->num_source_rates = size;
 533 }
 534
 535 static int intersect_rates(const int *source_rates, int source_len,
 536                            const int *sink_rates, int sink_len,
 537                            int *common_rates)
 538 {
 539         int i = 0, j = 0, k = 0;
 540
 541         while (i < source_len && j < sink_len) {
 542                 if (source_rates[i] == sink_rates[j]) {
 543                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 544                                 return k;
 545                         common_rates[k] = source_rates[i];
 546                         ++k;
 547                         ++i;
 548                         ++j;
 549                 } else if (source_rates[i] < sink_rates[j]) {
 550                         ++i;
 551                 } else {
 552                         ++j;
 553                 }
 554         }
 555         return k;
 556 }
 557
 558 /* return index of rate in rates array, or -1 if not found */
 559 static int intel_dp_rate_index(const int *rates, int len, int rate)
 560 {
 561         int i;
 562
 563         for (i = 0; i < len; i++)
 564                 if (rate == rates[i])
 565                         return i;
 566
 567         return -1;
 568 }
 569
 570 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 571 {
 572         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 573
 574         drm_WARN_ON(&i915->drm,
 575                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 576
 577         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 578                                                      intel_dp->num_source_rates,
 579                                                      intel_dp->sink_rates,
 580                                                      intel_dp->num_sink_rates,
 581                                                      intel_dp->common_rates);
 582
 583         /* Paranoia, there should always be something in common. */
 584         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 585                 intel_dp->common_rates[0] = 162000;
 586                 intel_dp->num_common_rates = 1;
 587         }
 588 }
 589
 590 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 591                                        u8 lane_count)
 592 {
 593         /*
 594          * FIXME: we need to synchronize the current link parameters with
 595          * hardware readout. Currently fast link training doesn't work on
 596          * boot-up.
 597          */
 598         if (link_rate == 0 ||
 599             link_rate > intel_dp->max_link_rate)
 600                 return false;
 601
 602         if (lane_count == 0 ||
 603             lane_count > intel_dp_max_lane_count(intel_dp))
 604                 return false;
 605
 606         return true;
 607 }
 608
 609 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 610                                                      int link_rate,
 611                                                      u8 lane_count)
 612 {
 613         /* FIXME figure out what we actually want here */
 614         const struct drm_display_mode *fixed_mode =
 615                 intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
 616         int mode_rate, max_rate;
 617
 618         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 619         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 620         if (mode_rate > max_rate)
 621                 return false;
 622
 623         return true;
 624 }
 625
 626 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 627                                             int link_rate, u8 lane_count)
 628 {
 629         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 630         int index;
 631
 632         /*
 633          * TODO: Enable fallback on MST links once MST link compute can handle
 634          * the fallback params.
 635          */
 636         if (intel_dp->is_mst) {
 637                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 638                 return -1;
 639         }
 640
 641         if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 642                 drm_dbg_kms(&i915->drm,
 643                             "Retrying Link training for eDP with max parameters\n");
 644                 intel_dp->use_max_params = true;
 645                 return 0;
 646         }
 647
 648         index = intel_dp_rate_index(intel_dp->common_rates,
 649                                     intel_dp->num_common_rates,
 650                                     link_rate);
 651         if (index > 0) {
 652                 if (intel_dp_is_edp(intel_dp) &&
 653                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 654                                                               intel_dp_common_rate(intel_dp, index - 1),
 655                                                               lane_count)) {
 656                         drm_dbg_kms(&i915->drm,
 657                                     "Retrying Link training for eDP with same parameters\n");
 658                         return 0;
 659                 }
 660                 intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1);
 661                 intel_dp->max_link_lane_count = lane_count;
 662         } else if (lane_count > 1) {
 663                 if (intel_dp_is_edp(intel_dp) &&
 664                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 665                                                               intel_dp_max_common_rate(intel_dp),
 666                                                               lane_count >> 1)) {
 667                         drm_dbg_kms(&i915->drm,
 668                                     "Retrying Link training for eDP with same parameters\n");
 669                         return 0;
 670                 }
 671                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 672                 intel_dp->max_link_lane_count = lane_count >> 1;
 673         } else {
 674                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 675                 return -1;
 676         }
 677
 678         return 0;
 679 }
 680
 681 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 682 {
 683         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 684                        DP_DSC_FEC_OVERHEAD_FACTOR);
 685 }
 686
 687 static int
 688 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 689 {
 690         if (DISPLAY_VER(i915) >= 13)
 691                 return 17280 * 8;
 692         else if (DISPLAY_VER(i915) >= 11)
 693                 return 7680 * 8;
 694         else
 695                 return 6144 * 8;
 696 }
 697
 698 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp)
 699 {
 700         u32 bits_per_pixel = bpp;
 701         int i;
 702
 703         /* Error out if the max bpp is less than smallest allowed valid bpp */
 704         if (bits_per_pixel < valid_dsc_bpp[0]) {
 705                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 706                             bits_per_pixel, valid_dsc_bpp[0]);
 707                 return 0;
 708         }
 709
 710         /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
 711         if (DISPLAY_VER(i915) >= 13) {
 712                 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
 713
 714                 /*
 715                  * According to BSpec, 27 is the max DSC output bpp,
 716                  * 8 is the min DSC output bpp.
 717                  * While we can still clamp higher bpp values to 27, saving bandwidth,
 718                  * if it is required to oompress up to bpp < 8, means we can't do
 719                  * that and probably means we can't fit the required mode, even with
 720                  * DSC enabled.
 721                  */
 722                 if (bits_per_pixel < 8) {
 723                         drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
 724                                     bits_per_pixel);
 725                         return 0;
 726                 }
 727                 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
 728         } else {
 729                 /* Find the nearest match in the array of known BPPs from VESA */
 730                 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 731                         if (bits_per_pixel < valid_dsc_bpp[i + 1])
 732                                 break;
 733                 }
 734                 drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",
 735                             bits_per_pixel, valid_dsc_bpp[i]);
 736
 737                 bits_per_pixel = valid_dsc_bpp[i];
 738         }
 739
 740         return bits_per_pixel;
 741 }
 742
 743 static
 744 u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
 745                                        u32 mode_clock, u32 mode_hdisplay,
 746                                        bool bigjoiner)
 747 {
 748         u32 max_bpp_small_joiner_ram;
 749
 750         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 751         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
 752
 753         if (bigjoiner) {
 754                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
 755                 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
 756                 int ppc = 2;
 757                 u32 max_bpp_bigjoiner =
 758                         i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
 759                         intel_dp_mode_to_fec_clock(mode_clock);
 760
 761                 max_bpp_small_joiner_ram *= 2;
 762
 763                 return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
 764         }
 765
 766         return max_bpp_small_joiner_ram;
 767 }
 768
 769 u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
 770                                         u32 link_clock, u32 lane_count,
 771                                         u32 mode_clock, u32 mode_hdisplay,
 772                                         bool bigjoiner,
 773                                         enum intel_output_format output_format,
 774                                         u32 pipe_bpp,
 775                                         u32 timeslots)
 776 {
 777         u32 bits_per_pixel, joiner_max_bpp;
 778
 779         /*
 780          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 781          * (LinkSymbolClock)* 8 * (TimeSlots / 64)
 782          * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
 783          * for MST -> TimeSlots has to be calculated, based on mode requirements
 784          *
 785          * Due to FEC overhead, the available bw is reduced to 97.2261%.
 786          * To support the given mode:
 787          * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
 788          * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
 789          * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
 790          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
 791          *                     (ModeClock / FEC Overhead)
 792          * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
 793          *                     (ModeClock / FEC Overhead * 8)
 794          */
 795         bits_per_pixel = ((link_clock * lane_count) * timeslots) /
 796                          (intel_dp_mode_to_fec_clock(mode_clock) * 8);
 797
 798         /* Bandwidth required for 420 is half, that of 444 format */
 799         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 800                 bits_per_pixel *= 2;
 801
 802         /*
 803          * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
 804          * supported PPS value can be 63.9375 and with the further
 805          * mention that for 420, 422 formats, bpp should be programmed double
 806          * the target bpp restricting our target bpp to be 31.9375 at max.
 807          */
 808         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 809                 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
 810
 811         drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "
 812                                 "total bw %u pixel clock %u\n",
 813                                 bits_per_pixel, timeslots,
 814                                 (link_clock * lane_count * 8),
 815                                 intel_dp_mode_to_fec_clock(mode_clock));
 816
 817         joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
 818                                                             mode_hdisplay, bigjoiner);
 819         bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
 820
 821         bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);
 822
 823         return bits_per_pixel;
 824 }
 825
 826 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
 827                                 int mode_clock, int mode_hdisplay,
 828                                 bool bigjoiner)
 829 {
 830         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 831         u8 min_slice_count, i;
 832         int max_slice_width;
 833
 834         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 835                 min_slice_count = DIV_ROUND_UP(mode_clock,
 836                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 837         else
 838                 min_slice_count = DIV_ROUND_UP(mode_clock,
 839                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 840
 841         /*
 842          * Due to some DSC engine BW limitations, we need to enable second
 843          * slice and VDSC engine, whenever we approach close enough to max CDCLK
 844          */
 845         if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))
 846                 min_slice_count = max_t(u8, min_slice_count, 2);
 847
 848         max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
 849         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 850                 drm_dbg_kms(&i915->drm,
 851                             "Unsupported slice width %d by DP DSC Sink device\n",
 852                             max_slice_width);
 853                 return 0;
 854         }
 855         /* Also take into account max slice width */
 856         min_slice_count = max_t(u8, min_slice_count,
 857                                 DIV_ROUND_UP(mode_hdisplay,
 858                                              max_slice_width));
 859
 860         /* Find the closest match to the valid slice count values */
 861         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 862                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 863
 864                 if (test_slice_count >
 865                     drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
 866                         break;
 867
 868                 /* big joiner needs small joiner to be enabled */
 869                 if (bigjoiner && test_slice_count < 4)
 870                         continue;
 871
 872                 if (min_slice_count <= test_slice_count)
 873                         return test_slice_count;
 874         }
 875
 876         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 877                     min_slice_count);
 878         return 0;
 879 }
 880
 881 static bool source_can_output(struct intel_dp *intel_dp,
 882                               enum intel_output_format format)
 883 {
 884         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 885
 886         switch (format) {
 887         case INTEL_OUTPUT_FORMAT_RGB:
 888                 return true;
 889
 890         case INTEL_OUTPUT_FORMAT_YCBCR444:
 891                 /*
 892                  * No YCbCr output support on gmch platforms.
 893                  * Also, ILK doesn't seem capable of DP YCbCr output.
 894                  * The displayed image is severly corrupted. SNB+ is fine.
 895                  */
 896                 return !HAS_GMCH(i915) && !IS_IRONLAKE(i915);
 897
 898         case INTEL_OUTPUT_FORMAT_YCBCR420:
 899                 /* Platform < Gen 11 cannot output YCbCr420 format */
 900                 return DISPLAY_VER(i915) >= 11;
 901
 902         default:
 903                 MISSING_CASE(format);
 904                 return false;
 905         }
 906 }
 907
 908 static bool
 909 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
 910                          enum intel_output_format sink_format)
 911 {
 912         if (!drm_dp_is_branch(intel_dp->dpcd))
 913                 return false;
 914
 915         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 916                 return intel_dp->dfp.rgb_to_ycbcr;
 917
 918         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 919                 return intel_dp->dfp.rgb_to_ycbcr &&
 920                         intel_dp->dfp.ycbcr_444_to_420;
 921
 922         return false;
 923 }
 924
 925 static bool
 926 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
 927                               enum intel_output_format sink_format)
 928 {
 929         if (!drm_dp_is_branch(intel_dp->dpcd))
 930                 return false;
 931
 932         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 933                 return intel_dp->dfp.ycbcr_444_to_420;
 934
 935         return false;
 936 }
 937
 938 static bool
 939 dfp_can_convert(struct intel_dp *intel_dp,
 940                 enum intel_output_format output_format,
 941                 enum intel_output_format sink_format)
 942 {
 943         switch (output_format) {
 944         case INTEL_OUTPUT_FORMAT_RGB:
 945                 return dfp_can_convert_from_rgb(intel_dp, sink_format);
 946         case INTEL_OUTPUT_FORMAT_YCBCR444:
 947                 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
 948         default:
 949                 MISSING_CASE(output_format);
 950                 return false;
 951         }
 952
 953         return false;
 954 }
 955
 956 static enum intel_output_format
 957 intel_dp_output_format(struct intel_connector *connector,
 958                        enum intel_output_format sink_format)
 959 {
 960         struct intel_dp *intel_dp = intel_attached_dp(connector);
 961         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 962         enum intel_output_format force_dsc_output_format =
 963                 intel_dp->force_dsc_output_format;
 964         enum intel_output_format output_format;
 965         if (force_dsc_output_format) {
 966                 if (source_can_output(intel_dp, force_dsc_output_format) &&
 967                     (!drm_dp_is_branch(intel_dp->dpcd) ||
 968                      sink_format != force_dsc_output_format ||
 969                      dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
 970                         return force_dsc_output_format;
 971
 972                 drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");
 973         }
 974
 975         if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
 976             dfp_can_convert_from_rgb(intel_dp, sink_format))
 977                 output_format = INTEL_OUTPUT_FORMAT_RGB;
 978
 979         else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
 980                  dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
 981                 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
 982
 983         else
 984                 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
 985
 986         drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));
 987
 988         return output_format;
 989 }
 990
 991 int intel_dp_min_bpp(enum intel_output_format output_format)
 992 {
 993         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 994                 return 6 * 3;
 995         else
 996                 return 8 * 3;
 997 }
 998
 999 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1000 {
1001         /*
1002          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1003          * format of the number of bytes per pixel will be half the number
1004          * of bytes of RGB pixel.
1005          */
1006         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1007                 bpp /= 2;
1008
1009         return bpp;
1010 }
1011
1012 static enum intel_output_format
1013 intel_dp_sink_format(struct intel_connector *connector,
1014                      const struct drm_display_mode *mode)
1015 {
1016         const struct drm_display_info *info = &connector->base.display_info;
1017
1018         if (drm_mode_is_420_only(info, mode))
1019                 return INTEL_OUTPUT_FORMAT_YCBCR420;
1020
1021         return INTEL_OUTPUT_FORMAT_RGB;
1022 }
1023
1024 static int
1025 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1026                              const struct drm_display_mode *mode)
1027 {
1028         enum intel_output_format output_format, sink_format;
1029
1030         sink_format = intel_dp_sink_format(connector, mode);
1031
1032         output_format = intel_dp_output_format(connector, sink_format);
1033
1034         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1035 }
1036
1037 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
1038                                   int hdisplay)
1039 {
1040         /*
1041          * Older platforms don't like hdisplay==4096 with DP.
1042          *
1043          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1044          * and frame counter increment), but we don't get vblank interrupts,
1045          * and the pipe underruns immediately. The link also doesn't seem
1046          * to get trained properly.
1047          *
1048          * On CHV the vblank interrupts don't seem to disappear but
1049          * otherwise the symptoms are similar.
1050          *
1051          * TODO: confirm the behaviour on HSW+
1052          */
1053         return hdisplay == 4096 && !HAS_DDI(dev_priv);
1054 }
1055
1056 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1057 {
1058         struct intel_connector *connector = intel_dp->attached_connector;
1059         const struct drm_display_info *info = &connector->base.display_info;
1060         int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1061
1062         /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1063         if (max_tmds_clock && info->max_tmds_clock)
1064                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1065
1066         return max_tmds_clock;
1067 }
1068
1069 static enum drm_mode_status
1070 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1071                           int clock, int bpc,
1072                           enum intel_output_format sink_format,
1073                           bool respect_downstream_limits)
1074 {
1075         int tmds_clock, min_tmds_clock, max_tmds_clock;
1076
1077         if (!respect_downstream_limits)
1078                 return MODE_OK;
1079
1080         tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1081
1082         min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1083         max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1084
1085         if (min_tmds_clock && tmds_clock < min_tmds_clock)
1086                 return MODE_CLOCK_LOW;
1087
1088         if (max_tmds_clock && tmds_clock > max_tmds_clock)
1089                 return MODE_CLOCK_HIGH;
1090
1091         return MODE_OK;
1092 }
1093
1094 static enum drm_mode_status
1095 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1096                                const struct drm_display_mode *mode,
1097                                int target_clock)
1098 {
1099         struct intel_dp *intel_dp = intel_attached_dp(connector);
1100         const struct drm_display_info *info = &connector->base.display_info;
1101         enum drm_mode_status status;
1102         enum intel_output_format sink_format;
1103
1104         /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1105         if (intel_dp->dfp.pcon_max_frl_bw) {
1106                 int target_bw;
1107                 int max_frl_bw;
1108                 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1109
1110                 target_bw = bpp * target_clock;
1111
1112                 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1113
1114                 /* converting bw from Gbps to Kbps*/
1115                 max_frl_bw = max_frl_bw * 1000000;
1116
1117                 if (target_bw > max_frl_bw)
1118                         return MODE_CLOCK_HIGH;
1119
1120                 return MODE_OK;
1121         }
1122
1123         if (intel_dp->dfp.max_dotclock &&
1124             target_clock > intel_dp->dfp.max_dotclock)
1125                 return MODE_CLOCK_HIGH;
1126
1127         sink_format = intel_dp_sink_format(connector, mode);
1128
1129         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1130         status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1131                                            8, sink_format, true);
1132
1133         if (status != MODE_OK) {
1134                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1135                     !connector->base.ycbcr_420_allowed ||
1136                     !drm_mode_is_420_also(info, mode))
1137                         return status;
1138                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1139                 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1140                                                    8, sink_format, true);
1141                 if (status != MODE_OK)
1142                         return status;
1143         }
1144
1145         return MODE_OK;
1146 }
1147
1148 bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
1149                              int hdisplay, int clock)
1150 {
1151         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1152
1153         if (!intel_dp_can_bigjoiner(intel_dp))
1154                 return false;
1155
1156         return clock > i915->max_dotclk_freq || hdisplay > 5120;
1157 }
1158
1159 static enum drm_mode_status
1160 intel_dp_mode_valid(struct drm_connector *_connector,
1161                     struct drm_display_mode *mode)
1162 {
1163         struct intel_connector *connector = to_intel_connector(_connector);
1164         struct intel_dp *intel_dp = intel_attached_dp(connector);
1165         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1166         const struct drm_display_mode *fixed_mode;
1167         int target_clock = mode->clock;
1168         int max_rate, mode_rate, max_lanes, max_link_clock;
1169         int max_dotclk = dev_priv->max_dotclk_freq;
1170         u16 dsc_max_compressed_bpp = 0;
1171         u8 dsc_slice_count = 0;
1172         enum drm_mode_status status;
1173         bool dsc = false, bigjoiner = false;
1174
1175         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1176                 return MODE_H_ILLEGAL;
1177
1178         fixed_mode = intel_panel_fixed_mode(connector, mode);
1179         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1180                 status = intel_panel_mode_valid(connector, mode);
1181                 if (status != MODE_OK)
1182                         return status;
1183
1184                 target_clock = fixed_mode->clock;
1185         }
1186
1187         if (mode->clock < 10000)
1188                 return MODE_CLOCK_LOW;
1189
1190         if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) {
1191                 bigjoiner = true;
1192                 max_dotclk *= 2;
1193         }
1194         if (target_clock > max_dotclk)
1195                 return MODE_CLOCK_HIGH;
1196
1197         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
1198                 return MODE_H_ILLEGAL;
1199
1200         max_link_clock = intel_dp_max_link_rate(intel_dp);
1201         max_lanes = intel_dp_max_lane_count(intel_dp);
1202
1203         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
1204         mode_rate = intel_dp_link_required(target_clock,
1205                                            intel_dp_mode_min_output_bpp(connector, mode));
1206
1207         if (HAS_DSC(dev_priv) &&
1208             drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) {
1209                 enum intel_output_format sink_format, output_format;
1210                 int pipe_bpp;
1211
1212                 sink_format = intel_dp_sink_format(connector, mode);
1213                 output_format = intel_dp_output_format(connector, sink_format);
1214                 /*
1215                  * TBD pass the connector BPC,
1216                  * for now U8_MAX so that max BPC on that platform would be picked
1217                  */
1218                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1219
1220                 /*
1221                  * Output bpp is stored in 6.4 format so right shift by 4 to get the
1222                  * integer value since we support only integer values of bpp.
1223                  */
1224                 if (intel_dp_is_edp(intel_dp)) {
1225                         dsc_max_compressed_bpp =
1226                                 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1227                         dsc_slice_count =
1228                                 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1229                                                                 true);
1230                 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1231                         dsc_max_compressed_bpp =
1232                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1233                                                                     max_link_clock,
1234                                                                     max_lanes,
1235                                                                     target_clock,
1236                                                                     mode->hdisplay,
1237                                                                     bigjoiner,
1238                                                                     output_format,
1239                                                                     pipe_bpp, 64);
1240                         dsc_slice_count =
1241                                 intel_dp_dsc_get_slice_count(connector,
1242                                                              target_clock,
1243                                                              mode->hdisplay,
1244                                                              bigjoiner);
1245                 }
1246
1247                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1248         }
1249
1250         /*
1251          * Big joiner configuration needs DSC for TGL which is not true for
1252          * XE_LPD where uncompressed joiner is supported.
1253          */
1254         if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc)
1255                 return MODE_CLOCK_HIGH;
1256
1257         if (mode_rate > max_rate && !dsc)
1258                 return MODE_CLOCK_HIGH;
1259
1260         status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1261         if (status != MODE_OK)
1262                 return status;
1263
1264         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1265 }
1266
1267 bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
1268 {
1269         return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
1270 }
1271
1272 bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
1273 {
1274         return DISPLAY_VER(i915) >= 10;
1275 }
1276
1277 static void snprintf_int_array(char *str, size_t len,
1278                                const int *array, int nelem)
1279 {
1280         int i;
1281
1282         str[0] = '\0';
1283
1284         for (i = 0; i < nelem; i++) {
1285                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1286                 if (r >= len)
1287                         return;
1288                 str += r;
1289                 len -= r;
1290         }
1291 }
1292
1293 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1294 {
1295         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1296         char str[128]; /* FIXME: too big for stack? */
1297
1298         if (!drm_debug_enabled(DRM_UT_KMS))
1299                 return;
1300
1301         snprintf_int_array(str, sizeof(str),
1302                            intel_dp->source_rates, intel_dp->num_source_rates);
1303         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
1304
1305         snprintf_int_array(str, sizeof(str),
1306                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1307         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
1308
1309         snprintf_int_array(str, sizeof(str),
1310                            intel_dp->common_rates, intel_dp->num_common_rates);
1311         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
1312 }
1313
1314 int
1315 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1316 {
1317         int len;
1318
1319         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1320
1321         return intel_dp_common_rate(intel_dp, len - 1);
1322 }
1323
1324 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1325 {
1326         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1327         int i = intel_dp_rate_index(intel_dp->sink_rates,
1328                                     intel_dp->num_sink_rates, rate);
1329
1330         if (drm_WARN_ON(&i915->drm, i < 0))
1331                 i = 0;
1332
1333         return i;
1334 }
1335
1336 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1337                            u8 *link_bw, u8 *rate_select)
1338 {
1339         /* eDP 1.4 rate select method. */
1340         if (intel_dp->use_rate_select) {
1341                 *link_bw = 0;
1342                 *rate_select =
1343                         intel_dp_rate_select(intel_dp, port_clock);
1344         } else {
1345                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1346                 *rate_select = 0;
1347         }
1348 }
1349
1350 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1351 {
1352         struct intel_connector *connector = intel_dp->attached_connector;
1353
1354         return connector->base.display_info.is_hdmi;
1355 }
1356
1357 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1358                                          const struct intel_crtc_state *pipe_config)
1359 {
1360         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1361         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1362
1363         if (DISPLAY_VER(dev_priv) >= 12)
1364                 return true;
1365
1366         if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1367                 return true;
1368
1369         return false;
1370 }
1371
1372 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1373                                   const struct intel_connector *connector,
1374                                   const struct intel_crtc_state *pipe_config)
1375 {
1376         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1377                 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1378 }
1379
1380 static bool intel_dp_supports_dsc(const struct intel_connector *connector,
1381                                   const struct intel_crtc_state *crtc_state)
1382 {
1383         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
1384                 return false;
1385
1386         return intel_dsc_source_support(crtc_state) &&
1387                 drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd);
1388 }
1389
1390 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1391                                      const struct intel_crtc_state *crtc_state,
1392                                      int bpc, bool respect_downstream_limits)
1393 {
1394         int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1395
1396         /*
1397          * Current bpc could already be below 8bpc due to
1398          * FDI bandwidth constraints or other limits.
1399          * HDMI minimum is 8bpc however.
1400          */
1401         bpc = max(bpc, 8);
1402
1403         /*
1404          * We will never exceed downstream TMDS clock limits while
1405          * attempting deep color. If the user insists on forcing an
1406          * out of spec mode they will have to be satisfied with 8bpc.
1407          */
1408         if (!respect_downstream_limits)
1409                 bpc = 8;
1410
1411         for (; bpc >= 8; bpc -= 2) {
1412                 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1413                                             intel_dp_has_hdmi_sink(intel_dp)) &&
1414                     intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1415                                               respect_downstream_limits) == MODE_OK)
1416                         return bpc;
1417         }
1418
1419         return -EINVAL;
1420 }
1421
1422 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1423                             const struct intel_crtc_state *crtc_state,
1424                             bool respect_downstream_limits)
1425 {
1426         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1427         struct intel_connector *intel_connector = intel_dp->attached_connector;
1428         int bpp, bpc;
1429
1430         bpc = crtc_state->pipe_bpp / 3;
1431
1432         if (intel_dp->dfp.max_bpc)
1433                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1434
1435         if (intel_dp->dfp.min_tmds_clock) {
1436                 int max_hdmi_bpc;
1437
1438                 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1439                                                          respect_downstream_limits);
1440                 if (max_hdmi_bpc < 0)
1441                         return 0;
1442
1443                 bpc = min(bpc, max_hdmi_bpc);
1444         }
1445
1446         bpp = bpc * 3;
1447         if (intel_dp_is_edp(intel_dp)) {
1448                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1449                 if (intel_connector->base.display_info.bpc == 0 &&
1450                     intel_connector->panel.vbt.edp.bpp &&
1451                     intel_connector->panel.vbt.edp.bpp < bpp) {
1452                         drm_dbg_kms(&dev_priv->drm,
1453                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
1454                                     intel_connector->panel.vbt.edp.bpp);
1455                         bpp = intel_connector->panel.vbt.edp.bpp;
1456                 }
1457         }
1458
1459         return bpp;
1460 }
1461
1462 /* Adjust link config limits based on compliance test requests. */
1463 void
1464 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1465                                   struct intel_crtc_state *pipe_config,
1466                                   struct link_config_limits *limits)
1467 {
1468         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1469
1470         /* For DP Compliance we override the computed bpp for the pipe */
1471         if (intel_dp->compliance.test_data.bpc != 0) {
1472                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1473
1474                 limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
1475                 pipe_config->dither_force_disable = bpp == 6 * 3;
1476
1477                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
1478         }
1479
1480         /* Use values requested by Compliance Test Request */
1481         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1482                 int index;
1483
1484                 /* Validate the compliance test data since max values
1485                  * might have changed due to link train fallback.
1486                  */
1487                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1488                                                intel_dp->compliance.test_lane_count)) {
1489                         index = intel_dp_rate_index(intel_dp->common_rates,
1490                                                     intel_dp->num_common_rates,
1491                                                     intel_dp->compliance.test_link_rate);
1492                         if (index >= 0)
1493                                 limits->min_rate = limits->max_rate =
1494                                         intel_dp->compliance.test_link_rate;
1495                         limits->min_lane_count = limits->max_lane_count =
1496                                 intel_dp->compliance.test_lane_count;
1497                 }
1498         }
1499 }
1500
1501 static bool has_seamless_m_n(struct intel_connector *connector)
1502 {
1503         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1504
1505         /*
1506          * Seamless M/N reprogramming only implemented
1507          * for BDW+ double buffered M/N registers so far.
1508          */
1509         return HAS_DOUBLE_BUFFERED_M_N(i915) &&
1510                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1511 }
1512
1513 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1514                                const struct drm_connector_state *conn_state)
1515 {
1516         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1517         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1518
1519         /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1520         if (has_seamless_m_n(connector))
1521                 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1522         else
1523                 return adjusted_mode->crtc_clock;
1524 }
1525
1526 /* Optimize link config in order: max bpp, min clock, min lanes */
1527 static int
1528 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1529                                   struct intel_crtc_state *pipe_config,
1530                                   const struct drm_connector_state *conn_state,
1531                                   const struct link_config_limits *limits)
1532 {
1533         int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1534         int mode_rate, link_rate, link_avail;
1535
1536         for (bpp = to_bpp_int(limits->link.max_bpp_x16);
1537              bpp >= to_bpp_int(limits->link.min_bpp_x16);
1538              bpp -= 2 * 3) {
1539                 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1540
1541                 mode_rate = intel_dp_link_required(clock, link_bpp);
1542
1543                 for (i = 0; i < intel_dp->num_common_rates; i++) {
1544                         link_rate = intel_dp_common_rate(intel_dp, i);
1545                         if (link_rate < limits->min_rate ||
1546                             link_rate > limits->max_rate)
1547                                 continue;
1548
1549                         for (lane_count = limits->min_lane_count;
1550                              lane_count <= limits->max_lane_count;
1551                              lane_count <<= 1) {
1552                                 link_avail = intel_dp_max_data_rate(link_rate,
1553                                                                     lane_count);
1554
1555                                 if (mode_rate <= link_avail) {
1556                                         pipe_config->lane_count = lane_count;
1557                                         pipe_config->pipe_bpp = bpp;
1558                                         pipe_config->port_clock = link_rate;
1559
1560                                         return 0;
1561                                 }
1562                         }
1563                 }
1564         }
1565
1566         return -EINVAL;
1567 }
1568
1569 static
1570 u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915)
1571 {
1572         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1573         if (DISPLAY_VER(i915) >= 12)
1574                 return 12;
1575         if (DISPLAY_VER(i915) == 11)
1576                 return 10;
1577
1578         return 0;
1579 }
1580
1581 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1582                                  u8 max_req_bpc)
1583 {
1584         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1585         int i, num_bpc;
1586         u8 dsc_bpc[3] = {};
1587         u8 dsc_max_bpc;
1588
1589         dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915);
1590
1591         if (!dsc_max_bpc)
1592                 return dsc_max_bpc;
1593
1594         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
1595
1596         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1597                                                        dsc_bpc);
1598         for (i = 0; i < num_bpc; i++) {
1599                 if (dsc_max_bpc >= dsc_bpc[i])
1600                         return dsc_bpc[i] * 3;
1601         }
1602
1603         return 0;
1604 }
1605
1606 static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915)
1607 {
1608         return DISPLAY_VER(i915) >= 14 ? 2 : 1;
1609 }
1610
1611 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1612 {
1613         return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1614                 DP_DSC_MINOR_SHIFT;
1615 }
1616
1617 static int intel_dp_get_slice_height(int vactive)
1618 {
1619         int slice_height;
1620
1621         /*
1622          * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1623          * lines is an optimal slice height, but any size can be used as long as
1624          * vertical active integer multiple and maximum vertical slice count
1625          * requirements are met.
1626          */
1627         for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1628                 if (vactive % slice_height == 0)
1629                         return slice_height;
1630
1631         /*
1632          * Highly unlikely we reach here as most of the resolutions will end up
1633          * finding appropriate slice_height in above loop but returning
1634          * slice_height as 2 here as it should work with all resolutions.
1635          */
1636         return 2;
1637 }
1638
1639 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1640                                        struct intel_crtc_state *crtc_state)
1641 {
1642         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1643         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1644         u8 line_buf_depth;
1645         int ret;
1646
1647         /*
1648          * RC_MODEL_SIZE is currently a constant across all configurations.
1649          *
1650          * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1651          * DP_DSC_RC_BUF_SIZE for this.
1652          */
1653         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1654         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1655
1656         vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1657
1658         ret = intel_dsc_compute_params(crtc_state);
1659         if (ret)
1660                 return ret;
1661
1662         vdsc_cfg->dsc_version_major =
1663                 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1664                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1665         vdsc_cfg->dsc_version_minor =
1666                 min(intel_dp_source_dsc_version_minor(i915),
1667                     intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1668         if (vdsc_cfg->convert_rgb)
1669                 vdsc_cfg->convert_rgb =
1670                         connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1671                         DP_DSC_RGB;
1672
1673         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd);
1674         if (!line_buf_depth) {
1675                 drm_dbg_kms(&i915->drm,
1676                             "DSC Sink Line Buffer Depth invalid\n");
1677                 return -EINVAL;
1678         }
1679
1680         if (vdsc_cfg->dsc_version_minor == 2)
1681                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
1682                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
1683         else
1684                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
1685                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
1686
1687         vdsc_cfg->block_pred_enable =
1688                 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1689                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1690
1691         return drm_dsc_compute_rc_parameters(vdsc_cfg);
1692 }
1693
1694 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1695                                          enum intel_output_format output_format)
1696 {
1697         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1698         u8 sink_dsc_format;
1699
1700         switch (output_format) {
1701         case INTEL_OUTPUT_FORMAT_RGB:
1702                 sink_dsc_format = DP_DSC_RGB;
1703                 break;
1704         case INTEL_OUTPUT_FORMAT_YCBCR444:
1705                 sink_dsc_format = DP_DSC_YCbCr444;
1706                 break;
1707         case INTEL_OUTPUT_FORMAT_YCBCR420:
1708                 if (min(intel_dp_source_dsc_version_minor(i915),
1709                         intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1710                         return false;
1711                 sink_dsc_format = DP_DSC_YCbCr420_Native;
1712                 break;
1713         default:
1714                 return false;
1715         }
1716
1717         return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1718 }
1719
1720 static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock,
1721                                             u32 lane_count, u32 mode_clock,
1722                                             enum intel_output_format output_format,
1723                                             int timeslots)
1724 {
1725         u32 available_bw, required_bw;
1726
1727         available_bw = (link_clock * lane_count * timeslots)  / 8;
1728         required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock));
1729
1730         return available_bw > required_bw;
1731 }
1732
1733 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1734                                    struct intel_crtc_state *pipe_config,
1735                                    struct link_config_limits *limits,
1736                                    u16 compressed_bpp,
1737                                    int timeslots)
1738 {
1739         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1740         int link_rate, lane_count;
1741         int i;
1742
1743         for (i = 0; i < intel_dp->num_common_rates; i++) {
1744                 link_rate = intel_dp_common_rate(intel_dp, i);
1745                 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1746                         continue;
1747
1748                 for (lane_count = limits->min_lane_count;
1749                      lane_count <= limits->max_lane_count;
1750                      lane_count <<= 1) {
1751                         if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count,
1752                                                              adjusted_mode->clock,
1753                                                              pipe_config->output_format,
1754                                                              timeslots))
1755                                 continue;
1756
1757                         pipe_config->lane_count = lane_count;
1758                         pipe_config->port_clock = link_rate;
1759
1760                         return 0;
1761                 }
1762         }
1763
1764         return -EINVAL;
1765 }
1766
1767 static
1768 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
1769                                             struct intel_crtc_state *pipe_config,
1770                                             int bpc)
1771 {
1772         u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
1773
1774         if (max_bppx16)
1775                 return max_bppx16;
1776         /*
1777          * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
1778          * values as given in spec Table 2-157 DP v2.0
1779          */
1780         switch (pipe_config->output_format) {
1781         case INTEL_OUTPUT_FORMAT_RGB:
1782         case INTEL_OUTPUT_FORMAT_YCBCR444:
1783                 return (3 * bpc) << 4;
1784         case INTEL_OUTPUT_FORMAT_YCBCR420:
1785                 return (3 * (bpc / 2)) << 4;
1786         default:
1787                 MISSING_CASE(pipe_config->output_format);
1788                 break;
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config)
1795 {
1796         /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
1797         switch (pipe_config->output_format) {
1798         case INTEL_OUTPUT_FORMAT_RGB:
1799         case INTEL_OUTPUT_FORMAT_YCBCR444:
1800                 return 8;
1801         case INTEL_OUTPUT_FORMAT_YCBCR420:
1802                 return 6;
1803         default:
1804                 MISSING_CASE(pipe_config->output_format);
1805                 break;
1806         }
1807
1808         return 0;
1809 }
1810
1811 static int dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
1812                                        struct intel_crtc_state *pipe_config,
1813                                        int bpc)
1814 {
1815         return intel_dp_dsc_max_sink_compressed_bppx16(connector,
1816                                                        pipe_config, bpc) >> 4;
1817 }
1818
1819 static int dsc_src_min_compressed_bpp(void)
1820 {
1821         /* Min Compressed bpp supported by source is 8 */
1822         return 8;
1823 }
1824
1825 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
1826 {
1827         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1828
1829         /*
1830          * Max Compressed bpp for Gen 13+ is 27bpp.
1831          * For earlier platform is 23bpp. (Bspec:49259).
1832          */
1833         if (DISPLAY_VER(i915) <= 12)
1834                 return 23;
1835         else
1836                 return 27;
1837 }
1838
1839 /*
1840  * From a list of valid compressed bpps try different compressed bpp and find a
1841  * suitable link configuration that can support it.
1842  */
1843 static int
1844 icl_dsc_compute_link_config(struct intel_dp *intel_dp,
1845                             struct intel_crtc_state *pipe_config,
1846                             struct link_config_limits *limits,
1847                             int dsc_max_bpp,
1848                             int dsc_min_bpp,
1849                             int pipe_bpp,
1850                             int timeslots)
1851 {
1852         int i, ret;
1853
1854         /* Compressed BPP should be less than the Input DSC bpp */
1855         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1856
1857         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1858                 if (valid_dsc_bpp[i] < dsc_min_bpp ||
1859                     valid_dsc_bpp[i] > dsc_max_bpp)
1860                         break;
1861
1862                 ret = dsc_compute_link_config(intel_dp,
1863                                               pipe_config,
1864                                               limits,
1865                                               valid_dsc_bpp[i],
1866                                               timeslots);
1867                 if (ret == 0) {
1868                         pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
1869                         return 0;
1870                 }
1871         }
1872
1873         return -EINVAL;
1874 }
1875
1876 /*
1877  * From XE_LPD onwards we supports compression bpps in steps of 1 up to
1878  * uncompressed bpp-1. So we start from max compressed bpp and see if any
1879  * link configuration is able to support that compressed bpp, if not we
1880  * step down and check for lower compressed bpp.
1881  */
1882 static int
1883 xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
1884                               struct intel_crtc_state *pipe_config,
1885                               struct link_config_limits *limits,
1886                               int dsc_max_bpp,
1887                               int dsc_min_bpp,
1888                               int pipe_bpp,
1889                               int timeslots)
1890 {
1891         u16 compressed_bpp;
1892         int ret;
1893
1894         /* Compressed BPP should be less than the Input DSC bpp */
1895         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
1896
1897         for (compressed_bpp = dsc_max_bpp;
1898              compressed_bpp >= dsc_min_bpp;
1899              compressed_bpp--) {
1900                 ret = dsc_compute_link_config(intel_dp,
1901                                               pipe_config,
1902                                               limits,
1903                                               compressed_bpp,
1904                                               timeslots);
1905                 if (ret == 0) {
1906                         pipe_config->dsc.compressed_bpp = compressed_bpp;
1907                         return 0;
1908                 }
1909         }
1910         return -EINVAL;
1911 }
1912
1913 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
1914                                       const struct intel_connector *connector,
1915                                       struct intel_crtc_state *pipe_config,
1916                                       struct link_config_limits *limits,
1917                                       int pipe_bpp,
1918                                       int timeslots)
1919 {
1920         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1921         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1922         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
1923         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
1924         int dsc_joiner_max_bpp;
1925
1926         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
1927         dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
1928         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
1929         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
1930
1931         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
1932         dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3);
1933         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
1934
1935         dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,
1936                                                                 adjusted_mode->hdisplay,
1937                                                                 pipe_config->bigjoiner_pipes);
1938         dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
1939         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
1940
1941         if (DISPLAY_VER(i915) >= 13)
1942                 return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
1943                                                      dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
1944         return icl_dsc_compute_link_config(intel_dp, pipe_config, limits,
1945                                            dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);
1946 }
1947
1948 static
1949 u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915)
1950 {
1951         /* Min DSC Input BPC for ICL+ is 8 */
1952         return HAS_DSC(i915) ? 8 : 0;
1953 }
1954
1955 static
1956 bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
1957                                 struct drm_connector_state *conn_state,
1958                                 struct link_config_limits *limits,
1959                                 int pipe_bpp)
1960 {
1961         u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp;
1962
1963         dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
1964         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
1965
1966         dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
1967         dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
1968
1969         return pipe_bpp >= dsc_min_pipe_bpp &&
1970                pipe_bpp <= dsc_max_pipe_bpp;
1971 }
1972
1973 static
1974 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
1975                                 struct drm_connector_state *conn_state,
1976                                 struct link_config_limits *limits)
1977 {
1978         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1979         int forced_bpp;
1980
1981         if (!intel_dp->force_dsc_bpc)
1982                 return 0;
1983
1984         forced_bpp = intel_dp->force_dsc_bpc * 3;
1985
1986         if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) {
1987                 drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);
1988                 return forced_bpp;
1989         }
1990
1991         drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
1992                     intel_dp->force_dsc_bpc);
1993
1994         return 0;
1995 }
1996
1997 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
1998                                          struct intel_crtc_state *pipe_config,
1999                                          struct drm_connector_state *conn_state,
2000                                          struct link_config_limits *limits,
2001                                          int timeslots)
2002 {
2003         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2004         const struct intel_connector *connector =
2005                 to_intel_connector(conn_state->connector);
2006         u8 max_req_bpc = conn_state->max_requested_bpc;
2007         u8 dsc_max_bpc, dsc_max_bpp;
2008         u8 dsc_min_bpc, dsc_min_bpp;
2009         u8 dsc_bpc[3] = {};
2010         int forced_bpp, pipe_bpp;
2011         int num_bpc, i, ret;
2012
2013         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2014
2015         if (forced_bpp) {
2016                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2017                                                  limits, forced_bpp, timeslots);
2018                 if (ret == 0) {
2019                         pipe_config->pipe_bpp = forced_bpp;
2020                         return 0;
2021                 }
2022         }
2023
2024         dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2025         if (!dsc_max_bpc)
2026                 return -EINVAL;
2027
2028         dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
2029         dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
2030
2031         dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
2032         dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
2033
2034         /*
2035          * Get the maximum DSC bpc that will be supported by any valid
2036          * link configuration and compressed bpp.
2037          */
2038         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2039         for (i = 0; i < num_bpc; i++) {
2040                 pipe_bpp = dsc_bpc[i] * 3;
2041                 if (pipe_bpp < dsc_min_bpp)
2042                         break;
2043                 if (pipe_bpp > dsc_max_bpp)
2044                         continue;
2045                 ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,
2046                                                  limits, pipe_bpp, timeslots);
2047                 if (ret == 0) {
2048                         pipe_config->pipe_bpp = pipe_bpp;
2049                         return 0;
2050                 }
2051         }
2052
2053         return -EINVAL;
2054 }
2055
2056 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2057                                           struct intel_crtc_state *pipe_config,
2058                                           struct drm_connector_state *conn_state,
2059                                           struct link_config_limits *limits)
2060 {
2061         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2062         struct intel_connector *connector =
2063                 to_intel_connector(conn_state->connector);
2064         int pipe_bpp, forced_bpp;
2065         int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2066         int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2067
2068         forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits);
2069
2070         if (forced_bpp) {
2071                 pipe_bpp = forced_bpp;
2072         } else {
2073                 int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);
2074
2075                 /* For eDP use max bpp that can be supported with DSC. */
2076                 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2077                 if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) {
2078                         drm_dbg_kms(&i915->drm,
2079                                     "Computed BPC is not in DSC BPC limits\n");
2080                         return -EINVAL;
2081                 }
2082         }
2083         pipe_config->port_clock = limits->max_rate;
2084         pipe_config->lane_count = limits->max_lane_count;
2085
2086         dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2087         dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
2088         dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2089         dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
2090
2091         dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2092         dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3);
2093         dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2094         dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
2095
2096         /* Compressed BPP should be less than the Input DSC bpp */
2097         dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2098
2099         pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
2100
2101         pipe_config->pipe_bpp = pipe_bpp;
2102
2103         return 0;
2104 }
2105
2106 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2107                                 struct intel_crtc_state *pipe_config,
2108                                 struct drm_connector_state *conn_state,
2109                                 struct link_config_limits *limits,
2110                                 int timeslots,
2111                                 bool compute_pipe_bpp)
2112 {
2113         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2114         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2115         const struct intel_connector *connector =
2116                 to_intel_connector(conn_state->connector);
2117         const struct drm_display_mode *adjusted_mode =
2118                 &pipe_config->hw.adjusted_mode;
2119         int ret;
2120
2121         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2122                 intel_dp_supports_fec(intel_dp, connector, pipe_config);
2123
2124         if (!intel_dp_supports_dsc(connector, pipe_config))
2125                 return -EINVAL;
2126
2127         if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2128                 return -EINVAL;
2129
2130         /*
2131          * compute pipe bpp is set to false for DP MST DSC case
2132          * and compressed_bpp is calculated same time once
2133          * vpci timeslots are allocated, because overall bpp
2134          * calculation procedure is bit different for MST case.
2135          */
2136         if (compute_pipe_bpp) {
2137                 if (intel_dp_is_edp(intel_dp))
2138                         ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2139                                                              conn_state, limits);
2140                 else
2141                         ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2142                                                             conn_state, limits, timeslots);
2143                 if (ret) {
2144                         drm_dbg_kms(&dev_priv->drm,
2145                                     "No Valid pipe bpp for given mode ret = %d\n", ret);
2146                         return ret;
2147                 }
2148         }
2149
2150         /* Calculate Slice count */
2151         if (intel_dp_is_edp(intel_dp)) {
2152                 pipe_config->dsc.slice_count =
2153                         drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2154                                                         true);
2155                 if (!pipe_config->dsc.slice_count) {
2156                         drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",
2157                                     pipe_config->dsc.slice_count);
2158                         return -EINVAL;
2159                 }
2160         } else {
2161                 u8 dsc_dp_slice_count;
2162
2163                 dsc_dp_slice_count =
2164                         intel_dp_dsc_get_slice_count(connector,
2165                                                      adjusted_mode->crtc_clock,
2166                                                      adjusted_mode->crtc_hdisplay,
2167                                                      pipe_config->bigjoiner_pipes);
2168                 if (!dsc_dp_slice_count) {
2169                         drm_dbg_kms(&dev_priv->drm,
2170                                     "Compressed Slice Count not supported\n");
2171                         return -EINVAL;
2172                 }
2173
2174                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2175         }
2176         /*
2177          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2178          * is greater than the maximum Cdclock and if slice count is even
2179          * then we need to use 2 VDSC instances.
2180          */
2181         if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1)
2182                 pipe_config->dsc.dsc_split = true;
2183
2184         ret = intel_dp_dsc_compute_params(connector, pipe_config);
2185         if (ret < 0) {
2186                 drm_dbg_kms(&dev_priv->drm,
2187                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2188                             "Compressed BPP = %d\n",
2189                             pipe_config->pipe_bpp,
2190                             pipe_config->dsc.compressed_bpp);
2191                 return ret;
2192         }
2193
2194         pipe_config->dsc.compression_enable = true;
2195         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2196                     "Compressed Bpp = %d Slice Count = %d\n",
2197                     pipe_config->pipe_bpp,
2198                     pipe_config->dsc.compressed_bpp,
2199                     pipe_config->dsc.slice_count);
2200
2201         return 0;
2202 }
2203
2204 /**
2205  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2206  * @intel_dp: intel DP
2207  * @crtc_state: crtc state
2208  * @dsc: DSC compression mode
2209  * @limits: link configuration limits
2210  *
2211  * Calculates the output link min, max bpp values in @limits based on the
2212  * pipe bpp range, @crtc_state and @dsc mode.
2213  *
2214  * Returns %true in case of success.
2215  */
2216 bool
2217 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2218                                         const struct intel_crtc_state *crtc_state,
2219                                         bool dsc,
2220                                         struct link_config_limits *limits)
2221 {
2222         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2223         const struct drm_display_mode *adjusted_mode =
2224                 &crtc_state->hw.adjusted_mode;
2225         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2226         const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2227         int max_link_bpp_x16;
2228
2229         max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2230                                to_bpp_x16(limits->pipe.max_bpp));
2231
2232         if (!dsc) {
2233                 max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
2234
2235                 if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
2236                         return false;
2237
2238                 limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
2239         } else {
2240                 /*
2241                  * TODO: set the DSC link limits already here, atm these are
2242                  * initialized only later in intel_edp_dsc_compute_pipe_bpp() /
2243                  * intel_dp_dsc_compute_pipe_bpp()
2244                  */
2245                 limits->link.min_bpp_x16 = 0;
2246         }
2247
2248         limits->link.max_bpp_x16 = max_link_bpp_x16;
2249
2250         drm_dbg_kms(&i915->drm,
2251                     "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " BPP_X16_FMT "\n",
2252                     encoder->base.base.id, encoder->base.name,
2253                     crtc->base.base.id, crtc->base.name,
2254                     adjusted_mode->crtc_clock,
2255                     dsc ? "on" : "off",
2256                     limits->max_lane_count,
2257                     limits->max_rate,
2258                     limits->pipe.max_bpp,
2259                     BPP_X16_ARGS(limits->link.max_bpp_x16));
2260
2261         return true;
2262 }
2263
2264 static bool
2265 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2266                                struct intel_crtc_state *crtc_state,
2267                                bool respect_downstream_limits,
2268                                bool dsc,
2269                                struct link_config_limits *limits)
2270 {
2271         limits->min_rate = intel_dp_common_rate(intel_dp, 0);
2272         limits->max_rate = intel_dp_max_link_rate(intel_dp);
2273
2274         limits->min_lane_count = 1;
2275         limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2276
2277         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2278         limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2279                                                      respect_downstream_limits);
2280
2281         if (intel_dp->use_max_params) {
2282                 /*
2283                  * Use the maximum clock and number of lanes the eDP panel
2284                  * advertizes being capable of in case the initial fast
2285                  * optimal params failed us. The panels are generally
2286                  * designed to support only a single clock and lane
2287                  * configuration, and typically on older panels these
2288                  * values correspond to the native resolution of the panel.
2289                  */
2290                 limits->min_lane_count = limits->max_lane_count;
2291                 limits->min_rate = limits->max_rate;
2292         }
2293
2294         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
2295
2296         return intel_dp_compute_config_link_bpp_limits(intel_dp,
2297                                                        crtc_state,
2298                                                        dsc,
2299                                                        limits);
2300 }
2301
2302 static int
2303 intel_dp_compute_link_config(struct intel_encoder *encoder,
2304                              struct intel_crtc_state *pipe_config,
2305                              struct drm_connector_state *conn_state,
2306                              bool respect_downstream_limits)
2307 {
2308         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2309         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2310         const struct drm_display_mode *adjusted_mode =
2311                 &pipe_config->hw.adjusted_mode;
2312         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2313         struct link_config_limits limits;
2314         bool joiner_needs_dsc = false;
2315         bool dsc_needed;
2316         int ret = 0;
2317
2318         if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
2319                                     adjusted_mode->crtc_clock))
2320                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
2321
2322         /*
2323          * Pipe joiner needs compression up to display 12 due to bandwidth
2324          * limitation. DG2 onwards pipe joiner can be enabled without
2325          * compression.
2326          */
2327         joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
2328
2329         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2330                      !intel_dp_compute_config_limits(intel_dp, pipe_config,
2331                                                      respect_downstream_limits,
2332                                                      false,
2333                                                      &limits);
2334
2335         if (!dsc_needed) {
2336                 /*
2337                  * Optimize for slow and wide for everything, because there are some
2338                  * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2339                  */
2340                 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2341                                                         conn_state, &limits);
2342                 if (ret)
2343                         dsc_needed = true;
2344         }
2345
2346         if (dsc_needed) {
2347                 drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2348                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2349                             str_yes_no(intel_dp->force_dsc_en));
2350
2351                 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2352                                                     respect_downstream_limits,
2353                                                     true,
2354                                                     &limits))
2355                         return -EINVAL;
2356
2357                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2358                                                   conn_state, &limits, 64, true);
2359                 if (ret < 0)
2360                         return ret;
2361         }
2362
2363         if (pipe_config->dsc.compression_enable) {
2364                 drm_dbg_kms(&i915->drm,
2365                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2366                             pipe_config->lane_count, pipe_config->port_clock,
2367                             pipe_config->pipe_bpp,
2368                             pipe_config->dsc.compressed_bpp);
2369
2370                 drm_dbg_kms(&i915->drm,
2371                             "DP link rate required %i available %i\n",
2372                             intel_dp_link_required(adjusted_mode->crtc_clock,
2373                                                    pipe_config->dsc.compressed_bpp),
2374                             intel_dp_max_data_rate(pipe_config->port_clock,
2375                                                    pipe_config->lane_count));
2376         } else {
2377                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2378                             pipe_config->lane_count, pipe_config->port_clock,
2379                             pipe_config->pipe_bpp);
2380
2381                 drm_dbg_kms(&i915->drm,
2382                             "DP link rate required %i available %i\n",
2383                             intel_dp_link_required(adjusted_mode->crtc_clock,
2384                                                    pipe_config->pipe_bpp),
2385                             intel_dp_max_data_rate(pipe_config->port_clock,
2386                                                    pipe_config->lane_count));
2387         }
2388         return 0;
2389 }
2390
2391 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2392                                   const struct drm_connector_state *conn_state)
2393 {
2394         const struct intel_digital_connector_state *intel_conn_state =
2395                 to_intel_digital_connector_state(conn_state);
2396         const struct drm_display_mode *adjusted_mode =
2397                 &crtc_state->hw.adjusted_mode;
2398
2399         /*
2400          * Our YCbCr output is always limited range.
2401          * crtc_state->limited_color_range only applies to RGB,
2402          * and it must never be set for YCbCr or we risk setting
2403          * some conflicting bits in TRANSCONF which will mess up
2404          * the colors on the monitor.
2405          */
2406         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2407                 return false;
2408
2409         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2410                 /*
2411                  * See:
2412                  * CEA-861-E - 5.1 Default Encoding Parameters
2413                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2414                  */
2415                 return crtc_state->pipe_bpp != 18 &&
2416                         drm_default_rgb_quant_range(adjusted_mode) ==
2417                         HDMI_QUANTIZATION_RANGE_LIMITED;
2418         } else {
2419                 return intel_conn_state->broadcast_rgb ==
2420                         INTEL_BROADCAST_RGB_LIMITED;
2421         }
2422 }
2423
2424 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2425                                     enum port port)
2426 {
2427         if (IS_G4X(dev_priv))
2428                 return false;
2429         if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A)
2430                 return false;
2431
2432         return true;
2433 }
2434
2435 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2436                                              const struct drm_connector_state *conn_state,
2437                                              struct drm_dp_vsc_sdp *vsc)
2438 {
2439         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2440         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2441
2442         /*
2443          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2444          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2445          * Colorimetry Format indication.
2446          */
2447         vsc->revision = 0x5;
2448         vsc->length = 0x13;
2449
2450         /* DP 1.4a spec, Table 2-120 */
2451         switch (crtc_state->output_format) {
2452         case INTEL_OUTPUT_FORMAT_YCBCR444:
2453                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2454                 break;
2455         case INTEL_OUTPUT_FORMAT_YCBCR420:
2456                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2457                 break;
2458         case INTEL_OUTPUT_FORMAT_RGB:
2459         default:
2460                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2461         }
2462
2463         switch (conn_state->colorspace) {
2464         case DRM_MODE_COLORIMETRY_BT709_YCC:
2465                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2466                 break;
2467         case DRM_MODE_COLORIMETRY_XVYCC_601:
2468                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2469                 break;
2470         case DRM_MODE_COLORIMETRY_XVYCC_709:
2471                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2472                 break;
2473         case DRM_MODE_COLORIMETRY_SYCC_601:
2474                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2475                 break;
2476         case DRM_MODE_COLORIMETRY_OPYCC_601:
2477                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2478                 break;
2479         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2480                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2481                 break;
2482         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2483                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2484                 break;
2485         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2486                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2487                 break;
2488         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2489         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2490                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2491                 break;
2492         default:
2493                 /*
2494                  * RGB->YCBCR color conversion uses the BT.709
2495                  * color space.
2496                  */
2497                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2498                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2499                 else
2500                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2501                 break;
2502         }
2503
2504         vsc->bpc = crtc_state->pipe_bpp / 3;
2505
2506         /* only RGB pixelformat supports 6 bpc */
2507         drm_WARN_ON(&dev_priv->drm,
2508                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2509
2510         /* all YCbCr are always limited range */
2511         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2512         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2513 }
2514
2515 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2516                                      struct intel_crtc_state *crtc_state,
2517                                      const struct drm_connector_state *conn_state)
2518 {
2519         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2520
2521         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2522         if (crtc_state->has_psr)
2523                 return;
2524
2525         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2526                 return;
2527
2528         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2529         vsc->sdp_type = DP_SDP_VSC;
2530         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2531                                          &crtc_state->infoframes.vsc);
2532 }
2533
2534 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2535                                   const struct intel_crtc_state *crtc_state,
2536                                   const struct drm_connector_state *conn_state,
2537                                   struct drm_dp_vsc_sdp *vsc)
2538 {
2539         vsc->sdp_type = DP_SDP_VSC;
2540
2541         if (crtc_state->has_psr2) {
2542                 if (intel_dp->psr.colorimetry_support &&
2543                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2544                         /* [PSR2, +Colorimetry] */
2545                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2546                                                          vsc);
2547                 } else {
2548                         /*
2549                          * [PSR2, -Colorimetry]
2550                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2551                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2552                          */
2553                         vsc->revision = 0x4;
2554                         vsc->length = 0xe;
2555                 }
2556         } else {
2557                 /*
2558                  * [PSR1]
2559                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2560                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2561                  * higher).
2562                  */
2563                 vsc->revision = 0x2;
2564                 vsc->length = 0x8;
2565         }
2566 }
2567
2568 static void
2569 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2570                                             struct intel_crtc_state *crtc_state,
2571                                             const struct drm_connector_state *conn_state)
2572 {
2573         int ret;
2574         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2575         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2576
2577         if (!conn_state->hdr_output_metadata)
2578                 return;
2579
2580         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2581
2582         if (ret) {
2583                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2584                 return;
2585         }
2586
2587         crtc_state->infoframes.enable |=
2588                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2589 }
2590
2591 static bool cpu_transcoder_has_drrs(struct drm_i915_private *i915,
2592                                     enum transcoder cpu_transcoder)
2593 {
2594         if (HAS_DOUBLE_BUFFERED_M_N(i915))
2595                 return true;
2596
2597         return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);
2598 }
2599
2600 static bool can_enable_drrs(struct intel_connector *connector,
2601                             const struct intel_crtc_state *pipe_config,
2602                             const struct drm_display_mode *downclock_mode)
2603 {
2604         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2605
2606         if (pipe_config->vrr.enable)
2607                 return false;
2608
2609         /*
2610          * DRRS and PSR can't be enable together, so giving preference to PSR
2611          * as it allows more power-savings by complete shutting down display,
2612          * so to guarantee this, intel_drrs_compute_config() must be called
2613          * after intel_psr_compute_config().
2614          */
2615         if (pipe_config->has_psr)
2616                 return false;
2617
2618         /* FIXME missing FDI M2/N2 etc. */
2619         if (pipe_config->has_pch_encoder)
2620                 return false;
2621
2622         if (!cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))
2623                 return false;
2624
2625         return downclock_mode &&
2626                 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2627 }
2628
2629 static void
2630 intel_dp_drrs_compute_config(struct intel_connector *connector,
2631                              struct intel_crtc_state *pipe_config,
2632                              int link_bpp)
2633 {
2634         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2635         const struct drm_display_mode *downclock_mode =
2636                 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2637         int pixel_clock;
2638
2639         if (has_seamless_m_n(connector))
2640                 pipe_config->update_m_n = true;
2641
2642         if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2643                 if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
2644                         intel_zero_m_n(&pipe_config->dp_m2_n2);
2645                 return;
2646         }
2647
2648         if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915))
2649                 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2650
2651         pipe_config->has_drrs = true;
2652
2653         pixel_clock = downclock_mode->clock;
2654         if (pipe_config->splitter.enable)
2655                 pixel_clock /= pipe_config->splitter.link_count;
2656
2657         intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock,
2658                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2659                                pipe_config->fec_enable);
2660
2661         /* FIXME: abstract this better */
2662         if (pipe_config->splitter.enable)
2663                 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
2664 }
2665
2666 static bool intel_dp_has_audio(struct intel_encoder *encoder,
2667                                struct intel_crtc_state *crtc_state,
2668                                const struct drm_connector_state *conn_state)
2669 {
2670         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2671         const struct intel_digital_connector_state *intel_conn_state =
2672                 to_intel_digital_connector_state(conn_state);
2673         struct intel_connector *connector =
2674                 to_intel_connector(conn_state->connector);
2675
2676         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
2677             !intel_dp_port_has_audio(i915, encoder->port))
2678                 return false;
2679
2680         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2681                 return connector->base.display_info.has_audio;
2682         else
2683                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2684 }
2685
2686 static int
2687 intel_dp_compute_output_format(struct intel_encoder *encoder,
2688                                struct intel_crtc_state *crtc_state,
2689                                struct drm_connector_state *conn_state,
2690                                bool respect_downstream_limits)
2691 {
2692         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2693         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2694         struct intel_connector *connector = intel_dp->attached_connector;
2695         const struct drm_display_info *info = &connector->base.display_info;
2696         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2697         bool ycbcr_420_only;
2698         int ret;
2699
2700         ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2701
2702         if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
2703                 drm_dbg_kms(&i915->drm,
2704                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2705                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2706         } else {
2707                 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
2708         }
2709
2710         crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
2711
2712         ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2713                                            respect_downstream_limits);
2714         if (ret) {
2715                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2716                     !connector->base.ycbcr_420_allowed ||
2717                     !drm_mode_is_420_also(info, adjusted_mode))
2718                         return ret;
2719
2720                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2721                 crtc_state->output_format = intel_dp_output_format(connector,
2722                                                                    crtc_state->sink_format);
2723                 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
2724                                                    respect_downstream_limits);
2725         }
2726
2727         return ret;
2728 }
2729
2730 void
2731 intel_dp_audio_compute_config(struct intel_encoder *encoder,
2732                               struct intel_crtc_state *pipe_config,
2733                               struct drm_connector_state *conn_state)
2734 {
2735         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2736         struct drm_connector *connector = conn_state->connector;
2737
2738         pipe_config->has_audio =
2739                 intel_dp_has_audio(encoder, pipe_config, conn_state) &&
2740                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2741
2742         pipe_config->sdp_split_enable = pipe_config->has_audio &&
2743                                         intel_dp_is_uhbr(pipe_config);
2744
2745         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDP split enable: %s\n",
2746                     connector->base.id, connector->name,
2747                     str_yes_no(pipe_config->sdp_split_enable));
2748 }
2749
2750 int
2751 intel_dp_compute_config(struct intel_encoder *encoder,
2752                         struct intel_crtc_state *pipe_config,
2753                         struct drm_connector_state *conn_state)
2754 {
2755         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2756         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2757         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2758         const struct drm_display_mode *fixed_mode;
2759         struct intel_connector *connector = intel_dp->attached_connector;
2760         int ret = 0, link_bpp;
2761
2762         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)
2763                 pipe_config->has_pch_encoder = true;
2764
2765         fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
2766         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
2767                 ret = intel_panel_compute_config(connector, adjusted_mode);
2768                 if (ret)
2769                         return ret;
2770         }
2771
2772         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2773                 return -EINVAL;
2774
2775         if (!connector->base.interlace_allowed &&
2776             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2777                 return -EINVAL;
2778
2779         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2780                 return -EINVAL;
2781
2782         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2783                 return -EINVAL;
2784
2785         /*
2786          * Try to respect downstream TMDS clock limits first, if
2787          * that fails assume the user might know something we don't.
2788          */
2789         ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
2790         if (ret)
2791                 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
2792         if (ret)
2793                 return ret;
2794
2795         if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
2796             pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2797                 ret = intel_panel_fitting(pipe_config, conn_state);
2798                 if (ret)
2799                         return ret;
2800         }
2801
2802         pipe_config->limited_color_range =
2803                 intel_dp_limited_color_range(pipe_config, conn_state);
2804
2805         pipe_config->enhanced_framing =
2806                 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
2807
2808         if (pipe_config->dsc.compression_enable)
2809                 link_bpp = pipe_config->dsc.compressed_bpp;
2810         else
2811                 link_bpp = intel_dp_output_bpp(pipe_config->output_format,
2812                                                pipe_config->pipe_bpp);
2813
2814         if (intel_dp->mso_link_count) {
2815                 int n = intel_dp->mso_link_count;
2816                 int overlap = intel_dp->mso_pixel_overlap;
2817
2818                 pipe_config->splitter.enable = true;
2819                 pipe_config->splitter.link_count = n;
2820                 pipe_config->splitter.pixel_overlap = overlap;
2821
2822                 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",
2823                             n, overlap);
2824
2825                 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
2826                 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
2827                 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
2828                 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
2829                 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
2830                 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
2831                 adjusted_mode->crtc_clock /= n;
2832         }
2833
2834         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
2835
2836         intel_link_compute_m_n(link_bpp,
2837                                pipe_config->lane_count,
2838                                adjusted_mode->crtc_clock,
2839                                pipe_config->port_clock,
2840                                &pipe_config->dp_m_n,
2841                                pipe_config->fec_enable);
2842
2843         /* FIXME: abstract this better */
2844         if (pipe_config->splitter.enable)
2845                 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
2846
2847         if (!HAS_DDI(dev_priv))
2848                 g4x_dp_set_clock(encoder, pipe_config);
2849
2850         intel_vrr_compute_config(pipe_config, conn_state);
2851         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
2852         intel_dp_drrs_compute_config(connector, pipe_config, link_bpp);
2853         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2854         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2855
2856         return 0;
2857 }
2858
2859 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2860                               int link_rate, int lane_count)
2861 {
2862         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2863         intel_dp->link_trained = false;
2864         intel_dp->link_rate = link_rate;
2865         intel_dp->lane_count = lane_count;
2866 }
2867
2868 static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp)
2869 {
2870         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
2871         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
2872 }
2873
2874 /* Enable backlight PWM and backlight PP control. */
2875 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2876                             const struct drm_connector_state *conn_state)
2877 {
2878         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
2879         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2880
2881         if (!intel_dp_is_edp(intel_dp))
2882                 return;
2883
2884         drm_dbg_kms(&i915->drm, "\n");
2885
2886         intel_backlight_enable(crtc_state, conn_state);
2887         intel_pps_backlight_on(intel_dp);
2888 }
2889
2890 /* Disable backlight PP control and backlight PWM. */
2891 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2892 {
2893         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
2894         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2895
2896         if (!intel_dp_is_edp(intel_dp))
2897                 return;
2898
2899         drm_dbg_kms(&i915->drm, "\n");
2900
2901         intel_pps_backlight_off(intel_dp);
2902         intel_backlight_disable(old_conn_state);
2903 }
2904
2905 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2906 {
2907         /*
2908          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2909          * be capable of signalling downstream hpd with a long pulse.
2910          * Whether or not that means D3 is safe to use is not clear,
2911          * but let's assume so until proven otherwise.
2912          *
2913          * FIXME should really check all downstream ports...
2914          */
2915         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2916                 drm_dp_is_branch(intel_dp->dpcd) &&
2917                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2918 }
2919
2920 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
2921                                            const struct intel_crtc_state *crtc_state,
2922                                            bool enable)
2923 {
2924         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2925         int ret;
2926
2927         if (!crtc_state->dsc.compression_enable)
2928                 return;
2929
2930         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
2931                                  enable ? DP_DECOMPRESSION_EN : 0);
2932         if (ret < 0)
2933                 drm_dbg_kms(&i915->drm,
2934                             "Failed to %s sink decompression state\n",
2935                             str_enable_disable(enable));
2936 }
2937
2938 static void
2939 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
2940 {
2941         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2942         u8 oui[] = { 0x00, 0xaa, 0x01 };
2943         u8 buf[3] = {};
2944
2945         /*
2946          * During driver init, we want to be careful and avoid changing the source OUI if it's
2947          * already set to what we want, so as to avoid clearing any state by accident
2948          */
2949         if (careful) {
2950                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
2951                         drm_err(&i915->drm, "Failed to read source OUI\n");
2952
2953                 if (memcmp(oui, buf, sizeof(oui)) == 0)
2954                         return;
2955         }
2956
2957         if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
2958                 drm_err(&i915->drm, "Failed to write source OUI\n");
2959
2960         intel_dp->last_oui_write = jiffies;
2961 }
2962
2963 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
2964 {
2965         struct intel_connector *connector = intel_dp->attached_connector;
2966         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2967
2968         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
2969                     connector->base.base.id, connector->base.name,
2970                     connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2971
2972         wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
2973                                        connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
2974 }
2975
2976 /* If the device supports it, try to set the power state appropriately */
2977 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
2978 {
2979         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2980         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2981         int ret, i;
2982
2983         /* Should have a valid DPCD by this point */
2984         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2985                 return;
2986
2987         if (mode != DP_SET_POWER_D0) {
2988                 if (downstream_hpd_needs_d0(intel_dp))
2989                         return;
2990
2991                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
2992         } else {
2993                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2994
2995                 lspcon_resume(dp_to_dig_port(intel_dp));
2996
2997                 /* Write the source OUI as early as possible */
2998                 if (intel_dp_is_edp(intel_dp))
2999                         intel_edp_init_source_oui(intel_dp, false);
3000
3001                 /*
3002                  * When turning on, we need to retry for 1ms to give the sink
3003                  * time to wake up.
3004                  */
3005                 for (i = 0; i < 3; i++) {
3006                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3007                         if (ret == 1)
3008                                 break;
3009                         msleep(1);
3010                 }
3011
3012                 if (ret == 1 && lspcon->active)
3013                         lspcon_wait_pcon_mode(lspcon);
3014         }
3015
3016         if (ret != 1)
3017                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3018                             encoder->base.base.id, encoder->base.name,
3019                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3020 }
3021
3022 static bool
3023 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3024
3025 /**
3026  * intel_dp_sync_state - sync the encoder state during init/resume
3027  * @encoder: intel encoder to sync
3028  * @crtc_state: state for the CRTC connected to the encoder
3029  *
3030  * Sync any state stored in the encoder wrt. HW state during driver init
3031  * and system resume.
3032  */
3033 void intel_dp_sync_state(struct intel_encoder *encoder,
3034                          const struct intel_crtc_state *crtc_state)
3035 {
3036         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3037
3038         if (!crtc_state)
3039                 return;
3040
3041         /*
3042          * Don't clobber DPCD if it's been already read out during output
3043          * setup (eDP) or detect.
3044          */
3045         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3046                 intel_dp_get_dpcd(intel_dp);
3047
3048         intel_dp_reset_max_link_params(intel_dp);
3049 }
3050
3051 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3052                                     struct intel_crtc_state *crtc_state)
3053 {
3054         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3055         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3056         bool fastset = true;
3057
3058         /*
3059          * If BIOS has set an unsupported or non-standard link rate for some
3060          * reason force an encoder recompute and full modeset.
3061          */
3062         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3063                                 crtc_state->port_clock) < 0) {
3064                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3065                             encoder->base.base.id, encoder->base.name);
3066                 crtc_state->uapi.connectors_changed = true;
3067                 fastset = false;
3068         }
3069
3070         /*
3071          * FIXME hack to force full modeset when DSC is being used.
3072          *
3073          * As long as we do not have full state readout and config comparison
3074          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3075          * Remove once we have readout for DSC.
3076          */
3077         if (crtc_state->dsc.compression_enable) {
3078                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3079                             encoder->base.base.id, encoder->base.name);
3080                 crtc_state->uapi.mode_changed = true;
3081                 fastset = false;
3082         }
3083
3084         if (CAN_PSR(intel_dp)) {
3085                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
3086                             encoder->base.base.id, encoder->base.name);
3087                 crtc_state->uapi.mode_changed = true;
3088                 fastset = false;
3089         }
3090
3091         return fastset;
3092 }
3093
3094 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3095 {
3096         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3097
3098         /* Clear the cached register set to avoid using stale values */
3099
3100         memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3101
3102         if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3103                              intel_dp->pcon_dsc_dpcd,
3104                              sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3105                 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",
3106                         DP_PCON_DSC_ENCODER);
3107
3108         drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3109                     (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3110 }
3111
3112 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3113 {
3114         int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3115         int i;
3116
3117         for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3118                 if (frl_bw_mask & (1 << i))
3119                         return bw_gbps[i];
3120         }
3121         return 0;
3122 }
3123
3124 static int intel_dp_pcon_set_frl_mask(int max_frl)
3125 {
3126         switch (max_frl) {
3127         case 48:
3128                 return DP_PCON_FRL_BW_MASK_48GBPS;
3129         case 40:
3130                 return DP_PCON_FRL_BW_MASK_40GBPS;
3131         case 32:
3132                 return DP_PCON_FRL_BW_MASK_32GBPS;
3133         case 24:
3134                 return DP_PCON_FRL_BW_MASK_24GBPS;
3135         case 18:
3136                 return DP_PCON_FRL_BW_MASK_18GBPS;
3137         case 9:
3138                 return DP_PCON_FRL_BW_MASK_9GBPS;
3139         }
3140
3141         return 0;
3142 }
3143
3144 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3145 {
3146         struct intel_connector *intel_connector = intel_dp->attached_connector;
3147         struct drm_connector *connector = &intel_connector->base;
3148         int max_frl_rate;
3149         int max_lanes, rate_per_lane;
3150         int max_dsc_lanes, dsc_rate_per_lane;
3151
3152         max_lanes = connector->display_info.hdmi.max_lanes;
3153         rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;
3154         max_frl_rate = max_lanes * rate_per_lane;
3155
3156         if (connector->display_info.hdmi.dsc_cap.v_1p2) {
3157                 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;
3158                 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;
3159                 if (max_dsc_lanes && dsc_rate_per_lane)
3160                         max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3161         }
3162
3163         return max_frl_rate;
3164 }
3165
3166 static bool
3167 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3168                              u8 max_frl_bw_mask, u8 *frl_trained_mask)
3169 {
3170         if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3171             drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3172             *frl_trained_mask >= max_frl_bw_mask)
3173                 return true;
3174
3175         return false;
3176 }
3177
3178 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3179 {
3180 #define TIMEOUT_FRL_READY_MS 500
3181 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3182
3183         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3184         int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3185         u8 max_frl_bw_mask = 0, frl_trained_mask;
3186         bool is_active;
3187
3188         max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3189         drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3190
3191         max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3192         drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);
3193
3194         max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3195
3196         if (max_frl_bw <= 0)
3197                 return -EINVAL;
3198
3199         max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3200         drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3201
3202         if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3203                 goto frl_trained;
3204
3205         ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3206         if (ret < 0)
3207                 return ret;
3208         /* Wait for PCON to be FRL Ready */
3209         wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3210
3211         if (!is_active)
3212                 return -ETIMEDOUT;
3213
3214         ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3215                                           DP_PCON_ENABLE_SEQUENTIAL_LINK);
3216         if (ret < 0)
3217                 return ret;
3218         ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3219                                           DP_PCON_FRL_LINK_TRAIN_NORMAL);
3220         if (ret < 0)
3221                 return ret;
3222         ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3223         if (ret < 0)
3224                 return ret;
3225         /*
3226          * Wait for FRL to be completed
3227          * Check if the HDMI Link is up and active.
3228          */
3229         wait_for(is_active =
3230                  intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3231                  TIMEOUT_HDMI_LINK_ACTIVE_MS);
3232
3233         if (!is_active)
3234                 return -ETIMEDOUT;
3235
3236 frl_trained:
3237         drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3238         intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3239         intel_dp->frl.is_trained = true;
3240         drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);
3241
3242         return 0;
3243 }
3244
3245 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3246 {
3247         if (drm_dp_is_branch(intel_dp->dpcd) &&
3248             intel_dp_has_hdmi_sink(intel_dp) &&
3249             intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3250                 return true;
3251
3252         return false;
3253 }
3254
3255 static
3256 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3257 {
3258         int ret;
3259         u8 buf = 0;
3260
3261         /* Set PCON source control mode */
3262         buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3263
3264         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3265         if (ret < 0)
3266                 return ret;
3267
3268         /* Set HDMI LINK ENABLE */
3269         buf |= DP_PCON_ENABLE_HDMI_LINK;
3270         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3271         if (ret < 0)
3272                 return ret;
3273
3274         return 0;
3275 }
3276
3277 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3278 {
3279         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3280
3281         /*
3282          * Always go for FRL training if:
3283          * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3284          * -sink is HDMI2.1
3285          */
3286         if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3287             !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3288             intel_dp->frl.is_trained)
3289                 return;
3290
3291         if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3292                 int ret, mode;
3293
3294                 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");
3295                 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3296                 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3297
3298                 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3299                         drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");
3300         } else {
3301                 drm_dbg(&dev_priv->drm, "FRL training Completed\n");
3302         }
3303 }
3304
3305 static int
3306 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3307 {
3308         int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3309
3310         return intel_hdmi_dsc_get_slice_height(vactive);
3311 }
3312
3313 static int
3314 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3315                              const struct intel_crtc_state *crtc_state)
3316 {
3317         struct intel_connector *intel_connector = intel_dp->attached_connector;
3318         struct drm_connector *connector = &intel_connector->base;
3319         int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;
3320         int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;
3321         int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3322         int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3323
3324         return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3325                                              pcon_max_slice_width,
3326                                              hdmi_max_slices, hdmi_throughput);
3327 }
3328
3329 static int
3330 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3331                           const struct intel_crtc_state *crtc_state,
3332                           int num_slices, int slice_width)
3333 {
3334         struct intel_connector *intel_connector = intel_dp->attached_connector;
3335         struct drm_connector *connector = &intel_connector->base;
3336         int output_format = crtc_state->output_format;
3337         bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;
3338         int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3339         int hdmi_max_chunk_bytes =
3340                 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;
3341
3342         return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3343                                       num_slices, output_format, hdmi_all_bpp,
3344                                       hdmi_max_chunk_bytes);
3345 }
3346
3347 void
3348 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3349                             const struct intel_crtc_state *crtc_state)
3350 {
3351         u8 pps_param[6];
3352         int slice_height;
3353         int slice_width;
3354         int num_slices;
3355         int bits_per_pixel;
3356         int ret;
3357         struct intel_connector *intel_connector = intel_dp->attached_connector;
3358         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3359         struct drm_connector *connector;
3360         bool hdmi_is_dsc_1_2;
3361
3362         if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3363                 return;
3364
3365         if (!intel_connector)
3366                 return;
3367         connector = &intel_connector->base;
3368         hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;
3369
3370         if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3371             !hdmi_is_dsc_1_2)
3372                 return;
3373
3374         slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3375         if (!slice_height)
3376                 return;
3377
3378         num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3379         if (!num_slices)
3380                 return;
3381
3382         slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3383                                    num_slices);
3384
3385         bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3386                                                    num_slices, slice_width);
3387         if (!bits_per_pixel)
3388                 return;
3389
3390         pps_param[0] = slice_height & 0xFF;
3391         pps_param[1] = slice_height >> 8;
3392         pps_param[2] = slice_width & 0xFF;
3393         pps_param[3] = slice_width >> 8;
3394         pps_param[4] = bits_per_pixel & 0xFF;
3395         pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3396
3397         ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3398         if (ret < 0)
3399                 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");
3400 }
3401
3402 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3403                                            const struct intel_crtc_state *crtc_state)
3404 {
3405         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3406         bool ycbcr444_to_420 = false;
3407         bool rgb_to_ycbcr = false;
3408         u8 tmp;
3409
3410         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3411                 return;
3412
3413         if (!drm_dp_is_branch(intel_dp->dpcd))
3414                 return;
3415
3416         tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3417
3418         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3419                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3420                 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",
3421                             str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3422
3423         if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3424                 switch (crtc_state->output_format) {
3425                 case INTEL_OUTPUT_FORMAT_YCBCR420:
3426                         break;
3427                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3428                         ycbcr444_to_420 = true;
3429                         break;
3430                 case INTEL_OUTPUT_FORMAT_RGB:
3431                         rgb_to_ycbcr = true;
3432                         ycbcr444_to_420 = true;
3433                         break;
3434                 default:
3435                         MISSING_CASE(crtc_state->output_format);
3436                         break;
3437                 }
3438         } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3439                 switch (crtc_state->output_format) {
3440                 case INTEL_OUTPUT_FORMAT_YCBCR444:
3441                         break;
3442                 case INTEL_OUTPUT_FORMAT_RGB:
3443                         rgb_to_ycbcr = true;
3444                         break;
3445                 default:
3446                         MISSING_CASE(crtc_state->output_format);
3447                         break;
3448                 }
3449         }
3450
3451         tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
3452
3453         if (drm_dp_dpcd_writeb(&intel_dp->aux,
3454                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
3455                 drm_dbg_kms(&i915->drm,
3456                             "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
3457                             str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
3458
3459         tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
3460
3461         if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
3462                 drm_dbg_kms(&i915->drm,
3463                             "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
3464                             str_enable_disable(tmp));
3465 }
3466
3467 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3468 {
3469         u8 dprx = 0;
3470
3471         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3472                               &dprx) != 1)
3473                 return false;
3474         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3475 }
3476
3477 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
3478                                    u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
3479 {
3480         if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
3481                              DP_DSC_RECEIVER_CAP_SIZE) < 0) {
3482                 drm_err(aux->drm_dev,
3483                         "Failed to read DPCD register 0x%x\n",
3484                         DP_DSC_SUPPORT);
3485                 return;
3486         }
3487
3488         drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
3489                     DP_DSC_RECEIVER_CAP_SIZE,
3490                     dsc_dpcd);
3491 }
3492
3493 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
3494 {
3495         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3496
3497         /*
3498          * Clear the cached register set to avoid using stale values
3499          * for the sinks that do not support DSC.
3500          */
3501         memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
3502
3503         /* Clear fec_capable to avoid using stale values */
3504         connector->dp.fec_capability = 0;
3505
3506         if (dpcd_rev < DP_DPCD_REV_14)
3507                 return;
3508
3509         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
3510                                connector->dp.dsc_dpcd);
3511
3512         if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
3513                               &connector->dp.fec_capability) < 0) {
3514                 drm_err(&i915->drm, "Failed to read FEC DPCD register\n");
3515                 return;
3516         }
3517
3518         drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
3519                     connector->dp.fec_capability);
3520 }
3521
3522 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
3523 {
3524         if (edp_dpcd_rev < DP_EDP_14)
3525                 return;
3526
3527         intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
3528 }
3529
3530 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
3531                                      struct drm_display_mode *mode)
3532 {
3533         struct intel_dp *intel_dp = intel_attached_dp(connector);
3534         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3535         int n = intel_dp->mso_link_count;
3536         int overlap = intel_dp->mso_pixel_overlap;
3537
3538         if (!mode || !n)
3539                 return;
3540
3541         mode->hdisplay = (mode->hdisplay - overlap) * n;
3542         mode->hsync_start = (mode->hsync_start - overlap) * n;
3543         mode->hsync_end = (mode->hsync_end - overlap) * n;
3544         mode->htotal = (mode->htotal - overlap) * n;
3545         mode->clock *= n;
3546
3547         drm_mode_set_name(mode);
3548
3549         drm_dbg_kms(&i915->drm,
3550                     "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
3551                     connector->base.base.id, connector->base.name,
3552                     DRM_MODE_ARG(mode));
3553 }
3554
3555 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
3556 {
3557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3558         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3559         struct intel_connector *connector = intel_dp->attached_connector;
3560
3561         if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
3562                 /*
3563                  * This is a big fat ugly hack.
3564                  *
3565                  * Some machines in UEFI boot mode provide us a VBT that has 18
3566                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3567                  * unknown we fail to light up. Yet the same BIOS boots up with
3568                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3569                  * max, not what it tells us to use.
3570                  *
3571                  * Note: This will still be broken if the eDP panel is not lit
3572                  * up by the BIOS, and thus we can't get the mode at module
3573                  * load.
3574                  */
3575                 drm_dbg_kms(&dev_priv->drm,
3576                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3577                             pipe_bpp, connector->panel.vbt.edp.bpp);
3578                 connector->panel.vbt.edp.bpp = pipe_bpp;
3579         }
3580 }
3581
3582 static void intel_edp_mso_init(struct intel_dp *intel_dp)
3583 {
3584         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3585         struct intel_connector *connector = intel_dp->attached_connector;
3586         struct drm_display_info *info = &connector->base.display_info;
3587         u8 mso;
3588
3589         if (intel_dp->edp_dpcd[0] < DP_EDP_14)
3590                 return;
3591
3592         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
3593                 drm_err(&i915->drm, "Failed to read MSO cap\n");
3594                 return;
3595         }
3596
3597         /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
3598         mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
3599         if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
3600                 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);
3601                 mso = 0;
3602         }
3603
3604         if (mso) {
3605                 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",
3606                             mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
3607                             info->mso_pixel_overlap);
3608                 if (!HAS_MSO(i915)) {
3609                         drm_err(&i915->drm, "No source MSO support, disabling\n");
3610                         mso = 0;
3611                 }
3612         }
3613
3614         intel_dp->mso_link_count = mso;
3615         intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
3616 }
3617
3618 static bool
3619 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
3620 {
3621         struct drm_i915_private *dev_priv =
3622                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3623
3624         /* this function is meant to be called only once */
3625         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
3626
3627         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
3628                 return false;
3629
3630         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3631                          drm_dp_is_branch(intel_dp->dpcd));
3632
3633         /*
3634          * Read the eDP display control registers.
3635          *
3636          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3637          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3638          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3639          * method). The display control registers should read zero if they're
3640          * not supported anyway.
3641          */
3642         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3643                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3644                              sizeof(intel_dp->edp_dpcd)) {
3645                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
3646                             (int)sizeof(intel_dp->edp_dpcd),
3647                             intel_dp->edp_dpcd);
3648
3649                 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
3650         }
3651
3652         /*
3653          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3654          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3655          */
3656         intel_psr_init_dpcd(intel_dp);
3657
3658         /* Clear the default sink rates */
3659         intel_dp->num_sink_rates = 0;
3660
3661         /* Read the eDP 1.4+ supported link rates. */
3662         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3663                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3664                 int i;
3665
3666                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3667                                 sink_rates, sizeof(sink_rates));
3668
3669                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3670                         int val = le16_to_cpu(sink_rates[i]);
3671
3672                         if (val == 0)
3673                                 break;
3674
3675                         /* Value read multiplied by 200kHz gives the per-lane
3676                          * link rate in kHz. The source rates are, however,
3677                          * stored in terms of LS_Clk kHz. The full conversion
3678                          * back to symbols is
3679                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3680                          */
3681                         intel_dp->sink_rates[i] = (val * 200) / 10;
3682                 }
3683                 intel_dp->num_sink_rates = i;
3684         }
3685
3686         /*
3687          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3688          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3689          */
3690         if (intel_dp->num_sink_rates)
3691                 intel_dp->use_rate_select = true;
3692         else
3693                 intel_dp_set_sink_rates(intel_dp);
3694         intel_dp_set_max_sink_lane_count(intel_dp);
3695
3696         /* Read the eDP DSC DPCD registers */
3697         if (HAS_DSC(dev_priv))
3698                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
3699                                            connector);
3700
3701         /*
3702          * If needed, program our source OUI so we can make various Intel-specific AUX services
3703          * available (such as HDR backlight controls)
3704          */
3705         intel_edp_init_source_oui(intel_dp, true);
3706
3707         return true;
3708 }
3709
3710 static bool
3711 intel_dp_has_sink_count(struct intel_dp *intel_dp)
3712 {
3713         if (!intel_dp->attached_connector)
3714                 return false;
3715
3716         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
3717                                           intel_dp->dpcd,
3718                                           &intel_dp->desc);
3719 }
3720
3721 static bool
3722 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3723 {
3724         int ret;
3725
3726         if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
3727                 return false;
3728
3729         /*
3730          * Don't clobber cached eDP rates. Also skip re-reading
3731          * the OUI/ID since we know it won't change.
3732          */
3733         if (!intel_dp_is_edp(intel_dp)) {
3734                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3735                                  drm_dp_is_branch(intel_dp->dpcd));
3736
3737                 intel_dp_set_sink_rates(intel_dp);
3738                 intel_dp_set_max_sink_lane_count(intel_dp);
3739                 intel_dp_set_common_rates(intel_dp);
3740         }
3741
3742         if (intel_dp_has_sink_count(intel_dp)) {
3743                 ret = drm_dp_read_sink_count(&intel_dp->aux);
3744                 if (ret < 0)
3745                         return false;
3746
3747                 /*
3748                  * Sink count can change between short pulse hpd hence
3749                  * a member variable in intel_dp will track any changes
3750                  * between short pulse interrupts.
3751                  */
3752                 intel_dp->sink_count = ret;
3753
3754                 /*
3755                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3756                  * a dongle is present but no display. Unless we require to know
3757                  * if a dongle is present or not, we don't need to update
3758                  * downstream port information. So, an early return here saves
3759                  * time from performing other operations which are not required.
3760                  */
3761                 if (!intel_dp->sink_count)
3762                         return false;
3763         }
3764
3765         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
3766                                            intel_dp->downstream_ports) == 0;
3767 }
3768
3769 static bool
3770 intel_dp_can_mst(struct intel_dp *intel_dp)
3771 {
3772         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3773
3774         return i915->params.enable_dp_mst &&
3775                 intel_dp_mst_source_support(intel_dp) &&
3776                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3777 }
3778
3779 static void
3780 intel_dp_configure_mst(struct intel_dp *intel_dp)
3781 {
3782         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3783         struct intel_encoder *encoder =
3784                 &dp_to_dig_port(intel_dp)->base;
3785         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
3786
3787         drm_dbg_kms(&i915->drm,
3788                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
3789                     encoder->base.base.id, encoder->base.name,
3790                     str_yes_no(intel_dp_mst_source_support(intel_dp)),
3791                     str_yes_no(sink_can_mst),
3792                     str_yes_no(i915->params.enable_dp_mst));
3793
3794         if (!intel_dp_mst_source_support(intel_dp))
3795                 return;
3796
3797         intel_dp->is_mst = sink_can_mst &&
3798                 i915->params.enable_dp_mst;
3799
3800         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3801                                         intel_dp->is_mst);
3802 }
3803
3804 static bool
3805 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
3806 {
3807         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
3808 }
3809
3810 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
3811 {
3812         int retry;
3813
3814         for (retry = 0; retry < 3; retry++) {
3815                 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
3816                                       &esi[1], 3) == 3)
3817                         return true;
3818         }
3819
3820         return false;
3821 }
3822
3823 bool
3824 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
3825                        const struct drm_connector_state *conn_state)
3826 {
3827         /*
3828          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
3829          * of Color Encoding Format and Content Color Gamut], in order to
3830          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
3831          */
3832         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3833                 return true;
3834
3835         switch (conn_state->colorspace) {
3836         case DRM_MODE_COLORIMETRY_SYCC_601:
3837         case DRM_MODE_COLORIMETRY_OPYCC_601:
3838         case DRM_MODE_COLORIMETRY_BT2020_YCC:
3839         case DRM_MODE_COLORIMETRY_BT2020_RGB:
3840         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
3841                 return true;
3842         default:
3843                 break;
3844         }
3845
3846         return false;
3847 }
3848
3849 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3850                                      struct dp_sdp *sdp, size_t size)
3851 {
3852         size_t length = sizeof(struct dp_sdp);
3853
3854         if (size < length)
3855                 return -ENOSPC;
3856
3857         memset(sdp, 0, size);
3858
3859         /*
3860          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3861          * VSC SDP Header Bytes
3862          */
3863         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3864         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3865         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3866         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3867
3868         /*
3869          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
3870          * per DP 1.4a spec.
3871          */
3872         if (vsc->revision != 0x5)
3873                 goto out;
3874
3875         /* VSC SDP Payload for DB16 through DB18 */
3876         /* Pixel Encoding and Colorimetry Formats  */
3877         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3878         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3879
3880         switch (vsc->bpc) {
3881         case 6:
3882                 /* 6bpc: 0x0 */
3883                 break;
3884         case 8:
3885                 sdp->db[17] = 0x1; /* DB17[3:0] */
3886                 break;
3887         case 10:
3888                 sdp->db[17] = 0x2;
3889                 break;
3890         case 12:
3891                 sdp->db[17] = 0x3;
3892                 break;
3893         case 16:
3894                 sdp->db[17] = 0x4;
3895                 break;
3896         default:
3897                 MISSING_CASE(vsc->bpc);
3898                 break;
3899         }
3900         /* Dynamic Range and Component Bit Depth */
3901         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3902                 sdp->db[17] |= 0x80;  /* DB17[7] */
3903
3904         /* Content Type */
3905         sdp->db[18] = vsc->content_type & 0x7;
3906
3907 out:
3908         return length;
3909 }
3910
3911 static ssize_t
3912 intel_dp_hdr_metadata_infoframe_sdp_pack(struct drm_i915_private *i915,
3913                                          const struct hdmi_drm_infoframe *drm_infoframe,
3914                                          struct dp_sdp *sdp,
3915                                          size_t size)
3916 {
3917         size_t length = sizeof(struct dp_sdp);
3918         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
3919         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
3920         ssize_t len;
3921
3922         if (size < length)
3923                 return -ENOSPC;
3924
3925         memset(sdp, 0, size);
3926
3927         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
3928         if (len < 0) {
3929                 drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");
3930                 return -ENOSPC;
3931         }
3932
3933         if (len != infoframe_size) {
3934                 drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");
3935                 return -ENOSPC;
3936         }
3937
3938         /*
3939          * Set up the infoframe sdp packet for HDR static metadata.
3940          * Prepare VSC Header for SU as per DP 1.4a spec,
3941          * Table 2-100 and Table 2-101
3942          */
3943
3944         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
3945         sdp->sdp_header.HB0 = 0;
3946         /*
3947          * Packet Type 80h + Non-audio INFOFRAME Type value
3948          * HDMI_INFOFRAME_TYPE_DRM: 0x87
3949          * - 80h + Non-audio INFOFRAME Type value
3950          * - InfoFrame Type: 0x07
3951          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
3952          */
3953         sdp->sdp_header.HB1 = drm_infoframe->type;
3954         /*
3955          * Least Significant Eight Bits of (Data Byte Count – 1)
3956          * infoframe_size - 1
3957          */
3958         sdp->sdp_header.HB2 = 0x1D;
3959         /* INFOFRAME SDP Version Number */
3960         sdp->sdp_header.HB3 = (0x13 << 2);
3961         /* CTA Header Byte 2 (INFOFRAME Version Number) */
3962         sdp->db[0] = drm_infoframe->version;
3963         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
3964         sdp->db[1] = drm_infoframe->length;
3965         /*
3966          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
3967          * HDMI_INFOFRAME_HEADER_SIZE
3968          */
3969         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
3970         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
3971                HDMI_DRM_INFOFRAME_SIZE);
3972
3973         /*
3974          * Size of DP infoframe sdp packet for HDR static metadata consists of
3975          * - DP SDP Header(struct dp_sdp_header): 4 bytes
3976          * - Two Data Blocks: 2 bytes
3977          *    CTA Header Byte2 (INFOFRAME Version Number)
3978          *    CTA Header Byte3 (Length of INFOFRAME)
3979          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
3980          *
3981          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
3982          * infoframe size. But GEN11+ has larger than that size, write_infoframe
3983          * will pad rest of the size.
3984          */
3985         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
3986 }
3987
3988 static void intel_write_dp_sdp(struct intel_encoder *encoder,
3989                                const struct intel_crtc_state *crtc_state,
3990                                unsigned int type)
3991 {
3992         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3993         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3994         struct dp_sdp sdp = {};
3995         ssize_t len;
3996
3997         if ((crtc_state->infoframes.enable &
3998              intel_hdmi_infoframe_enable(type)) == 0)
3999                 return;
4000
4001         switch (type) {
4002         case DP_SDP_VSC:
4003                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
4004                                             sizeof(sdp));
4005                 break;
4006         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4007                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(dev_priv,
4008                                                                &crtc_state->infoframes.drm.drm,
4009                                                                &sdp, sizeof(sdp));
4010                 break;
4011         default:
4012                 MISSING_CASE(type);
4013                 return;
4014         }
4015
4016         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4017                 return;
4018
4019         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4020 }
4021
4022 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
4023                             const struct intel_crtc_state *crtc_state,
4024                             const struct drm_dp_vsc_sdp *vsc)
4025 {
4026         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4027         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4028         struct dp_sdp sdp = {};
4029         ssize_t len;
4030
4031         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
4032
4033         if (drm_WARN_ON(&dev_priv->drm, len < 0))
4034                 return;
4035
4036         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
4037                                         &sdp, len);
4038 }
4039
4040 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4041                              bool enable,
4042                              const struct intel_crtc_state *crtc_state,
4043                              const struct drm_connector_state *conn_state)
4044 {
4045         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4046         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
4047         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4048                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4049                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4050         u32 val = intel_de_read(dev_priv, reg) & ~dip_enable;
4051
4052         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
4053         /* When PSR is enabled, this routine doesn't disable VSC DIP */
4054         if (!crtc_state->has_psr)
4055                 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4056
4057         intel_de_write(dev_priv, reg, val);
4058         intel_de_posting_read(dev_priv, reg);
4059
4060         if (!enable)
4061                 return;
4062
4063         /* When PSR is enabled, VSC SDP is handled by PSR routine */
4064         if (!crtc_state->has_psr)
4065                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4066
4067         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4068 }
4069
4070 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4071                                    const void *buffer, size_t size)
4072 {
4073         const struct dp_sdp *sdp = buffer;
4074
4075         if (size < sizeof(struct dp_sdp))
4076                 return -EINVAL;
4077
4078         memset(vsc, 0, sizeof(*vsc));
4079
4080         if (sdp->sdp_header.HB0 != 0)
4081                 return -EINVAL;
4082
4083         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4084                 return -EINVAL;
4085
4086         vsc->sdp_type = sdp->sdp_header.HB1;
4087         vsc->revision = sdp->sdp_header.HB2;
4088         vsc->length = sdp->sdp_header.HB3;
4089
4090         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4091             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
4092                 /*
4093                  * - HB2 = 0x2, HB3 = 0x8
4094                  *   VSC SDP supporting 3D stereo + PSR
4095                  * - HB2 = 0x4, HB3 = 0xe
4096                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4097                  *   first scan line of the SU region (applies to eDP v1.4b
4098                  *   and higher).
4099                  */
4100                 return 0;
4101         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4102                 /*
4103                  * - HB2 = 0x5, HB3 = 0x13
4104                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4105                  *   Format.
4106                  */
4107                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4108                 vsc->colorimetry = sdp->db[16] & 0xf;
4109                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4110
4111                 switch (sdp->db[17] & 0x7) {
4112                 case 0x0:
4113                         vsc->bpc = 6;
4114                         break;
4115                 case 0x1:
4116                         vsc->bpc = 8;
4117                         break;
4118                 case 0x2:
4119                         vsc->bpc = 10;
4120                         break;
4121                 case 0x3:
4122                         vsc->bpc = 12;
4123                         break;
4124                 case 0x4:
4125                         vsc->bpc = 16;
4126                         break;
4127                 default:
4128                         MISSING_CASE(sdp->db[17] & 0x7);
4129                         return -EINVAL;
4130                 }
4131
4132                 vsc->content_type = sdp->db[18] & 0x7;
4133         } else {
4134                 return -EINVAL;
4135         }
4136
4137         return 0;
4138 }
4139
4140 static int
4141 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4142                                            const void *buffer, size_t size)
4143 {
4144         int ret;
4145
4146         const struct dp_sdp *sdp = buffer;
4147
4148         if (size < sizeof(struct dp_sdp))
4149                 return -EINVAL;
4150
4151         if (sdp->sdp_header.HB0 != 0)
4152                 return -EINVAL;
4153
4154         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4155                 return -EINVAL;
4156
4157         /*
4158          * Least Significant Eight Bits of (Data Byte Count – 1)
4159          * 1Dh (i.e., Data Byte Count = 30 bytes).
4160          */
4161         if (sdp->sdp_header.HB2 != 0x1D)
4162                 return -EINVAL;
4163
4164         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4165         if ((sdp->sdp_header.HB3 & 0x3) != 0)
4166                 return -EINVAL;
4167
4168         /* INFOFRAME SDP Version Number */
4169         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4170                 return -EINVAL;
4171
4172         /* CTA Header Byte 2 (INFOFRAME Version Number) */
4173         if (sdp->db[0] != 1)
4174                 return -EINVAL;
4175
4176         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4177         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4178                 return -EINVAL;
4179
4180         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4181                                              HDMI_DRM_INFOFRAME_SIZE);
4182
4183         return ret;
4184 }
4185
4186 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4187                                   struct intel_crtc_state *crtc_state,
4188                                   struct drm_dp_vsc_sdp *vsc)
4189 {
4190         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4191         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4192         unsigned int type = DP_SDP_VSC;
4193         struct dp_sdp sdp = {};
4194         int ret;
4195
4196         /* When PSR is enabled, VSC SDP is handled by PSR routine */
4197         if (crtc_state->has_psr)
4198                 return;
4199
4200         if ((crtc_state->infoframes.enable &
4201              intel_hdmi_infoframe_enable(type)) == 0)
4202                 return;
4203
4204         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4205
4206         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4207
4208         if (ret)
4209                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
4210 }
4211
4212 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4213                                                      struct intel_crtc_state *crtc_state,
4214                                                      struct hdmi_drm_infoframe *drm_infoframe)
4215 {
4216         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4217         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4218         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4219         struct dp_sdp sdp = {};
4220         int ret;
4221
4222         if ((crtc_state->infoframes.enable &
4223             intel_hdmi_infoframe_enable(type)) == 0)
4224                 return;
4225
4226         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4227                                  sizeof(sdp));
4228
4229         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4230                                                          sizeof(sdp));
4231
4232         if (ret)
4233                 drm_dbg_kms(&dev_priv->drm,
4234                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4235 }
4236
4237 void intel_read_dp_sdp(struct intel_encoder *encoder,
4238                        struct intel_crtc_state *crtc_state,
4239                        unsigned int type)
4240 {
4241         switch (type) {
4242         case DP_SDP_VSC:
4243                 intel_read_dp_vsc_sdp(encoder, crtc_state,
4244                                       &crtc_state->infoframes.vsc);
4245                 break;
4246         case HDMI_PACKET_TYPE_GAMUT_METADATA:
4247                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4248                                                          &crtc_state->infoframes.drm.drm);
4249                 break;
4250         default:
4251                 MISSING_CASE(type);
4252                 break;
4253         }
4254 }
4255
4256 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4257 {
4258         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4259         int status = 0;
4260         int test_link_rate;
4261         u8 test_lane_count, test_link_bw;
4262         /* (DP CTS 1.2)
4263          * 4.3.1.11
4264          */
4265         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4266         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4267                                    &test_lane_count);
4268
4269         if (status <= 0) {
4270                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
4271                 return DP_TEST_NAK;
4272         }
4273         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4274
4275         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4276                                    &test_link_bw);
4277         if (status <= 0) {
4278                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
4279                 return DP_TEST_NAK;
4280         }
4281         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4282
4283         /* Validate the requested link rate and lane count */
4284         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4285                                         test_lane_count))
4286                 return DP_TEST_NAK;
4287
4288         intel_dp->compliance.test_lane_count = test_lane_count;
4289         intel_dp->compliance.test_link_rate = test_link_rate;
4290
4291         return DP_TEST_ACK;
4292 }
4293
4294 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4295 {
4296         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4297         u8 test_pattern;
4298         u8 test_misc;
4299         __be16 h_width, v_height;
4300         int status = 0;
4301
4302         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4303         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4304                                    &test_pattern);
4305         if (status <= 0) {
4306                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
4307                 return DP_TEST_NAK;
4308         }
4309         if (test_pattern != DP_COLOR_RAMP)
4310                 return DP_TEST_NAK;
4311
4312         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4313                                   &h_width, 2);
4314         if (status <= 0) {
4315                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
4316                 return DP_TEST_NAK;
4317         }
4318
4319         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4320                                   &v_height, 2);
4321         if (status <= 0) {
4322                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
4323                 return DP_TEST_NAK;
4324         }
4325
4326         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4327                                    &test_misc);
4328         if (status <= 0) {
4329                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
4330                 return DP_TEST_NAK;
4331         }
4332         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4333                 return DP_TEST_NAK;
4334         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4335                 return DP_TEST_NAK;
4336         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4337         case DP_TEST_BIT_DEPTH_6:
4338                 intel_dp->compliance.test_data.bpc = 6;
4339                 break;
4340         case DP_TEST_BIT_DEPTH_8:
4341                 intel_dp->compliance.test_data.bpc = 8;
4342                 break;
4343         default:
4344                 return DP_TEST_NAK;
4345         }
4346
4347         intel_dp->compliance.test_data.video_pattern = test_pattern;
4348         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4349         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4350         /* Set test active flag here so userspace doesn't interrupt things */
4351         intel_dp->compliance.test_active = true;
4352
4353         return DP_TEST_ACK;
4354 }
4355
4356 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4357 {
4358         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4359         u8 test_result = DP_TEST_ACK;
4360         struct intel_connector *intel_connector = intel_dp->attached_connector;
4361         struct drm_connector *connector = &intel_connector->base;
4362
4363         if (intel_connector->detect_edid == NULL ||
4364             connector->edid_corrupt ||
4365             intel_dp->aux.i2c_defer_count > 6) {
4366                 /* Check EDID read for NACKs, DEFERs and corruption
4367                  * (DP CTS 1.2 Core r1.1)
4368                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4369                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4370                  *    4.2.2.6 : EDID corruption detected
4371                  * Use failsafe mode for all cases
4372                  */
4373                 if (intel_dp->aux.i2c_nack_count > 0 ||
4374                         intel_dp->aux.i2c_defer_count > 0)
4375                         drm_dbg_kms(&i915->drm,
4376                                     "EDID read had %d NACKs, %d DEFERs\n",
4377                                     intel_dp->aux.i2c_nack_count,
4378                                     intel_dp->aux.i2c_defer_count);
4379                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4380         } else {
4381                 /* FIXME: Get rid of drm_edid_raw() */
4382                 const struct edid *block = drm_edid_raw(intel_connector->detect_edid);
4383
4384                 /* We have to write the checksum of the last block read */
4385                 block += block->extensions;
4386
4387                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4388                                        block->checksum) <= 0)
4389                         drm_dbg_kms(&i915->drm,
4390                                     "Failed to write EDID checksum\n");
4391
4392                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4393                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4394         }
4395
4396         /* Set test active flag here so userspace doesn't interrupt things */
4397         intel_dp->compliance.test_active = true;
4398
4399         return test_result;
4400 }
4401
4402 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
4403                                         const struct intel_crtc_state *crtc_state)
4404 {
4405         struct drm_i915_private *dev_priv =
4406                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4407         struct drm_dp_phy_test_params *data =
4408                         &intel_dp->compliance.test_data.phytest;
4409         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4410         enum pipe pipe = crtc->pipe;
4411         u32 pattern_val;
4412
4413         switch (data->phy_pattern) {
4414         case DP_PHY_TEST_PATTERN_NONE:
4415                 drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");
4416                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
4417                 break;
4418         case DP_PHY_TEST_PATTERN_D10_2:
4419                 drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");
4420                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4421                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
4422                 break;
4423         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
4424                 drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");
4425                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4426                                DDI_DP_COMP_CTL_ENABLE |
4427                                DDI_DP_COMP_CTL_SCRAMBLED_0);
4428                 break;
4429         case DP_PHY_TEST_PATTERN_PRBS7:
4430                 drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");
4431                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4432                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
4433                 break;
4434         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
4435                 /*
4436                  * FIXME: Ideally pattern should come from DPCD 0x250. As
4437                  * current firmware of DPR-100 could not set it, so hardcoding
4438                  * now for complaince test.
4439                  */
4440                 drm_dbg_kms(&dev_priv->drm,
4441                             "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
4442                 pattern_val = 0x3e0f83e0;
4443                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
4444                 pattern_val = 0x0f83e0f8;
4445                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
4446                 pattern_val = 0x0000f83e;
4447                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
4448                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4449                                DDI_DP_COMP_CTL_ENABLE |
4450                                DDI_DP_COMP_CTL_CUSTOM80);
4451                 break;
4452         case DP_PHY_TEST_PATTERN_CP2520:
4453                 /*
4454                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
4455                  * current firmware of DPR-100 could not set it, so hardcoding
4456                  * now for complaince test.
4457                  */
4458                 drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");
4459                 pattern_val = 0xFB;
4460                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
4461                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
4462                                pattern_val);
4463                 break;
4464         default:
4465                 WARN(1, "Invalid Phy Test Pattern\n");
4466         }
4467 }
4468
4469 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
4470                                          const struct intel_crtc_state *crtc_state)
4471 {
4472         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4473         struct drm_dp_phy_test_params *data =
4474                 &intel_dp->compliance.test_data.phytest;
4475         u8 link_status[DP_LINK_STATUS_SIZE];
4476
4477         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4478                                              link_status) < 0) {
4479                 drm_dbg_kms(&i915->drm, "failed to get link status\n");
4480                 return;
4481         }
4482
4483         /* retrieve vswing & pre-emphasis setting */
4484         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
4485                                   link_status);
4486
4487         intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);
4488
4489         intel_dp_phy_pattern_update(intel_dp, crtc_state);
4490
4491         drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
4492                           intel_dp->train_set, crtc_state->lane_count);
4493
4494         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
4495                                     link_status[DP_DPCD_REV]);
4496 }
4497
4498 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4499 {
4500         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4501         struct drm_dp_phy_test_params *data =
4502                 &intel_dp->compliance.test_data.phytest;
4503
4504         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
4505                 drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");
4506                 return DP_TEST_NAK;
4507         }
4508
4509         /* Set test active flag here so userspace doesn't interrupt things */
4510         intel_dp->compliance.test_active = true;
4511
4512         return DP_TEST_ACK;
4513 }
4514
4515 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4516 {
4517         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4518         u8 response = DP_TEST_NAK;
4519         u8 request = 0;
4520         int status;
4521
4522         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4523         if (status <= 0) {
4524                 drm_dbg_kms(&i915->drm,
4525                             "Could not read test request from sink\n");
4526                 goto update_status;
4527         }
4528
4529         switch (request) {
4530         case DP_TEST_LINK_TRAINING:
4531                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
4532                 response = intel_dp_autotest_link_training(intel_dp);
4533                 break;
4534         case DP_TEST_LINK_VIDEO_PATTERN:
4535                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
4536                 response = intel_dp_autotest_video_pattern(intel_dp);
4537                 break;
4538         case DP_TEST_LINK_EDID_READ:
4539                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
4540                 response = intel_dp_autotest_edid(intel_dp);
4541                 break;
4542         case DP_TEST_LINK_PHY_TEST_PATTERN:
4543                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
4544                 response = intel_dp_autotest_phy_pattern(intel_dp);
4545                 break;
4546         default:
4547                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
4548                             request);
4549                 break;
4550         }
4551
4552         if (response & DP_TEST_ACK)
4553                 intel_dp->compliance.test_type = request;
4554
4555 update_status:
4556         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4557         if (status <= 0)
4558                 drm_dbg_kms(&i915->drm,
4559                             "Could not write test response to sink\n");
4560 }
4561
4562 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4563                              u8 link_status[DP_LINK_STATUS_SIZE])
4564 {
4565         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4566         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4567         bool uhbr = intel_dp->link_rate >= 1000000;
4568         bool ok;
4569
4570         if (uhbr)
4571                 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4572                                                           intel_dp->lane_count);
4573         else
4574                 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4575
4576         if (ok)
4577                 return true;
4578
4579         intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4580         drm_dbg_kms(&i915->drm,
4581                     "[ENCODER:%d:%s] %s link not ok, retraining\n",
4582                     encoder->base.base.id, encoder->base.name,
4583                     uhbr ? "128b/132b" : "8b/10b");
4584
4585         return false;
4586 }
4587
4588 static void
4589 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4590 {
4591         bool handled = false;
4592
4593         drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);
4594
4595         if (esi[1] & DP_CP_IRQ) {
4596                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4597                 ack[1] |= DP_CP_IRQ;
4598         }
4599 }
4600
4601 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4602 {
4603         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4604         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4605         u8 link_status[DP_LINK_STATUS_SIZE] = {};
4606         const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4607
4608         if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4609                              esi_link_status_size) != esi_link_status_size) {
4610                 drm_err(&i915->drm,
4611                         "[ENCODER:%d:%s] Failed to read link status\n",
4612                         encoder->base.base.id, encoder->base.name);
4613                 return false;
4614         }
4615
4616         return intel_dp_link_ok(intel_dp, link_status);
4617 }
4618
4619 /**
4620  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4621  * @intel_dp: Intel DP struct
4622  *
4623  * Read any pending MST interrupts, call MST core to handle these and ack the
4624  * interrupts. Check if the main and AUX link state is ok.
4625  *
4626  * Returns:
4627  * - %true if pending interrupts were serviced (or no interrupts were
4628  *   pending) w/o detecting an error condition.
4629  * - %false if an error condition - like AUX failure or a loss of link - is
4630  *   detected, which needs servicing from the hotplug work.
4631  */
4632 static bool
4633 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4634 {
4635         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4636         bool link_ok = true;
4637
4638         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
4639
4640         for (;;) {
4641                 u8 esi[4] = {};
4642                 u8 ack[4] = {};
4643
4644                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
4645                         drm_dbg_kms(&i915->drm,
4646                                     "failed to get ESI - device may have failed\n");
4647                         link_ok = false;
4648
4649                         break;
4650                 }
4651
4652                 drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);
4653
4654                 if (intel_dp->active_mst_links > 0 && link_ok &&
4655                     esi[3] & LINK_STATUS_CHANGED) {
4656                         if (!intel_dp_mst_link_status(intel_dp))
4657                                 link_ok = false;
4658                         ack[3] |= LINK_STATUS_CHANGED;
4659                 }
4660
4661                 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
4662
4663                 if (!memchr_inv(ack, 0, sizeof(ack)))
4664                         break;
4665
4666                 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
4667                         drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");
4668
4669                 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
4670                         drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);
4671         }
4672
4673         return link_ok;
4674 }
4675
4676 static void
4677 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
4678 {
4679         bool is_active;
4680         u8 buf = 0;
4681
4682         is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
4683         if (intel_dp->frl.is_trained && !is_active) {
4684                 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
4685                         return;
4686
4687                 buf &=  ~DP_PCON_ENABLE_HDMI_LINK;
4688                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
4689                         return;
4690
4691                 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
4692
4693                 intel_dp->frl.is_trained = false;
4694
4695                 /* Restart FRL training or fall back to TMDS mode */
4696                 intel_dp_check_frl_training(intel_dp);
4697         }
4698 }
4699
4700 static bool
4701 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4702 {
4703         u8 link_status[DP_LINK_STATUS_SIZE];
4704
4705         if (!intel_dp->link_trained)
4706                 return false;
4707
4708         /*
4709          * While PSR source HW is enabled, it will control main-link sending
4710          * frames, enabling and disabling it so trying to do a retrain will fail
4711          * as the link would or not be on or it could mix training patterns
4712          * and frame data at the same time causing retrain to fail.
4713          * Also when exiting PSR, HW will retrain the link anyways fixing
4714          * any link status error.
4715          */
4716         if (intel_psr_enabled(intel_dp))
4717                 return false;
4718
4719         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
4720                                              link_status) < 0)
4721                 return false;
4722
4723         /*
4724          * Validate the cached values of intel_dp->link_rate and
4725          * intel_dp->lane_count before attempting to retrain.
4726          *
4727          * FIXME would be nice to user the crtc state here, but since
4728          * we need to call this from the short HPD handler that seems
4729          * a bit hard.
4730          */
4731         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4732                                         intel_dp->lane_count))
4733                 return false;
4734
4735         /* Retrain if link not ok */
4736         return !intel_dp_link_ok(intel_dp, link_status);
4737 }
4738
4739 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
4740                                    const struct drm_connector_state *conn_state)
4741 {
4742         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4743         struct intel_encoder *encoder;
4744         enum pipe pipe;
4745
4746         if (!conn_state->best_encoder)
4747                 return false;
4748
4749         /* SST */
4750         encoder = &dp_to_dig_port(intel_dp)->base;
4751         if (conn_state->best_encoder == &encoder->base)
4752                 return true;
4753
4754         /* MST */
4755         for_each_pipe(i915, pipe) {
4756                 encoder = &intel_dp->mst_encoders[pipe]->base;
4757                 if (conn_state->best_encoder == &encoder->base)
4758                         return true;
4759         }
4760
4761         return false;
4762 }
4763
4764 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
4765                               struct drm_modeset_acquire_ctx *ctx,
4766                               u8 *pipe_mask)
4767 {
4768         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4769         struct drm_connector_list_iter conn_iter;
4770         struct intel_connector *connector;
4771         int ret = 0;
4772
4773         *pipe_mask = 0;
4774
4775         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4776         for_each_intel_connector_iter(connector, &conn_iter) {
4777                 struct drm_connector_state *conn_state =
4778                         connector->base.state;
4779                 struct intel_crtc_state *crtc_state;
4780                 struct intel_crtc *crtc;
4781
4782                 if (!intel_dp_has_connector(intel_dp, conn_state))
4783                         continue;
4784
4785                 crtc = to_intel_crtc(conn_state->crtc);
4786                 if (!crtc)
4787                         continue;
4788
4789                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4790                 if (ret)
4791                         break;
4792
4793                 crtc_state = to_intel_crtc_state(crtc->base.state);
4794
4795                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4796
4797                 if (!crtc_state->hw.active)
4798                         continue;
4799
4800                 if (conn_state->commit &&
4801                     !try_wait_for_completion(&conn_state->commit->hw_done))
4802                         continue;
4803
4804                 *pipe_mask |= BIT(crtc->pipe);
4805         }
4806         drm_connector_list_iter_end(&conn_iter);
4807
4808         return ret;
4809 }
4810
4811 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
4812 {
4813         struct intel_connector *connector = intel_dp->attached_connector;
4814
4815         return connector->base.status == connector_status_connected ||
4816                 intel_dp->is_mst;
4817 }
4818
4819 int intel_dp_retrain_link(struct intel_encoder *encoder,
4820                           struct drm_modeset_acquire_ctx *ctx)
4821 {
4822         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4823         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4824         struct intel_crtc *crtc;
4825         u8 pipe_mask;
4826         int ret;
4827
4828         if (!intel_dp_is_connected(intel_dp))
4829                 return 0;
4830
4831         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4832                                ctx);
4833         if (ret)
4834                 return ret;
4835
4836         if (!intel_dp_needs_link_retrain(intel_dp))
4837                 return 0;
4838
4839         ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
4840         if (ret)
4841                 return ret;
4842
4843         if (pipe_mask == 0)
4844                 return 0;
4845
4846         if (!intel_dp_needs_link_retrain(intel_dp))
4847                 return 0;
4848
4849         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
4850                     encoder->base.base.id, encoder->base.name);
4851
4852         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4853                 const struct intel_crtc_state *crtc_state =
4854                         to_intel_crtc_state(crtc->base.state);
4855
4856                 /* Suppress underruns caused by re-training */
4857                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4858                 if (crtc_state->has_pch_encoder)
4859                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4860                                                               intel_crtc_pch_transcoder(crtc), false);
4861         }
4862
4863         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4864                 const struct intel_crtc_state *crtc_state =
4865                         to_intel_crtc_state(crtc->base.state);
4866
4867                 /* retrain on the MST master transcoder */
4868                 if (DISPLAY_VER(dev_priv) >= 12 &&
4869                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4870                     !intel_dp_mst_is_master_trans(crtc_state))
4871                         continue;
4872
4873                 intel_dp_check_frl_training(intel_dp);
4874                 intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
4875                 intel_dp_start_link_train(intel_dp, crtc_state);
4876                 intel_dp_stop_link_train(intel_dp, crtc_state);
4877                 break;
4878         }
4879
4880         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4881                 const struct intel_crtc_state *crtc_state =
4882                         to_intel_crtc_state(crtc->base.state);
4883
4884                 /* Keep underrun reporting disabled until things are stable */
4885                 intel_crtc_wait_for_next_vblank(crtc);
4886
4887                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4888                 if (crtc_state->has_pch_encoder)
4889                         intel_set_pch_fifo_underrun_reporting(dev_priv,
4890                                                               intel_crtc_pch_transcoder(crtc), true);
4891         }
4892
4893         return 0;
4894 }
4895
4896 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
4897                                   struct drm_modeset_acquire_ctx *ctx,
4898                                   u8 *pipe_mask)
4899 {
4900         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4901         struct drm_connector_list_iter conn_iter;
4902         struct intel_connector *connector;
4903         int ret = 0;
4904
4905         *pipe_mask = 0;
4906
4907         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
4908         for_each_intel_connector_iter(connector, &conn_iter) {
4909                 struct drm_connector_state *conn_state =
4910                         connector->base.state;
4911                 struct intel_crtc_state *crtc_state;
4912                 struct intel_crtc *crtc;
4913
4914                 if (!intel_dp_has_connector(intel_dp, conn_state))
4915                         continue;
4916
4917                 crtc = to_intel_crtc(conn_state->crtc);
4918                 if (!crtc)
4919                         continue;
4920
4921                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4922                 if (ret)
4923                         break;
4924
4925                 crtc_state = to_intel_crtc_state(crtc->base.state);
4926
4927                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
4928
4929                 if (!crtc_state->hw.active)
4930                         continue;
4931
4932                 if (conn_state->commit &&
4933                     !try_wait_for_completion(&conn_state->commit->hw_done))
4934                         continue;
4935
4936                 *pipe_mask |= BIT(crtc->pipe);
4937         }
4938         drm_connector_list_iter_end(&conn_iter);
4939
4940         return ret;
4941 }
4942
4943 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
4944                                 struct drm_modeset_acquire_ctx *ctx)
4945 {
4946         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4947         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4948         struct intel_crtc *crtc;
4949         u8 pipe_mask;
4950         int ret;
4951
4952         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4953                                ctx);
4954         if (ret)
4955                 return ret;
4956
4957         ret = intel_dp_prep_phy_test(intel_dp, ctx, &pipe_mask);
4958         if (ret)
4959                 return ret;
4960
4961         if (pipe_mask == 0)
4962                 return 0;
4963
4964         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
4965                     encoder->base.base.id, encoder->base.name);
4966
4967         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {
4968                 const struct intel_crtc_state *crtc_state =
4969                         to_intel_crtc_state(crtc->base.state);
4970
4971                 /* test on the MST master transcoder */
4972                 if (DISPLAY_VER(dev_priv) >= 12 &&
4973                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
4974                     !intel_dp_mst_is_master_trans(crtc_state))
4975                         continue;
4976
4977                 intel_dp_process_phy_request(intel_dp, crtc_state);
4978                 break;
4979         }
4980
4981         return 0;
4982 }
4983
4984 void intel_dp_phy_test(struct intel_encoder *encoder)
4985 {
4986         struct drm_modeset_acquire_ctx ctx;
4987         int ret;
4988
4989         drm_modeset_acquire_init(&ctx, 0);
4990
4991         for (;;) {
4992                 ret = intel_dp_do_phy_test(encoder, &ctx);
4993
4994                 if (ret == -EDEADLK) {
4995                         drm_modeset_backoff(&ctx);
4996                         continue;
4997                 }
4998
4999                 break;
5000         }
5001
5002         drm_modeset_drop_locks(&ctx);
5003         drm_modeset_acquire_fini(&ctx);
5004         drm_WARN(encoder->base.dev, ret,
5005                  "Acquiring modeset locks failed with %i\n", ret);
5006 }
5007
5008 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5009 {
5010         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5011         u8 val;
5012
5013         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5014                 return;
5015
5016         if (drm_dp_dpcd_readb(&intel_dp->aux,
5017                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5018                 return;
5019
5020         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5021
5022         if (val & DP_AUTOMATED_TEST_REQUEST)
5023                 intel_dp_handle_test_request(intel_dp);
5024
5025         if (val & DP_CP_IRQ)
5026                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5027
5028         if (val & DP_SINK_SPECIFIC_IRQ)
5029                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
5030 }
5031
5032 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5033 {
5034         u8 val;
5035
5036         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5037                 return;
5038
5039         if (drm_dp_dpcd_readb(&intel_dp->aux,
5040                               DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5041                 return;
5042
5043         if (drm_dp_dpcd_writeb(&intel_dp->aux,
5044                                DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5045                 return;
5046
5047         if (val & HDMI_LINK_STATUS_CHANGED)
5048                 intel_dp_handle_hdmi_link_status_change(intel_dp);
5049 }
5050
5051 /*
5052  * According to DP spec
5053  * 5.1.2:
5054  *  1. Read DPCD
5055  *  2. Configure link according to Receiver Capabilities
5056  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
5057  *  4. Check link status on receipt of hot-plug interrupt
5058  *
5059  * intel_dp_short_pulse -  handles short pulse interrupts
5060  * when full detection is not required.
5061  * Returns %true if short pulse is handled and full detection
5062  * is NOT required and %false otherwise.
5063  */
5064 static bool
5065 intel_dp_short_pulse(struct intel_dp *intel_dp)
5066 {
5067         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5068         u8 old_sink_count = intel_dp->sink_count;
5069         bool ret;
5070
5071         /*
5072          * Clearing compliance test variables to allow capturing
5073          * of values for next automated test request.
5074          */
5075         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5076
5077         /*
5078          * Now read the DPCD to see if it's actually running
5079          * If the current value of sink count doesn't match with
5080          * the value that was stored earlier or dpcd read failed
5081          * we need to do full detection
5082          */
5083         ret = intel_dp_get_dpcd(intel_dp);
5084
5085         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5086                 /* No need to proceed if we are going to do full detect */
5087                 return false;
5088         }
5089
5090         intel_dp_check_device_service_irq(intel_dp);
5091         intel_dp_check_link_service_irq(intel_dp);
5092
5093         /* Handle CEC interrupts, if any */
5094         drm_dp_cec_irq(&intel_dp->aux);
5095
5096         /* defer to the hotplug work for link retraining if needed */
5097         if (intel_dp_needs_link_retrain(intel_dp))
5098                 return false;
5099
5100         intel_psr_short_pulse(intel_dp);
5101
5102         switch (intel_dp->compliance.test_type) {
5103         case DP_TEST_LINK_TRAINING:
5104                 drm_dbg_kms(&dev_priv->drm,
5105                             "Link Training Compliance Test requested\n");
5106                 /* Send a Hotplug Uevent to userspace to start modeset */
5107                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5108                 break;
5109         case DP_TEST_LINK_PHY_TEST_PATTERN:
5110                 drm_dbg_kms(&dev_priv->drm,
5111                             "PHY test pattern Compliance Test requested\n");
5112                 /*
5113                  * Schedule long hpd to do the test
5114                  *
5115                  * FIXME get rid of the ad-hoc phy test modeset code
5116                  * and properly incorporate it into the normal modeset.
5117                  */
5118                 return false;
5119         }
5120
5121         return true;
5122 }
5123
5124 /* XXX this is probably wrong for multiple downstream ports */
5125 static enum drm_connector_status
5126 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5127 {
5128         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5129         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5130         u8 *dpcd = intel_dp->dpcd;
5131         u8 type;
5132
5133         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
5134                 return connector_status_connected;
5135
5136         lspcon_resume(dig_port);
5137
5138         if (!intel_dp_get_dpcd(intel_dp))
5139                 return connector_status_disconnected;
5140
5141         /* if there's no downstream port, we're done */
5142         if (!drm_dp_is_branch(dpcd))
5143                 return connector_status_connected;
5144
5145         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5146         if (intel_dp_has_sink_count(intel_dp) &&
5147             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5148                 return intel_dp->sink_count ?
5149                 connector_status_connected : connector_status_disconnected;
5150         }
5151
5152         if (intel_dp_can_mst(intel_dp))
5153                 return connector_status_connected;
5154
5155         /* If no HPD, poke DDC gently */
5156         if (drm_probe_ddc(&intel_dp->aux.ddc))
5157                 return connector_status_connected;
5158
5159         /* Well we tried, say unknown for unreliable port types */
5160         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5161                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5162                 if (type == DP_DS_PORT_TYPE_VGA ||
5163                     type == DP_DS_PORT_TYPE_NON_EDID)
5164                         return connector_status_unknown;
5165         } else {
5166                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5167                         DP_DWN_STRM_PORT_TYPE_MASK;
5168                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5169                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5170                         return connector_status_unknown;
5171         }
5172
5173         /* Anything else is out of spec, warn and ignore */
5174         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
5175         return connector_status_disconnected;
5176 }
5177
5178 static enum drm_connector_status
5179 edp_detect(struct intel_dp *intel_dp)
5180 {
5181         return connector_status_connected;
5182 }
5183
5184 /*
5185  * intel_digital_port_connected - is the specified port connected?
5186  * @encoder: intel_encoder
5187  *
5188  * In cases where there's a connector physically connected but it can't be used
5189  * by our hardware we also return false, since the rest of the driver should
5190  * pretty much treat the port as disconnected. This is relevant for type-C
5191  * (starting on ICL) where there's ownership involved.
5192  *
5193  * Return %true if port is connected, %false otherwise.
5194  */
5195 bool intel_digital_port_connected(struct intel_encoder *encoder)
5196 {
5197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5198         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5199         bool is_connected = false;
5200         intel_wakeref_t wakeref;
5201
5202         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5203                 is_connected = dig_port->connected(encoder);
5204
5205         return is_connected;
5206 }
5207
5208 static const struct drm_edid *
5209 intel_dp_get_edid(struct intel_dp *intel_dp)
5210 {
5211         struct intel_connector *connector = intel_dp->attached_connector;
5212         const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5213
5214         /* Use panel fixed edid if we have one */
5215         if (fixed_edid) {
5216                 /* invalid edid */
5217                 if (IS_ERR(fixed_edid))
5218                         return NULL;
5219
5220                 return drm_edid_dup(fixed_edid);
5221         }
5222
5223         return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5224 }
5225
5226 static void
5227 intel_dp_update_dfp(struct intel_dp *intel_dp,
5228                     const struct drm_edid *drm_edid)
5229 {
5230         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5231         struct intel_connector *connector = intel_dp->attached_connector;
5232
5233         intel_dp->dfp.max_bpc =
5234                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5235                                           intel_dp->downstream_ports, drm_edid);
5236
5237         intel_dp->dfp.max_dotclock =
5238                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5239                                                intel_dp->downstream_ports);
5240
5241         intel_dp->dfp.min_tmds_clock =
5242                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5243                                                  intel_dp->downstream_ports,
5244                                                  drm_edid);
5245         intel_dp->dfp.max_tmds_clock =
5246                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5247                                                  intel_dp->downstream_ports,
5248                                                  drm_edid);
5249
5250         intel_dp->dfp.pcon_max_frl_bw =
5251                 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5252                                            intel_dp->downstream_ports);
5253
5254         drm_dbg_kms(&i915->drm,
5255                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5256                     connector->base.base.id, connector->base.name,
5257                     intel_dp->dfp.max_bpc,
5258                     intel_dp->dfp.max_dotclock,
5259                     intel_dp->dfp.min_tmds_clock,
5260                     intel_dp->dfp.max_tmds_clock,
5261                     intel_dp->dfp.pcon_max_frl_bw);
5262
5263         intel_dp_get_pcon_dsc_cap(intel_dp);
5264 }
5265
5266 static bool
5267 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5268 {
5269         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5270             (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5271                 return true;
5272
5273         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5274             dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5275                 return true;
5276
5277         if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5278             dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5279                 return true;
5280
5281         return false;
5282 }
5283
5284 static void
5285 intel_dp_update_420(struct intel_dp *intel_dp)
5286 {
5287         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5288         struct intel_connector *connector = intel_dp->attached_connector;
5289
5290         intel_dp->dfp.ycbcr420_passthrough =
5291                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5292                                                   intel_dp->downstream_ports);
5293         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5294         intel_dp->dfp.ycbcr_444_to_420 =
5295                 dp_to_dig_port(intel_dp)->lspcon.active ||
5296                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5297                                                         intel_dp->downstream_ports);
5298         intel_dp->dfp.rgb_to_ycbcr =
5299                 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5300                                                           intel_dp->downstream_ports,
5301                                                           DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5302
5303         connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5304
5305         drm_dbg_kms(&i915->drm,
5306                     "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5307                     connector->base.base.id, connector->base.name,
5308                     str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5309                     str_yes_no(connector->base.ycbcr_420_allowed),
5310                     str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5311 }
5312
5313 static void
5314 intel_dp_set_edid(struct intel_dp *intel_dp)
5315 {
5316         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5317         struct intel_connector *connector = intel_dp->attached_connector;
5318         const struct drm_edid *drm_edid;
5319         bool vrr_capable;
5320
5321         intel_dp_unset_edid(intel_dp);
5322         drm_edid = intel_dp_get_edid(intel_dp);
5323         connector->detect_edid = drm_edid;
5324
5325         /* Below we depend on display info having been updated */
5326         drm_edid_connector_update(&connector->base, drm_edid);
5327
5328         vrr_capable = intel_vrr_is_capable(connector);
5329         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5330                     connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5331         drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5332
5333         intel_dp_update_dfp(intel_dp, drm_edid);
5334         intel_dp_update_420(intel_dp);
5335
5336         drm_dp_cec_attach(&intel_dp->aux,
5337                           connector->base.display_info.source_physical_address);
5338 }
5339
5340 static void
5341 intel_dp_unset_edid(struct intel_dp *intel_dp)
5342 {
5343         struct intel_connector *connector = intel_dp->attached_connector;
5344
5345         drm_dp_cec_unset_edid(&intel_dp->aux);
5346         drm_edid_free(connector->detect_edid);
5347         connector->detect_edid = NULL;
5348
5349         intel_dp->dfp.max_bpc = 0;
5350         intel_dp->dfp.max_dotclock = 0;
5351         intel_dp->dfp.min_tmds_clock = 0;
5352         intel_dp->dfp.max_tmds_clock = 0;
5353
5354         intel_dp->dfp.pcon_max_frl_bw = 0;
5355
5356         intel_dp->dfp.ycbcr_444_to_420 = false;
5357         connector->base.ycbcr_420_allowed = false;
5358
5359         drm_connector_set_vrr_capable_property(&connector->base,
5360                                                false);
5361 }
5362
5363 static void
5364 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
5365 {
5366         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5367
5368         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5369         if (!HAS_DSC(i915))
5370                 return;
5371
5372         if (intel_dp_is_edp(intel_dp))
5373                 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
5374                                            connector);
5375         else
5376                 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
5377                                           connector);
5378 }
5379
5380 static int
5381 intel_dp_detect(struct drm_connector *connector,
5382                 struct drm_modeset_acquire_ctx *ctx,
5383                 bool force)
5384 {
5385         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5386         struct intel_connector *intel_connector =
5387                 to_intel_connector(connector);
5388         struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5389         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5390         struct intel_encoder *encoder = &dig_port->base;
5391         enum drm_connector_status status;
5392
5393         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5394                     connector->base.id, connector->name);
5395         drm_WARN_ON(&dev_priv->drm,
5396                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5397
5398         if (!intel_display_device_enabled(dev_priv))
5399                 return connector_status_disconnected;
5400
5401         /* Can't disconnect eDP */
5402         if (intel_dp_is_edp(intel_dp))
5403                 status = edp_detect(intel_dp);
5404         else if (intel_digital_port_connected(encoder))
5405                 status = intel_dp_detect_dpcd(intel_dp);
5406         else
5407                 status = connector_status_disconnected;
5408
5409         if (status == connector_status_disconnected) {
5410                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5411                 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));
5412
5413                 if (intel_dp->is_mst) {
5414                         drm_dbg_kms(&dev_priv->drm,
5415                                     "MST device may have disappeared %d vs %d\n",
5416                                     intel_dp->is_mst,
5417                                     intel_dp->mst_mgr.mst_state);
5418                         intel_dp->is_mst = false;
5419                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5420                                                         intel_dp->is_mst);
5421                 }
5422
5423                 goto out;
5424         }
5425
5426         intel_dp_detect_dsc_caps(intel_dp, intel_connector);
5427
5428         intel_dp_configure_mst(intel_dp);
5429
5430         /*
5431          * TODO: Reset link params when switching to MST mode, until MST
5432          * supports link training fallback params.
5433          */
5434         if (intel_dp->reset_link_params || intel_dp->is_mst) {
5435                 intel_dp_reset_max_link_params(intel_dp);
5436                 intel_dp->reset_link_params = false;
5437         }
5438
5439         intel_dp_print_rates(intel_dp);
5440
5441         if (intel_dp->is_mst) {
5442                 /*
5443                  * If we are in MST mode then this connector
5444                  * won't appear connected or have anything
5445                  * with EDID on it
5446                  */
5447                 status = connector_status_disconnected;
5448                 goto out;
5449         }
5450
5451         /*
5452          * Some external monitors do not signal loss of link synchronization
5453          * with an IRQ_HPD, so force a link status check.
5454          */
5455         if (!intel_dp_is_edp(intel_dp)) {
5456                 int ret;
5457
5458                 ret = intel_dp_retrain_link(encoder, ctx);
5459                 if (ret)
5460                         return ret;
5461         }
5462
5463         /*
5464          * Clearing NACK and defer counts to get their exact values
5465          * while reading EDID which are required by Compliance tests
5466          * 4.2.2.4 and 4.2.2.5
5467          */
5468         intel_dp->aux.i2c_nack_count = 0;
5469         intel_dp->aux.i2c_defer_count = 0;
5470
5471         intel_dp_set_edid(intel_dp);
5472         if (intel_dp_is_edp(intel_dp) ||
5473             to_intel_connector(connector)->detect_edid)
5474                 status = connector_status_connected;
5475
5476         intel_dp_check_device_service_irq(intel_dp);
5477
5478 out:
5479         if (status != connector_status_connected && !intel_dp->is_mst)
5480                 intel_dp_unset_edid(intel_dp);
5481
5482         if (!intel_dp_is_edp(intel_dp))
5483                 drm_dp_set_subconnector_property(connector,
5484                                                  status,
5485                                                  intel_dp->dpcd,
5486                                                  intel_dp->downstream_ports);
5487         return status;
5488 }
5489
5490 static void
5491 intel_dp_force(struct drm_connector *connector)
5492 {
5493         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5494         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5495         struct intel_encoder *intel_encoder = &dig_port->base;
5496         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5497
5498         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
5499                     connector->base.id, connector->name);
5500         intel_dp_unset_edid(intel_dp);
5501
5502         if (connector->status != connector_status_connected)
5503                 return;
5504
5505         intel_dp_set_edid(intel_dp);
5506 }
5507
5508 static int intel_dp_get_modes(struct drm_connector *connector)
5509 {
5510         struct intel_connector *intel_connector = to_intel_connector(connector);
5511         int num_modes;
5512
5513         /* drm_edid_connector_update() done in ->detect() or ->force() */
5514         num_modes = drm_edid_connector_add_modes(connector);
5515
5516         /* Also add fixed mode, which may or may not be present in EDID */
5517         if (intel_dp_is_edp(intel_attached_dp(intel_connector)))
5518                 num_modes += intel_panel_get_modes(intel_connector);
5519
5520         if (num_modes)
5521                 return num_modes;
5522
5523         if (!intel_connector->detect_edid) {
5524                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
5525                 struct drm_display_mode *mode;
5526
5527                 mode = drm_dp_downstream_mode(connector->dev,
5528                                               intel_dp->dpcd,
5529                                               intel_dp->downstream_ports);
5530                 if (mode) {
5531                         drm_mode_probed_add(connector, mode);
5532                         num_modes++;
5533                 }
5534         }
5535
5536         return num_modes;
5537 }
5538
5539 static int
5540 intel_dp_connector_register(struct drm_connector *connector)
5541 {
5542         struct drm_i915_private *i915 = to_i915(connector->dev);
5543         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5544         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5545         struct intel_lspcon *lspcon = &dig_port->lspcon;
5546         int ret;
5547
5548         ret = intel_connector_register(connector);
5549         if (ret)
5550                 return ret;
5551
5552         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
5553                     intel_dp->aux.name, connector->kdev->kobj.name);
5554
5555         intel_dp->aux.dev = connector->kdev;
5556         ret = drm_dp_aux_register(&intel_dp->aux);
5557         if (!ret)
5558                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5559
5560         if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5561                 return ret;
5562
5563         /*
5564          * ToDo: Clean this up to handle lspcon init and resume more
5565          * efficiently and streamlined.
5566          */
5567         if (lspcon_init(dig_port)) {
5568                 lspcon_detect_hdr_capability(lspcon);
5569                 if (lspcon->hdr_supported)
5570                         drm_connector_attach_hdr_output_metadata_property(connector);
5571         }
5572
5573         return ret;
5574 }
5575
5576 static void
5577 intel_dp_connector_unregister(struct drm_connector *connector)
5578 {
5579         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5580
5581         drm_dp_cec_unregister_connector(&intel_dp->aux);
5582         drm_dp_aux_unregister(&intel_dp->aux);
5583         intel_connector_unregister(connector);
5584 }
5585
5586 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5587 {
5588         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
5589         struct intel_dp *intel_dp = &dig_port->dp;
5590
5591         intel_dp_mst_encoder_cleanup(dig_port);
5592
5593         intel_pps_vdd_off_sync(intel_dp);
5594
5595         /*
5596          * Ensure power off delay is respected on module remove, so that we can
5597          * reduce delays at driver probe. See pps_init_timestamps().
5598          */
5599         intel_pps_wait_power_cycle(intel_dp);
5600
5601         intel_dp_aux_fini(intel_dp);
5602 }
5603
5604 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5605 {
5606         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5607
5608         intel_pps_vdd_off_sync(intel_dp);
5609 }
5610
5611 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
5612 {
5613         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
5614
5615         intel_pps_wait_power_cycle(intel_dp);
5616 }
5617
5618 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5619                                     int tile_group_id)
5620 {
5621         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5622         struct drm_connector_list_iter conn_iter;
5623         struct drm_connector *connector;
5624         int ret = 0;
5625
5626         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
5627         drm_for_each_connector_iter(connector, &conn_iter) {
5628                 struct drm_connector_state *conn_state;
5629                 struct intel_crtc_state *crtc_state;
5630                 struct intel_crtc *crtc;
5631
5632                 if (!connector->has_tile ||
5633                     connector->tile_group->id != tile_group_id)
5634                         continue;
5635
5636                 conn_state = drm_atomic_get_connector_state(&state->base,
5637                                                             connector);
5638                 if (IS_ERR(conn_state)) {
5639                         ret = PTR_ERR(conn_state);
5640                         break;
5641                 }
5642
5643                 crtc = to_intel_crtc(conn_state->crtc);
5644
5645                 if (!crtc)
5646                         continue;
5647
5648                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5649                 crtc_state->uapi.mode_changed = true;
5650
5651                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5652                 if (ret)
5653                         break;
5654         }
5655         drm_connector_list_iter_end(&conn_iter);
5656
5657         return ret;
5658 }
5659
5660 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
5661 {
5662         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5663         struct intel_crtc *crtc;
5664
5665         if (transcoders == 0)
5666                 return 0;
5667
5668         for_each_intel_crtc(&dev_priv->drm, crtc) {
5669                 struct intel_crtc_state *crtc_state;
5670                 int ret;
5671
5672                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5673                 if (IS_ERR(crtc_state))
5674                         return PTR_ERR(crtc_state);
5675
5676                 if (!crtc_state->hw.enable)
5677                         continue;
5678
5679                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
5680                         continue;
5681
5682                 crtc_state->uapi.mode_changed = true;
5683
5684                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
5685                 if (ret)
5686                         return ret;
5687
5688                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
5689                 if (ret)
5690                         return ret;
5691
5692                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
5693         }
5694
5695         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
5696
5697         return 0;
5698 }
5699
5700 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
5701                                       struct drm_connector *connector)
5702 {
5703         const struct drm_connector_state *old_conn_state =
5704                 drm_atomic_get_old_connector_state(&state->base, connector);
5705         const struct intel_crtc_state *old_crtc_state;
5706         struct intel_crtc *crtc;
5707         u8 transcoders;
5708
5709         crtc = to_intel_crtc(old_conn_state->crtc);
5710         if (!crtc)
5711                 return 0;
5712
5713         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5714
5715         if (!old_crtc_state->hw.active)
5716                 return 0;
5717
5718         transcoders = old_crtc_state->sync_mode_slaves_mask;
5719         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
5720                 transcoders |= BIT(old_crtc_state->master_transcoder);
5721
5722         return intel_modeset_affected_transcoders(state,
5723                                                   transcoders);
5724 }
5725
5726 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
5727                                            struct drm_atomic_state *_state)
5728 {
5729         struct drm_i915_private *dev_priv = to_i915(conn->dev);
5730         struct intel_atomic_state *state = to_intel_atomic_state(_state);
5731         struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
5732         struct intel_connector *intel_conn = to_intel_connector(conn);
5733         struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
5734         int ret;
5735
5736         ret = intel_digital_connector_atomic_check(conn, &state->base);
5737         if (ret)
5738                 return ret;
5739
5740         if (intel_dp_mst_source_support(intel_dp)) {
5741                 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);
5742                 if (ret)
5743                         return ret;
5744         }
5745
5746         /*
5747          * We don't enable port sync on BDW due to missing w/as and
5748          * due to not having adjusted the modeset sequence appropriately.
5749          */
5750         if (DISPLAY_VER(dev_priv) < 9)
5751                 return 0;
5752
5753         if (!intel_connector_needs_modeset(state, conn))
5754                 return 0;
5755
5756         if (conn->has_tile) {
5757                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
5758                 if (ret)
5759                         return ret;
5760         }
5761
5762         return intel_modeset_synced_crtcs(state, conn);
5763 }
5764
5765 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
5766                                        enum drm_connector_status hpd_state)
5767 {
5768         struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
5769         struct drm_i915_private *i915 = to_i915(connector->dev);
5770         bool hpd_high = hpd_state == connector_status_connected;
5771         unsigned int hpd_pin = encoder->hpd_pin;
5772         bool need_work = false;
5773
5774         spin_lock_irq(&i915->irq_lock);
5775         if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {
5776                 i915->display.hotplug.event_bits |= BIT(hpd_pin);
5777
5778                 __assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);
5779                 need_work = true;
5780         }
5781         spin_unlock_irq(&i915->irq_lock);
5782
5783         if (need_work)
5784                 queue_delayed_work(i915->unordered_wq, &i915->display.hotplug.hotplug_work, 0);
5785 }
5786
5787 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5788         .force = intel_dp_force,
5789         .fill_modes = drm_helper_probe_single_connector_modes,
5790         .atomic_get_property = intel_digital_connector_atomic_get_property,
5791         .atomic_set_property = intel_digital_connector_atomic_set_property,
5792         .late_register = intel_dp_connector_register,
5793         .early_unregister = intel_dp_connector_unregister,
5794         .destroy = intel_connector_destroy,
5795         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5796         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5797         .oob_hotplug_event = intel_dp_oob_hotplug_event,
5798 };
5799
5800 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5801         .detect_ctx = intel_dp_detect,
5802         .get_modes = intel_dp_get_modes,
5803         .mode_valid = intel_dp_mode_valid,
5804         .atomic_check = intel_dp_connector_atomic_check,
5805 };
5806
5807 enum irqreturn
5808 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
5809 {
5810         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
5811         struct intel_dp *intel_dp = &dig_port->dp;
5812
5813         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
5814             (long_hpd || !intel_pps_have_panel_power_or_vdd(intel_dp))) {
5815                 /*
5816                  * vdd off can generate a long/short pulse on eDP which
5817                  * would require vdd on to handle it, and thus we
5818                  * would end up in an endless cycle of
5819                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
5820                  */
5821                 drm_dbg_kms(&i915->drm,
5822                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
5823                             long_hpd ? "long" : "short",
5824                             dig_port->base.base.base.id,
5825                             dig_port->base.base.name);
5826                 return IRQ_HANDLED;
5827         }
5828
5829         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
5830                     dig_port->base.base.base.id,
5831                     dig_port->base.base.name,
5832                     long_hpd ? "long" : "short");
5833
5834         if (long_hpd) {
5835                 intel_dp->reset_link_params = true;
5836                 return IRQ_NONE;
5837         }
5838
5839         if (intel_dp->is_mst) {
5840                 if (!intel_dp_check_mst_status(intel_dp))
5841                         return IRQ_NONE;
5842         } else if (!intel_dp_short_pulse(intel_dp)) {
5843                 return IRQ_NONE;
5844         }
5845
5846         return IRQ_HANDLED;
5847 }
5848
5849 static bool _intel_dp_is_port_edp(struct drm_i915_private *dev_priv,
5850                                   const struct intel_bios_encoder_data *devdata,
5851                                   enum port port)
5852 {
5853         /*
5854          * eDP not supported on g4x. so bail out early just
5855          * for a bit extra safety in case the VBT is bonkers.
5856          */
5857         if (DISPLAY_VER(dev_priv) < 5)
5858                 return false;
5859
5860         if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)
5861                 return true;
5862
5863         return devdata && intel_bios_encoder_supports_edp(devdata);
5864 }
5865
5866 bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port)
5867 {
5868         const struct intel_bios_encoder_data *devdata =
5869                 intel_bios_encoder_data_lookup(i915, port);
5870
5871         return _intel_dp_is_port_edp(i915, devdata, port);
5872 }
5873
5874 static bool
5875 has_gamut_metadata_dip(struct intel_encoder *encoder)
5876 {
5877         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
5878         enum port port = encoder->port;
5879
5880         if (intel_bios_encoder_is_lspcon(encoder->devdata))
5881                 return false;
5882
5883         if (DISPLAY_VER(i915) >= 11)
5884                 return true;
5885
5886         if (port == PORT_A)
5887                 return false;
5888
5889         if (IS_HASWELL(i915) || IS_BROADWELL(i915) ||
5890             DISPLAY_VER(i915) >= 9)
5891                 return true;
5892
5893         return false;
5894 }
5895
5896 static void
5897 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5898 {
5899         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5900         enum port port = dp_to_dig_port(intel_dp)->base.port;
5901
5902         if (!intel_dp_is_edp(intel_dp))
5903                 drm_connector_attach_dp_subconnector_property(connector);
5904
5905         if (!IS_G4X(dev_priv) && port != PORT_A)
5906                 intel_attach_force_audio_property(connector);
5907
5908         intel_attach_broadcast_rgb_property(connector);
5909         if (HAS_GMCH(dev_priv))
5910                 drm_connector_attach_max_bpc_property(connector, 6, 10);
5911         else if (DISPLAY_VER(dev_priv) >= 5)
5912                 drm_connector_attach_max_bpc_property(connector, 6, 12);
5913
5914         /* Register HDMI colorspace for case of lspcon */
5915         if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
5916                 drm_connector_attach_content_type_property(connector);
5917                 intel_attach_hdmi_colorspace_property(connector);
5918         } else {
5919                 intel_attach_dp_colorspace_property(connector);
5920         }
5921
5922         if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
5923                 drm_connector_attach_hdr_output_metadata_property(connector);
5924
5925         if (HAS_VRR(dev_priv))
5926                 drm_connector_attach_vrr_capable_property(connector);
5927 }
5928
5929 static void
5930 intel_edp_add_properties(struct intel_dp *intel_dp)
5931 {
5932         struct intel_connector *connector = intel_dp->attached_connector;
5933         struct drm_i915_private *i915 = to_i915(connector->base.dev);
5934         const struct drm_display_mode *fixed_mode =
5935                 intel_panel_preferred_fixed_mode(connector);
5936
5937         intel_attach_scaling_mode_property(&connector->base);
5938
5939         drm_connector_set_panel_orientation_with_quirk(&connector->base,
5940                                                        i915->display.vbt.orientation,
5941                                                        fixed_mode->hdisplay,
5942                                                        fixed_mode->vdisplay);
5943 }
5944
5945 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
5946                                       struct intel_connector *connector)
5947 {
5948         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5949         enum pipe pipe = INVALID_PIPE;
5950
5951         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
5952                 /*
5953                  * Figure out the current pipe for the initial backlight setup.
5954                  * If the current pipe isn't valid, try the PPS pipe, and if that
5955                  * fails just assume pipe A.
5956                  */
5957                 pipe = vlv_active_pipe(intel_dp);
5958
5959                 if (pipe != PIPE_A && pipe != PIPE_B)
5960                         pipe = intel_dp->pps.pps_pipe;
5961
5962                 if (pipe != PIPE_A && pipe != PIPE_B)
5963                         pipe = PIPE_A;
5964         }
5965
5966         intel_backlight_setup(connector, pipe);
5967 }
5968
5969 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5970                                      struct intel_connector *intel_connector)
5971 {
5972         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5973         struct drm_connector *connector = &intel_connector->base;
5974         struct drm_display_mode *fixed_mode;
5975         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5976         bool has_dpcd;
5977         const struct drm_edid *drm_edid;
5978
5979         if (!intel_dp_is_edp(intel_dp))
5980                 return true;
5981
5982         /*
5983          * On IBX/CPT we may get here with LVDS already registered. Since the
5984          * driver uses the only internal power sequencer available for both
5985          * eDP and LVDS bail out early in this case to prevent interfering
5986          * with an already powered-on LVDS power sequencer.
5987          */
5988         if (intel_get_lvds_encoder(dev_priv)) {
5989                 drm_WARN_ON(&dev_priv->drm,
5990                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5991                 drm_info(&dev_priv->drm,
5992                          "LVDS was detected, not registering eDP\n");
5993
5994                 return false;
5995         }
5996
5997         intel_bios_init_panel_early(dev_priv, &intel_connector->panel,
5998                                     encoder->devdata);
5999
6000         if (!intel_pps_init(intel_dp)) {
6001                 drm_info(&dev_priv->drm,
6002                          "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6003                          encoder->base.base.id, encoder->base.name);
6004                 /*
6005                  * The BIOS may have still enabled VDD on the PPS even
6006                  * though it's unusable. Make sure we turn it back off
6007                  * and to release the power domain references/etc.
6008                  */
6009                 goto out_vdd_off;
6010         }
6011
6012         /*
6013          * Enable HPD sense for live status check.
6014          * intel_hpd_irq_setup() will turn it off again
6015          * if it's no longer needed later.
6016          *
6017          * The DPCD probe below will make sure VDD is on.
6018          */
6019         intel_hpd_enable_detection(encoder);
6020
6021         /* Cache DPCD and EDID for edp. */
6022         has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector);
6023
6024         if (!has_dpcd) {
6025                 /* if this fails, presume the device is a ghost */
6026                 drm_info(&dev_priv->drm,
6027                          "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6028                          encoder->base.base.id, encoder->base.name);
6029                 goto out_vdd_off;
6030         }
6031
6032         /*
6033          * VBT and straps are liars. Also check HPD as that seems
6034          * to be the most reliable piece of information available.
6035          *
6036          * ... expect on devices that forgot to hook HPD up for eDP
6037          * (eg. Acer Chromebook C710), so we'll check it only if multiple
6038          * ports are attempting to use the same AUX CH, according to VBT.
6039          */
6040         if (intel_bios_dp_has_shared_aux_ch(encoder->devdata) &&
6041             !intel_digital_port_connected(encoder)) {
6042                 /*
6043                  * If this fails, presume the DPCD answer came
6044                  * from some other port using the same AUX CH.
6045                  *
6046                  * FIXME maybe cleaner to check this before the
6047                  * DPCD read? Would need sort out the VDD handling...
6048                  */
6049                 drm_info(&dev_priv->drm,
6050                          "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6051                          encoder->base.base.id, encoder->base.name);
6052                 goto out_vdd_off;
6053         }
6054
6055         mutex_lock(&dev_priv->drm.mode_config.mutex);
6056         drm_edid = drm_edid_read_ddc(connector, connector->ddc);
6057         if (!drm_edid) {
6058                 /* Fallback to EDID from ACPI OpRegion, if any */
6059                 drm_edid = intel_opregion_get_edid(intel_connector);
6060                 if (drm_edid)
6061                         drm_dbg_kms(&dev_priv->drm,
6062                                     "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6063                                     connector->base.id, connector->name);
6064         }
6065         if (drm_edid) {
6066                 if (drm_edid_connector_update(connector, drm_edid) ||
6067                     !drm_edid_connector_add_modes(connector)) {
6068                         drm_edid_connector_update(connector, NULL);
6069                         drm_edid_free(drm_edid);
6070                         drm_edid = ERR_PTR(-EINVAL);
6071                 }
6072         } else {
6073                 drm_edid = ERR_PTR(-ENOENT);
6074         }
6075
6076         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata,
6077                                    IS_ERR(drm_edid) ? NULL : drm_edid);
6078
6079         intel_panel_add_edid_fixed_modes(intel_connector, true);
6080
6081         /* MSO requires information from the EDID */
6082         intel_edp_mso_init(intel_dp);
6083
6084         /* multiply the mode clock and horizontal timings for MSO */
6085         list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)
6086                 intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
6087
6088         /* fallback to VBT if available for eDP */
6089         if (!intel_panel_preferred_fixed_mode(intel_connector))
6090                 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
6091
6092         mutex_unlock(&dev_priv->drm.mode_config.mutex);
6093
6094         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
6095                 drm_info(&dev_priv->drm,
6096                          "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6097                          encoder->base.base.id, encoder->base.name);
6098                 goto out_vdd_off;
6099         }
6100
6101         intel_panel_init(intel_connector, drm_edid);
6102
6103         intel_edp_backlight_setup(intel_dp, intel_connector);
6104
6105         intel_edp_add_properties(intel_dp);
6106
6107         intel_pps_init_late(intel_dp);
6108
6109         return true;
6110
6111 out_vdd_off:
6112         intel_pps_vdd_off_sync(intel_dp);
6113
6114         return false;
6115 }
6116
6117 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6118 {
6119         struct intel_connector *intel_connector;
6120         struct drm_connector *connector;
6121
6122         intel_connector = container_of(work, typeof(*intel_connector),
6123                                        modeset_retry_work);
6124         connector = &intel_connector->base;
6125         drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
6126                     connector->name);
6127
6128         /* Grab the locks before changing connector property*/
6129         mutex_lock(&connector->dev->mode_config.mutex);
6130         /* Set connector link status to BAD and send a Uevent to notify
6131          * userspace to do a modeset.
6132          */
6133         drm_connector_set_link_status_property(connector,
6134                                                DRM_MODE_LINK_STATUS_BAD);
6135         mutex_unlock(&connector->dev->mode_config.mutex);
6136         /* Send Hotplug uevent so userspace can reprobe */
6137         drm_kms_helper_connector_hotplug_event(connector);
6138 }
6139
6140 bool
6141 intel_dp_init_connector(struct intel_digital_port *dig_port,
6142                         struct intel_connector *intel_connector)
6143 {
6144         struct drm_connector *connector = &intel_connector->base;
6145         struct intel_dp *intel_dp = &dig_port->dp;
6146         struct intel_encoder *intel_encoder = &dig_port->base;
6147         struct drm_device *dev = intel_encoder->base.dev;
6148         struct drm_i915_private *dev_priv = to_i915(dev);
6149         enum port port = intel_encoder->port;
6150         enum phy phy = intel_port_to_phy(dev_priv, port);
6151         int type;
6152
6153         /* Initialize the work for modeset in case of link train failure */
6154         INIT_WORK(&intel_connector->modeset_retry_work,
6155                   intel_dp_modeset_retry_work_fn);
6156
6157         if (drm_WARN(dev, dig_port->max_lanes < 1,
6158                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6159                      dig_port->max_lanes, intel_encoder->base.base.id,
6160                      intel_encoder->base.name))
6161                 return false;
6162
6163         intel_dp->reset_link_params = true;
6164         intel_dp->pps.pps_pipe = INVALID_PIPE;
6165         intel_dp->pps.active_pipe = INVALID_PIPE;
6166
6167         /* Preserve the current hw state. */
6168         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6169         intel_dp->attached_connector = intel_connector;
6170
6171         if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
6172                 /*
6173                  * Currently we don't support eDP on TypeC ports, although in
6174                  * theory it could work on TypeC legacy ports.
6175                  */
6176                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
6177                 type = DRM_MODE_CONNECTOR_eDP;
6178                 intel_encoder->type = INTEL_OUTPUT_EDP;
6179
6180                 /* eDP only on port B and/or C on vlv/chv */
6181                 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
6182                                       IS_CHERRYVIEW(dev_priv)) &&
6183                                 port != PORT_B && port != PORT_C))
6184                         return false;
6185         } else {
6186                 type = DRM_MODE_CONNECTOR_DisplayPort;
6187         }
6188
6189         intel_dp_set_default_sink_rates(intel_dp);
6190         intel_dp_set_default_max_sink_lane_count(intel_dp);
6191
6192         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6193                 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
6194
6195         intel_dp_aux_init(intel_dp);
6196         intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;
6197
6198         drm_dbg_kms(&dev_priv->drm,
6199                     "Adding %s connector on [ENCODER:%d:%s]\n",
6200                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6201                     intel_encoder->base.base.id, intel_encoder->base.name);
6202
6203         drm_connector_init_with_ddc(dev, connector, &intel_dp_connector_funcs,
6204                                     type, &intel_dp->aux.ddc);
6205         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6206
6207         if (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) < 12)
6208                 connector->interlace_allowed = true;
6209
6210         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
6211
6212         intel_connector_attach_encoder(intel_connector, intel_encoder);
6213
6214         if (HAS_DDI(dev_priv))
6215                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6216         else
6217                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6218
6219         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6220                 intel_dp_aux_fini(intel_dp);
6221                 goto fail;
6222         }
6223
6224         intel_dp_set_source_rates(intel_dp);
6225         intel_dp_set_common_rates(intel_dp);
6226         intel_dp_reset_max_link_params(intel_dp);
6227
6228         /* init MST on ports that can support it */
6229         intel_dp_mst_encoder_init(dig_port,
6230                                   intel_connector->base.base.id);
6231
6232         intel_dp_add_properties(intel_dp, connector);
6233
6234         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6235                 int ret = intel_dp_hdcp_init(dig_port, intel_connector);
6236                 if (ret)
6237                         drm_dbg_kms(&dev_priv->drm,
6238                                     "HDCP init failed, skipping.\n");
6239         }
6240
6241         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6242          * 0xd.  Failure to do so will result in spurious interrupts being
6243          * generated on the port when a cable is not attached.
6244          */
6245         if (IS_G45(dev_priv)) {
6246                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
6247                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
6248                                (temp & ~0xf) | 0xd);
6249         }
6250
6251         intel_dp->frl.is_trained = false;
6252         intel_dp->frl.trained_rate_gbps = 0;
6253
6254         intel_psr_init(intel_dp);
6255
6256         return true;
6257
6258 fail:
6259         intel_display_power_flush_work(dev_priv);
6260         drm_connector_cleanup(connector);
6261
6262         return false;
6263 }
6264
6265 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6266 {
6267         struct intel_encoder *encoder;
6268
6269         if (!HAS_DISPLAY(dev_priv))
6270                 return;
6271
6272         for_each_intel_encoder(&dev_priv->drm, encoder) {
6273                 struct intel_dp *intel_dp;
6274
6275                 if (encoder->type != INTEL_OUTPUT_DDI)
6276                         continue;
6277
6278                 intel_dp = enc_to_intel_dp(encoder);
6279
6280                 if (!intel_dp_mst_source_support(intel_dp))
6281                         continue;
6282
6283                 if (intel_dp->is_mst)
6284                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6285         }
6286 }
6287
6288 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6289 {
6290         struct intel_encoder *encoder;
6291
6292         if (!HAS_DISPLAY(dev_priv))
6293                 return;
6294
6295         for_each_intel_encoder(&dev_priv->drm, encoder) {
6296                 struct intel_dp *intel_dp;
6297                 int ret;
6298
6299                 if (encoder->type != INTEL_OUTPUT_DDI)
6300                         continue;
6301
6302                 intel_dp = enc_to_intel_dp(encoder);
6303
6304                 if (!intel_dp_mst_source_support(intel_dp))
6305                         continue;
6306
6307                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
6308                                                      true);
6309                 if (ret) {
6310                         intel_dp->is_mst = false;
6311                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6312                                                         false);
6313                 }
6314         }
6315 }